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authorDavid S. Miller <davem@davemloft.net>2018-01-16 14:40:02 -0500
committerDavid S. Miller <davem@davemloft.net>2018-01-16 14:40:02 -0500
commit10a435ab3097a916c6989d53d4f5637621a009b5 (patch)
treeb1cff77e0cd7e44e657940e19769303e244977cc
parent3b039b42e42e3e7f70c3aa61ade73d4ef3e322dc (diff)
parent9ec03bf63965c970f1b750d4adbea88c8363b03b (diff)
Merge branch 'aquantia-next'
Igor Russkikh says: ==================== Aquantia atlantic driver update 2018/01 This patch is a set of cleanups and bugfixes in preparation to new Aquantia hardware support. Standard ARRAY_SIZE is now used through all the code, some unused abstraction structures removed and cleaned up, duplicate declarations removed. Also two large declaration styling fixes: - Hardware register set defines are lined up with kernel style - Hardware access functions were not prefixed, now already defined hw_atl prefix is used. patch v2 changes: - patch reorganized because of its big size. New HW support will be submitted as a separate patchset. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_common.h1
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_hw.h35
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c6
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_main.c96
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_main.h2
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_nic.c41
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_nic.h41
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_nic_internal.h45
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c99
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h7
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_ring.c4
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_ring.h2
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_utils.h6
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_vec.c5
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_vec.h4
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c349
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.h2
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h31
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c375
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h2
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h31
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c1326
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h544
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h1521
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c82
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h62
26 files changed, 2385 insertions, 2334 deletions
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_common.h b/drivers/net/ethernet/aquantia/atlantic/aq_common.h
index 9eb5e222a234..f79da4b5900b 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_common.h
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_common.h
@@ -16,7 +16,6 @@
16#include <linux/pci.h> 16#include <linux/pci.h>
17 17
18#include "ver.h" 18#include "ver.h"
19#include "aq_nic.h"
20#include "aq_cfg.h" 19#include "aq_cfg.h"
21#include "aq_utils.h" 20#include "aq_utils.h"
22 21
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h
index b3825de6cdfb..5d67f1335f4d 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h
@@ -7,7 +7,7 @@
7 * version 2, as published by the Free Software Foundation. 7 * version 2, as published by the Free Software Foundation.
8 */ 8 */
9 9
10/* File aq_hw.h: Declaraion of abstract interface for NIC hardware specific 10/* File aq_hw.h: Declaration of abstract interface for NIC hardware specific
11 * functions. 11 * functions.
12 */ 12 */
13 13
@@ -15,6 +15,8 @@
15#define AQ_HW_H 15#define AQ_HW_H
16 16
17#include "aq_common.h" 17#include "aq_common.h"
18#include "aq_rss.h"
19#include "hw_atl/hw_atl_utils.h"
18 20
19/* NIC H/W capabilities */ 21/* NIC H/W capabilities */
20struct aq_hw_caps_s { 22struct aq_hw_caps_s {
@@ -86,13 +88,33 @@ struct aq_stats_s {
86 88
87#define AQ_HW_FLAG_ERRORS (AQ_HW_FLAG_ERR_HW | AQ_HW_FLAG_ERR_UNPLUG) 89#define AQ_HW_FLAG_ERRORS (AQ_HW_FLAG_ERR_HW | AQ_HW_FLAG_ERR_UNPLUG)
88 90
91#define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING | \
92 AQ_NIC_FLAG_RESETTING | AQ_NIC_FLAG_CLOSING | \
93 AQ_NIC_FLAG_ERR_UNPLUG | AQ_NIC_FLAG_ERR_HW)
94
95#define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \
96 AQ_NIC_LINK_DOWN)
97
89struct aq_hw_s { 98struct aq_hw_s {
90 struct aq_obj_s header; 99 atomic_t flags;
91 struct aq_nic_cfg_s *aq_nic_cfg; 100 struct aq_nic_cfg_s *aq_nic_cfg;
92 struct aq_pci_func_s *aq_pci_func; 101 struct aq_pci_func_s *aq_pci_func;
93 void __iomem *mmio; 102 void __iomem *mmio;
94 unsigned int not_ff_addr; 103 unsigned int not_ff_addr;
95 struct aq_hw_link_status_s aq_link_status; 104 struct aq_hw_link_status_s aq_link_status;
105 struct hw_aq_atl_utils_mbox mbox;
106 struct hw_atl_stats_s last_stats;
107 struct aq_stats_s curr_stats;
108 u64 speed;
109 u32 itr_tx;
110 u32 itr_rx;
111 unsigned int chip_features;
112 u32 fw_ver_actual;
113 atomic_t dpc;
114 u32 mbox_addr;
115 u32 rpc_addr;
116 u32 rpc_tid;
117 struct hw_aq_atl_utils_fw_rpc rpc;
96}; 118};
97 119
98struct aq_ring_s; 120struct aq_ring_s;
@@ -102,7 +124,7 @@ struct sk_buff;
102 124
103struct aq_hw_ops { 125struct aq_hw_ops {
104 struct aq_hw_s *(*create)(struct aq_pci_func_s *aq_pci_func, 126 struct aq_hw_s *(*create)(struct aq_pci_func_s *aq_pci_func,
105 unsigned int port, struct aq_hw_ops *ops); 127 unsigned int port);
106 128
107 void (*destroy)(struct aq_hw_s *self); 129 void (*destroy)(struct aq_hw_s *self);
108 130
@@ -124,7 +146,6 @@ struct aq_hw_ops {
124 struct aq_ring_s *aq_ring); 146 struct aq_ring_s *aq_ring);
125 147
126 int (*hw_get_mac_permanent)(struct aq_hw_s *self, 148 int (*hw_get_mac_permanent)(struct aq_hw_s *self,
127 struct aq_hw_caps_s *aq_hw_caps,
128 u8 *mac); 149 u8 *mac);
129 150
130 int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr); 151 int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr);
@@ -135,8 +156,7 @@ struct aq_hw_ops {
135 156
136 int (*hw_reset)(struct aq_hw_s *self); 157 int (*hw_reset)(struct aq_hw_s *self);
137 158
138 int (*hw_init)(struct aq_hw_s *self, struct aq_nic_cfg_s *aq_nic_cfg, 159 int (*hw_init)(struct aq_hw_s *self, u8 *mac_addr);
139 u8 *mac_addr);
140 160
141 int (*hw_start)(struct aq_hw_s *self); 161 int (*hw_start)(struct aq_hw_s *self);
142 162
@@ -184,7 +204,8 @@ struct aq_hw_ops {
184 struct aq_rss_parameters *rss_params); 204 struct aq_rss_parameters *rss_params);
185 205
186 int (*hw_get_regs)(struct aq_hw_s *self, 206 int (*hw_get_regs)(struct aq_hw_s *self,
187 struct aq_hw_caps_s *aq_hw_caps, u32 *regs_buff); 207 const struct aq_hw_caps_s *aq_hw_caps,
208 u32 *regs_buff);
188 209
189 int (*hw_update_stats)(struct aq_hw_s *self); 210 int (*hw_update_stats)(struct aq_hw_s *self);
190 211
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c
index 5f13465995f6..27e250d61da7 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c
@@ -40,7 +40,7 @@ u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg)
40 u32 value = readl(hw->mmio + reg); 40 u32 value = readl(hw->mmio + reg);
41 41
42 if ((~0U) == value && (~0U) == readl(hw->mmio + hw->not_ff_addr)) 42 if ((~0U) == value && (~0U) == readl(hw->mmio + hw->not_ff_addr))
43 aq_utils_obj_set(&hw->header.flags, AQ_HW_FLAG_ERR_UNPLUG); 43 aq_utils_obj_set(&hw->flags, AQ_HW_FLAG_ERR_UNPLUG);
44 44
45 return value; 45 return value;
46} 46}
@@ -54,11 +54,11 @@ int aq_hw_err_from_flags(struct aq_hw_s *hw)
54{ 54{
55 int err = 0; 55 int err = 0;
56 56
57 if (aq_utils_obj_test(&hw->header.flags, AQ_HW_FLAG_ERR_UNPLUG)) { 57 if (aq_utils_obj_test(&hw->flags, AQ_HW_FLAG_ERR_UNPLUG)) {
58 err = -ENXIO; 58 err = -ENXIO;
59 goto err_exit; 59 goto err_exit;
60 } 60 }
61 if (aq_utils_obj_test(&hw->header.flags, AQ_HW_FLAG_ERR_HW)) { 61 if (aq_utils_obj_test(&hw->flags, AQ_HW_FLAG_ERR_HW)) {
62 err = -EIO; 62 err = -EIO;
63 goto err_exit; 63 goto err_exit;
64 } 64 }
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_main.c b/drivers/net/ethernet/aquantia/atlantic/aq_main.c
index 5d6c40d86775..887bc846375a 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_main.c
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_main.c
@@ -13,37 +13,32 @@
13#include "aq_nic.h" 13#include "aq_nic.h"
14#include "aq_pci_func.h" 14#include "aq_pci_func.h"
15#include "aq_ethtool.h" 15#include "aq_ethtool.h"
16#include "hw_atl/hw_atl_a0.h"
17#include "hw_atl/hw_atl_b0.h"
18 16
19#include <linux/netdevice.h> 17#include <linux/netdevice.h>
20#include <linux/module.h> 18#include <linux/module.h>
21 19
22static const struct pci_device_id aq_pci_tbl[] = {
23 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_0001), },
24 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D100), },
25 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D107), },
26 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D108), },
27 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D109), },
28 {}
29};
30
31MODULE_DEVICE_TABLE(pci, aq_pci_tbl);
32
33MODULE_LICENSE("GPL v2"); 20MODULE_LICENSE("GPL v2");
34MODULE_VERSION(AQ_CFG_DRV_VERSION); 21MODULE_VERSION(AQ_CFG_DRV_VERSION);
35MODULE_AUTHOR(AQ_CFG_DRV_AUTHOR); 22MODULE_AUTHOR(AQ_CFG_DRV_AUTHOR);
36MODULE_DESCRIPTION(AQ_CFG_DRV_DESC); 23MODULE_DESCRIPTION(AQ_CFG_DRV_DESC);
37 24
38static struct aq_hw_ops *aq_pci_probe_get_hw_ops_by_id(struct pci_dev *pdev) 25static const struct net_device_ops aq_ndev_ops;
26
27struct net_device *aq_ndev_alloc(void)
39{ 28{
40 struct aq_hw_ops *ops = NULL; 29 struct net_device *ndev = NULL;
30 struct aq_nic_s *aq_nic = NULL;
41 31
42 ops = hw_atl_a0_get_ops_by_id(pdev); 32 ndev = alloc_etherdev_mq(sizeof(struct aq_nic_s), AQ_CFG_VECS_MAX);
43 if (!ops) 33 if (!ndev)
44 ops = hw_atl_b0_get_ops_by_id(pdev); 34 return NULL;
45 35
46 return ops; 36 aq_nic = netdev_priv(ndev);
37 aq_nic->ndev = ndev;
38 ndev->netdev_ops = &aq_ndev_ops;
39 ndev->ethtool_ops = &aq_ethtool_ops;
40
41 return ndev;
47} 42}
48 43
49static int aq_ndev_open(struct net_device *ndev) 44static int aq_ndev_open(struct net_device *ndev)
@@ -170,66 +165,3 @@ static const struct net_device_ops aq_ndev_ops = {
170 .ndo_set_mac_address = aq_ndev_set_mac_address, 165 .ndo_set_mac_address = aq_ndev_set_mac_address,
171 .ndo_set_features = aq_ndev_set_features 166 .ndo_set_features = aq_ndev_set_features
172}; 167};
173
174static int aq_pci_probe(struct pci_dev *pdev,
175 const struct pci_device_id *pci_id)
176{
177 struct aq_hw_ops *aq_hw_ops = NULL;
178 struct aq_pci_func_s *aq_pci_func = NULL;
179 int err = 0;
180
181 err = pci_enable_device(pdev);
182 if (err < 0)
183 goto err_exit;
184 aq_hw_ops = aq_pci_probe_get_hw_ops_by_id(pdev);
185 aq_pci_func = aq_pci_func_alloc(aq_hw_ops, pdev,
186 &aq_ndev_ops, &aq_ethtool_ops);
187 if (!aq_pci_func) {
188 err = -ENOMEM;
189 goto err_exit;
190 }
191 err = aq_pci_func_init(aq_pci_func);
192 if (err < 0)
193 goto err_exit;
194
195err_exit:
196 if (err < 0) {
197 if (aq_pci_func)
198 aq_pci_func_free(aq_pci_func);
199 }
200 return err;
201}
202
203static void aq_pci_remove(struct pci_dev *pdev)
204{
205 struct aq_pci_func_s *aq_pci_func = pci_get_drvdata(pdev);
206
207 aq_pci_func_deinit(aq_pci_func);
208 aq_pci_func_free(aq_pci_func);
209}
210
211static int aq_pci_suspend(struct pci_dev *pdev, pm_message_t pm_msg)
212{
213 struct aq_pci_func_s *aq_pci_func = pci_get_drvdata(pdev);
214
215 return aq_pci_func_change_pm_state(aq_pci_func, &pm_msg);
216}
217
218static int aq_pci_resume(struct pci_dev *pdev)
219{
220 struct aq_pci_func_s *aq_pci_func = pci_get_drvdata(pdev);
221 pm_message_t pm_msg = PMSG_RESTORE;
222
223 return aq_pci_func_change_pm_state(aq_pci_func, &pm_msg);
224}
225
226static struct pci_driver aq_pci_ops = {
227 .name = AQ_CFG_DRV_NAME,
228 .id_table = aq_pci_tbl,
229 .probe = aq_pci_probe,
230 .remove = aq_pci_remove,
231 .suspend = aq_pci_suspend,
232 .resume = aq_pci_resume,
233};
234
235module_pci_driver(aq_pci_ops);
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_main.h b/drivers/net/ethernet/aquantia/atlantic/aq_main.h
index 9748e7e575e0..ce92152eb43e 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_main.h
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_main.h
@@ -14,4 +14,6 @@
14 14
15#include "aq_common.h" 15#include "aq_common.h"
16 16
17struct net_device *aq_ndev_alloc(void);
18
17#endif /* AQ_MAIN_H */ 19#endif /* AQ_MAIN_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c
index 75a894a9251c..d98251371ee4 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c
@@ -14,7 +14,7 @@
14#include "aq_vec.h" 14#include "aq_vec.h"
15#include "aq_hw.h" 15#include "aq_hw.h"
16#include "aq_pci_func.h" 16#include "aq_pci_func.h"
17#include "aq_nic_internal.h" 17#include "aq_main.h"
18 18
19#include <linux/moduleparam.h> 19#include <linux/moduleparam.h>
20#include <linux/netdevice.h> 20#include <linux/netdevice.h>
@@ -150,9 +150,9 @@ static int aq_nic_update_link_status(struct aq_nic_s *self)
150 150
151 self->link_status = self->aq_hw->aq_link_status; 151 self->link_status = self->aq_hw->aq_link_status;
152 if (!netif_carrier_ok(self->ndev) && self->link_status.mbps) { 152 if (!netif_carrier_ok(self->ndev) && self->link_status.mbps) {
153 aq_utils_obj_set(&self->header.flags, 153 aq_utils_obj_set(&self->flags,
154 AQ_NIC_FLAG_STARTED); 154 AQ_NIC_FLAG_STARTED);
155 aq_utils_obj_clear(&self->header.flags, 155 aq_utils_obj_clear(&self->flags,
156 AQ_NIC_LINK_DOWN); 156 AQ_NIC_LINK_DOWN);
157 netif_carrier_on(self->ndev); 157 netif_carrier_on(self->ndev);
158 netif_tx_wake_all_queues(self->ndev); 158 netif_tx_wake_all_queues(self->ndev);
@@ -160,7 +160,7 @@ static int aq_nic_update_link_status(struct aq_nic_s *self)
160 if (netif_carrier_ok(self->ndev) && !self->link_status.mbps) { 160 if (netif_carrier_ok(self->ndev) && !self->link_status.mbps) {
161 netif_carrier_off(self->ndev); 161 netif_carrier_off(self->ndev);
162 netif_tx_disable(self->ndev); 162 netif_tx_disable(self->ndev);
163 aq_utils_obj_set(&self->header.flags, AQ_NIC_LINK_DOWN); 163 aq_utils_obj_set(&self->flags, AQ_NIC_LINK_DOWN);
164 } 164 }
165 return 0; 165 return 0;
166} 166}
@@ -171,7 +171,7 @@ static void aq_nic_service_timer_cb(struct timer_list *t)
171 int ctimer = AQ_CFG_SERVICE_TIMER_INTERVAL; 171 int ctimer = AQ_CFG_SERVICE_TIMER_INTERVAL;
172 int err = 0; 172 int err = 0;
173 173
174 if (aq_utils_obj_test(&self->header.flags, AQ_NIC_FLAGS_IS_NOT_READY)) 174 if (aq_utils_obj_test(&self->flags, AQ_NIC_FLAGS_IS_NOT_READY))
175 goto err_exit; 175 goto err_exit;
176 176
177 err = aq_nic_update_link_status(self); 177 err = aq_nic_update_link_status(self);
@@ -205,14 +205,7 @@ static void aq_nic_polling_timer_cb(struct timer_list *t)
205 AQ_CFG_POLLING_TIMER_INTERVAL); 205 AQ_CFG_POLLING_TIMER_INTERVAL);
206} 206}
207 207
208static struct net_device *aq_nic_ndev_alloc(void) 208struct aq_nic_s *aq_nic_alloc_cold(struct pci_dev *pdev,
209{
210 return alloc_etherdev_mq(sizeof(struct aq_nic_s), AQ_CFG_VECS_MAX);
211}
212
213struct aq_nic_s *aq_nic_alloc_cold(const struct net_device_ops *ndev_ops,
214 const struct ethtool_ops *et_ops,
215 struct pci_dev *pdev,
216 struct aq_pci_func_s *aq_pci_func, 209 struct aq_pci_func_s *aq_pci_func,
217 unsigned int port, 210 unsigned int port,
218 const struct aq_hw_ops *aq_hw_ops) 211 const struct aq_hw_ops *aq_hw_ops)
@@ -221,7 +214,7 @@ struct aq_nic_s *aq_nic_alloc_cold(const struct net_device_ops *ndev_ops,
221 struct aq_nic_s *self = NULL; 214 struct aq_nic_s *self = NULL;
222 int err = 0; 215 int err = 0;
223 216
224 ndev = aq_nic_ndev_alloc(); 217 ndev = aq_ndev_alloc();
225 if (!ndev) { 218 if (!ndev) {
226 err = -ENOMEM; 219 err = -ENOMEM;
227 goto err_exit; 220 goto err_exit;
@@ -229,9 +222,6 @@ struct aq_nic_s *aq_nic_alloc_cold(const struct net_device_ops *ndev_ops,
229 222
230 self = netdev_priv(ndev); 223 self = netdev_priv(ndev);
231 224
232 ndev->netdev_ops = ndev_ops;
233 ndev->ethtool_ops = et_ops;
234
235 SET_NETDEV_DEV(ndev, &pdev->dev); 225 SET_NETDEV_DEV(ndev, &pdev->dev);
236 226
237 ndev->if_port = port; 227 ndev->if_port = port;
@@ -242,8 +232,9 @@ struct aq_nic_s *aq_nic_alloc_cold(const struct net_device_ops *ndev_ops,
242 self->aq_hw_ops = *aq_hw_ops; 232 self->aq_hw_ops = *aq_hw_ops;
243 self->port = (u8)port; 233 self->port = (u8)port;
244 234
245 self->aq_hw = self->aq_hw_ops.create(aq_pci_func, self->port, 235 self->aq_hw = self->aq_hw_ops.create(aq_pci_func, self->port);
246 &self->aq_hw_ops); 236 self->aq_hw->aq_nic_cfg = &self->aq_nic_cfg;
237
247 err = self->aq_hw_ops.get_hw_caps(self->aq_hw, &self->aq_hw_caps, 238 err = self->aq_hw_ops.get_hw_caps(self->aq_hw, &self->aq_hw_caps,
248 pdev->device, pdev->subsystem_device); 239 pdev->device, pdev->subsystem_device);
249 if (err < 0) 240 if (err < 0)
@@ -268,7 +259,6 @@ int aq_nic_ndev_register(struct aq_nic_s *self)
268 goto err_exit; 259 goto err_exit;
269 } 260 }
270 err = self->aq_hw_ops.hw_get_mac_permanent(self->aq_hw, 261 err = self->aq_hw_ops.hw_get_mac_permanent(self->aq_hw,
271 self->aq_nic_cfg.aq_hw_caps,
272 self->ndev->dev_addr); 262 self->ndev->dev_addr);
273 if (err < 0) 263 if (err < 0)
274 goto err_exit; 264 goto err_exit;
@@ -295,7 +285,7 @@ err_exit:
295 285
296int aq_nic_ndev_init(struct aq_nic_s *self) 286int aq_nic_ndev_init(struct aq_nic_s *self)
297{ 287{
298 struct aq_hw_caps_s *aq_hw_caps = self->aq_nic_cfg.aq_hw_caps; 288 const struct aq_hw_caps_s *aq_hw_caps = self->aq_nic_cfg.aq_hw_caps;
299 struct aq_nic_cfg_s *aq_nic_cfg = &self->aq_nic_cfg; 289 struct aq_nic_cfg_s *aq_nic_cfg = &self->aq_nic_cfg;
300 290
301 self->ndev->hw_features |= aq_hw_caps->hw_features; 291 self->ndev->hw_features |= aq_hw_caps->hw_features;
@@ -366,11 +356,6 @@ void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx,
366 self->aq_ring_tx[idx] = ring; 356 self->aq_ring_tx[idx] = ring;
367} 357}
368 358
369struct device *aq_nic_get_dev(struct aq_nic_s *self)
370{
371 return self->ndev->dev.parent;
372}
373
374struct net_device *aq_nic_get_ndev(struct aq_nic_s *self) 359struct net_device *aq_nic_get_ndev(struct aq_nic_s *self)
375{ 360{
376 return self->ndev; 361 return self->ndev;
@@ -387,7 +372,7 @@ int aq_nic_init(struct aq_nic_s *self)
387 if (err < 0) 372 if (err < 0)
388 goto err_exit; 373 goto err_exit;
389 374
390 err = self->aq_hw_ops.hw_init(self->aq_hw, &self->aq_nic_cfg, 375 err = self->aq_hw_ops.hw_init(self->aq_hw,
391 aq_nic_get_ndev(self)->dev_addr); 376 aq_nic_get_ndev(self)->dev_addr);
392 if (err < 0) 377 if (err < 0)
393 goto err_exit; 378 goto err_exit;
@@ -992,7 +977,7 @@ void aq_nic_free_hot_resources(struct aq_nic_s *self)
992 if (!self) 977 if (!self)
993 goto err_exit; 978 goto err_exit;
994 979
995 for (i = AQ_DIMOF(self->aq_vec); i--;) { 980 for (i = ARRAY_SIZE(self->aq_vec); i--;) {
996 if (self->aq_vec[i]) { 981 if (self->aq_vec[i]) {
997 aq_vec_free(self->aq_vec[i]); 982 aq_vec_free(self->aq_vec[i]);
998 self->aq_vec[i] = NULL; 983 self->aq_vec[i] = NULL;
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.h b/drivers/net/ethernet/aquantia/atlantic/aq_nic.h
index 3c9f8db03d5f..1cd7d728e91b 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.h
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.h
@@ -14,10 +14,13 @@
14 14
15#include "aq_common.h" 15#include "aq_common.h"
16#include "aq_rss.h" 16#include "aq_rss.h"
17#include "aq_hw.h"
17 18
18struct aq_ring_s; 19struct aq_ring_s;
19struct aq_pci_func_s; 20struct aq_pci_func_s;
20struct aq_hw_ops; 21struct aq_hw_ops;
22struct aq_fw_s;
23struct aq_vec_s;
21 24
22#define AQ_NIC_FC_OFF 0U 25#define AQ_NIC_FC_OFF 0U
23#define AQ_NIC_FC_TX 1U 26#define AQ_NIC_FC_TX 1U
@@ -33,7 +36,7 @@ struct aq_hw_ops;
33#define AQ_NIC_RATE_100M BIT(5) 36#define AQ_NIC_RATE_100M BIT(5)
34 37
35struct aq_nic_cfg_s { 38struct aq_nic_cfg_s {
36 struct aq_hw_caps_s *aq_hw_caps; 39 const struct aq_hw_caps_s *aq_hw_caps;
37 u64 hw_features; 40 u64 hw_features;
38 u32 rxds; /* rx ring size, descriptors # */ 41 u32 rxds; /* rx ring size, descriptors # */
39 u32 txds; /* tx ring size, descriptors # */ 42 u32 txds; /* tx ring size, descriptors # */
@@ -44,7 +47,6 @@ struct aq_nic_cfg_s {
44 u16 tx_itr; 47 u16 tx_itr;
45 u32 num_rss_queues; 48 u32 num_rss_queues;
46 u32 mtu; 49 u32 mtu;
47 u32 ucp_0x364;
48 u32 flow_control; 50 u32 flow_control;
49 u32 link_speed_msk; 51 u32 link_speed_msk;
50 u32 vlan_id; 52 u32 vlan_id;
@@ -69,9 +71,38 @@ struct aq_nic_cfg_s {
69#define AQ_NIC_TCVEC2RING(_NIC_, _TC_, _VEC_) \ 71#define AQ_NIC_TCVEC2RING(_NIC_, _TC_, _VEC_) \
70 ((_TC_) * AQ_CFG_TCS_MAX + (_VEC_)) 72 ((_TC_) * AQ_CFG_TCS_MAX + (_VEC_))
71 73
72struct aq_nic_s *aq_nic_alloc_cold(const struct net_device_ops *ndev_ops, 74struct aq_nic_s {
73 const struct ethtool_ops *et_ops, 75 atomic_t flags;
74 struct pci_dev *pdev, 76 struct aq_vec_s *aq_vec[AQ_CFG_VECS_MAX];
77 struct aq_ring_s *aq_ring_tx[AQ_CFG_VECS_MAX * AQ_CFG_TCS_MAX];
78 struct aq_hw_s *aq_hw;
79 struct net_device *ndev;
80 struct aq_pci_func_s *aq_pci_func;
81 unsigned int aq_vecs;
82 unsigned int packet_filter;
83 unsigned int power_state;
84 u8 port;
85 struct aq_hw_ops aq_hw_ops;
86 struct aq_hw_caps_s aq_hw_caps;
87 struct aq_nic_cfg_s aq_nic_cfg;
88 struct timer_list service_timer;
89 struct timer_list polling_timer;
90 struct aq_hw_link_status_s link_status;
91 struct {
92 u32 count;
93 u8 ar[AQ_CFG_MULTICAST_ADDRESS_MAX][ETH_ALEN];
94 } mc_list;
95
96 struct pci_dev *pdev;
97 unsigned int msix_entry_mask;
98};
99
100static inline struct device *aq_nic_get_dev(struct aq_nic_s *self)
101{
102 return self->ndev->dev.parent;
103}
104
105struct aq_nic_s *aq_nic_alloc_cold(struct pci_dev *pdev,
75 struct aq_pci_func_s *aq_pci_func, 106 struct aq_pci_func_s *aq_pci_func,
76 unsigned int port, 107 unsigned int port,
77 const struct aq_hw_ops *aq_hw_ops); 108 const struct aq_hw_ops *aq_hw_ops);
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic_internal.h b/drivers/net/ethernet/aquantia/atlantic/aq_nic_internal.h
deleted file mode 100644
index e7d2711dc165..000000000000
--- a/drivers/net/ethernet/aquantia/atlantic/aq_nic_internal.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_nic_internal.h: Definition of private object structure. */
11
12#ifndef AQ_NIC_INTERNAL_H
13#define AQ_NIC_INTERNAL_H
14
15struct aq_nic_s {
16 struct aq_obj_s header;
17 struct aq_vec_s *aq_vec[AQ_CFG_VECS_MAX];
18 struct aq_ring_s *aq_ring_tx[AQ_CFG_VECS_MAX * AQ_CFG_TCS_MAX];
19 struct aq_hw_s *aq_hw;
20 struct net_device *ndev;
21 struct aq_pci_func_s *aq_pci_func;
22 unsigned int aq_vecs;
23 unsigned int packet_filter;
24 unsigned int power_state;
25 u8 port;
26 struct aq_hw_ops aq_hw_ops;
27 struct aq_hw_caps_s aq_hw_caps;
28 struct aq_nic_cfg_s aq_nic_cfg;
29 struct timer_list service_timer;
30 struct timer_list polling_timer;
31 struct aq_hw_link_status_s link_status;
32 struct {
33 u32 count;
34 u8 ar[AQ_CFG_MULTICAST_ADDRESS_MAX][ETH_ALEN];
35 } mc_list;
36};
37
38#define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING | \
39 AQ_NIC_FLAG_RESETTING | AQ_NIC_FLAG_CLOSING | \
40 AQ_NIC_FLAG_ERR_UNPLUG | AQ_NIC_FLAG_ERR_HW)
41
42#define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \
43 AQ_NIC_LINK_DOWN)
44
45#endif /* AQ_NIC_INTERNAL_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c
index 58c29d04b186..78ef7d2deffe 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c
@@ -9,11 +9,15 @@
9 9
10/* File aq_pci_func.c: Definition of PCI functions. */ 10/* File aq_pci_func.c: Definition of PCI functions. */
11 11
12#include <linux/interrupt.h>
13#include <linux/module.h>
14
12#include "aq_pci_func.h" 15#include "aq_pci_func.h"
13#include "aq_nic.h" 16#include "aq_nic.h"
14#include "aq_vec.h" 17#include "aq_vec.h"
15#include "aq_hw.h" 18#include "aq_hw.h"
16#include <linux/interrupt.h> 19#include "hw_atl/hw_atl_a0.h"
20#include "hw_atl/hw_atl_b0.h"
17 21
18struct aq_pci_func_s { 22struct aq_pci_func_s {
19 struct pci_dev *pdev; 23 struct pci_dev *pdev;
@@ -29,10 +33,30 @@ struct aq_pci_func_s {
29 struct aq_hw_caps_s aq_hw_caps; 33 struct aq_hw_caps_s aq_hw_caps;
30}; 34};
31 35
32struct aq_pci_func_s *aq_pci_func_alloc(struct aq_hw_ops *aq_hw_ops, 36static const struct pci_device_id aq_pci_tbl[] = {
33 struct pci_dev *pdev, 37 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_0001), },
34 const struct net_device_ops *ndev_ops, 38 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D100), },
35 const struct ethtool_ops *eth_ops) 39 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D107), },
40 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D108), },
41 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D109), },
42 {}
43};
44
45MODULE_DEVICE_TABLE(pci, aq_pci_tbl);
46
47static const struct aq_hw_ops *aq_pci_probe_get_hw_ops_by_id(struct pci_dev *pdev)
48{
49 const struct aq_hw_ops *ops = NULL;
50
51 ops = hw_atl_a0_get_ops_by_id(pdev);
52 if (!ops)
53 ops = hw_atl_b0_get_ops_by_id(pdev);
54
55 return ops;
56}
57
58struct aq_pci_func_s *aq_pci_func_alloc(const struct aq_hw_ops *aq_hw_ops,
59 struct pci_dev *pdev)
36{ 60{
37 struct aq_pci_func_s *self = NULL; 61 struct aq_pci_func_s *self = NULL;
38 int err = 0; 62 int err = 0;
@@ -59,8 +83,7 @@ struct aq_pci_func_s *aq_pci_func_alloc(struct aq_hw_ops *aq_hw_ops,
59 self->ports = self->aq_hw_caps.ports; 83 self->ports = self->aq_hw_caps.ports;
60 84
61 for (port = 0; port < self->ports; ++port) { 85 for (port = 0; port < self->ports; ++port) {
62 struct aq_nic_s *aq_nic = aq_nic_alloc_cold(ndev_ops, eth_ops, 86 struct aq_nic_s *aq_nic = aq_nic_alloc_cold(pdev, self,
63 pdev, self,
64 port, aq_hw_ops); 87 port, aq_hw_ops);
65 88
66 if (!aq_nic) { 89 if (!aq_nic) {
@@ -297,3 +320,65 @@ int aq_pci_func_change_pm_state(struct aq_pci_func_s *self,
297err_exit: 320err_exit:
298 return err; 321 return err;
299} 322}
323
324static int aq_pci_probe(struct pci_dev *pdev,
325 const struct pci_device_id *pci_id)
326{
327 const struct aq_hw_ops *aq_hw_ops = NULL;
328 struct aq_pci_func_s *aq_pci_func = NULL;
329 int err = 0;
330
331 err = pci_enable_device(pdev);
332 if (err < 0)
333 goto err_exit;
334 aq_hw_ops = aq_pci_probe_get_hw_ops_by_id(pdev);
335 aq_pci_func = aq_pci_func_alloc(aq_hw_ops, pdev);
336 if (!aq_pci_func) {
337 err = -ENOMEM;
338 goto err_exit;
339 }
340 err = aq_pci_func_init(aq_pci_func);
341 if (err < 0)
342 goto err_exit;
343
344err_exit:
345 if (err < 0) {
346 if (aq_pci_func)
347 aq_pci_func_free(aq_pci_func);
348 }
349 return err;
350}
351
352static void aq_pci_remove(struct pci_dev *pdev)
353{
354 struct aq_pci_func_s *aq_pci_func = pci_get_drvdata(pdev);
355
356 aq_pci_func_deinit(aq_pci_func);
357 aq_pci_func_free(aq_pci_func);
358}
359
360static int aq_pci_suspend(struct pci_dev *pdev, pm_message_t pm_msg)
361{
362 struct aq_pci_func_s *aq_pci_func = pci_get_drvdata(pdev);
363
364 return aq_pci_func_change_pm_state(aq_pci_func, &pm_msg);
365}
366
367static int aq_pci_resume(struct pci_dev *pdev)
368{
369 struct aq_pci_func_s *aq_pci_func = pci_get_drvdata(pdev);
370 pm_message_t pm_msg = PMSG_RESTORE;
371
372 return aq_pci_func_change_pm_state(aq_pci_func, &pm_msg);
373}
374
375static struct pci_driver aq_pci_ops = {
376 .name = AQ_CFG_DRV_NAME,
377 .id_table = aq_pci_tbl,
378 .probe = aq_pci_probe,
379 .remove = aq_pci_remove,
380 .suspend = aq_pci_suspend,
381 .resume = aq_pci_resume,
382};
383
384module_pci_driver(aq_pci_ops);
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h
index ecb033791203..5f100ea1b0d6 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h
@@ -13,11 +13,10 @@
13#define AQ_PCI_FUNC_H 13#define AQ_PCI_FUNC_H
14 14
15#include "aq_common.h" 15#include "aq_common.h"
16#include "aq_nic.h"
16 17
17struct aq_pci_func_s *aq_pci_func_alloc(struct aq_hw_ops *hw_ops, 18struct aq_pci_func_s *aq_pci_func_alloc(const struct aq_hw_ops *hw_ops,
18 struct pci_dev *pdev, 19 struct pci_dev *pdev);
19 const struct net_device_ops *ndev_ops,
20 const struct ethtool_ops *eth_ops);
21int aq_pci_func_init(struct aq_pci_func_s *self); 20int aq_pci_func_init(struct aq_pci_func_s *self);
22int aq_pci_func_alloc_irq(struct aq_pci_func_s *self, unsigned int i, 21int aq_pci_func_alloc_irq(struct aq_pci_func_s *self, unsigned int i,
23 char *name, void *aq_vec, 22 char *name, void *aq_vec,
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ring.c b/drivers/net/ethernet/aquantia/atlantic/aq_ring.c
index 519ca6534b85..0be6a11370bb 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_ring.c
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_ring.c
@@ -279,10 +279,10 @@ int aq_ring_rx_clean(struct aq_ring_s *self,
279 279
280 skb_record_rx_queue(skb, self->idx); 280 skb_record_rx_queue(skb, self->idx);
281 281
282 napi_gro_receive(napi, skb);
283
284 ++self->stats.rx.packets; 282 ++self->stats.rx.packets;
285 self->stats.rx.bytes += skb->len; 283 self->stats.rx.bytes += skb->len;
284
285 napi_gro_receive(napi, skb);
286 } 286 }
287 287
288err_exit: 288err_exit:
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ring.h b/drivers/net/ethernet/aquantia/atlantic/aq_ring.h
index 5844078764bd..965fae0fb6e0 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_ring.h
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_ring.h
@@ -15,6 +15,7 @@
15#include "aq_common.h" 15#include "aq_common.h"
16 16
17struct page; 17struct page;
18struct aq_nic_cfg_s;
18 19
19/* TxC SOP DX EOP 20/* TxC SOP DX EOP
20 * +----------+----------+----------+----------- 21 * +----------+----------+----------+-----------
@@ -105,7 +106,6 @@ union aq_ring_stats_s {
105}; 106};
106 107
107struct aq_ring_s { 108struct aq_ring_s {
108 struct aq_obj_s header;
109 struct aq_ring_buff_s *buff_ring; 109 struct aq_ring_buff_s *buff_ring;
110 u8 *dx_ring; /* descriptors ring, dma shared mem */ 110 u8 *dx_ring; /* descriptors ring, dma shared mem */
111 struct aq_nic_s *aq_nic; 111 struct aq_nic_s *aq_nic;
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_utils.h b/drivers/net/ethernet/aquantia/atlantic/aq_utils.h
index e12bcdfb874a..786ea8187c69 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_utils.h
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_utils.h
@@ -14,12 +14,6 @@
14 14
15#include "aq_common.h" 15#include "aq_common.h"
16 16
17#define AQ_DIMOF(_ARY_) ARRAY_SIZE(_ARY_)
18
19struct aq_obj_s {
20 atomic_t flags;
21};
22
23static inline void aq_utils_obj_set(atomic_t *flags, u32 mask) 17static inline void aq_utils_obj_set(atomic_t *flags, u32 mask)
24{ 18{
25 unsigned long flags_old, flags_new; 19 unsigned long flags_old, flags_new;
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_vec.c b/drivers/net/ethernet/aquantia/atlantic/aq_vec.c
index 5fecc9a099ef..f890b8a5a862 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_vec.c
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_vec.c
@@ -19,8 +19,7 @@
19#include <linux/netdevice.h> 19#include <linux/netdevice.h>
20 20
21struct aq_vec_s { 21struct aq_vec_s {
22 struct aq_obj_s header; 22 const struct aq_hw_ops *aq_hw_ops;
23 struct aq_hw_ops *aq_hw_ops;
24 struct aq_hw_s *aq_hw; 23 struct aq_hw_s *aq_hw;
25 struct aq_nic_s *aq_nic; 24 struct aq_nic_s *aq_nic;
26 unsigned int tx_rings; 25 unsigned int tx_rings;
@@ -166,7 +165,7 @@ err_exit:
166 return self; 165 return self;
167} 166}
168 167
169int aq_vec_init(struct aq_vec_s *self, struct aq_hw_ops *aq_hw_ops, 168int aq_vec_init(struct aq_vec_s *self, const struct aq_hw_ops *aq_hw_ops,
170 struct aq_hw_s *aq_hw) 169 struct aq_hw_s *aq_hw)
171{ 170{
172 struct aq_ring_s *ring = NULL; 171 struct aq_ring_s *ring = NULL;
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_vec.h b/drivers/net/ethernet/aquantia/atlantic/aq_vec.h
index 6c68b184236c..8bdf60bb3f63 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_vec.h
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_vec.h
@@ -19,6 +19,8 @@
19 19
20struct aq_hw_s; 20struct aq_hw_s;
21struct aq_hw_ops; 21struct aq_hw_ops;
22struct aq_nic_s;
23struct aq_nic_cfg_s;
22struct aq_ring_stats_rx_s; 24struct aq_ring_stats_rx_s;
23struct aq_ring_stats_tx_s; 25struct aq_ring_stats_tx_s;
24 26
@@ -26,7 +28,7 @@ irqreturn_t aq_vec_isr(int irq, void *private);
26irqreturn_t aq_vec_isr_legacy(int irq, void *private); 28irqreturn_t aq_vec_isr_legacy(int irq, void *private);
27struct aq_vec_s *aq_vec_alloc(struct aq_nic_s *aq_nic, unsigned int idx, 29struct aq_vec_s *aq_vec_alloc(struct aq_nic_s *aq_nic, unsigned int idx,
28 struct aq_nic_cfg_s *aq_nic_cfg); 30 struct aq_nic_cfg_s *aq_nic_cfg);
29int aq_vec_init(struct aq_vec_s *self, struct aq_hw_ops *aq_hw_ops, 31int aq_vec_init(struct aq_vec_s *self, const struct aq_hw_ops *aq_hw_ops,
30 struct aq_hw_s *aq_hw); 32 struct aq_hw_s *aq_hw);
31void aq_vec_deinit(struct aq_vec_s *self); 33void aq_vec_deinit(struct aq_vec_s *self);
32void aq_vec_free(struct aq_vec_s *self); 34void aq_vec_free(struct aq_vec_s *self);
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c
index f18dce14c93c..4a1c1b96b8b6 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c
@@ -12,6 +12,7 @@
12#include "../aq_hw.h" 12#include "../aq_hw.h"
13#include "../aq_hw_utils.h" 13#include "../aq_hw_utils.h"
14#include "../aq_ring.h" 14#include "../aq_ring.h"
15#include "../aq_nic.h"
15#include "hw_atl_a0.h" 16#include "hw_atl_a0.h"
16#include "hw_atl_utils.h" 17#include "hw_atl_utils.h"
17#include "hw_atl_llh.h" 18#include "hw_atl_llh.h"
@@ -36,21 +37,20 @@ static int hw_atl_a0_get_hw_caps(struct aq_hw_s *self,
36} 37}
37 38
38static struct aq_hw_s *hw_atl_a0_create(struct aq_pci_func_s *aq_pci_func, 39static struct aq_hw_s *hw_atl_a0_create(struct aq_pci_func_s *aq_pci_func,
39 unsigned int port, 40 unsigned int port)
40 struct aq_hw_ops *ops)
41{ 41{
42 struct hw_atl_s *self = NULL; 42 struct aq_hw_s *self = NULL;
43 43
44 self = kzalloc(sizeof(*self), GFP_KERNEL); 44 self = kzalloc(sizeof(*self), GFP_KERNEL);
45 if (!self) 45 if (!self)
46 goto err_exit; 46 goto err_exit;
47 47
48 self->base.aq_pci_func = aq_pci_func; 48 self->aq_pci_func = aq_pci_func;
49 49
50 self->base.not_ff_addr = 0x10U; 50 self->not_ff_addr = 0x10U;
51 51
52err_exit: 52err_exit:
53 return (struct aq_hw_s *)self; 53 return self;
54} 54}
55 55
56static void hw_atl_a0_destroy(struct aq_hw_s *self) 56static void hw_atl_a0_destroy(struct aq_hw_s *self)
@@ -62,24 +62,24 @@ static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
62{ 62{
63 int err = 0; 63 int err = 0;
64 64
65 glb_glb_reg_res_dis_set(self, 1U); 65 hw_atl_glb_glb_reg_res_dis_set(self, 1U);
66 pci_pci_reg_res_dis_set(self, 0U); 66 hw_atl_pci_pci_reg_res_dis_set(self, 0U);
67 rx_rx_reg_res_dis_set(self, 0U); 67 hw_atl_rx_rx_reg_res_dis_set(self, 0U);
68 tx_tx_reg_res_dis_set(self, 0U); 68 hw_atl_tx_tx_reg_res_dis_set(self, 0U);
69 69
70 HW_ATL_FLUSH(); 70 HW_ATL_FLUSH();
71 glb_soft_res_set(self, 1); 71 hw_atl_glb_soft_res_set(self, 1);
72 72
73 /* check 10 times by 1ms */ 73 /* check 10 times by 1ms */
74 AQ_HW_WAIT_FOR(glb_soft_res_get(self) == 0, 1000U, 10U); 74 AQ_HW_WAIT_FOR(hw_atl_glb_soft_res_get(self) == 0, 1000U, 10U);
75 if (err < 0) 75 if (err < 0)
76 goto err_exit; 76 goto err_exit;
77 77
78 itr_irq_reg_res_dis_set(self, 0U); 78 hw_atl_itr_irq_reg_res_dis_set(self, 0U);
79 itr_res_irq_set(self, 1U); 79 hw_atl_itr_res_irq_set(self, 1U);
80 80
81 /* check 10 times by 1ms */ 81 /* check 10 times by 1ms */
82 AQ_HW_WAIT_FOR(itr_res_irq_get(self) == 0, 1000U, 10U); 82 AQ_HW_WAIT_FOR(hw_atl_itr_res_irq_get(self) == 0, 1000U, 10U);
83 if (err < 0) 83 if (err < 0)
84 goto err_exit; 84 goto err_exit;
85 85
@@ -99,51 +99,53 @@ static int hw_atl_a0_hw_qos_set(struct aq_hw_s *self)
99 bool is_rx_flow_control = false; 99 bool is_rx_flow_control = false;
100 100
101 /* TPS Descriptor rate init */ 101 /* TPS Descriptor rate init */
102 tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U); 102 hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
103 tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA); 103 hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
104 104
105 /* TPS VM init */ 105 /* TPS VM init */
106 tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U); 106 hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
107 107
108 /* TPS TC credits init */ 108 /* TPS TC credits init */
109 tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U); 109 hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
110 tps_tx_pkt_shed_data_arb_mode_set(self, 0U); 110 hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
111 111
112 tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U); 112 hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
113 tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U); 113 hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
114 tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U); 114 hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
115 tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U); 115 hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
116 116
117 /* Tx buf size */ 117 /* Tx buf size */
118 buff_size = HW_ATL_A0_TXBUF_MAX; 118 buff_size = HW_ATL_A0_TXBUF_MAX;
119 119
120 tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc); 120 hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
121 tpb_tx_buff_hi_threshold_per_tc_set(self, 121 hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self,
122 (buff_size * (1024 / 32U) * 66U) / 122 (buff_size *
123 100U, tc); 123 (1024 / 32U) * 66U) /
124 tpb_tx_buff_lo_threshold_per_tc_set(self, 124 100U, tc);
125 (buff_size * (1024 / 32U) * 50U) / 125 hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self,
126 100U, tc); 126 (buff_size *
127 (1024 / 32U) * 50U) /
128 100U, tc);
127 129
128 /* QoS Rx buf size per TC */ 130 /* QoS Rx buf size per TC */
129 tc = 0; 131 tc = 0;
130 is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control); 132 is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
131 buff_size = HW_ATL_A0_RXBUF_MAX; 133 buff_size = HW_ATL_A0_RXBUF_MAX;
132 134
133 rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc); 135 hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
134 rpb_rx_buff_hi_threshold_per_tc_set(self, 136 hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self,
135 (buff_size * 137 (buff_size *
136 (1024U / 32U) * 66U) / 138 (1024U / 32U) * 66U) /
137 100U, tc); 139 100U, tc);
138 rpb_rx_buff_lo_threshold_per_tc_set(self, 140 hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self,
139 (buff_size * 141 (buff_size *
140 (1024U / 32U) * 50U) / 142 (1024U / 32U) * 50U) /
141 100U, tc); 143 100U, tc);
142 rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc); 144 hw_atl_rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
143 145
144 /* QoS 802.1p priority -> TC mapping */ 146 /* QoS 802.1p priority -> TC mapping */
145 for (i_priority = 8U; i_priority--;) 147 for (i_priority = 8U; i_priority--;)
146 rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U); 148 hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
147 149
148 return aq_hw_err_from_flags(self); 150 return aq_hw_err_from_flags(self);
149} 151}
@@ -151,20 +153,19 @@ static int hw_atl_a0_hw_qos_set(struct aq_hw_s *self)
151static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *self, 153static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *self,
152 struct aq_rss_parameters *rss_params) 154 struct aq_rss_parameters *rss_params)
153{ 155{
154 struct aq_nic_cfg_s *cfg = NULL; 156 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
155 int err = 0; 157 int err = 0;
156 unsigned int i = 0U; 158 unsigned int i = 0U;
157 unsigned int addr = 0U; 159 unsigned int addr = 0U;
158 160
159 cfg = self->aq_nic_cfg;
160
161 for (i = 10, addr = 0U; i--; ++addr) { 161 for (i = 10, addr = 0U; i--; ++addr) {
162 u32 key_data = cfg->is_rss ? 162 u32 key_data = cfg->is_rss ?
163 __swab32(rss_params->hash_secret_key[i]) : 0U; 163 __swab32(rss_params->hash_secret_key[i]) : 0U;
164 rpf_rss_key_wr_data_set(self, key_data); 164 hw_atl_rpf_rss_key_wr_data_set(self, key_data);
165 rpf_rss_key_addr_set(self, addr); 165 hw_atl_rpf_rss_key_addr_set(self, addr);
166 rpf_rss_key_wr_en_set(self, 1U); 166 hw_atl_rpf_rss_key_wr_en_set(self, 1U);
167 AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self) == 0, 1000U, 10U); 167 AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,
168 1000U, 10U);
168 if (err < 0) 169 if (err < 0)
169 goto err_exit; 170 goto err_exit;
170 } 171 }
@@ -193,11 +194,12 @@ static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self,
193 ((i * 3U) & 0xFU)); 194 ((i * 3U) & 0xFU));
194 } 195 }
195 196
196 for (i = AQ_DIMOF(bitary); i--;) { 197 for (i = ARRAY_SIZE(bitary); i--;) {
197 rpf_rss_redir_tbl_wr_data_set(self, bitary[i]); 198 hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
198 rpf_rss_redir_tbl_addr_set(self, i); 199 hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
199 rpf_rss_redir_wr_en_set(self, 1U); 200 hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
200 AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self) == 0, 1000U, 10U); 201 AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,
202 1000U, 10U);
201 if (err < 0) 203 if (err < 0)
202 goto err_exit; 204 goto err_exit;
203 } 205 }
@@ -212,35 +214,35 @@ static int hw_atl_a0_hw_offload_set(struct aq_hw_s *self,
212 struct aq_nic_cfg_s *aq_nic_cfg) 214 struct aq_nic_cfg_s *aq_nic_cfg)
213{ 215{
214 /* TX checksums offloads*/ 216 /* TX checksums offloads*/
215 tpo_ipv4header_crc_offload_en_set(self, 1); 217 hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1);
216 tpo_tcp_udp_crc_offload_en_set(self, 1); 218 hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1);
217 219
218 /* RX checksums offloads*/ 220 /* RX checksums offloads*/
219 rpo_ipv4header_crc_offload_en_set(self, 1); 221 hw_atl_rpo_ipv4header_crc_offload_en_set(self, 1);
220 rpo_tcp_udp_crc_offload_en_set(self, 1); 222 hw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1);
221 223
222 /* LSO offloads*/ 224 /* LSO offloads*/
223 tdm_large_send_offload_en_set(self, 0xFFFFFFFFU); 225 hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
224 226
225 return aq_hw_err_from_flags(self); 227 return aq_hw_err_from_flags(self);
226} 228}
227 229
228static int hw_atl_a0_hw_init_tx_path(struct aq_hw_s *self) 230static int hw_atl_a0_hw_init_tx_path(struct aq_hw_s *self)
229{ 231{
230 thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U); 232 hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
231 thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U); 233 hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
232 thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU); 234 hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
233 235
234 /* Tx interrupts */ 236 /* Tx interrupts */
235 tdm_tx_desc_wr_wb_irq_en_set(self, 1U); 237 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
236 238
237 /* misc */ 239 /* misc */
238 aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ? 240 aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
239 0x00010000U : 0x00000000U); 241 0x00010000U : 0x00000000U);
240 tdm_tx_dca_en_set(self, 0U); 242 hw_atl_tdm_tx_dca_en_set(self, 0U);
241 tdm_tx_dca_mode_set(self, 0U); 243 hw_atl_tdm_tx_dca_mode_set(self, 0U);
242 244
243 tpb_tx_path_scp_ins_en_set(self, 1U); 245 hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U);
244 246
245 return aq_hw_err_from_flags(self); 247 return aq_hw_err_from_flags(self);
246} 248}
@@ -251,38 +253,38 @@ static int hw_atl_a0_hw_init_rx_path(struct aq_hw_s *self)
251 int i; 253 int i;
252 254
253 /* Rx TC/RSS number config */ 255 /* Rx TC/RSS number config */
254 rpb_rpf_rx_traf_class_mode_set(self, 1U); 256 hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U);
255 257
256 /* Rx flow control */ 258 /* Rx flow control */
257 rpb_rx_flow_ctl_mode_set(self, 1U); 259 hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);
258 260
259 /* RSS Ring selection */ 261 /* RSS Ring selection */
260 reg_rx_flr_rss_control1set(self, cfg->is_rss ? 262 hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?
261 0xB3333333U : 0x00000000U); 263 0xB3333333U : 0x00000000U);
262 264
263 /* Multicast filters */ 265 /* Multicast filters */
264 for (i = HW_ATL_A0_MAC_MAX; i--;) { 266 for (i = HW_ATL_A0_MAC_MAX; i--;) {
265 rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i); 267 hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
266 rpfl2unicast_flr_act_set(self, 1U, i); 268 hw_atl_rpfl2unicast_flr_act_set(self, 1U, i);
267 } 269 }
268 270
269 reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U); 271 hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
270 reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U); 272 hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
271 273
272 /* Vlan filters */ 274 /* Vlan filters */
273 rpf_vlan_outer_etht_set(self, 0x88A8U); 275 hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U);
274 rpf_vlan_inner_etht_set(self, 0x8100U); 276 hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U);
275 rpf_vlan_prom_mode_en_set(self, 1); 277 hw_atl_rpf_vlan_prom_mode_en_set(self, 1);
276 278
277 /* Rx Interrupts */ 279 /* Rx Interrupts */
278 rdm_rx_desc_wr_wb_irq_en_set(self, 1U); 280 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
279 281
280 /* misc */ 282 /* misc */
281 rpfl2broadcast_flr_act_set(self, 1U); 283 hw_atl_rpfl2broadcast_flr_act_set(self, 1U);
282 rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U)); 284 hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
283 285
284 rdm_rx_dca_en_set(self, 0U); 286 hw_atl_rdm_rx_dca_en_set(self, 0U);
285 rdm_rx_dca_mode_set(self, 0U); 287 hw_atl_rdm_rx_dca_mode_set(self, 0U);
286 288
287 return aq_hw_err_from_flags(self); 289 return aq_hw_err_from_flags(self);
288} 290}
@@ -301,10 +303,10 @@ static int hw_atl_a0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
301 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 303 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
302 (mac_addr[4] << 8) | mac_addr[5]; 304 (mac_addr[4] << 8) | mac_addr[5];
303 305
304 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC); 306 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC);
305 rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_A0_MAC); 307 hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_A0_MAC);
306 rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_A0_MAC); 308 hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_A0_MAC);
307 rpfl2_uc_flr_en_set(self, 1U, HW_ATL_A0_MAC); 309 hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_A0_MAC);
308 310
309 err = aq_hw_err_from_flags(self); 311 err = aq_hw_err_from_flags(self);
310 312
@@ -312,9 +314,7 @@ err_exit:
312 return err; 314 return err;
313} 315}
314 316
315static int hw_atl_a0_hw_init(struct aq_hw_s *self, 317static int hw_atl_a0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
316 struct aq_nic_cfg_s *aq_nic_cfg,
317 u8 *mac_addr)
318{ 318{
319 static u32 aq_hw_atl_igcr_table_[4][2] = { 319 static u32 aq_hw_atl_igcr_table_[4][2] = {
320 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */ 320 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
@@ -325,10 +325,7 @@ static int hw_atl_a0_hw_init(struct aq_hw_s *self,
325 325
326 int err = 0; 326 int err = 0;
327 327
328 self->aq_nic_cfg = aq_nic_cfg; 328 struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg;
329
330 hw_atl_utils_hw_chip_features_init(self,
331 &PHAL_ATLANTIC_A0->chip_features);
332 329
333 hw_atl_a0_hw_init_tx_path(self); 330 hw_atl_a0_hw_init_tx_path(self);
334 hw_atl_a0_hw_init_rx_path(self); 331 hw_atl_a0_hw_init_rx_path(self);
@@ -337,8 +334,8 @@ static int hw_atl_a0_hw_init(struct aq_hw_s *self,
337 334
338 hw_atl_utils_mpi_set(self, MPI_INIT, aq_nic_cfg->link_speed_msk); 335 hw_atl_utils_mpi_set(self, MPI_INIT, aq_nic_cfg->link_speed_msk);
339 336
340 reg_tx_dma_debug_ctl_set(self, 0x800000b8U); 337 hw_atl_reg_tx_dma_debug_ctl_set(self, 0x800000b8U);
341 reg_tx_dma_debug_ctl_set(self, 0x000000b8U); 338 hw_atl_reg_tx_dma_debug_ctl_set(self, 0x000000b8U);
342 339
343 hw_atl_a0_hw_qos_set(self); 340 hw_atl_a0_hw_qos_set(self);
344 hw_atl_a0_hw_rss_set(self, &aq_nic_cfg->aq_rss); 341 hw_atl_a0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
@@ -353,19 +350,18 @@ static int hw_atl_a0_hw_init(struct aq_hw_s *self,
353 goto err_exit; 350 goto err_exit;
354 351
355 /* Interrupts */ 352 /* Interrupts */
356 reg_irq_glb_ctl_set(self, 353 hw_atl_reg_irq_glb_ctl_set(self,
357 aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type] 354 aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
358 [(aq_nic_cfg->vecs > 1U) ? 355 [(aq_nic_cfg->vecs > 1U) ? 1 : 0]);
359 1 : 0]);
360 356
361 itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask); 357 hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
362 358
363 /* Interrupts */ 359 /* Interrupts */
364 reg_gen_irq_map_set(self, 360 hw_atl_reg_gen_irq_map_set(self,
365 ((HW_ATL_A0_ERR_INT << 0x18) | (1U << 0x1F)) | 361 ((HW_ATL_A0_ERR_INT << 0x18) | (1U << 0x1F)) |
366 ((HW_ATL_A0_ERR_INT << 0x10) | (1U << 0x17)) | 362 ((HW_ATL_A0_ERR_INT << 0x10) | (1U << 0x17)) |
367 ((HW_ATL_A0_ERR_INT << 8) | (1U << 0xF)) | 363 ((HW_ATL_A0_ERR_INT << 8) | (1U << 0xF)) |
368 ((HW_ATL_A0_ERR_INT) | (1U << 0x7)), 0U); 364 ((HW_ATL_A0_ERR_INT) | (1U << 0x7)), 0U);
369 365
370 hw_atl_a0_hw_offload_set(self, aq_nic_cfg); 366 hw_atl_a0_hw_offload_set(self, aq_nic_cfg);
371 367
@@ -376,28 +372,28 @@ err_exit:
376static int hw_atl_a0_hw_ring_tx_start(struct aq_hw_s *self, 372static int hw_atl_a0_hw_ring_tx_start(struct aq_hw_s *self,
377 struct aq_ring_s *ring) 373 struct aq_ring_s *ring)
378{ 374{
379 tdm_tx_desc_en_set(self, 1, ring->idx); 375 hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx);
380 return aq_hw_err_from_flags(self); 376 return aq_hw_err_from_flags(self);
381} 377}
382 378
383static int hw_atl_a0_hw_ring_rx_start(struct aq_hw_s *self, 379static int hw_atl_a0_hw_ring_rx_start(struct aq_hw_s *self,
384 struct aq_ring_s *ring) 380 struct aq_ring_s *ring)
385{ 381{
386 rdm_rx_desc_en_set(self, 1, ring->idx); 382 hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx);
387 return aq_hw_err_from_flags(self); 383 return aq_hw_err_from_flags(self);
388} 384}
389 385
390static int hw_atl_a0_hw_start(struct aq_hw_s *self) 386static int hw_atl_a0_hw_start(struct aq_hw_s *self)
391{ 387{
392 tpb_tx_buff_en_set(self, 1); 388 hw_atl_tpb_tx_buff_en_set(self, 1);
393 rpb_rx_buff_en_set(self, 1); 389 hw_atl_rpb_rx_buff_en_set(self, 1);
394 return aq_hw_err_from_flags(self); 390 return aq_hw_err_from_flags(self);
395} 391}
396 392
397static int hw_atl_a0_hw_tx_ring_tail_update(struct aq_hw_s *self, 393static int hw_atl_a0_hw_tx_ring_tail_update(struct aq_hw_s *self,
398 struct aq_ring_s *ring) 394 struct aq_ring_s *ring)
399{ 395{
400 reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx); 396 hw_atl_reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
401 return 0; 397 return 0;
402} 398}
403 399
@@ -483,36 +479,37 @@ static int hw_atl_a0_hw_ring_rx_init(struct aq_hw_s *self,
483 u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa; 479 u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
484 u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32); 480 u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
485 481
486 rdm_rx_desc_en_set(self, false, aq_ring->idx); 482 hw_atl_rdm_rx_desc_en_set(self, false, aq_ring->idx);
487 483
488 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx); 484 hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
489 485
490 reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw, 486 hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
491 aq_ring->idx); 487 aq_ring->idx);
492 488
493 reg_rx_dma_desc_base_addressmswset(self, 489 hw_atl_reg_rx_dma_desc_base_addressmswset(self,
494 dma_desc_addr_msw, aq_ring->idx); 490 dma_desc_addr_msw,
491 aq_ring->idx);
495 492
496 rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx); 493 hw_atl_rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
497 494
498 rdm_rx_desc_data_buff_size_set(self, 495 hw_atl_rdm_rx_desc_data_buff_size_set(self,
499 AQ_CFG_RX_FRAME_MAX / 1024U, 496 AQ_CFG_RX_FRAME_MAX / 1024U,
500 aq_ring->idx); 497 aq_ring->idx);
501 498
502 rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx); 499 hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
503 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx); 500 hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
504 rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx); 501 hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
505 502
506 /* Rx ring set mode */ 503 /* Rx ring set mode */
507 504
508 /* Mapping interrupt vector */ 505 /* Mapping interrupt vector */
509 itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx); 506 hw_atl_itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
510 itr_irq_map_en_rx_set(self, true, aq_ring->idx); 507 hw_atl_itr_irq_map_en_rx_set(self, true, aq_ring->idx);
511 508
512 rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx); 509 hw_atl_rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
513 rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx); 510 hw_atl_rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
514 rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx); 511 hw_atl_rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
515 rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx); 512 hw_atl_rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
516 513
517 return aq_hw_err_from_flags(self); 514 return aq_hw_err_from_flags(self);
518} 515}
@@ -524,25 +521,25 @@ static int hw_atl_a0_hw_ring_tx_init(struct aq_hw_s *self,
524 u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa; 521 u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
525 u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32); 522 u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
526 523
527 reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr, 524 hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
528 aq_ring->idx); 525 aq_ring->idx);
529 526
530 reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr, 527 hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
531 aq_ring->idx); 528 aq_ring->idx);
532 529
533 tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx); 530 hw_atl_tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
534 531
535 hw_atl_a0_hw_tx_ring_tail_update(self, aq_ring); 532 hw_atl_a0_hw_tx_ring_tail_update(self, aq_ring);
536 533
537 /* Set Tx threshold */ 534 /* Set Tx threshold */
538 tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx); 535 hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
539 536
540 /* Mapping interrupt vector */ 537 /* Mapping interrupt vector */
541 itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx); 538 hw_atl_itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
542 itr_irq_map_en_tx_set(self, true, aq_ring->idx); 539 hw_atl_itr_irq_map_en_tx_set(self, true, aq_ring->idx);
543 540
544 tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx); 541 hw_atl_tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
545 tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx); 542 hw_atl_tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
546 543
547 return aq_hw_err_from_flags(self); 544 return aq_hw_err_from_flags(self);
548} 545}
@@ -563,7 +560,7 @@ static int hw_atl_a0_hw_ring_rx_fill(struct aq_hw_s *self,
563 rxd->hdr_addr = 0U; 560 rxd->hdr_addr = 0U;
564 } 561 }
565 562
566 reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx); 563 hw_atl_reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
567 564
568 return aq_hw_err_from_flags(self); 565 return aq_hw_err_from_flags(self);
569} 566}
@@ -572,13 +569,13 @@ static int hw_atl_a0_hw_ring_tx_head_update(struct aq_hw_s *self,
572 struct aq_ring_s *ring) 569 struct aq_ring_s *ring)
573{ 570{
574 int err = 0; 571 int err = 0;
575 unsigned int hw_head_ = tdm_tx_desc_head_ptr_get(self, ring->idx); 572 unsigned int hw_head = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx);
576 573
577 if (aq_utils_obj_test(&self->header.flags, AQ_HW_FLAG_ERR_UNPLUG)) { 574 if (aq_utils_obj_test(&self->flags, AQ_HW_FLAG_ERR_UNPLUG)) {
578 err = -ENXIO; 575 err = -ENXIO;
579 goto err_exit; 576 goto err_exit;
580 } 577 }
581 ring->hw_head = hw_head_; 578 ring->hw_head = hw_head;
582 err = aq_hw_err_from_flags(self); 579 err = aq_hw_err_from_flags(self);
583 580
584err_exit: 581err_exit:
@@ -602,15 +599,16 @@ static int hw_atl_a0_hw_ring_rx_receive(struct aq_hw_s *self,
602 599
603 if (!(rxd_wb->status & 0x5U)) { /* RxD is not done */ 600 if (!(rxd_wb->status & 0x5U)) { /* RxD is not done */
604 if ((1U << 4) & 601 if ((1U << 4) &
605 reg_rx_dma_desc_status_get(self, ring->idx)) { 602 hw_atl_reg_rx_dma_desc_status_get(self, ring->idx)) {
606 rdm_rx_desc_en_set(self, false, ring->idx); 603 hw_atl_rdm_rx_desc_en_set(self, false, ring->idx);
607 rdm_rx_desc_res_set(self, true, ring->idx); 604 hw_atl_rdm_rx_desc_res_set(self, true, ring->idx);
608 rdm_rx_desc_res_set(self, false, ring->idx); 605 hw_atl_rdm_rx_desc_res_set(self, false, ring->idx);
609 rdm_rx_desc_en_set(self, true, ring->idx); 606 hw_atl_rdm_rx_desc_en_set(self, true, ring->idx);
610 } 607 }
611 608
612 if (ring->hw_head || 609 if (ring->hw_head ||
613 (rdm_rx_desc_head_ptr_get(self, ring->idx) < 2U)) { 610 (hw_atl_rdm_rx_desc_head_ptr_get(self,
611 ring->idx) < 2U)) {
614 break; 612 break;
615 } else if (!(rxd_wb->status & 0x1U)) { 613 } else if (!(rxd_wb->status & 0x1U)) {
616 struct hw_atl_rxd_wb_s *rxd_wb1 = 614 struct hw_atl_rxd_wb_s *rxd_wb1 =
@@ -693,26 +691,25 @@ static int hw_atl_a0_hw_ring_rx_receive(struct aq_hw_s *self,
693 691
694static int hw_atl_a0_hw_irq_enable(struct aq_hw_s *self, u64 mask) 692static int hw_atl_a0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
695{ 693{
696 itr_irq_msk_setlsw_set(self, LODWORD(mask) | 694 hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask) |
697 (1U << HW_ATL_A0_ERR_INT)); 695 (1U << HW_ATL_A0_ERR_INT));
698 return aq_hw_err_from_flags(self); 696 return aq_hw_err_from_flags(self);
699} 697}
700 698
701static int hw_atl_a0_hw_irq_disable(struct aq_hw_s *self, u64 mask) 699static int hw_atl_a0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
702{ 700{
703 itr_irq_msk_clearlsw_set(self, LODWORD(mask)); 701 hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask));
704 itr_irq_status_clearlsw_set(self, LODWORD(mask)); 702 hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask));
705
706 if ((1U << 16) & reg_gen_irq_status_get(self))
707 703
708 atomic_inc(&PHAL_ATLANTIC_A0->dpc); 704 if ((1U << 16) & hw_atl_reg_gen_irq_status_get(self))
705 atomic_inc(&self->dpc);
709 706
710 return aq_hw_err_from_flags(self); 707 return aq_hw_err_from_flags(self);
711} 708}
712 709
713static int hw_atl_a0_hw_irq_read(struct aq_hw_s *self, u64 *mask) 710static int hw_atl_a0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
714{ 711{
715 *mask = itr_irq_statuslsw_get(self); 712 *mask = hw_atl_itr_irq_statuslsw_get(self);
716 return aq_hw_err_from_flags(self); 713 return aq_hw_err_from_flags(self);
717} 714}
718 715
@@ -723,18 +720,20 @@ static int hw_atl_a0_hw_packet_filter_set(struct aq_hw_s *self,
723{ 720{
724 unsigned int i = 0U; 721 unsigned int i = 0U;
725 722
726 rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC)); 723 hw_atl_rpfl2promiscuous_mode_en_set(self,
727 rpfl2multicast_flr_en_set(self, IS_FILTER_ENABLED(IFF_MULTICAST), 0); 724 IS_FILTER_ENABLED(IFF_PROMISC));
728 rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST)); 725 hw_atl_rpfl2multicast_flr_en_set(self,
726 IS_FILTER_ENABLED(IFF_MULTICAST), 0);
727 hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
729 728
730 self->aq_nic_cfg->is_mc_list_enabled = 729 self->aq_nic_cfg->is_mc_list_enabled =
731 IS_FILTER_ENABLED(IFF_MULTICAST); 730 IS_FILTER_ENABLED(IFF_MULTICAST);
732 731
733 for (i = HW_ATL_A0_MAC_MIN; i < HW_ATL_A0_MAC_MAX; ++i) 732 for (i = HW_ATL_A0_MAC_MIN; i < HW_ATL_A0_MAC_MAX; ++i)
734 rpfl2_uc_flr_en_set(self, 733 hw_atl_rpfl2_uc_flr_en_set(self,
735 (self->aq_nic_cfg->is_mc_list_enabled && 734 (self->aq_nic_cfg->is_mc_list_enabled &&
736 (i <= self->aq_nic_cfg->mc_list_count)) ? 735 (i <= self->aq_nic_cfg->mc_list_count)) ?
737 1U : 0U, i); 736 1U : 0U, i);
738 737
739 return aq_hw_err_from_flags(self); 738 return aq_hw_err_from_flags(self);
740} 739}
@@ -761,17 +760,19 @@ static int hw_atl_a0_hw_multicast_list_set(struct aq_hw_s *self,
761 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) | 760 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
762 (ar_mac[i][4] << 8) | ar_mac[i][5]; 761 (ar_mac[i][4] << 8) | ar_mac[i][5];
763 762
764 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC_MIN + i); 763 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC_MIN + i);
765 764
766 rpfl2unicast_dest_addresslsw_set(self, 765 hw_atl_rpfl2unicast_dest_addresslsw_set(self,
767 l, HW_ATL_A0_MAC_MIN + i); 766 l,
767 HW_ATL_A0_MAC_MIN + i);
768 768
769 rpfl2unicast_dest_addressmsw_set(self, 769 hw_atl_rpfl2unicast_dest_addressmsw_set(self,
770 h, HW_ATL_A0_MAC_MIN + i); 770 h,
771 HW_ATL_A0_MAC_MIN + i);
771 772
772 rpfl2_uc_flr_en_set(self, 773 hw_atl_rpfl2_uc_flr_en_set(self,
773 (self->aq_nic_cfg->is_mc_list_enabled), 774 (self->aq_nic_cfg->is_mc_list_enabled),
774 HW_ATL_A0_MAC_MIN + i); 775 HW_ATL_A0_MAC_MIN + i);
775 } 776 }
776 777
777 err = aq_hw_err_from_flags(self); 778 err = aq_hw_err_from_flags(self);
@@ -823,7 +824,7 @@ static int hw_atl_a0_hw_interrupt_moderation_set(struct aq_hw_s *self)
823 } 824 }
824 825
825 for (i = HW_ATL_A0_RINGS_MAX; i--;) 826 for (i = HW_ATL_A0_RINGS_MAX; i--;)
826 reg_irq_thr_set(self, itr_rx, i); 827 hw_atl_reg_irq_thr_set(self, itr_rx, i);
827 828
828 return aq_hw_err_from_flags(self); 829 return aq_hw_err_from_flags(self);
829} 830}
@@ -837,14 +838,14 @@ static int hw_atl_a0_hw_stop(struct aq_hw_s *self)
837static int hw_atl_a0_hw_ring_tx_stop(struct aq_hw_s *self, 838static int hw_atl_a0_hw_ring_tx_stop(struct aq_hw_s *self,
838 struct aq_ring_s *ring) 839 struct aq_ring_s *ring)
839{ 840{
840 tdm_tx_desc_en_set(self, 0U, ring->idx); 841 hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx);
841 return aq_hw_err_from_flags(self); 842 return aq_hw_err_from_flags(self);
842} 843}
843 844
844static int hw_atl_a0_hw_ring_rx_stop(struct aq_hw_s *self, 845static int hw_atl_a0_hw_ring_rx_stop(struct aq_hw_s *self,
845 struct aq_ring_s *ring) 846 struct aq_ring_s *ring)
846{ 847{
847 rdm_rx_desc_en_set(self, 0U, ring->idx); 848 hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx);
848 return aq_hw_err_from_flags(self); 849 return aq_hw_err_from_flags(self);
849} 850}
850 851
@@ -860,7 +861,7 @@ err_exit:
860 return err; 861 return err;
861} 862}
862 863
863static struct aq_hw_ops hw_atl_ops_ = { 864static const struct aq_hw_ops hw_atl_ops_ = {
864 .create = hw_atl_a0_create, 865 .create = hw_atl_a0_create,
865 .destroy = hw_atl_a0_destroy, 866 .destroy = hw_atl_a0_destroy,
866 .get_hw_caps = hw_atl_a0_get_hw_caps, 867 .get_hw_caps = hw_atl_a0_get_hw_caps,
@@ -903,7 +904,7 @@ static struct aq_hw_ops hw_atl_ops_ = {
903 .hw_get_fw_version = hw_atl_utils_get_fw_version, 904 .hw_get_fw_version = hw_atl_utils_get_fw_version,
904}; 905};
905 906
906struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev) 907const struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev)
907{ 908{
908 bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA); 909 bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
909 bool is_did_ok = ((pdev->device == HW_ATL_DEVICE_ID_0001) || 910 bool is_did_ok = ((pdev->device == HW_ATL_DEVICE_ID_0001) ||
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.h
index 6e1d527954c9..4fdd51b67097 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.h
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.h
@@ -29,6 +29,6 @@
29 29
30#endif 30#endif
31 31
32struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev); 32const struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev);
33 33
34#endif /* HW_ATL_A0_H */ 34#endif /* HW_ATL_A0_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h
index 0592a0330cf0..7a71330252bd 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h
@@ -88,37 +88,6 @@
88 88
89#define HW_ATL_A0_FW_VER_EXPECTED 0x01050006U 89#define HW_ATL_A0_FW_VER_EXPECTED 0x01050006U
90 90
91/* Hardware tx descriptor */
92struct __packed hw_atl_txd_s {
93 u64 buf_addr;
94 u32 ctl;
95 u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */
96};
97
98/* Hardware tx context descriptor */
99struct __packed hw_atl_txc_s {
100 u32 rsvd;
101 u32 len;
102 u32 ctl;
103 u32 len2;
104};
105
106/* Hardware rx descriptor */
107struct __packed hw_atl_rxd_s {
108 u64 buf_addr;
109 u64 hdr_addr;
110};
111
112/* Hardware rx descriptor writeback */
113struct __packed hw_atl_rxd_wb_s {
114 u32 type;
115 u32 rss_hash;
116 u16 status;
117 u16 pkt_len;
118 u16 next_desc_ptr;
119 u16 vlan;
120};
121
122/* HW layer capabilities */ 91/* HW layer capabilities */
123static struct aq_hw_caps_s hw_atl_a0_hw_caps_ = { 92static struct aq_hw_caps_s hw_atl_a0_hw_caps_ = {
124 .ports = 1U, 93 .ports = 1U,
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
index e4a22ce7bf09..0b090161ed79 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
@@ -12,6 +12,7 @@
12#include "../aq_hw.h" 12#include "../aq_hw.h"
13#include "../aq_hw_utils.h" 13#include "../aq_hw_utils.h"
14#include "../aq_ring.h" 14#include "../aq_ring.h"
15#include "../aq_nic.h"
15#include "hw_atl_b0.h" 16#include "hw_atl_b0.h"
16#include "hw_atl_utils.h" 17#include "hw_atl_utils.h"
17#include "hw_atl_llh.h" 18#include "hw_atl_llh.h"
@@ -37,21 +38,20 @@ static int hw_atl_b0_get_hw_caps(struct aq_hw_s *self,
37} 38}
38 39
39static struct aq_hw_s *hw_atl_b0_create(struct aq_pci_func_s *aq_pci_func, 40static struct aq_hw_s *hw_atl_b0_create(struct aq_pci_func_s *aq_pci_func,
40 unsigned int port, 41 unsigned int port)
41 struct aq_hw_ops *ops)
42{ 42{
43 struct hw_atl_s *self = NULL; 43 struct aq_hw_s *self = NULL;
44 44
45 self = kzalloc(sizeof(*self), GFP_KERNEL); 45 self = kzalloc(sizeof(*self), GFP_KERNEL);
46 if (!self) 46 if (!self)
47 goto err_exit; 47 goto err_exit;
48 48
49 self->base.aq_pci_func = aq_pci_func; 49 self->aq_pci_func = aq_pci_func;
50 50
51 self->base.not_ff_addr = 0x10U; 51 self->not_ff_addr = 0x10U;
52 52
53err_exit: 53err_exit:
54 return (struct aq_hw_s *)self; 54 return self;
55} 55}
56 56
57static void hw_atl_b0_destroy(struct aq_hw_s *self) 57static void hw_atl_b0_destroy(struct aq_hw_s *self)
@@ -63,24 +63,24 @@ static int hw_atl_b0_hw_reset(struct aq_hw_s *self)
63{ 63{
64 int err = 0; 64 int err = 0;
65 65
66 glb_glb_reg_res_dis_set(self, 1U); 66 hw_atl_glb_glb_reg_res_dis_set(self, 1U);
67 pci_pci_reg_res_dis_set(self, 0U); 67 hw_atl_pci_pci_reg_res_dis_set(self, 0U);
68 rx_rx_reg_res_dis_set(self, 0U); 68 hw_atl_rx_rx_reg_res_dis_set(self, 0U);
69 tx_tx_reg_res_dis_set(self, 0U); 69 hw_atl_tx_tx_reg_res_dis_set(self, 0U);
70 70
71 HW_ATL_FLUSH(); 71 HW_ATL_FLUSH();
72 glb_soft_res_set(self, 1); 72 hw_atl_glb_soft_res_set(self, 1);
73 73
74 /* check 10 times by 1ms */ 74 /* check 10 times by 1ms */
75 AQ_HW_WAIT_FOR(glb_soft_res_get(self) == 0, 1000U, 10U); 75 AQ_HW_WAIT_FOR(hw_atl_glb_soft_res_get(self) == 0, 1000U, 10U);
76 if (err < 0) 76 if (err < 0)
77 goto err_exit; 77 goto err_exit;
78 78
79 itr_irq_reg_res_dis_set(self, 0U); 79 hw_atl_itr_irq_reg_res_dis_set(self, 0U);
80 itr_res_irq_set(self, 1U); 80 hw_atl_itr_res_irq_set(self, 1U);
81 81
82 /* check 10 times by 1ms */ 82 /* check 10 times by 1ms */
83 AQ_HW_WAIT_FOR(itr_res_irq_get(self) == 0, 1000U, 10U); 83 AQ_HW_WAIT_FOR(hw_atl_itr_res_irq_get(self) == 0, 1000U, 10U);
84 if (err < 0) 84 if (err < 0)
85 goto err_exit; 85 goto err_exit;
86 86
@@ -100,51 +100,53 @@ static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
100 bool is_rx_flow_control = false; 100 bool is_rx_flow_control = false;
101 101
102 /* TPS Descriptor rate init */ 102 /* TPS Descriptor rate init */
103 tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U); 103 hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
104 tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA); 104 hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
105 105
106 /* TPS VM init */ 106 /* TPS VM init */
107 tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U); 107 hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
108 108
109 /* TPS TC credits init */ 109 /* TPS TC credits init */
110 tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U); 110 hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
111 tps_tx_pkt_shed_data_arb_mode_set(self, 0U); 111 hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
112 112
113 tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U); 113 hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
114 tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U); 114 hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
115 tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U); 115 hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
116 tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U); 116 hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
117 117
118 /* Tx buf size */ 118 /* Tx buf size */
119 buff_size = HW_ATL_B0_TXBUF_MAX; 119 buff_size = HW_ATL_B0_TXBUF_MAX;
120 120
121 tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc); 121 hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
122 tpb_tx_buff_hi_threshold_per_tc_set(self, 122 hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self,
123 (buff_size * (1024 / 32U) * 66U) / 123 (buff_size *
124 100U, tc); 124 (1024 / 32U) * 66U) /
125 tpb_tx_buff_lo_threshold_per_tc_set(self, 125 100U, tc);
126 (buff_size * (1024 / 32U) * 50U) / 126 hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self,
127 100U, tc); 127 (buff_size *
128 (1024 / 32U) * 50U) /
129 100U, tc);
128 130
129 /* QoS Rx buf size per TC */ 131 /* QoS Rx buf size per TC */
130 tc = 0; 132 tc = 0;
131 is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control); 133 is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
132 buff_size = HW_ATL_B0_RXBUF_MAX; 134 buff_size = HW_ATL_B0_RXBUF_MAX;
133 135
134 rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc); 136 hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
135 rpb_rx_buff_hi_threshold_per_tc_set(self, 137 hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self,
136 (buff_size * 138 (buff_size *
137 (1024U / 32U) * 66U) / 139 (1024U / 32U) * 66U) /
138 100U, tc); 140 100U, tc);
139 rpb_rx_buff_lo_threshold_per_tc_set(self, 141 hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self,
140 (buff_size * 142 (buff_size *
141 (1024U / 32U) * 50U) / 143 (1024U / 32U) * 50U) /
142 100U, tc); 144 100U, tc);
143 rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc); 145 hw_atl_rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
144 146
145 /* QoS 802.1p priority -> TC mapping */ 147 /* QoS 802.1p priority -> TC mapping */
146 for (i_priority = 8U; i_priority--;) 148 for (i_priority = 8U; i_priority--;)
147 rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U); 149 hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
148 150
149 return aq_hw_err_from_flags(self); 151 return aq_hw_err_from_flags(self);
150} 152}
@@ -152,20 +154,19 @@ static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
152static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self, 154static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
153 struct aq_rss_parameters *rss_params) 155 struct aq_rss_parameters *rss_params)
154{ 156{
155 struct aq_nic_cfg_s *cfg = NULL; 157 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
156 int err = 0; 158 int err = 0;
157 unsigned int i = 0U; 159 unsigned int i = 0U;
158 unsigned int addr = 0U; 160 unsigned int addr = 0U;
159 161
160 cfg = self->aq_nic_cfg;
161
162 for (i = 10, addr = 0U; i--; ++addr) { 162 for (i = 10, addr = 0U; i--; ++addr) {
163 u32 key_data = cfg->is_rss ? 163 u32 key_data = cfg->is_rss ?
164 __swab32(rss_params->hash_secret_key[i]) : 0U; 164 __swab32(rss_params->hash_secret_key[i]) : 0U;
165 rpf_rss_key_wr_data_set(self, key_data); 165 hw_atl_rpf_rss_key_wr_data_set(self, key_data);
166 rpf_rss_key_addr_set(self, addr); 166 hw_atl_rpf_rss_key_addr_set(self, addr);
167 rpf_rss_key_wr_en_set(self, 1U); 167 hw_atl_rpf_rss_key_wr_en_set(self, 1U);
168 AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self) == 0, 1000U, 10U); 168 AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,
169 1000U, 10U);
169 if (err < 0) 170 if (err < 0)
170 goto err_exit; 171 goto err_exit;
171 } 172 }
@@ -194,11 +195,12 @@ static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
194 ((i * 3U) & 0xFU)); 195 ((i * 3U) & 0xFU));
195 } 196 }
196 197
197 for (i = AQ_DIMOF(bitary); i--;) { 198 for (i = ARRAY_SIZE(bitary); i--;) {
198 rpf_rss_redir_tbl_wr_data_set(self, bitary[i]); 199 hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
199 rpf_rss_redir_tbl_addr_set(self, i); 200 hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
200 rpf_rss_redir_wr_en_set(self, 1U); 201 hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
201 AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self) == 0, 1000U, 10U); 202 AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,
203 1000U, 10U);
202 if (err < 0) 204 if (err < 0)
203 goto err_exit; 205 goto err_exit;
204 } 206 }
@@ -215,15 +217,15 @@ static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
215 unsigned int i; 217 unsigned int i;
216 218
217 /* TX checksums offloads*/ 219 /* TX checksums offloads*/
218 tpo_ipv4header_crc_offload_en_set(self, 1); 220 hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1);
219 tpo_tcp_udp_crc_offload_en_set(self, 1); 221 hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1);
220 222
221 /* RX checksums offloads*/ 223 /* RX checksums offloads*/
222 rpo_ipv4header_crc_offload_en_set(self, 1); 224 hw_atl_rpo_ipv4header_crc_offload_en_set(self, 1);
223 rpo_tcp_udp_crc_offload_en_set(self, 1); 225 hw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1);
224 226
225 /* LSO offloads*/ 227 /* LSO offloads*/
226 tdm_large_send_offload_en_set(self, 0xFFFFFFFFU); 228 hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
227 229
228/* LRO offloads */ 230/* LRO offloads */
229 { 231 {
@@ -232,43 +234,44 @@ static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
232 ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0)); 234 ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0));
233 235
234 for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++) 236 for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++)
235 rpo_lro_max_num_of_descriptors_set(self, val, i); 237 hw_atl_rpo_lro_max_num_of_descriptors_set(self, val, i);
236 238
237 rpo_lro_time_base_divider_set(self, 0x61AU); 239 hw_atl_rpo_lro_time_base_divider_set(self, 0x61AU);
238 rpo_lro_inactive_interval_set(self, 0); 240 hw_atl_rpo_lro_inactive_interval_set(self, 0);
239 rpo_lro_max_coalescing_interval_set(self, 2); 241 hw_atl_rpo_lro_max_coalescing_interval_set(self, 2);
240 242
241 rpo_lro_qsessions_lim_set(self, 1U); 243 hw_atl_rpo_lro_qsessions_lim_set(self, 1U);
242 244
243 rpo_lro_total_desc_lim_set(self, 2U); 245 hw_atl_rpo_lro_total_desc_lim_set(self, 2U);
244 246
245 rpo_lro_patch_optimization_en_set(self, 0U); 247 hw_atl_rpo_lro_patch_optimization_en_set(self, 0U);
246 248
247 rpo_lro_min_pay_of_first_pkt_set(self, 10U); 249 hw_atl_rpo_lro_min_pay_of_first_pkt_set(self, 10U);
248 250
249 rpo_lro_pkt_lim_set(self, 1U); 251 hw_atl_rpo_lro_pkt_lim_set(self, 1U);
250 252
251 rpo_lro_en_set(self, aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U); 253 hw_atl_rpo_lro_en_set(self,
254 aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);
252 } 255 }
253 return aq_hw_err_from_flags(self); 256 return aq_hw_err_from_flags(self);
254} 257}
255 258
256static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self) 259static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)
257{ 260{
258 thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U); 261 hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
259 thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U); 262 hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
260 thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU); 263 hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
261 264
262 /* Tx interrupts */ 265 /* Tx interrupts */
263 tdm_tx_desc_wr_wb_irq_en_set(self, 1U); 266 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
264 267
265 /* misc */ 268 /* misc */
266 aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ? 269 aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
267 0x00010000U : 0x00000000U); 270 0x00010000U : 0x00000000U);
268 tdm_tx_dca_en_set(self, 0U); 271 hw_atl_tdm_tx_dca_en_set(self, 0U);
269 tdm_tx_dca_mode_set(self, 0U); 272 hw_atl_tdm_tx_dca_mode_set(self, 0U);
270 273
271 tpb_tx_path_scp_ins_en_set(self, 1U); 274 hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U);
272 275
273 return aq_hw_err_from_flags(self); 276 return aq_hw_err_from_flags(self);
274} 277}
@@ -279,55 +282,55 @@ static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self)
279 int i; 282 int i;
280 283
281 /* Rx TC/RSS number config */ 284 /* Rx TC/RSS number config */
282 rpb_rpf_rx_traf_class_mode_set(self, 1U); 285 hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U);
283 286
284 /* Rx flow control */ 287 /* Rx flow control */
285 rpb_rx_flow_ctl_mode_set(self, 1U); 288 hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);
286 289
287 /* RSS Ring selection */ 290 /* RSS Ring selection */
288 reg_rx_flr_rss_control1set(self, cfg->is_rss ? 291 hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?
289 0xB3333333U : 0x00000000U); 292 0xB3333333U : 0x00000000U);
290 293
291 /* Multicast filters */ 294 /* Multicast filters */
292 for (i = HW_ATL_B0_MAC_MAX; i--;) { 295 for (i = HW_ATL_B0_MAC_MAX; i--;) {
293 rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i); 296 hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
294 rpfl2unicast_flr_act_set(self, 1U, i); 297 hw_atl_rpfl2unicast_flr_act_set(self, 1U, i);
295 } 298 }
296 299
297 reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U); 300 hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
298 reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U); 301 hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
299 302
300 /* Vlan filters */ 303 /* Vlan filters */
301 rpf_vlan_outer_etht_set(self, 0x88A8U); 304 hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U);
302 rpf_vlan_inner_etht_set(self, 0x8100U); 305 hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U);
303 306
304 if (cfg->vlan_id) { 307 if (cfg->vlan_id) {
305 rpf_vlan_flr_act_set(self, 1U, 0U); 308 hw_atl_rpf_vlan_flr_act_set(self, 1U, 0U);
306 rpf_vlan_id_flr_set(self, 0U, 0U); 309 hw_atl_rpf_vlan_id_flr_set(self, 0U, 0U);
307 rpf_vlan_flr_en_set(self, 0U, 0U); 310 hw_atl_rpf_vlan_flr_en_set(self, 0U, 0U);
308 311
309 rpf_vlan_accept_untagged_packets_set(self, 1U); 312 hw_atl_rpf_vlan_accept_untagged_packets_set(self, 1U);
310 rpf_vlan_untagged_act_set(self, 1U); 313 hw_atl_rpf_vlan_untagged_act_set(self, 1U);
311 314
312 rpf_vlan_flr_act_set(self, 1U, 1U); 315 hw_atl_rpf_vlan_flr_act_set(self, 1U, 1U);
313 rpf_vlan_id_flr_set(self, cfg->vlan_id, 0U); 316 hw_atl_rpf_vlan_id_flr_set(self, cfg->vlan_id, 0U);
314 rpf_vlan_flr_en_set(self, 1U, 1U); 317 hw_atl_rpf_vlan_flr_en_set(self, 1U, 1U);
315 } else { 318 } else {
316 rpf_vlan_prom_mode_en_set(self, 1); 319 hw_atl_rpf_vlan_prom_mode_en_set(self, 1);
317 } 320 }
318 321
319 /* Rx Interrupts */ 322 /* Rx Interrupts */
320 rdm_rx_desc_wr_wb_irq_en_set(self, 1U); 323 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
321 324
322 /* misc */ 325 /* misc */
323 aq_hw_write_reg(self, 0x00005040U, 326 aq_hw_write_reg(self, 0x00005040U,
324 IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U); 327 IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U);
325 328
326 rpfl2broadcast_flr_act_set(self, 1U); 329 hw_atl_rpfl2broadcast_flr_act_set(self, 1U);
327 rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U)); 330 hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
328 331
329 rdm_rx_dca_en_set(self, 0U); 332 hw_atl_rdm_rx_dca_en_set(self, 0U);
330 rdm_rx_dca_mode_set(self, 0U); 333 hw_atl_rdm_rx_dca_mode_set(self, 0U);
331 334
332 return aq_hw_err_from_flags(self); 335 return aq_hw_err_from_flags(self);
333} 336}
@@ -346,10 +349,10 @@ static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
346 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 349 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
347 (mac_addr[4] << 8) | mac_addr[5]; 350 (mac_addr[4] << 8) | mac_addr[5];
348 351
349 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC); 352 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC);
350 rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC); 353 hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC);
351 rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC); 354 hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC);
352 rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC); 355 hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC);
353 356
354 err = aq_hw_err_from_flags(self); 357 err = aq_hw_err_from_flags(self);
355 358
@@ -357,9 +360,7 @@ err_exit:
357 return err; 360 return err;
358} 361}
359 362
360static int hw_atl_b0_hw_init(struct aq_hw_s *self, 363static int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
361 struct aq_nic_cfg_s *aq_nic_cfg,
362 u8 *mac_addr)
363{ 364{
364 static u32 aq_hw_atl_igcr_table_[4][2] = { 365 static u32 aq_hw_atl_igcr_table_[4][2] = {
365 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */ 366 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
@@ -371,10 +372,7 @@ static int hw_atl_b0_hw_init(struct aq_hw_s *self,
371 int err = 0; 372 int err = 0;
372 u32 val; 373 u32 val;
373 374
374 self->aq_nic_cfg = aq_nic_cfg; 375 struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg;
375
376 hw_atl_utils_hw_chip_features_init(self,
377 &PHAL_ATLANTIC_B0->chip_features);
378 376
379 hw_atl_b0_hw_init_tx_path(self); 377 hw_atl_b0_hw_init_tx_path(self);
380 hw_atl_b0_hw_init_rx_path(self); 378 hw_atl_b0_hw_init_rx_path(self);
@@ -388,14 +386,15 @@ static int hw_atl_b0_hw_init(struct aq_hw_s *self,
388 hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss); 386 hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
389 387
390 /* Force limit MRRS on RDM/TDM to 2K */ 388 /* Force limit MRRS on RDM/TDM to 2K */
391 val = aq_hw_read_reg(self, pci_reg_control6_adr); 389 val = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR);
392 aq_hw_write_reg(self, pci_reg_control6_adr, (val & ~0x707) | 0x404); 390 aq_hw_write_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR,
391 (val & ~0x707) | 0x404);
393 392
394 /* TX DMA total request limit. B0 hardware is not capable to 393 /* TX DMA total request limit. B0 hardware is not capable to
395 * handle more than (8K-MRRS) incoming DMA data. 394 * handle more than (8K-MRRS) incoming DMA data.
396 * Value 24 in 256byte units 395 * Value 24 in 256byte units
397 */ 396 */
398 aq_hw_write_reg(self, tx_dma_total_req_limit_adr, 24); 397 aq_hw_write_reg(self, HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24);
399 398
400 /* Reset link status and read out initial hardware counters */ 399 /* Reset link status and read out initial hardware counters */
401 self->aq_link_status.mbps = 0; 400 self->aq_link_status.mbps = 0;
@@ -406,16 +405,16 @@ static int hw_atl_b0_hw_init(struct aq_hw_s *self,
406 goto err_exit; 405 goto err_exit;
407 406
408 /* Interrupts */ 407 /* Interrupts */
409 reg_irq_glb_ctl_set(self, 408 hw_atl_reg_irq_glb_ctl_set(self,
410 aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type] 409 aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
411 [(aq_nic_cfg->vecs > 1U) ? 410 [(aq_nic_cfg->vecs > 1U) ?
412 1 : 0]); 411 1 : 0]);
413 412
414 itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask); 413 hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
415 414
416 /* Interrupts */ 415 /* Interrupts */
417 reg_gen_irq_map_set(self, 416 hw_atl_reg_gen_irq_map_set(self,
418 ((HW_ATL_B0_ERR_INT << 0x18) | (1U << 0x1F)) | 417 ((HW_ATL_B0_ERR_INT << 0x18) | (1U << 0x1F)) |
419 ((HW_ATL_B0_ERR_INT << 0x10) | (1U << 0x17)), 0U); 418 ((HW_ATL_B0_ERR_INT << 0x10) | (1U << 0x17)), 0U);
420 419
421 hw_atl_b0_hw_offload_set(self, aq_nic_cfg); 420 hw_atl_b0_hw_offload_set(self, aq_nic_cfg);
@@ -427,28 +426,28 @@ err_exit:
427static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, 426static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self,
428 struct aq_ring_s *ring) 427 struct aq_ring_s *ring)
429{ 428{
430 tdm_tx_desc_en_set(self, 1, ring->idx); 429 hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx);
431 return aq_hw_err_from_flags(self); 430 return aq_hw_err_from_flags(self);
432} 431}
433 432
434static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, 433static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self,
435 struct aq_ring_s *ring) 434 struct aq_ring_s *ring)
436{ 435{
437 rdm_rx_desc_en_set(self, 1, ring->idx); 436 hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx);
438 return aq_hw_err_from_flags(self); 437 return aq_hw_err_from_flags(self);
439} 438}
440 439
441static int hw_atl_b0_hw_start(struct aq_hw_s *self) 440static int hw_atl_b0_hw_start(struct aq_hw_s *self)
442{ 441{
443 tpb_tx_buff_en_set(self, 1); 442 hw_atl_tpb_tx_buff_en_set(self, 1);
444 rpb_rx_buff_en_set(self, 1); 443 hw_atl_rpb_rx_buff_en_set(self, 1);
445 return aq_hw_err_from_flags(self); 444 return aq_hw_err_from_flags(self);
446} 445}
447 446
448static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self, 447static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self,
449 struct aq_ring_s *ring) 448 struct aq_ring_s *ring)
450{ 449{
451 reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx); 450 hw_atl_reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
452 return 0; 451 return 0;
453} 452}
454 453
@@ -534,36 +533,36 @@ static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self,
534 u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa; 533 u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
535 u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32); 534 u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
536 535
537 rdm_rx_desc_en_set(self, false, aq_ring->idx); 536 hw_atl_rdm_rx_desc_en_set(self, false, aq_ring->idx);
538 537
539 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx); 538 hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
540 539
541 reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw, 540 hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
542 aq_ring->idx); 541 aq_ring->idx);
543 542
544 reg_rx_dma_desc_base_addressmswset(self, 543 hw_atl_reg_rx_dma_desc_base_addressmswset(self,
545 dma_desc_addr_msw, aq_ring->idx); 544 dma_desc_addr_msw, aq_ring->idx);
546 545
547 rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx); 546 hw_atl_rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
548 547
549 rdm_rx_desc_data_buff_size_set(self, 548 hw_atl_rdm_rx_desc_data_buff_size_set(self,
550 AQ_CFG_RX_FRAME_MAX / 1024U, 549 AQ_CFG_RX_FRAME_MAX / 1024U,
551 aq_ring->idx); 550 aq_ring->idx);
552 551
553 rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx); 552 hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
554 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx); 553 hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
555 rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx); 554 hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
556 555
557 /* Rx ring set mode */ 556 /* Rx ring set mode */
558 557
559 /* Mapping interrupt vector */ 558 /* Mapping interrupt vector */
560 itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx); 559 hw_atl_itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
561 itr_irq_map_en_rx_set(self, true, aq_ring->idx); 560 hw_atl_itr_irq_map_en_rx_set(self, true, aq_ring->idx);
562 561
563 rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx); 562 hw_atl_rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
564 rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx); 563 hw_atl_rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
565 rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx); 564 hw_atl_rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
566 rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx); 565 hw_atl_rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
567 566
568 return aq_hw_err_from_flags(self); 567 return aq_hw_err_from_flags(self);
569} 568}
@@ -575,25 +574,25 @@ static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self,
575 u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa; 574 u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
576 u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32); 575 u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
577 576
578 reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr, 577 hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
579 aq_ring->idx); 578 aq_ring->idx);
580 579
581 reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr, 580 hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
582 aq_ring->idx); 581 aq_ring->idx);
583 582
584 tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx); 583 hw_atl_tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
585 584
586 hw_atl_b0_hw_tx_ring_tail_update(self, aq_ring); 585 hw_atl_b0_hw_tx_ring_tail_update(self, aq_ring);
587 586
588 /* Set Tx threshold */ 587 /* Set Tx threshold */
589 tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx); 588 hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
590 589
591 /* Mapping interrupt vector */ 590 /* Mapping interrupt vector */
592 itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx); 591 hw_atl_itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
593 itr_irq_map_en_tx_set(self, true, aq_ring->idx); 592 hw_atl_itr_irq_map_en_tx_set(self, true, aq_ring->idx);
594 593
595 tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx); 594 hw_atl_tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
596 tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx); 595 hw_atl_tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
597 596
598 return aq_hw_err_from_flags(self); 597 return aq_hw_err_from_flags(self);
599} 598}
@@ -614,7 +613,7 @@ static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self,
614 rxd->hdr_addr = 0U; 613 rxd->hdr_addr = 0U;
615 } 614 }
616 615
617 reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx); 616 hw_atl_reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
618 617
619 return aq_hw_err_from_flags(self); 618 return aq_hw_err_from_flags(self);
620} 619}
@@ -623,9 +622,9 @@ static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self,
623 struct aq_ring_s *ring) 622 struct aq_ring_s *ring)
624{ 623{
625 int err = 0; 624 int err = 0;
626 unsigned int hw_head_ = tdm_tx_desc_head_ptr_get(self, ring->idx); 625 unsigned int hw_head_ = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx);
627 626
628 if (aq_utils_obj_test(&self->header.flags, AQ_HW_FLAG_ERR_UNPLUG)) { 627 if (aq_utils_obj_test(&self->flags, AQ_HW_FLAG_ERR_UNPLUG)) {
629 err = -ENXIO; 628 err = -ENXIO;
630 goto err_exit; 629 goto err_exit;
631 } 630 }
@@ -728,22 +727,22 @@ static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self,
728 727
729static int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask) 728static int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
730{ 729{
731 itr_irq_msk_setlsw_set(self, LODWORD(mask)); 730 hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask));
732 return aq_hw_err_from_flags(self); 731 return aq_hw_err_from_flags(self);
733} 732}
734 733
735static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask) 734static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
736{ 735{
737 itr_irq_msk_clearlsw_set(self, LODWORD(mask)); 736 hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask));
738 itr_irq_status_clearlsw_set(self, LODWORD(mask)); 737 hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask));
739 738
740 atomic_inc(&PHAL_ATLANTIC_B0->dpc); 739 atomic_inc(&self->dpc);
741 return aq_hw_err_from_flags(self); 740 return aq_hw_err_from_flags(self);
742} 741}
743 742
744static int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask) 743static int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
745{ 744{
746 *mask = itr_irq_statuslsw_get(self); 745 *mask = hw_atl_itr_irq_statuslsw_get(self);
747 return aq_hw_err_from_flags(self); 746 return aq_hw_err_from_flags(self);
748} 747}
749 748
@@ -754,20 +753,20 @@ static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self,
754{ 753{
755 unsigned int i = 0U; 754 unsigned int i = 0U;
756 755
757 rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC)); 756 hw_atl_rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
758 rpfl2multicast_flr_en_set(self, 757 hw_atl_rpfl2multicast_flr_en_set(self,
759 IS_FILTER_ENABLED(IFF_MULTICAST), 0); 758 IS_FILTER_ENABLED(IFF_MULTICAST), 0);
760 759
761 rpfl2_accept_all_mc_packets_set(self, 760 hw_atl_rpfl2_accept_all_mc_packets_set(self,
762 IS_FILTER_ENABLED(IFF_ALLMULTI)); 761 IS_FILTER_ENABLED(IFF_ALLMULTI));
763 762
764 rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST)); 763 hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
765 764
766 self->aq_nic_cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST); 765 self->aq_nic_cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST);
767 766
768 for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i) 767 for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i)
769 rpfl2_uc_flr_en_set(self, 768 hw_atl_rpfl2_uc_flr_en_set(self,
770 (self->aq_nic_cfg->is_mc_list_enabled && 769 (self->aq_nic_cfg->is_mc_list_enabled &&
771 (i <= self->aq_nic_cfg->mc_list_count)) ? 770 (i <= self->aq_nic_cfg->mc_list_count)) ?
772 1U : 0U, i); 771 1U : 0U, i);
773 772
@@ -796,16 +795,16 @@ static int hw_atl_b0_hw_multicast_list_set(struct aq_hw_s *self,
796 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) | 795 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
797 (ar_mac[i][4] << 8) | ar_mac[i][5]; 796 (ar_mac[i][4] << 8) | ar_mac[i][5];
798 797
799 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i); 798 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i);
800 799
801 rpfl2unicast_dest_addresslsw_set(self, 800 hw_atl_rpfl2unicast_dest_addresslsw_set(self,
802 l, HW_ATL_B0_MAC_MIN + i); 801 l, HW_ATL_B0_MAC_MIN + i);
803 802
804 rpfl2unicast_dest_addressmsw_set(self, 803 hw_atl_rpfl2unicast_dest_addressmsw_set(self,
805 h, HW_ATL_B0_MAC_MIN + i); 804 h, HW_ATL_B0_MAC_MIN + i);
806 805
807 rpfl2_uc_flr_en_set(self, 806 hw_atl_rpfl2_uc_flr_en_set(self,
808 (self->aq_nic_cfg->is_mc_list_enabled), 807 (self->aq_nic_cfg->is_mc_list_enabled),
809 HW_ATL_B0_MAC_MIN + i); 808 HW_ATL_B0_MAC_MIN + i);
810 } 809 }
811 810
@@ -824,10 +823,10 @@ static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
824 switch (self->aq_nic_cfg->itr) { 823 switch (self->aq_nic_cfg->itr) {
825 case AQ_CFG_INTERRUPT_MODERATION_ON: 824 case AQ_CFG_INTERRUPT_MODERATION_ON:
826 case AQ_CFG_INTERRUPT_MODERATION_AUTO: 825 case AQ_CFG_INTERRUPT_MODERATION_AUTO:
827 tdm_tx_desc_wr_wb_irq_en_set(self, 0U); 826 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U);
828 tdm_tdm_intr_moder_en_set(self, 1U); 827 hw_atl_tdm_tdm_intr_moder_en_set(self, 1U);
829 rdm_rx_desc_wr_wb_irq_en_set(self, 0U); 828 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U);
830 rdm_rdm_intr_moder_en_set(self, 1U); 829 hw_atl_rdm_rdm_intr_moder_en_set(self, 1U);
831 830
832 if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) { 831 if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) {
833 /* HW timers are in 2us units */ 832 /* HW timers are in 2us units */
@@ -887,18 +886,18 @@ static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
887 } 886 }
888 break; 887 break;
889 case AQ_CFG_INTERRUPT_MODERATION_OFF: 888 case AQ_CFG_INTERRUPT_MODERATION_OFF:
890 tdm_tx_desc_wr_wb_irq_en_set(self, 1U); 889 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
891 tdm_tdm_intr_moder_en_set(self, 0U); 890 hw_atl_tdm_tdm_intr_moder_en_set(self, 0U);
892 rdm_rx_desc_wr_wb_irq_en_set(self, 1U); 891 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
893 rdm_rdm_intr_moder_en_set(self, 0U); 892 hw_atl_rdm_rdm_intr_moder_en_set(self, 0U);
894 itr_tx = 0U; 893 itr_tx = 0U;
895 itr_rx = 0U; 894 itr_rx = 0U;
896 break; 895 break;
897 } 896 }
898 897
899 for (i = HW_ATL_B0_RINGS_MAX; i--;) { 898 for (i = HW_ATL_B0_RINGS_MAX; i--;) {
900 reg_tx_intr_moder_ctrl_set(self, itr_tx, i); 899 hw_atl_reg_tx_intr_moder_ctrl_set(self, itr_tx, i);
901 reg_rx_intr_moder_ctrl_set(self, itr_rx, i); 900 hw_atl_reg_rx_intr_moder_ctrl_set(self, itr_rx, i);
902 } 901 }
903 902
904 return aq_hw_err_from_flags(self); 903 return aq_hw_err_from_flags(self);
@@ -913,14 +912,14 @@ static int hw_atl_b0_hw_stop(struct aq_hw_s *self)
913static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, 912static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self,
914 struct aq_ring_s *ring) 913 struct aq_ring_s *ring)
915{ 914{
916 tdm_tx_desc_en_set(self, 0U, ring->idx); 915 hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx);
917 return aq_hw_err_from_flags(self); 916 return aq_hw_err_from_flags(self);
918} 917}
919 918
920static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, 919static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self,
921 struct aq_ring_s *ring) 920 struct aq_ring_s *ring)
922{ 921{
923 rdm_rx_desc_en_set(self, 0U, ring->idx); 922 hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx);
924 return aq_hw_err_from_flags(self); 923 return aq_hw_err_from_flags(self);
925} 924}
926 925
@@ -936,7 +935,7 @@ err_exit:
936 return err; 935 return err;
937} 936}
938 937
939static struct aq_hw_ops hw_atl_ops_ = { 938static const struct aq_hw_ops hw_atl_ops_ = {
940 .create = hw_atl_b0_create, 939 .create = hw_atl_b0_create,
941 .destroy = hw_atl_b0_destroy, 940 .destroy = hw_atl_b0_destroy,
942 .get_hw_caps = hw_atl_b0_get_hw_caps, 941 .get_hw_caps = hw_atl_b0_get_hw_caps,
@@ -979,7 +978,7 @@ static struct aq_hw_ops hw_atl_ops_ = {
979 .hw_get_fw_version = hw_atl_utils_get_fw_version, 978 .hw_get_fw_version = hw_atl_utils_get_fw_version,
980}; 979};
981 980
982struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev) 981const struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev)
983{ 982{
984 bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA); 983 bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
985 bool is_did_ok = ((pdev->device == HW_ATL_DEVICE_ID_0001) || 984 bool is_did_ok = ((pdev->device == HW_ATL_DEVICE_ID_0001) ||
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h
index a1e1bce6c1f3..3e10969c1df5 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h
@@ -29,6 +29,6 @@
29 29
30#endif 30#endif
31 31
32struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev); 32const struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev);
33 33
34#endif /* HW_ATL_B0_H */ 34#endif /* HW_ATL_B0_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h
index 9aa2c6edfca2..740ff73c6d67 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h
@@ -142,37 +142,6 @@
142#define HW_ATL_INTR_MODER_MAX 0x1FF 142#define HW_ATL_INTR_MODER_MAX 0x1FF
143#define HW_ATL_INTR_MODER_MIN 0xFF 143#define HW_ATL_INTR_MODER_MIN 0xFF
144 144
145/* Hardware tx descriptor */
146struct __packed hw_atl_txd_s {
147 u64 buf_addr;
148 u32 ctl;
149 u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */
150};
151
152/* Hardware tx context descriptor */
153struct __packed hw_atl_txc_s {
154 u32 rsvd;
155 u32 len;
156 u32 ctl;
157 u32 len2;
158};
159
160/* Hardware rx descriptor */
161struct __packed hw_atl_rxd_s {
162 u64 buf_addr;
163 u64 hdr_addr;
164};
165
166/* Hardware rx descriptor writeback */
167struct __packed hw_atl_rxd_wb_s {
168 u32 type;
169 u32 rss_hash;
170 u16 status;
171 u16 pkt_len;
172 u16 next_desc_ptr;
173 u16 vlan;
174};
175
176/* HW layer capabilities */ 145/* HW layer capabilities */
177static struct aq_hw_caps_s hw_atl_b0_hw_caps_ = { 146static struct aq_hw_caps_s hw_atl_b0_hw_caps_ = {
178 .ports = 1U, 147 .ports = 1U,
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c
index 3de651afa8c7..10ba035dadb1 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c
@@ -16,111 +16,115 @@
16#include "../aq_hw_utils.h" 16#include "../aq_hw_utils.h"
17 17
18/* global */ 18/* global */
19void reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem, u32 semaphore) 19void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem,
20 u32 semaphore)
20{ 21{
21 aq_hw_write_reg(aq_hw, glb_cpu_sem_adr(semaphore), glb_cpu_sem); 22 aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore), glb_cpu_sem);
22} 23}
23 24
24u32 reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore) 25u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore)
25{ 26{
26 return aq_hw_read_reg(aq_hw, glb_cpu_sem_adr(semaphore)); 27 return aq_hw_read_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore));
27} 28}
28 29
29void glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis) 30void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis)
30{ 31{
31 aq_hw_write_reg_bit(aq_hw, glb_reg_res_dis_adr, 32 aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_REG_RES_DIS_ADR,
32 glb_reg_res_dis_msk, 33 HW_ATL_GLB_REG_RES_DIS_MSK,
33 glb_reg_res_dis_shift, 34 HW_ATL_GLB_REG_RES_DIS_SHIFT,
34 glb_reg_res_dis); 35 glb_reg_res_dis);
35} 36}
36 37
37void glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res) 38void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res)
38{ 39{
39 aq_hw_write_reg_bit(aq_hw, glb_soft_res_adr, glb_soft_res_msk, 40 aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
40 glb_soft_res_shift, soft_res); 41 HW_ATL_GLB_SOFT_RES_MSK,
42 HW_ATL_GLB_SOFT_RES_SHIFT, soft_res);
41} 43}
42 44
43u32 glb_soft_res_get(struct aq_hw_s *aq_hw) 45u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw)
44{ 46{
45 return aq_hw_read_reg_bit(aq_hw, glb_soft_res_adr, 47 return aq_hw_read_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
46 glb_soft_res_msk, 48 HW_ATL_GLB_SOFT_RES_MSK,
47 glb_soft_res_shift); 49 HW_ATL_GLB_SOFT_RES_SHIFT);
48} 50}
49 51
50u32 reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw) 52u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw)
51{ 53{
52 return aq_hw_read_reg(aq_hw, rx_dma_stat_counter7_adr); 54 return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_STAT_COUNTER7_ADR);
53} 55}
54 56
55u32 reg_glb_mif_id_get(struct aq_hw_s *aq_hw) 57u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw)
56{ 58{
57 return aq_hw_read_reg(aq_hw, glb_mif_id_adr); 59 return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR);
58} 60}
59 61
60/* stats */ 62/* stats */
61u32 rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw) 63u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw)
62{ 64{
63 return aq_hw_read_reg(aq_hw, rpb_rx_dma_drop_pkt_cnt_adr); 65 return aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR);
64} 66}
65 67
66u32 stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw) 68u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
67{ 69{
68 return aq_hw_read_reg(aq_hw, stats_rx_dma_good_octet_counterlsw__adr); 70 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW);
69} 71}
70 72
71u32 stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw) 73u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
72{ 74{
73 return aq_hw_read_reg(aq_hw, stats_rx_dma_good_pkt_counterlsw__adr); 75 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW);
74} 76}
75 77
76u32 stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw) 78u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
77{ 79{
78 return aq_hw_read_reg(aq_hw, stats_tx_dma_good_octet_counterlsw__adr); 80 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW);
79} 81}
80 82
81u32 stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw) 83u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
82{ 84{
83 return aq_hw_read_reg(aq_hw, stats_tx_dma_good_pkt_counterlsw__adr); 85 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW);
84} 86}
85 87
86u32 stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw) 88u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
87{ 89{
88 return aq_hw_read_reg(aq_hw, stats_rx_dma_good_octet_countermsw__adr); 90 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW);
89} 91}
90 92
91u32 stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw) 93u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
92{ 94{
93 return aq_hw_read_reg(aq_hw, stats_rx_dma_good_pkt_countermsw__adr); 95 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW);
94} 96}
95 97
96u32 stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw) 98u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
97{ 99{
98 return aq_hw_read_reg(aq_hw, stats_tx_dma_good_octet_countermsw__adr); 100 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW);
99} 101}
100 102
101u32 stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw) 103u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
102{ 104{
103 return aq_hw_read_reg(aq_hw, stats_tx_dma_good_pkt_countermsw__adr); 105 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW);
104} 106}
105 107
106/* interrupt */ 108/* interrupt */
107void itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw, u32 irq_auto_masklsw) 109void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw,
110 u32 irq_auto_masklsw)
108{ 111{
109 aq_hw_write_reg(aq_hw, itr_iamrlsw_adr, irq_auto_masklsw); 112 aq_hw_write_reg(aq_hw, HW_ATL_ITR_IAMRLSW_ADR, irq_auto_masklsw);
110} 113}
111 114
112void itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, u32 rx) 115void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx,
116 u32 rx)
113{ 117{
114/* register address for bitfield imr_rx{r}_en */ 118/* register address for bitfield imr_rx{r}_en */
115 static u32 itr_imr_rxren_adr[32] = { 119 static u32 itr_imr_rxren_adr[32] = {
116 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, 120 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
117 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU, 121 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
118 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, 122 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
119 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU, 123 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
120 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, 124 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
121 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU, 125 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
122 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, 126 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
123 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU 127 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
124 }; 128 };
125 129
126/* bitmask for bitfield imr_rx{r}_en */ 130/* bitmask for bitfield imr_rx{r}_en */
@@ -149,18 +153,19 @@ void itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, u32 rx)
149 irq_map_en_rx); 153 irq_map_en_rx);
150} 154}
151 155
152void itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, u32 tx) 156void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx,
157 u32 tx)
153{ 158{
154/* register address for bitfield imr_tx{t}_en */ 159/* register address for bitfield imr_tx{t}_en */
155 static u32 itr_imr_txten_adr[32] = { 160 static u32 itr_imr_txten_adr[32] = {
156 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, 161 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
157 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU, 162 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
158 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, 163 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
159 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU, 164 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
160 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, 165 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
161 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU, 166 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
162 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, 167 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
163 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU 168 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
164 }; 169 };
165 170
166/* bitmask for bitfield imr_tx{t}_en */ 171/* bitmask for bitfield imr_tx{t}_en */
@@ -189,30 +194,30 @@ void itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, u32 tx)
189 irq_map_en_tx); 194 irq_map_en_tx);
190} 195}
191 196
192void itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx) 197void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx)
193{ 198{
194/* register address for bitfield imr_rx{r}[4:0] */ 199/* register address for bitfield imr_rx{r}[4:0] */
195 static u32 itr_imr_rxr_adr[32] = { 200 static u32 itr_imr_rxr_adr[32] = {
196 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, 201 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
197 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU, 202 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
198 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, 203 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
199 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU, 204 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
200 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, 205 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
201 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU, 206 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
202 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, 207 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
203 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU 208 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
204 }; 209 };
205 210
206/* bitmask for bitfield imr_rx{r}[4:0] */ 211/* bitmask for bitfield imr_rx{r}[4:0] */
207 static u32 itr_imr_rxr_msk[32] = { 212 static u32 itr_imr_rxr_msk[32] = {
208 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, 213 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
209 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, 214 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
210 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, 215 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
211 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, 216 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
212 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, 217 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
213 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, 218 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
214 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU, 219 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
215 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU 220 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU
216 }; 221 };
217 222
218/* lower bit position of bitfield imr_rx{r}[4:0] */ 223/* lower bit position of bitfield imr_rx{r}[4:0] */
@@ -229,30 +234,30 @@ void itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx)
229 irq_map_rx); 234 irq_map_rx);
230} 235}
231 236
232void itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx) 237void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx)
233{ 238{
234/* register address for bitfield imr_tx{t}[4:0] */ 239/* register address for bitfield imr_tx{t}[4:0] */
235 static u32 itr_imr_txt_adr[32] = { 240 static u32 itr_imr_txt_adr[32] = {
236 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, 241 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
237 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU, 242 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
238 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, 243 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
239 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU, 244 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
240 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, 245 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
241 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU, 246 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
242 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, 247 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
243 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU 248 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
244 }; 249 };
245 250
246/* bitmask for bitfield imr_tx{t}[4:0] */ 251/* bitmask for bitfield imr_tx{t}[4:0] */
247 static u32 itr_imr_txt_msk[32] = { 252 static u32 itr_imr_txt_msk[32] = {
248 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, 253 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
249 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, 254 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
250 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, 255 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
251 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, 256 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
252 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, 257 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
253 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, 258 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
254 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U, 259 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
255 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U 260 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U
256 }; 261 };
257 262
258/* lower bit position of bitfield imr_tx{t}[4:0] */ 263/* lower bit position of bitfield imr_tx{t}[4:0] */
@@ -269,429 +274,463 @@ void itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx)
269 irq_map_tx); 274 irq_map_tx);
270} 275}
271 276
272void itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_clearlsw) 277void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw,
278 u32 irq_msk_clearlsw)
273{ 279{
274 aq_hw_write_reg(aq_hw, itr_imcrlsw_adr, irq_msk_clearlsw); 280 aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMCRLSW_ADR, irq_msk_clearlsw);
275} 281}
276 282
277void itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw) 283void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw)
278{ 284{
279 aq_hw_write_reg(aq_hw, itr_imsrlsw_adr, irq_msk_setlsw); 285 aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMSRLSW_ADR, irq_msk_setlsw);
280} 286}
281 287
282void itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis) 288void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis)
283{ 289{
284 aq_hw_write_reg_bit(aq_hw, itr_reg_res_dsbl_adr, 290 aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_REG_RES_DSBL_ADR,
285 itr_reg_res_dsbl_msk, 291 HW_ATL_ITR_REG_RES_DSBL_MSK,
286 itr_reg_res_dsbl_shift, irq_reg_res_dis); 292 HW_ATL_ITR_REG_RES_DSBL_SHIFT, irq_reg_res_dis);
287} 293}
288 294
289void itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw, 295void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
290 u32 irq_status_clearlsw) 296 u32 irq_status_clearlsw)
291{ 297{
292 aq_hw_write_reg(aq_hw, itr_iscrlsw_adr, irq_status_clearlsw); 298 aq_hw_write_reg(aq_hw, HW_ATL_ITR_ISCRLSW_ADR, irq_status_clearlsw);
293} 299}
294 300
295u32 itr_irq_statuslsw_get(struct aq_hw_s *aq_hw) 301u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw)
296{ 302{
297 return aq_hw_read_reg(aq_hw, itr_isrlsw_adr); 303 return aq_hw_read_reg(aq_hw, HW_ATL_ITR_ISRLSW_ADR);
298} 304}
299 305
300u32 itr_res_irq_get(struct aq_hw_s *aq_hw) 306u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw)
301{ 307{
302 return aq_hw_read_reg_bit(aq_hw, itr_res_adr, itr_res_msk, 308 return aq_hw_read_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
303 itr_res_shift); 309 HW_ATL_ITR_RES_SHIFT);
304} 310}
305 311
306void itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq) 312void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq)
307{ 313{
308 aq_hw_write_reg_bit(aq_hw, itr_res_adr, itr_res_msk, 314 aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
309 itr_res_shift, res_irq); 315 HW_ATL_ITR_RES_SHIFT, res_irq);
310} 316}
311 317
312/* rdm */ 318/* rdm */
313void rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca) 319void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
314{ 320{
315 aq_hw_write_reg_bit(aq_hw, rdm_dcadcpuid_adr(dca), 321 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADCPUID_ADR(dca),
316 rdm_dcadcpuid_msk, 322 HW_ATL_RDM_DCADCPUID_MSK,
317 rdm_dcadcpuid_shift, cpuid); 323 HW_ATL_RDM_DCADCPUID_SHIFT, cpuid);
318} 324}
319 325
320void rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en) 326void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en)
321{ 327{
322 aq_hw_write_reg_bit(aq_hw, rdm_dca_en_adr, rdm_dca_en_msk, 328 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_EN_ADR, HW_ATL_RDM_DCA_EN_MSK,
323 rdm_dca_en_shift, rx_dca_en); 329 HW_ATL_RDM_DCA_EN_SHIFT, rx_dca_en);
324} 330}
325 331
326void rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode) 332void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode)
327{ 333{
328 aq_hw_write_reg_bit(aq_hw, rdm_dca_mode_adr, rdm_dca_mode_msk, 334 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_MODE_ADR,
329 rdm_dca_mode_shift, rx_dca_mode); 335 HW_ATL_RDM_DCA_MODE_MSK,
336 HW_ATL_RDM_DCA_MODE_SHIFT, rx_dca_mode);
330} 337}
331 338
332void rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw, 339void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
333 u32 rx_desc_data_buff_size, u32 descriptor) 340 u32 rx_desc_data_buff_size,
341 u32 descriptor)
334{ 342{
335 aq_hw_write_reg_bit(aq_hw, rdm_descddata_size_adr(descriptor), 343 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor),
336 rdm_descddata_size_msk, 344 HW_ATL_RDM_DESCDDATA_SIZE_MSK,
337 rdm_descddata_size_shift, 345 HW_ATL_RDM_DESCDDATA_SIZE_SHIFT,
338 rx_desc_data_buff_size); 346 rx_desc_data_buff_size);
339} 347}
340 348
341void rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en, u32 dca) 349void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
350 u32 dca)
342{ 351{
343 aq_hw_write_reg_bit(aq_hw, rdm_dcaddesc_en_adr(dca), 352 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADDESC_EN_ADR(dca),
344 rdm_dcaddesc_en_msk, 353 HW_ATL_RDM_DCADDESC_EN_MSK,
345 rdm_dcaddesc_en_shift, 354 HW_ATL_RDM_DCADDESC_EN_SHIFT,
346 rx_desc_dca_en); 355 rx_desc_dca_en);
347} 356}
348 357
349void rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en, u32 descriptor) 358void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
359 u32 descriptor)
350{ 360{
351 aq_hw_write_reg_bit(aq_hw, rdm_descden_adr(descriptor), 361 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDEN_ADR(descriptor),
352 rdm_descden_msk, 362 HW_ATL_RDM_DESCDEN_MSK,
353 rdm_descden_shift, 363 HW_ATL_RDM_DESCDEN_SHIFT,
354 rx_desc_en); 364 rx_desc_en);
355} 365}
356 366
357void rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw, 367void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
358 u32 rx_desc_head_buff_size, u32 descriptor) 368 u32 rx_desc_head_buff_size,
369 u32 descriptor)
359{ 370{
360 aq_hw_write_reg_bit(aq_hw, rdm_descdhdr_size_adr(descriptor), 371 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor),
361 rdm_descdhdr_size_msk, 372 HW_ATL_RDM_DESCDHDR_SIZE_MSK,
362 rdm_descdhdr_size_shift, 373 HW_ATL_RDM_DESCDHDR_SIZE_SHIFT,
363 rx_desc_head_buff_size); 374 rx_desc_head_buff_size);
364} 375}
365 376
366void rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw, 377void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
367 u32 rx_desc_head_splitting, u32 descriptor) 378 u32 rx_desc_head_splitting,
379 u32 descriptor)
368{ 380{
369 aq_hw_write_reg_bit(aq_hw, rdm_descdhdr_split_adr(descriptor), 381 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor),
370 rdm_descdhdr_split_msk, 382 HW_ATL_RDM_DESCDHDR_SPLIT_MSK,
371 rdm_descdhdr_split_shift, 383 HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT,
372 rx_desc_head_splitting); 384 rx_desc_head_splitting);
373} 385}
374 386
375u32 rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor) 387u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
376{ 388{
377 return aq_hw_read_reg_bit(aq_hw, rdm_descdhd_adr(descriptor), 389 return aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_DESCDHD_ADR(descriptor),
378 rdm_descdhd_msk, rdm_descdhd_shift); 390 HW_ATL_RDM_DESCDHD_MSK,
391 HW_ATL_RDM_DESCDHD_SHIFT);
379} 392}
380 393
381void rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len, u32 descriptor) 394void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
395 u32 descriptor)
382{ 396{
383 aq_hw_write_reg_bit(aq_hw, rdm_descdlen_adr(descriptor), 397 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDLEN_ADR(descriptor),
384 rdm_descdlen_msk, rdm_descdlen_shift, 398 HW_ATL_RDM_DESCDLEN_MSK, HW_ATL_RDM_DESCDLEN_SHIFT,
385 rx_desc_len); 399 rx_desc_len);
386} 400}
387 401
388void rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res, u32 descriptor) 402void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
403 u32 descriptor)
389{ 404{
390 aq_hw_write_reg_bit(aq_hw, rdm_descdreset_adr(descriptor), 405 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDRESET_ADR(descriptor),
391 rdm_descdreset_msk, rdm_descdreset_shift, 406 HW_ATL_RDM_DESCDRESET_MSK,
407 HW_ATL_RDM_DESCDRESET_SHIFT,
392 rx_desc_res); 408 rx_desc_res);
393} 409}
394 410
395void rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, 411void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
396 u32 rx_desc_wr_wb_irq_en) 412 u32 rx_desc_wr_wb_irq_en)
397{ 413{
398 aq_hw_write_reg_bit(aq_hw, rdm_int_desc_wrb_en_adr, 414 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_DESC_WRB_EN_ADR,
399 rdm_int_desc_wrb_en_msk, 415 HW_ATL_RDM_INT_DESC_WRB_EN_MSK,
400 rdm_int_desc_wrb_en_shift, 416 HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT,
401 rx_desc_wr_wb_irq_en); 417 rx_desc_wr_wb_irq_en);
402} 418}
403 419
404void rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en, u32 dca) 420void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
421 u32 dca)
405{ 422{
406 aq_hw_write_reg_bit(aq_hw, rdm_dcadhdr_en_adr(dca), 423 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADHDR_EN_ADR(dca),
407 rdm_dcadhdr_en_msk, 424 HW_ATL_RDM_DCADHDR_EN_MSK,
408 rdm_dcadhdr_en_shift, 425 HW_ATL_RDM_DCADHDR_EN_SHIFT,
409 rx_head_dca_en); 426 rx_head_dca_en);
410} 427}
411 428
412void rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, u32 dca) 429void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en,
430 u32 dca)
413{ 431{
414 aq_hw_write_reg_bit(aq_hw, rdm_dcadpay_en_adr(dca), 432 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADPAY_EN_ADR(dca),
415 rdm_dcadpay_en_msk, rdm_dcadpay_en_shift, 433 HW_ATL_RDM_DCADPAY_EN_MSK,
434 HW_ATL_RDM_DCADPAY_EN_SHIFT,
416 rx_pld_dca_en); 435 rx_pld_dca_en);
417} 436}
418 437
419void rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, u32 rdm_intr_moder_en) 438void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
439 u32 rdm_intr_moder_en)
420{ 440{
421 aq_hw_write_reg_bit(aq_hw, rdm_int_rim_en_adr, 441 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_RIM_EN_ADR,
422 rdm_int_rim_en_msk, 442 HW_ATL_RDM_INT_RIM_EN_MSK,
423 rdm_int_rim_en_shift, 443 HW_ATL_RDM_INT_RIM_EN_SHIFT,
424 rdm_intr_moder_en); 444 rdm_intr_moder_en);
425} 445}
426 446
427/* reg */ 447/* reg */
428void reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map, u32 regidx) 448void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map,
449 u32 regidx)
429{ 450{
430 aq_hw_write_reg(aq_hw, gen_intr_map_adr(regidx), gen_intr_map); 451 aq_hw_write_reg(aq_hw, HW_ATL_GEN_INTR_MAP_ADR(regidx), gen_intr_map);
431} 452}
432 453
433u32 reg_gen_irq_status_get(struct aq_hw_s *aq_hw) 454u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw)
434{ 455{
435 return aq_hw_read_reg(aq_hw, gen_intr_stat_adr); 456 return aq_hw_read_reg(aq_hw, HW_ATL_GEN_INTR_STAT_ADR);
436} 457}
437 458
438void reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl) 459void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl)
439{ 460{
440 aq_hw_write_reg(aq_hw, intr_glb_ctl_adr, intr_glb_ctl); 461 aq_hw_write_reg(aq_hw, HW_ATL_INTR_GLB_CTL_ADR, intr_glb_ctl);
441} 462}
442 463
443void reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle) 464void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle)
444{ 465{
445 aq_hw_write_reg(aq_hw, intr_thr_adr(throttle), intr_thr); 466 aq_hw_write_reg(aq_hw, HW_ATL_INTR_THR_ADR(throttle), intr_thr);
446} 467}
447 468
448void reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, 469void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
449 u32 rx_dma_desc_base_addrlsw, 470 u32 rx_dma_desc_base_addrlsw,
450 u32 descriptor) 471 u32 descriptor)
451{ 472{
452 aq_hw_write_reg(aq_hw, rx_dma_desc_base_addrlsw_adr(descriptor), 473 aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
453 rx_dma_desc_base_addrlsw); 474 rx_dma_desc_base_addrlsw);
454} 475}
455 476
456void reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, 477void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
457 u32 rx_dma_desc_base_addrmsw, 478 u32 rx_dma_desc_base_addrmsw,
458 u32 descriptor) 479 u32 descriptor)
459{ 480{
460 aq_hw_write_reg(aq_hw, rx_dma_desc_base_addrmsw_adr(descriptor), 481 aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
461 rx_dma_desc_base_addrmsw); 482 rx_dma_desc_base_addrmsw);
462} 483}
463 484
464u32 reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor) 485u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor)
465{ 486{
466 return aq_hw_read_reg(aq_hw, rx_dma_desc_stat_adr(descriptor)); 487 return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor));
467} 488}
468 489
469void reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, 490void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
470 u32 rx_dma_desc_tail_ptr, u32 descriptor) 491 u32 rx_dma_desc_tail_ptr,
492 u32 descriptor)
471{ 493{
472 aq_hw_write_reg(aq_hw, rx_dma_desc_tail_ptr_adr(descriptor), 494 aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor),
473 rx_dma_desc_tail_ptr); 495 rx_dma_desc_tail_ptr);
474} 496}
475 497
476void reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr_msk) 498void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
499 u32 rx_flr_mcst_flr_msk)
477{ 500{
478 aq_hw_write_reg(aq_hw, rx_flr_mcst_flr_msk_adr, rx_flr_mcst_flr_msk); 501 aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_MSK_ADR,
502 rx_flr_mcst_flr_msk);
479} 503}
480 504
481void reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr, 505void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
482 u32 filter) 506 u32 filter)
483{ 507{
484 aq_hw_write_reg(aq_hw, rx_flr_mcst_flr_adr(filter), rx_flr_mcst_flr); 508 aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_ADR(filter),
509 rx_flr_mcst_flr);
485} 510}
486 511
487void reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw, u32 rx_flr_rss_control1) 512void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,
513 u32 rx_flr_rss_control1)
488{ 514{
489 aq_hw_write_reg(aq_hw, rx_flr_rss_control1_adr, rx_flr_rss_control1); 515 aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_RSS_CONTROL1_ADR,
516 rx_flr_rss_control1);
490} 517}
491 518
492void reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_filter_control2) 519void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw,
520 u32 rx_filter_control2)
493{ 521{
494 aq_hw_write_reg(aq_hw, rx_flr_control2_adr, rx_filter_control2); 522 aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_CONTROL2_ADR, rx_filter_control2);
495} 523}
496 524
497void reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, 525void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
498 u32 rx_intr_moderation_ctl, 526 u32 rx_intr_moderation_ctl,
499 u32 queue) 527 u32 queue)
500{ 528{
501 aq_hw_write_reg(aq_hw, rx_intr_moderation_ctl_adr(queue), 529 aq_hw_write_reg(aq_hw, HW_ATL_RX_INTR_MODERATION_CTL_ADR(queue),
502 rx_intr_moderation_ctl); 530 rx_intr_moderation_ctl);
503} 531}
504 532
505void reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw, u32 tx_dma_debug_ctl) 533void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw,
534 u32 tx_dma_debug_ctl)
506{ 535{
507 aq_hw_write_reg(aq_hw, tx_dma_debug_ctl_adr, tx_dma_debug_ctl); 536 aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DEBUG_CTL_ADR, tx_dma_debug_ctl);
508} 537}
509 538
510void reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, 539void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
511 u32 tx_dma_desc_base_addrlsw, 540 u32 tx_dma_desc_base_addrlsw,
512 u32 descriptor) 541 u32 descriptor)
513{ 542{
514 aq_hw_write_reg(aq_hw, tx_dma_desc_base_addrlsw_adr(descriptor), 543 aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
515 tx_dma_desc_base_addrlsw); 544 tx_dma_desc_base_addrlsw);
516} 545}
517 546
518void reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, 547void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
519 u32 tx_dma_desc_base_addrmsw, 548 u32 tx_dma_desc_base_addrmsw,
520 u32 descriptor) 549 u32 descriptor)
521{ 550{
522 aq_hw_write_reg(aq_hw, tx_dma_desc_base_addrmsw_adr(descriptor), 551 aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
523 tx_dma_desc_base_addrmsw); 552 tx_dma_desc_base_addrmsw);
524} 553}
525 554
526void reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, 555void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
527 u32 tx_dma_desc_tail_ptr, u32 descriptor) 556 u32 tx_dma_desc_tail_ptr,
557 u32 descriptor)
528{ 558{
529 aq_hw_write_reg(aq_hw, tx_dma_desc_tail_ptr_adr(descriptor), 559 aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor),
530 tx_dma_desc_tail_ptr); 560 tx_dma_desc_tail_ptr);
531} 561}
532 562
533void reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, 563void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
534 u32 tx_intr_moderation_ctl, 564 u32 tx_intr_moderation_ctl,
535 u32 queue) 565 u32 queue)
536{ 566{
537 aq_hw_write_reg(aq_hw, tx_intr_moderation_ctl_adr(queue), 567 aq_hw_write_reg(aq_hw, HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue),
538 tx_intr_moderation_ctl); 568 tx_intr_moderation_ctl);
539} 569}
540 570
541/* RPB: rx packet buffer */ 571/* RPB: rx packet buffer */
542void rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk) 572void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk)
543{ 573{
544 aq_hw_write_reg_bit(aq_hw, rpb_dma_sys_lbk_adr, 574 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_SYS_LBK_ADR,
545 rpb_dma_sys_lbk_msk, 575 HW_ATL_RPB_DMA_SYS_LBK_MSK,
546 rpb_dma_sys_lbk_shift, dma_sys_lbk); 576 HW_ATL_RPB_DMA_SYS_LBK_SHIFT, dma_sys_lbk);
547} 577}
548 578
549void rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw, 579void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
550 u32 rx_traf_class_mode) 580 u32 rx_traf_class_mode)
551{ 581{
552 aq_hw_write_reg_bit(aq_hw, rpb_rpf_rx_tc_mode_adr, 582 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR,
553 rpb_rpf_rx_tc_mode_msk, 583 HW_ATL_RPB_RPF_RX_TC_MODE_MSK,
554 rpb_rpf_rx_tc_mode_shift, 584 HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT,
555 rx_traf_class_mode); 585 rx_traf_class_mode);
556} 586}
557 587
558void rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en) 588void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en)
559{ 589{
560 aq_hw_write_reg_bit(aq_hw, rpb_rx_buf_en_adr, rpb_rx_buf_en_msk, 590 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_BUF_EN_ADR,
561 rpb_rx_buf_en_shift, rx_buff_en); 591 HW_ATL_RPB_RX_BUF_EN_MSK,
592 HW_ATL_RPB_RX_BUF_EN_SHIFT, rx_buff_en);
562} 593}
563 594
564void rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, 595void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
565 u32 rx_buff_hi_threshold_per_tc, 596 u32 rx_buff_hi_threshold_per_tc,
566 u32 buffer) 597 u32 buffer)
567{ 598{
568 aq_hw_write_reg_bit(aq_hw, rpb_rxbhi_thresh_adr(buffer), 599 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBHI_THRESH_ADR(buffer),
569 rpb_rxbhi_thresh_msk, rpb_rxbhi_thresh_shift, 600 HW_ATL_RPB_RXBHI_THRESH_MSK,
601 HW_ATL_RPB_RXBHI_THRESH_SHIFT,
570 rx_buff_hi_threshold_per_tc); 602 rx_buff_hi_threshold_per_tc);
571} 603}
572 604
573void rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, 605void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
574 u32 rx_buff_lo_threshold_per_tc, 606 u32 rx_buff_lo_threshold_per_tc,
575 u32 buffer) 607 u32 buffer)
576{ 608{
577 aq_hw_write_reg_bit(aq_hw, rpb_rxblo_thresh_adr(buffer), 609 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBLO_THRESH_ADR(buffer),
578 rpb_rxblo_thresh_msk, 610 HW_ATL_RPB_RXBLO_THRESH_MSK,
579 rpb_rxblo_thresh_shift, 611 HW_ATL_RPB_RXBLO_THRESH_SHIFT,
580 rx_buff_lo_threshold_per_tc); 612 rx_buff_lo_threshold_per_tc);
581} 613}
582 614
583void rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode) 615void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode)
584{ 616{
585 aq_hw_write_reg_bit(aq_hw, rpb_rx_fc_mode_adr, 617 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_FC_MODE_ADR,
586 rpb_rx_fc_mode_msk, 618 HW_ATL_RPB_RX_FC_MODE_MSK,
587 rpb_rx_fc_mode_shift, rx_flow_ctl_mode); 619 HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode);
588} 620}
589 621
590void rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, 622void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
591 u32 rx_pkt_buff_size_per_tc, u32 buffer) 623 u32 rx_pkt_buff_size_per_tc, u32 buffer)
592{ 624{
593 aq_hw_write_reg_bit(aq_hw, rpb_rxbbuf_size_adr(buffer), 625 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer),
594 rpb_rxbbuf_size_msk, rpb_rxbbuf_size_shift, 626 HW_ATL_RPB_RXBBUF_SIZE_MSK,
627 HW_ATL_RPB_RXBBUF_SIZE_SHIFT,
595 rx_pkt_buff_size_per_tc); 628 rx_pkt_buff_size_per_tc);
596} 629}
597 630
598void rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc, 631void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
599 u32 buffer) 632 u32 buffer)
600{ 633{
601 aq_hw_write_reg_bit(aq_hw, rpb_rxbxoff_en_adr(buffer), 634 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBXOFF_EN_ADR(buffer),
602 rpb_rxbxoff_en_msk, rpb_rxbxoff_en_shift, 635 HW_ATL_RPB_RXBXOFF_EN_MSK,
636 HW_ATL_RPB_RXBXOFF_EN_SHIFT,
603 rx_xoff_en_per_tc); 637 rx_xoff_en_per_tc);
604} 638}
605 639
606/* rpf */ 640/* rpf */
607 641
608void rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw, 642void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
609 u32 l2broadcast_count_threshold) 643 u32 l2broadcast_count_threshold)
610{ 644{
611 aq_hw_write_reg_bit(aq_hw, rpfl2bc_thresh_adr, 645 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_THRESH_ADR,
612 rpfl2bc_thresh_msk, 646 HW_ATL_RPFL2BC_THRESH_MSK,
613 rpfl2bc_thresh_shift, 647 HW_ATL_RPFL2BC_THRESH_SHIFT,
614 l2broadcast_count_threshold); 648 l2broadcast_count_threshold);
615} 649}
616 650
617void rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en) 651void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en)
618{ 652{
619 aq_hw_write_reg_bit(aq_hw, rpfl2bc_en_adr, rpfl2bc_en_msk, 653 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_EN_ADR, HW_ATL_RPFL2BC_EN_MSK,
620 rpfl2bc_en_shift, l2broadcast_en); 654 HW_ATL_RPFL2BC_EN_SHIFT, l2broadcast_en);
621} 655}
622 656
623void rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw, u32 l2broadcast_flr_act) 657void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,
658 u32 l2broadcast_flr_act)
624{ 659{
625 aq_hw_write_reg_bit(aq_hw, rpfl2bc_act_adr, rpfl2bc_act_msk, 660 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_ACT_ADR,
626 rpfl2bc_act_shift, l2broadcast_flr_act); 661 HW_ATL_RPFL2BC_ACT_MSK,
662 HW_ATL_RPFL2BC_ACT_SHIFT, l2broadcast_flr_act);
627} 663}
628 664
629void rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, u32 l2multicast_flr_en, 665void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,
630 u32 filter) 666 u32 l2multicast_flr_en,
667 u32 filter)
631{ 668{
632 aq_hw_write_reg_bit(aq_hw, rpfl2mc_enf_adr(filter), 669 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ENF_ADR(filter),
633 rpfl2mc_enf_msk, 670 HW_ATL_RPFL2MC_ENF_MSK,
634 rpfl2mc_enf_shift, l2multicast_flr_en); 671 HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en);
635} 672}
636 673
637void rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw, 674void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
638 u32 l2promiscuous_mode_en) 675 u32 l2promiscuous_mode_en)
639{ 676{
640 aq_hw_write_reg_bit(aq_hw, rpfl2promis_mode_adr, 677 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR,
641 rpfl2promis_mode_msk, 678 HW_ATL_RPFL2PROMIS_MODE_MSK,
642 rpfl2promis_mode_shift, 679 HW_ATL_RPFL2PROMIS_MODE_SHIFT,
643 l2promiscuous_mode_en); 680 l2promiscuous_mode_en);
644} 681}
645 682
646void rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_act, 683void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw,
647 u32 filter) 684 u32 l2unicast_flr_act,
685 u32 filter)
648{ 686{
649 aq_hw_write_reg_bit(aq_hw, rpfl2uc_actf_adr(filter), 687 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ACTF_ADR(filter),
650 rpfl2uc_actf_msk, rpfl2uc_actf_shift, 688 HW_ATL_RPFL2UC_ACTF_MSK, HW_ATL_RPFL2UC_ACTF_SHIFT,
651 l2unicast_flr_act); 689 l2unicast_flr_act);
652} 690}
653 691
654void rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en, 692void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
655 u32 filter) 693 u32 filter)
656{ 694{
657 aq_hw_write_reg_bit(aq_hw, rpfl2uc_enf_adr(filter), 695 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ENF_ADR(filter),
658 rpfl2uc_enf_msk, 696 HW_ATL_RPFL2UC_ENF_MSK,
659 rpfl2uc_enf_shift, l2unicast_flr_en); 697 HW_ATL_RPFL2UC_ENF_SHIFT, l2unicast_flr_en);
660} 698}
661 699
662void rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw, 700void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
663 u32 l2unicast_dest_addresslsw, 701 u32 l2unicast_dest_addresslsw,
664 u32 filter) 702 u32 filter)
665{ 703{
666 aq_hw_write_reg(aq_hw, rpfl2uc_daflsw_adr(filter), 704 aq_hw_write_reg(aq_hw, HW_ATL_RPFL2UC_DAFLSW_ADR(filter),
667 l2unicast_dest_addresslsw); 705 l2unicast_dest_addresslsw);
668} 706}
669 707
670void rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw, 708void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
671 u32 l2unicast_dest_addressmsw, 709 u32 l2unicast_dest_addressmsw,
672 u32 filter) 710 u32 filter)
673{ 711{
674 aq_hw_write_reg_bit(aq_hw, rpfl2uc_dafmsw_adr(filter), 712 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_DAFMSW_ADR(filter),
675 rpfl2uc_dafmsw_msk, rpfl2uc_dafmsw_shift, 713 HW_ATL_RPFL2UC_DAFMSW_MSK,
714 HW_ATL_RPFL2UC_DAFMSW_SHIFT,
676 l2unicast_dest_addressmsw); 715 l2unicast_dest_addressmsw);
677} 716}
678 717
679void rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw, 718void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
680 u32 l2_accept_all_mc_packets) 719 u32 l2_accept_all_mc_packets)
681{ 720{
682 aq_hw_write_reg_bit(aq_hw, rpfl2mc_accept_all_adr, 721 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ACCEPT_ALL_ADR,
683 rpfl2mc_accept_all_msk, 722 HW_ATL_RPFL2MC_ACCEPT_ALL_MSK,
684 rpfl2mc_accept_all_shift, 723 HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT,
685 l2_accept_all_mc_packets); 724 l2_accept_all_mc_packets);
686} 725}
687 726
688void rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw, 727void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
689 u32 user_priority_tc_map, u32 tc) 728 u32 user_priority_tc_map, u32 tc)
690{ 729{
691/* register address for bitfield rx_tc_up{t}[2:0] */ 730/* register address for bitfield rx_tc_up{t}[2:0] */
692 static u32 rpf_rpb_rx_tc_upt_adr[8] = { 731 static u32 rpf_rpb_rx_tc_upt_adr[8] = {
693 0x000054c4U, 0x000054c4U, 0x000054c4U, 0x000054c4U, 732 0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U,
694 0x000054c4U, 0x000054c4U, 0x000054c4U, 0x000054c4U 733 0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U
695 }; 734 };
696 735
697/* bitmask for bitfield rx_tc_up{t}[2:0] */ 736/* bitmask for bitfield rx_tc_up{t}[2:0] */
@@ -711,273 +750,290 @@ void rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
711 user_priority_tc_map); 750 user_priority_tc_map);
712} 751}
713 752
714void rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr) 753void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr)
715{ 754{
716 aq_hw_write_reg_bit(aq_hw, rpf_rss_key_addr_adr, 755 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_ADDR_ADR,
717 rpf_rss_key_addr_msk, 756 HW_ATL_RPF_RSS_KEY_ADDR_MSK,
718 rpf_rss_key_addr_shift, 757 HW_ATL_RPF_RSS_KEY_ADDR_SHIFT,
719 rss_key_addr); 758 rss_key_addr);
720} 759}
721 760
722void rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data) 761void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data)
723{ 762{
724 aq_hw_write_reg(aq_hw, rpf_rss_key_wr_data_adr, 763 aq_hw_write_reg(aq_hw, HW_ATL_RPF_RSS_KEY_WR_DATA_ADR,
725 rss_key_wr_data); 764 rss_key_wr_data);
726} 765}
727 766
728u32 rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw) 767u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw)
729{ 768{
730 return aq_hw_read_reg_bit(aq_hw, rpf_rss_key_wr_eni_adr, 769 return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
731 rpf_rss_key_wr_eni_msk, 770 HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
732 rpf_rss_key_wr_eni_shift); 771 HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT);
733} 772}
734 773
735void rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en) 774void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en)
736{ 775{
737 aq_hw_write_reg_bit(aq_hw, rpf_rss_key_wr_eni_adr, 776 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
738 rpf_rss_key_wr_eni_msk, 777 HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
739 rpf_rss_key_wr_eni_shift, 778 HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT,
740 rss_key_wr_en); 779 rss_key_wr_en);
741} 780}
742 781
743void rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw, u32 rss_redir_tbl_addr) 782void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,
783 u32 rss_redir_tbl_addr)
744{ 784{
745 aq_hw_write_reg_bit(aq_hw, rpf_rss_redir_addr_adr, 785 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_ADDR_ADR,
746 rpf_rss_redir_addr_msk, 786 HW_ATL_RPF_RSS_REDIR_ADDR_MSK,
747 rpf_rss_redir_addr_shift, rss_redir_tbl_addr); 787 HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT,
788 rss_redir_tbl_addr);
748} 789}
749 790
750void rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw, 791void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
751 u32 rss_redir_tbl_wr_data) 792 u32 rss_redir_tbl_wr_data)
752{ 793{
753 aq_hw_write_reg_bit(aq_hw, rpf_rss_redir_wr_data_adr, 794 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR,
754 rpf_rss_redir_wr_data_msk, 795 HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK,
755 rpf_rss_redir_wr_data_shift, 796 HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT,
756 rss_redir_tbl_wr_data); 797 rss_redir_tbl_wr_data);
757} 798}
758 799
759u32 rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw) 800u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw)
760{ 801{
761 return aq_hw_read_reg_bit(aq_hw, rpf_rss_redir_wr_eni_adr, 802 return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
762 rpf_rss_redir_wr_eni_msk, 803 HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
763 rpf_rss_redir_wr_eni_shift); 804 HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT);
764} 805}
765 806
766void rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en) 807void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en)
767{ 808{
768 aq_hw_write_reg_bit(aq_hw, rpf_rss_redir_wr_eni_adr, 809 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
769 rpf_rss_redir_wr_eni_msk, 810 HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
770 rpf_rss_redir_wr_eni_shift, rss_redir_wr_en); 811 HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT, rss_redir_wr_en);
771} 812}
772 813
773void rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw, u32 tpo_to_rpf_sys_lbk) 814void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,
815 u32 tpo_to_rpf_sys_lbk)
774{ 816{
775 aq_hw_write_reg_bit(aq_hw, rpf_tpo_rpf_sys_lbk_adr, 817 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR,
776 rpf_tpo_rpf_sys_lbk_msk, 818 HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK,
777 rpf_tpo_rpf_sys_lbk_shift, 819 HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT,
778 tpo_to_rpf_sys_lbk); 820 tpo_to_rpf_sys_lbk);
779} 821}
780 822
781void rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht) 823void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht)
782{ 824{
783 aq_hw_write_reg_bit(aq_hw, rpf_vl_inner_tpid_adr, 825 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_INNER_TPID_ADR,
784 rpf_vl_inner_tpid_msk, 826 HW_ATL_RPF_VL_INNER_TPID_MSK,
785 rpf_vl_inner_tpid_shift, 827 HW_ATL_RPF_VL_INNER_TPID_SHIFT,
786 vlan_inner_etht); 828 vlan_inner_etht);
787} 829}
788 830
789void rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht) 831void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht)
790{ 832{
791 aq_hw_write_reg_bit(aq_hw, rpf_vl_outer_tpid_adr, 833 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_OUTER_TPID_ADR,
792 rpf_vl_outer_tpid_msk, 834 HW_ATL_RPF_VL_OUTER_TPID_MSK,
793 rpf_vl_outer_tpid_shift, 835 HW_ATL_RPF_VL_OUTER_TPID_SHIFT,
794 vlan_outer_etht); 836 vlan_outer_etht);
795} 837}
796 838
797void rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, u32 vlan_prom_mode_en) 839void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,
840 u32 vlan_prom_mode_en)
798{ 841{
799 aq_hw_write_reg_bit(aq_hw, rpf_vl_promis_mode_adr, 842 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR,
800 rpf_vl_promis_mode_msk, 843 HW_ATL_RPF_VL_PROMIS_MODE_MSK,
801 rpf_vl_promis_mode_shift, 844 HW_ATL_RPF_VL_PROMIS_MODE_SHIFT,
802 vlan_prom_mode_en); 845 vlan_prom_mode_en);
803} 846}
804 847
805void rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw, 848void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
806 u32 vlan_accept_untagged_packets) 849 u32 vlan_acc_untagged_packets)
807{ 850{
808 aq_hw_write_reg_bit(aq_hw, rpf_vl_accept_untagged_mode_adr, 851 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR,
809 rpf_vl_accept_untagged_mode_msk, 852 HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK,
810 rpf_vl_accept_untagged_mode_shift, 853 HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT,
811 vlan_accept_untagged_packets); 854 vlan_acc_untagged_packets);
812} 855}
813 856
814void rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, u32 vlan_untagged_act) 857void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,
858 u32 vlan_untagged_act)
815{ 859{
816 aq_hw_write_reg_bit(aq_hw, rpf_vl_untagged_act_adr, 860 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR,
817 rpf_vl_untagged_act_msk, 861 HW_ATL_RPF_VL_UNTAGGED_ACT_MSK,
818 rpf_vl_untagged_act_shift, 862 HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT,
819 vlan_untagged_act); 863 vlan_untagged_act);
820} 864}
821 865
822void rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en, u32 filter) 866void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en,
867 u32 filter)
823{ 868{
824 aq_hw_write_reg_bit(aq_hw, rpf_vl_en_f_adr(filter), 869 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter),
825 rpf_vl_en_f_msk, 870 HW_ATL_RPF_VL_EN_F_MSK,
826 rpf_vl_en_f_shift, 871 HW_ATL_RPF_VL_EN_F_SHIFT,
827 vlan_flr_en); 872 vlan_flr_en);
828} 873}
829 874
830void rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act, u32 filter) 875void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act,
876 u32 filter)
831{ 877{
832 aq_hw_write_reg_bit(aq_hw, rpf_vl_act_f_adr(filter), 878 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter),
833 rpf_vl_act_f_msk, 879 HW_ATL_RPF_VL_ACT_F_MSK,
834 rpf_vl_act_f_shift, 880 HW_ATL_RPF_VL_ACT_F_SHIFT,
835 vlan_flr_act); 881 vlan_flr_act);
836} 882}
837 883
838void rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, u32 filter) 884void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
885 u32 filter)
839{ 886{
840 aq_hw_write_reg_bit(aq_hw, rpf_vl_id_f_adr(filter), 887 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter),
841 rpf_vl_id_f_msk, 888 HW_ATL_RPF_VL_ID_F_MSK,
842 rpf_vl_id_f_shift, 889 HW_ATL_RPF_VL_ID_F_SHIFT,
843 vlan_id_flr); 890 vlan_id_flr);
844} 891}
845 892
846void rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en, u32 filter) 893void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
894 u32 filter)
847{ 895{
848 aq_hw_write_reg_bit(aq_hw, rpf_et_enf_adr(filter), 896 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter),
849 rpf_et_enf_msk, 897 HW_ATL_RPF_ET_ENF_MSK,
850 rpf_et_enf_shift, etht_flr_en); 898 HW_ATL_RPF_ET_ENF_SHIFT, etht_flr_en);
851} 899}
852 900
853void rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw, 901void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
854 u32 etht_user_priority_en, u32 filter) 902 u32 etht_user_priority_en, u32 filter)
855{ 903{
856 aq_hw_write_reg_bit(aq_hw, rpf_et_upfen_adr(filter), 904 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPFEN_ADR(filter),
857 rpf_et_upfen_msk, rpf_et_upfen_shift, 905 HW_ATL_RPF_ET_UPFEN_MSK, HW_ATL_RPF_ET_UPFEN_SHIFT,
858 etht_user_priority_en); 906 etht_user_priority_en);
859} 907}
860 908
861void rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue_en, 909void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,
862 u32 filter) 910 u32 etht_rx_queue_en,
911 u32 filter)
863{ 912{
864 aq_hw_write_reg_bit(aq_hw, rpf_et_rxqfen_adr(filter), 913 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter),
865 rpf_et_rxqfen_msk, rpf_et_rxqfen_shift, 914 HW_ATL_RPF_ET_RXQFEN_MSK,
915 HW_ATL_RPF_ET_RXQFEN_SHIFT,
866 etht_rx_queue_en); 916 etht_rx_queue_en);
867} 917}
868 918
869void rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, u32 etht_user_priority, 919void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,
870 u32 filter) 920 u32 etht_user_priority,
921 u32 filter)
871{ 922{
872 aq_hw_write_reg_bit(aq_hw, rpf_et_upf_adr(filter), 923 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter),
873 rpf_et_upf_msk, 924 HW_ATL_RPF_ET_UPF_MSK,
874 rpf_et_upf_shift, etht_user_priority); 925 HW_ATL_RPF_ET_UPF_SHIFT, etht_user_priority);
875} 926}
876 927
877void rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue, 928void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
878 u32 filter) 929 u32 filter)
879{ 930{
880 aq_hw_write_reg_bit(aq_hw, rpf_et_rxqf_adr(filter), 931 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQF_ADR(filter),
881 rpf_et_rxqf_msk, 932 HW_ATL_RPF_ET_RXQF_MSK,
882 rpf_et_rxqf_shift, etht_rx_queue); 933 HW_ATL_RPF_ET_RXQF_SHIFT, etht_rx_queue);
883} 934}
884 935
885void rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue, 936void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
886 u32 filter) 937 u32 filter)
887{ 938{
888 aq_hw_write_reg_bit(aq_hw, rpf_et_mng_rxqf_adr(filter), 939 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_MNG_RXQF_ADR(filter),
889 rpf_et_mng_rxqf_msk, rpf_et_mng_rxqf_shift, 940 HW_ATL_RPF_ET_MNG_RXQF_MSK,
941 HW_ATL_RPF_ET_MNG_RXQF_SHIFT,
890 etht_mgt_queue); 942 etht_mgt_queue);
891} 943}
892 944
893void rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act, u32 filter) 945void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
946 u32 filter)
894{ 947{
895 aq_hw_write_reg_bit(aq_hw, rpf_et_actf_adr(filter), 948 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ACTF_ADR(filter),
896 rpf_et_actf_msk, 949 HW_ATL_RPF_ET_ACTF_MSK,
897 rpf_et_actf_shift, etht_flr_act); 950 HW_ATL_RPF_ET_ACTF_SHIFT, etht_flr_act);
898} 951}
899 952
900void rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter) 953void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter)
901{ 954{
902 aq_hw_write_reg_bit(aq_hw, rpf_et_valf_adr(filter), 955 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter),
903 rpf_et_valf_msk, 956 HW_ATL_RPF_ET_VALF_MSK,
904 rpf_et_valf_shift, etht_flr); 957 HW_ATL_RPF_ET_VALF_SHIFT, etht_flr);
905} 958}
906 959
907/* RPO: rx packet offload */ 960/* RPO: rx packet offload */
908void rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, 961void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
909 u32 ipv4header_crc_offload_en) 962 u32 ipv4header_crc_offload_en)
910{ 963{
911 aq_hw_write_reg_bit(aq_hw, rpo_ipv4chk_en_adr, 964 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_IPV4CHK_EN_ADR,
912 rpo_ipv4chk_en_msk, 965 HW_ATL_RPO_IPV4CHK_EN_MSK,
913 rpo_ipv4chk_en_shift, 966 HW_ATL_RPO_IPV4CHK_EN_SHIFT,
914 ipv4header_crc_offload_en); 967 ipv4header_crc_offload_en);
915} 968}
916 969
917void rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw, 970void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
918 u32 rx_desc_vlan_stripping, u32 descriptor) 971 u32 rx_desc_vlan_stripping,
972 u32 descriptor)
919{ 973{
920 aq_hw_write_reg_bit(aq_hw, rpo_descdvl_strip_adr(descriptor), 974 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor),
921 rpo_descdvl_strip_msk, 975 HW_ATL_RPO_DESCDVL_STRIP_MSK,
922 rpo_descdvl_strip_shift, 976 HW_ATL_RPO_DESCDVL_STRIP_SHIFT,
923 rx_desc_vlan_stripping); 977 rx_desc_vlan_stripping);
924} 978}
925 979
926void rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, 980void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
927 u32 tcp_udp_crc_offload_en) 981 u32 tcp_udp_crc_offload_en)
928{ 982{
929 aq_hw_write_reg_bit(aq_hw, rpol4chk_en_adr, rpol4chk_en_msk, 983 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPOL4CHK_EN_ADR,
930 rpol4chk_en_shift, tcp_udp_crc_offload_en); 984 HW_ATL_RPOL4CHK_EN_MSK,
985 HW_ATL_RPOL4CHK_EN_SHIFT, tcp_udp_crc_offload_en);
931} 986}
932 987
933void rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en) 988void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en)
934{ 989{
935 aq_hw_write_reg(aq_hw, rpo_lro_en_adr, lro_en); 990 aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_EN_ADR, lro_en);
936} 991}
937 992
938void rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw, 993void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
939 u32 lro_patch_optimization_en) 994 u32 lro_patch_optimization_en)
940{ 995{
941 aq_hw_write_reg_bit(aq_hw, rpo_lro_ptopt_en_adr, 996 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PTOPT_EN_ADR,
942 rpo_lro_ptopt_en_msk, 997 HW_ATL_RPO_LRO_PTOPT_EN_MSK,
943 rpo_lro_ptopt_en_shift, 998 HW_ATL_RPO_LRO_PTOPT_EN_SHIFT,
944 lro_patch_optimization_en); 999 lro_patch_optimization_en);
945} 1000}
946 1001
947void rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw, 1002void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
948 u32 lro_qsessions_lim) 1003 u32 lro_qsessions_lim)
949{ 1004{
950 aq_hw_write_reg_bit(aq_hw, rpo_lro_qses_lmt_adr, 1005 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_QSES_LMT_ADR,
951 rpo_lro_qses_lmt_msk, 1006 HW_ATL_RPO_LRO_QSES_LMT_MSK,
952 rpo_lro_qses_lmt_shift, 1007 HW_ATL_RPO_LRO_QSES_LMT_SHIFT,
953 lro_qsessions_lim); 1008 lro_qsessions_lim);
954} 1009}
955 1010
956void rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw, u32 lro_total_desc_lim) 1011void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw,
1012 u32 lro_total_desc_lim)
957{ 1013{
958 aq_hw_write_reg_bit(aq_hw, rpo_lro_tot_dsc_lmt_adr, 1014 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR,
959 rpo_lro_tot_dsc_lmt_msk, 1015 HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK,
960 rpo_lro_tot_dsc_lmt_shift, 1016 HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT,
961 lro_total_desc_lim); 1017 lro_total_desc_lim);
962} 1018}
963 1019
964void rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw, 1020void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
965 u32 lro_min_pld_of_first_pkt) 1021 u32 lro_min_pld_of_first_pkt)
966{ 1022{
967 aq_hw_write_reg_bit(aq_hw, rpo_lro_pkt_min_adr, 1023 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PKT_MIN_ADR,
968 rpo_lro_pkt_min_msk, 1024 HW_ATL_RPO_LRO_PKT_MIN_MSK,
969 rpo_lro_pkt_min_shift, 1025 HW_ATL_RPO_LRO_PKT_MIN_SHIFT,
970 lro_min_pld_of_first_pkt); 1026 lro_min_pld_of_first_pkt);
971} 1027}
972 1028
973void rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim) 1029void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim)
974{ 1030{
975 aq_hw_write_reg(aq_hw, rpo_lro_rsc_max_adr, lro_pkt_lim); 1031 aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_RSC_MAX_ADR, lro_pkt_lim);
976} 1032}
977 1033
978void rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw, 1034void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
979 u32 lro_max_number_of_descriptors, 1035 u32 lro_max_number_of_descriptors,
980 u32 lro) 1036 u32 lro)
981{ 1037{
982/* Register address for bitfield lro{L}_des_max[1:0] */ 1038/* Register address for bitfield lro{L}_des_max[1:0] */
983 static u32 rpo_lro_ldes_max_adr[32] = { 1039 static u32 rpo_lro_ldes_max_adr[32] = {
@@ -1017,378 +1073,390 @@ void rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
1017 lro_max_number_of_descriptors); 1073 lro_max_number_of_descriptors);
1018} 1074}
1019 1075
1020void rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw, 1076void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
1021 u32 lro_time_base_divider) 1077 u32 lro_time_base_divider)
1022{ 1078{
1023 aq_hw_write_reg_bit(aq_hw, rpo_lro_tb_div_adr, 1079 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TB_DIV_ADR,
1024 rpo_lro_tb_div_msk, 1080 HW_ATL_RPO_LRO_TB_DIV_MSK,
1025 rpo_lro_tb_div_shift, 1081 HW_ATL_RPO_LRO_TB_DIV_SHIFT,
1026 lro_time_base_divider); 1082 lro_time_base_divider);
1027} 1083}
1028 1084
1029void rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw, 1085void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
1030 u32 lro_inactive_interval) 1086 u32 lro_inactive_interval)
1031{ 1087{
1032 aq_hw_write_reg_bit(aq_hw, rpo_lro_ina_ival_adr, 1088 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_INA_IVAL_ADR,
1033 rpo_lro_ina_ival_msk, 1089 HW_ATL_RPO_LRO_INA_IVAL_MSK,
1034 rpo_lro_ina_ival_shift, 1090 HW_ATL_RPO_LRO_INA_IVAL_SHIFT,
1035 lro_inactive_interval); 1091 lro_inactive_interval);
1036} 1092}
1037 1093
1038void rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw, 1094void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
1039 u32 lro_max_coalescing_interval) 1095 u32 lro_max_coal_interval)
1040{ 1096{
1041 aq_hw_write_reg_bit(aq_hw, rpo_lro_max_ival_adr, 1097 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_MAX_IVAL_ADR,
1042 rpo_lro_max_ival_msk, 1098 HW_ATL_RPO_LRO_MAX_IVAL_MSK,
1043 rpo_lro_max_ival_shift, 1099 HW_ATL_RPO_LRO_MAX_IVAL_SHIFT,
1044 lro_max_coalescing_interval); 1100 lro_max_coal_interval);
1045} 1101}
1046 1102
1047/* rx */ 1103/* rx */
1048void rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis) 1104void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis)
1049{ 1105{
1050 aq_hw_write_reg_bit(aq_hw, rx_reg_res_dsbl_adr, 1106 aq_hw_write_reg_bit(aq_hw, HW_ATL_RX_REG_RES_DSBL_ADR,
1051 rx_reg_res_dsbl_msk, 1107 HW_ATL_RX_REG_RES_DSBL_MSK,
1052 rx_reg_res_dsbl_shift, 1108 HW_ATL_RX_REG_RES_DSBL_SHIFT,
1053 rx_reg_res_dis); 1109 rx_reg_res_dis);
1054} 1110}
1055 1111
1056/* tdm */ 1112/* tdm */
1057void tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca) 1113void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
1058{ 1114{
1059 aq_hw_write_reg_bit(aq_hw, tdm_dcadcpuid_adr(dca), 1115 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADCPUID_ADR(dca),
1060 tdm_dcadcpuid_msk, 1116 HW_ATL_TDM_DCADCPUID_MSK,
1061 tdm_dcadcpuid_shift, cpuid); 1117 HW_ATL_TDM_DCADCPUID_SHIFT, cpuid);
1062} 1118}
1063 1119
1064void tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw, 1120void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
1065 u32 large_send_offload_en) 1121 u32 large_send_offload_en)
1066{ 1122{
1067 aq_hw_write_reg(aq_hw, tdm_lso_en_adr, large_send_offload_en); 1123 aq_hw_write_reg(aq_hw, HW_ATL_TDM_LSO_EN_ADR, large_send_offload_en);
1068} 1124}
1069 1125
1070void tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en) 1126void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en)
1071{ 1127{
1072 aq_hw_write_reg_bit(aq_hw, tdm_dca_en_adr, tdm_dca_en_msk, 1128 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_EN_ADR, HW_ATL_TDM_DCA_EN_MSK,
1073 tdm_dca_en_shift, tx_dca_en); 1129 HW_ATL_TDM_DCA_EN_SHIFT, tx_dca_en);
1074} 1130}
1075 1131
1076void tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode) 1132void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode)
1077{ 1133{
1078 aq_hw_write_reg_bit(aq_hw, tdm_dca_mode_adr, tdm_dca_mode_msk, 1134 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_MODE_ADR,
1079 tdm_dca_mode_shift, tx_dca_mode); 1135 HW_ATL_TDM_DCA_MODE_MSK,
1136 HW_ATL_TDM_DCA_MODE_SHIFT, tx_dca_mode);
1080} 1137}
1081 1138
1082void tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en, u32 dca) 1139void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en,
1140 u32 dca)
1083{ 1141{
1084 aq_hw_write_reg_bit(aq_hw, tdm_dcaddesc_en_adr(dca), 1142 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADDESC_EN_ADR(dca),
1085 tdm_dcaddesc_en_msk, tdm_dcaddesc_en_shift, 1143 HW_ATL_TDM_DCADDESC_EN_MSK,
1144 HW_ATL_TDM_DCADDESC_EN_SHIFT,
1086 tx_desc_dca_en); 1145 tx_desc_dca_en);
1087} 1146}
1088 1147
1089void tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en, u32 descriptor) 1148void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en,
1149 u32 descriptor)
1090{ 1150{
1091 aq_hw_write_reg_bit(aq_hw, tdm_descden_adr(descriptor), 1151 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDEN_ADR(descriptor),
1092 tdm_descden_msk, 1152 HW_ATL_TDM_DESCDEN_MSK,
1093 tdm_descden_shift, 1153 HW_ATL_TDM_DESCDEN_SHIFT,
1094 tx_desc_en); 1154 tx_desc_en);
1095} 1155}
1096 1156
1097u32 tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor) 1157u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
1098{ 1158{
1099 return aq_hw_read_reg_bit(aq_hw, tdm_descdhd_adr(descriptor), 1159 return aq_hw_read_reg_bit(aq_hw, HW_ATL_TDM_DESCDHD_ADR(descriptor),
1100 tdm_descdhd_msk, tdm_descdhd_shift); 1160 HW_ATL_TDM_DESCDHD_MSK,
1161 HW_ATL_TDM_DESCDHD_SHIFT);
1101} 1162}
1102 1163
1103void tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len, 1164void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
1104 u32 descriptor) 1165 u32 descriptor)
1105{ 1166{
1106 aq_hw_write_reg_bit(aq_hw, tdm_descdlen_adr(descriptor), 1167 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDLEN_ADR(descriptor),
1107 tdm_descdlen_msk, 1168 HW_ATL_TDM_DESCDLEN_MSK,
1108 tdm_descdlen_shift, 1169 HW_ATL_TDM_DESCDLEN_SHIFT,
1109 tx_desc_len); 1170 tx_desc_len);
1110} 1171}
1111 1172
1112void tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, 1173void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
1113 u32 tx_desc_wr_wb_irq_en) 1174 u32 tx_desc_wr_wb_irq_en)
1114{ 1175{
1115 aq_hw_write_reg_bit(aq_hw, tdm_int_desc_wrb_en_adr, 1176 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_DESC_WRB_EN_ADR,
1116 tdm_int_desc_wrb_en_msk, 1177 HW_ATL_TDM_INT_DESC_WRB_EN_MSK,
1117 tdm_int_desc_wrb_en_shift, 1178 HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT,
1118 tx_desc_wr_wb_irq_en); 1179 tx_desc_wr_wb_irq_en);
1119} 1180}
1120 1181
1121void tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw, 1182void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
1122 u32 tx_desc_wr_wb_threshold, 1183 u32 tx_desc_wr_wb_threshold,
1123 u32 descriptor) 1184 u32 descriptor)
1124{ 1185{
1125 aq_hw_write_reg_bit(aq_hw, tdm_descdwrb_thresh_adr(descriptor), 1186 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor),
1126 tdm_descdwrb_thresh_msk, 1187 HW_ATL_TDM_DESCDWRB_THRESH_MSK,
1127 tdm_descdwrb_thresh_shift, 1188 HW_ATL_TDM_DESCDWRB_THRESH_SHIFT,
1128 tx_desc_wr_wb_threshold); 1189 tx_desc_wr_wb_threshold);
1129} 1190}
1130 1191
1131void tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw, 1192void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
1132 u32 tdm_irq_moderation_en) 1193 u32 tdm_irq_moderation_en)
1133{ 1194{
1134 aq_hw_write_reg_bit(aq_hw, tdm_int_mod_en_adr, 1195 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_MOD_EN_ADR,
1135 tdm_int_mod_en_msk, 1196 HW_ATL_TDM_INT_MOD_EN_MSK,
1136 tdm_int_mod_en_shift, 1197 HW_ATL_TDM_INT_MOD_EN_SHIFT,
1137 tdm_irq_moderation_en); 1198 tdm_irq_moderation_en);
1138} 1199}
1139 1200
1140/* thm */ 1201/* thm */
1141void thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw, 1202void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
1142 u32 lso_tcp_flag_of_first_pkt) 1203 u32 lso_tcp_flag_of_first_pkt)
1143{ 1204{
1144 aq_hw_write_reg_bit(aq_hw, thm_lso_tcp_flag_first_adr, 1205 aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR,
1145 thm_lso_tcp_flag_first_msk, 1206 HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK,
1146 thm_lso_tcp_flag_first_shift, 1207 HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT,
1147 lso_tcp_flag_of_first_pkt); 1208 lso_tcp_flag_of_first_pkt);
1148} 1209}
1149 1210
1150void thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw, 1211void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
1151 u32 lso_tcp_flag_of_last_pkt) 1212 u32 lso_tcp_flag_of_last_pkt)
1152{ 1213{
1153 aq_hw_write_reg_bit(aq_hw, thm_lso_tcp_flag_last_adr, 1214 aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR,
1154 thm_lso_tcp_flag_last_msk, 1215 HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK,
1155 thm_lso_tcp_flag_last_shift, 1216 HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT,
1156 lso_tcp_flag_of_last_pkt); 1217 lso_tcp_flag_of_last_pkt);
1157} 1218}
1158 1219
1159void thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw, 1220void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
1160 u32 lso_tcp_flag_of_middle_pkt) 1221 u32 lso_tcp_flag_of_middle_pkt)
1161{ 1222{
1162 aq_hw_write_reg_bit(aq_hw, thm_lso_tcp_flag_mid_adr, 1223 aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_MID_ADR,
1163 thm_lso_tcp_flag_mid_msk, 1224 HW_ATL_THM_LSO_TCP_FLAG_MID_MSK,
1164 thm_lso_tcp_flag_mid_shift, 1225 HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT,
1165 lso_tcp_flag_of_middle_pkt); 1226 lso_tcp_flag_of_middle_pkt);
1166} 1227}
1167 1228
1168/* TPB: tx packet buffer */ 1229/* TPB: tx packet buffer */
1169void tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en) 1230void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en)
1170{ 1231{
1171 aq_hw_write_reg_bit(aq_hw, tpb_tx_buf_en_adr, tpb_tx_buf_en_msk, 1232 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_BUF_EN_ADR,
1172 tpb_tx_buf_en_shift, tx_buff_en); 1233 HW_ATL_TPB_TX_BUF_EN_MSK,
1234 HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en);
1173} 1235}
1174 1236
1175void tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, 1237void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1176 u32 tx_buff_hi_threshold_per_tc, 1238 u32 tx_buff_hi_threshold_per_tc,
1177 u32 buffer) 1239 u32 buffer)
1178{ 1240{
1179 aq_hw_write_reg_bit(aq_hw, tpb_txbhi_thresh_adr(buffer), 1241 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBHI_THRESH_ADR(buffer),
1180 tpb_txbhi_thresh_msk, tpb_txbhi_thresh_shift, 1242 HW_ATL_TPB_TXBHI_THRESH_MSK,
1243 HW_ATL_TPB_TXBHI_THRESH_SHIFT,
1181 tx_buff_hi_threshold_per_tc); 1244 tx_buff_hi_threshold_per_tc);
1182} 1245}
1183 1246
1184void tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, 1247void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1185 u32 tx_buff_lo_threshold_per_tc, 1248 u32 tx_buff_lo_threshold_per_tc,
1186 u32 buffer) 1249 u32 buffer)
1187{ 1250{
1188 aq_hw_write_reg_bit(aq_hw, tpb_txblo_thresh_adr(buffer), 1251 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBLO_THRESH_ADR(buffer),
1189 tpb_txblo_thresh_msk, tpb_txblo_thresh_shift, 1252 HW_ATL_TPB_TXBLO_THRESH_MSK,
1253 HW_ATL_TPB_TXBLO_THRESH_SHIFT,
1190 tx_buff_lo_threshold_per_tc); 1254 tx_buff_lo_threshold_per_tc);
1191} 1255}
1192 1256
1193void tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en) 1257void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en)
1194{ 1258{
1195 aq_hw_write_reg_bit(aq_hw, tpb_dma_sys_lbk_adr, 1259 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_SYS_LBK_ADR,
1196 tpb_dma_sys_lbk_msk, 1260 HW_ATL_TPB_DMA_SYS_LBK_MSK,
1197 tpb_dma_sys_lbk_shift, 1261 HW_ATL_TPB_DMA_SYS_LBK_SHIFT,
1198 tx_dma_sys_lbk_en); 1262 tx_dma_sys_lbk_en);
1199} 1263}
1200 1264
1201void tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, 1265void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
1202 u32 tx_pkt_buff_size_per_tc, u32 buffer) 1266 u32 tx_pkt_buff_size_per_tc, u32 buffer)
1203{ 1267{
1204 aq_hw_write_reg_bit(aq_hw, tpb_txbbuf_size_adr(buffer), 1268 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer),
1205 tpb_txbbuf_size_msk, 1269 HW_ATL_TPB_TXBBUF_SIZE_MSK,
1206 tpb_txbbuf_size_shift, 1270 HW_ATL_TPB_TXBBUF_SIZE_SHIFT,
1207 tx_pkt_buff_size_per_tc); 1271 tx_pkt_buff_size_per_tc);
1208} 1272}
1209 1273
1210void tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en) 1274void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en)
1211{ 1275{
1212 aq_hw_write_reg_bit(aq_hw, tpb_tx_scp_ins_en_adr, 1276 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_SCP_INS_EN_ADR,
1213 tpb_tx_scp_ins_en_msk, 1277 HW_ATL_TPB_TX_SCP_INS_EN_MSK,
1214 tpb_tx_scp_ins_en_shift, 1278 HW_ATL_TPB_TX_SCP_INS_EN_SHIFT,
1215 tx_path_scp_ins_en); 1279 tx_path_scp_ins_en);
1216} 1280}
1217 1281
1218/* TPO: tx packet offload */ 1282/* TPO: tx packet offload */
1219void tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, 1283void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
1220 u32 ipv4header_crc_offload_en) 1284 u32 ipv4header_crc_offload_en)
1221{ 1285{
1222 aq_hw_write_reg_bit(aq_hw, tpo_ipv4chk_en_adr, 1286 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_IPV4CHK_EN_ADR,
1223 tpo_ipv4chk_en_msk, 1287 HW_ATL_TPO_IPV4CHK_EN_MSK,
1224 tpo_ipv4chk_en_shift, 1288 HW_ATL_TPO_IPV4CHK_EN_SHIFT,
1225 ipv4header_crc_offload_en); 1289 ipv4header_crc_offload_en);
1226} 1290}
1227 1291
1228void tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, 1292void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
1229 u32 tcp_udp_crc_offload_en) 1293 u32 tcp_udp_crc_offload_en)
1230{ 1294{
1231 aq_hw_write_reg_bit(aq_hw, tpol4chk_en_adr, 1295 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPOL4CHK_EN_ADR,
1232 tpol4chk_en_msk, 1296 HW_ATL_TPOL4CHK_EN_MSK,
1233 tpol4chk_en_shift, 1297 HW_ATL_TPOL4CHK_EN_SHIFT,
1234 tcp_udp_crc_offload_en); 1298 tcp_udp_crc_offload_en);
1235} 1299}
1236 1300
1237void tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_pkt_sys_lbk_en) 1301void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw,
1302 u32 tx_pkt_sys_lbk_en)
1238{ 1303{
1239 aq_hw_write_reg_bit(aq_hw, tpo_pkt_sys_lbk_adr, 1304 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_PKT_SYS_LBK_ADR,
1240 tpo_pkt_sys_lbk_msk, 1305 HW_ATL_TPO_PKT_SYS_LBK_MSK,
1241 tpo_pkt_sys_lbk_shift, 1306 HW_ATL_TPO_PKT_SYS_LBK_SHIFT,
1242 tx_pkt_sys_lbk_en); 1307 tx_pkt_sys_lbk_en);
1243} 1308}
1244 1309
1245/* TPS: tx packet scheduler */ 1310/* TPS: tx packet scheduler */
1246void tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw, 1311void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
1247 u32 tx_pkt_shed_data_arb_mode) 1312 u32 tx_pkt_shed_data_arb_mode)
1248{ 1313{
1249 aq_hw_write_reg_bit(aq_hw, tps_data_tc_arb_mode_adr, 1314 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TC_ARB_MODE_ADR,
1250 tps_data_tc_arb_mode_msk, 1315 HW_ATL_TPS_DATA_TC_ARB_MODE_MSK,
1251 tps_data_tc_arb_mode_shift, 1316 HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT,
1252 tx_pkt_shed_data_arb_mode); 1317 tx_pkt_shed_data_arb_mode);
1253} 1318}
1254 1319
1255void tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw, 1320void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
1256 u32 curr_time_res) 1321 u32 curr_time_res)
1257{ 1322{
1258 aq_hw_write_reg_bit(aq_hw, tps_desc_rate_ta_rst_adr, 1323 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_TA_RST_ADR,
1259 tps_desc_rate_ta_rst_msk, 1324 HW_ATL_TPS_DESC_RATE_TA_RST_MSK,
1260 tps_desc_rate_ta_rst_shift, 1325 HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT,
1261 curr_time_res); 1326 curr_time_res);
1262} 1327}
1263 1328
1264void tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw, 1329void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
1265 u32 tx_pkt_shed_desc_rate_lim) 1330 u32 tx_pkt_shed_desc_rate_lim)
1266{ 1331{
1267 aq_hw_write_reg_bit(aq_hw, tps_desc_rate_lim_adr, 1332 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_LIM_ADR,
1268 tps_desc_rate_lim_msk, 1333 HW_ATL_TPS_DESC_RATE_LIM_MSK,
1269 tps_desc_rate_lim_shift, 1334 HW_ATL_TPS_DESC_RATE_LIM_SHIFT,
1270 tx_pkt_shed_desc_rate_lim); 1335 tx_pkt_shed_desc_rate_lim);
1271} 1336}
1272 1337
1273void tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw, 1338void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
1274 u32 tx_pkt_shed_desc_tc_arb_mode) 1339 u32 arb_mode)
1275{ 1340{
1276 aq_hw_write_reg_bit(aq_hw, tps_desc_tc_arb_mode_adr, 1341 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TC_ARB_MODE_ADR,
1277 tps_desc_tc_arb_mode_msk, 1342 HW_ATL_TPS_DESC_TC_ARB_MODE_MSK,
1278 tps_desc_tc_arb_mode_shift, 1343 HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT,
1279 tx_pkt_shed_desc_tc_arb_mode); 1344 arb_mode);
1280} 1345}
1281 1346
1282void tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw, 1347void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
1283 u32 tx_pkt_shed_desc_tc_max_credit, 1348 u32 max_credit,
1284 u32 tc) 1349 u32 tc)
1285{ 1350{
1286 aq_hw_write_reg_bit(aq_hw, tps_desc_tctcredit_max_adr(tc), 1351 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc),
1287 tps_desc_tctcredit_max_msk, 1352 HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK,
1288 tps_desc_tctcredit_max_shift, 1353 HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT,
1289 tx_pkt_shed_desc_tc_max_credit); 1354 max_credit);
1290} 1355}
1291 1356
1292void tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw, 1357void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
1293 u32 tx_pkt_shed_desc_tc_weight, u32 tc) 1358 u32 tx_pkt_shed_desc_tc_weight,
1359 u32 tc)
1294{ 1360{
1295 aq_hw_write_reg_bit(aq_hw, tps_desc_tctweight_adr(tc), 1361 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc),
1296 tps_desc_tctweight_msk, 1362 HW_ATL_TPS_DESC_TCTWEIGHT_MSK,
1297 tps_desc_tctweight_shift, 1363 HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT,
1298 tx_pkt_shed_desc_tc_weight); 1364 tx_pkt_shed_desc_tc_weight);
1299} 1365}
1300 1366
1301void tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw, 1367void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
1302 u32 tx_pkt_shed_desc_vm_arb_mode) 1368 u32 arb_mode)
1303{ 1369{
1304 aq_hw_write_reg_bit(aq_hw, tps_desc_vm_arb_mode_adr, 1370 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_VM_ARB_MODE_ADR,
1305 tps_desc_vm_arb_mode_msk, 1371 HW_ATL_TPS_DESC_VM_ARB_MODE_MSK,
1306 tps_desc_vm_arb_mode_shift, 1372 HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT,
1307 tx_pkt_shed_desc_vm_arb_mode); 1373 arb_mode);
1308} 1374}
1309 1375
1310void tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw, 1376void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
1311 u32 tx_pkt_shed_tc_data_max_credit, 1377 u32 max_credit,
1312 u32 tc) 1378 u32 tc)
1313{ 1379{
1314 aq_hw_write_reg_bit(aq_hw, tps_data_tctcredit_max_adr(tc), 1380 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc),
1315 tps_data_tctcredit_max_msk, 1381 HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK,
1316 tps_data_tctcredit_max_shift, 1382 HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT,
1317 tx_pkt_shed_tc_data_max_credit); 1383 max_credit);
1318} 1384}
1319 1385
1320void tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw, 1386void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
1321 u32 tx_pkt_shed_tc_data_weight, u32 tc) 1387 u32 tx_pkt_shed_tc_data_weight,
1388 u32 tc)
1322{ 1389{
1323 aq_hw_write_reg_bit(aq_hw, tps_data_tctweight_adr(tc), 1390 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc),
1324 tps_data_tctweight_msk, 1391 HW_ATL_TPS_DATA_TCTWEIGHT_MSK,
1325 tps_data_tctweight_shift, 1392 HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT,
1326 tx_pkt_shed_tc_data_weight); 1393 tx_pkt_shed_tc_data_weight);
1327} 1394}
1328 1395
1329/* tx */ 1396/* tx */
1330void tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis) 1397void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis)
1331{ 1398{
1332 aq_hw_write_reg_bit(aq_hw, tx_reg_res_dsbl_adr, 1399 aq_hw_write_reg_bit(aq_hw, HW_ATL_TX_REG_RES_DSBL_ADR,
1333 tx_reg_res_dsbl_msk, 1400 HW_ATL_TX_REG_RES_DSBL_MSK,
1334 tx_reg_res_dsbl_shift, tx_reg_res_dis); 1401 HW_ATL_TX_REG_RES_DSBL_SHIFT, tx_reg_res_dis);
1335} 1402}
1336 1403
1337/* msm */ 1404/* msm */
1338u32 msm_reg_access_status_get(struct aq_hw_s *aq_hw) 1405u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw)
1339{ 1406{
1340 return aq_hw_read_reg_bit(aq_hw, msm_reg_access_busy_adr, 1407 return aq_hw_read_reg_bit(aq_hw, HW_ATL_MSM_REG_ACCESS_BUSY_ADR,
1341 msm_reg_access_busy_msk, 1408 HW_ATL_MSM_REG_ACCESS_BUSY_MSK,
1342 msm_reg_access_busy_shift); 1409 HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT);
1343} 1410}
1344 1411
1345void msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw, 1412void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
1346 u32 reg_addr_for_indirect_addr) 1413 u32 reg_addr_for_indirect_addr)
1347{ 1414{
1348 aq_hw_write_reg_bit(aq_hw, msm_reg_addr_adr, 1415 aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_ADDR_ADR,
1349 msm_reg_addr_msk, 1416 HW_ATL_MSM_REG_ADDR_MSK,
1350 msm_reg_addr_shift, 1417 HW_ATL_MSM_REG_ADDR_SHIFT,
1351 reg_addr_for_indirect_addr); 1418 reg_addr_for_indirect_addr);
1352} 1419}
1353 1420
1354void msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe) 1421void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe)
1355{ 1422{
1356 aq_hw_write_reg_bit(aq_hw, msm_reg_rd_strobe_adr, 1423 aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_RD_STROBE_ADR,
1357 msm_reg_rd_strobe_msk, 1424 HW_ATL_MSM_REG_RD_STROBE_MSK,
1358 msm_reg_rd_strobe_shift, 1425 HW_ATL_MSM_REG_RD_STROBE_SHIFT,
1359 reg_rd_strobe); 1426 reg_rd_strobe);
1360} 1427}
1361 1428
1362u32 msm_reg_rd_data_get(struct aq_hw_s *aq_hw) 1429u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw)
1363{ 1430{
1364 return aq_hw_read_reg(aq_hw, msm_reg_rd_data_adr); 1431 return aq_hw_read_reg(aq_hw, HW_ATL_MSM_REG_RD_DATA_ADR);
1365} 1432}
1366 1433
1367void msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data) 1434void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data)
1368{ 1435{
1369 aq_hw_write_reg(aq_hw, msm_reg_wr_data_adr, reg_wr_data); 1436 aq_hw_write_reg(aq_hw, HW_ATL_MSM_REG_WR_DATA_ADR, reg_wr_data);
1370} 1437}
1371 1438
1372void msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe) 1439void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe)
1373{ 1440{
1374 aq_hw_write_reg_bit(aq_hw, msm_reg_wr_strobe_adr, 1441 aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_WR_STROBE_ADR,
1375 msm_reg_wr_strobe_msk, 1442 HW_ATL_MSM_REG_WR_STROBE_MSK,
1376 msm_reg_wr_strobe_shift, 1443 HW_ATL_MSM_REG_WR_STROBE_SHIFT,
1377 reg_wr_strobe); 1444 reg_wr_strobe);
1378} 1445}
1379 1446
1380/* pci */ 1447/* pci */
1381void pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis) 1448void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis)
1382{ 1449{
1383 aq_hw_write_reg_bit(aq_hw, pci_reg_res_dsbl_adr, 1450 aq_hw_write_reg_bit(aq_hw, HW_ATL_PCI_REG_RES_DSBL_ADR,
1384 pci_reg_res_dsbl_msk, 1451 HW_ATL_PCI_REG_RES_DSBL_MSK,
1385 pci_reg_res_dsbl_shift, 1452 HW_ATL_PCI_REG_RES_DSBL_SHIFT,
1386 pci_reg_res_dis); 1453 pci_reg_res_dis);
1387} 1454}
1388 1455
1389void reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw, u32 glb_cpu_scratch_scp, 1456void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
1390 u32 scratch_scp) 1457 u32 glb_cpu_scratch_scp,
1458 u32 scratch_scp)
1391{ 1459{
1392 aq_hw_write_reg(aq_hw, glb_cpu_scratch_scp_adr(scratch_scp), 1460 aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp),
1393 glb_cpu_scratch_scp); 1461 glb_cpu_scratch_scp);
1394} 1462}
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h
index ed1085b95adb..dfb426f2dc2c 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h
@@ -21,657 +21,681 @@ struct aq_hw_s;
21/* global */ 21/* global */
22 22
23/* set global microprocessor semaphore */ 23/* set global microprocessor semaphore */
24void reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem, 24void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem,
25 u32 semaphore); 25 u32 semaphore);
26 26
27/* get global microprocessor semaphore */ 27/* get global microprocessor semaphore */
28u32 reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore); 28u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore);
29 29
30/* set global register reset disable */ 30/* set global register reset disable */
31void glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis); 31void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis);
32 32
33/* set soft reset */ 33/* set soft reset */
34void glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res); 34void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res);
35 35
36/* get soft reset */ 36/* get soft reset */
37u32 glb_soft_res_get(struct aq_hw_s *aq_hw); 37u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw);
38 38
39/* stats */ 39/* stats */
40 40
41u32 rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw); 41u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw);
42 42
43/* get rx dma good octet counter lsw */ 43/* get rx dma good octet counter lsw */
44u32 stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw); 44u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
45 45
46/* get rx dma good packet counter lsw */ 46/* get rx dma good packet counter lsw */
47u32 stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw); 47u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
48 48
49/* get tx dma good octet counter lsw */ 49/* get tx dma good octet counter lsw */
50u32 stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw); 50u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
51 51
52/* get tx dma good packet counter lsw */ 52/* get tx dma good packet counter lsw */
53u32 stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw); 53u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
54 54
55/* get rx dma good octet counter msw */ 55/* get rx dma good octet counter msw */
56u32 stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw); 56u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
57 57
58/* get rx dma good packet counter msw */ 58/* get rx dma good packet counter msw */
59u32 stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw); 59u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
60 60
61/* get tx dma good octet counter msw */ 61/* get tx dma good octet counter msw */
62u32 stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw); 62u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
63 63
64/* get tx dma good packet counter msw */ 64/* get tx dma good packet counter msw */
65u32 stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw); 65u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
66 66
67/* get msm rx errors counter register */ 67/* get msm rx errors counter register */
68u32 reg_mac_msm_rx_errs_cnt_get(struct aq_hw_s *aq_hw); 68u32 hw_atl_reg_mac_msm_rx_errs_cnt_get(struct aq_hw_s *aq_hw);
69 69
70/* get msm rx unicast frames counter register */ 70/* get msm rx unicast frames counter register */
71u32 reg_mac_msm_rx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw); 71u32 hw_atl_reg_mac_msm_rx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);
72 72
73/* get msm rx multicast frames counter register */ 73/* get msm rx multicast frames counter register */
74u32 reg_mac_msm_rx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw); 74u32 hw_atl_reg_mac_msm_rx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);
75 75
76/* get msm rx broadcast frames counter register */ 76/* get msm rx broadcast frames counter register */
77u32 reg_mac_msm_rx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw); 77u32 hw_atl_reg_mac_msm_rx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);
78 78
79/* get msm rx broadcast octets counter register 1 */ 79/* get msm rx broadcast octets counter register 1 */
80u32 reg_mac_msm_rx_bcst_octets_counter1get(struct aq_hw_s *aq_hw); 80u32 hw_atl_reg_mac_msm_rx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);
81 81
82/* get msm rx unicast octets counter register 0 */ 82/* get msm rx unicast octets counter register 0 */
83u32 reg_mac_msm_rx_ucst_octets_counter0get(struct aq_hw_s *aq_hw); 83u32 hw_atl_reg_mac_msm_rx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);
84 84
85/* get rx dma statistics counter 7 */ 85/* get rx dma statistics counter 7 */
86u32 reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw); 86u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw);
87 87
88/* get msm tx errors counter register */ 88/* get msm tx errors counter register */
89u32 reg_mac_msm_tx_errs_cnt_get(struct aq_hw_s *aq_hw); 89u32 hw_atl_reg_mac_msm_tx_errs_cnt_get(struct aq_hw_s *aq_hw);
90 90
91/* get msm tx unicast frames counter register */ 91/* get msm tx unicast frames counter register */
92u32 reg_mac_msm_tx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw); 92u32 hw_atl_reg_mac_msm_tx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);
93 93
94/* get msm tx multicast frames counter register */ 94/* get msm tx multicast frames counter register */
95u32 reg_mac_msm_tx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw); 95u32 hw_atl_reg_mac_msm_tx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);
96 96
97/* get msm tx broadcast frames counter register */ 97/* get msm tx broadcast frames counter register */
98u32 reg_mac_msm_tx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw); 98u32 hw_atl_reg_mac_msm_tx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);
99 99
100/* get msm tx multicast octets counter register 1 */ 100/* get msm tx multicast octets counter register 1 */
101u32 reg_mac_msm_tx_mcst_octets_counter1get(struct aq_hw_s *aq_hw); 101u32 hw_atl_reg_mac_msm_tx_mcst_octets_counter1get(struct aq_hw_s *aq_hw);
102 102
103/* get msm tx broadcast octets counter register 1 */ 103/* get msm tx broadcast octets counter register 1 */
104u32 reg_mac_msm_tx_bcst_octets_counter1get(struct aq_hw_s *aq_hw); 104u32 hw_atl_reg_mac_msm_tx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);
105 105
106/* get msm tx unicast octets counter register 0 */ 106/* get msm tx unicast octets counter register 0 */
107u32 reg_mac_msm_tx_ucst_octets_counter0get(struct aq_hw_s *aq_hw); 107u32 hw_atl_reg_mac_msm_tx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);
108 108
109/* get global mif identification */ 109/* get global mif identification */
110u32 reg_glb_mif_id_get(struct aq_hw_s *aq_hw); 110u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw);
111 111
112/* interrupt */ 112/* interrupt */
113 113
114/* set interrupt auto mask lsw */ 114/* set interrupt auto mask lsw */
115void itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw, u32 irq_auto_masklsw); 115void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw,
116 u32 irq_auto_masklsw);
116 117
117/* set interrupt mapping enable rx */ 118/* set interrupt mapping enable rx */
118void itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, u32 rx); 119void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx,
120 u32 rx);
119 121
120/* set interrupt mapping enable tx */ 122/* set interrupt mapping enable tx */
121void itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, u32 tx); 123void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx,
124 u32 tx);
122 125
123/* set interrupt mapping rx */ 126/* set interrupt mapping rx */
124void itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx); 127void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx);
125 128
126/* set interrupt mapping tx */ 129/* set interrupt mapping tx */
127void itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx); 130void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx);
128 131
129/* set interrupt mask clear lsw */ 132/* set interrupt mask clear lsw */
130void itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_clearlsw); 133void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw,
134 u32 irq_msk_clearlsw);
131 135
132/* set interrupt mask set lsw */ 136/* set interrupt mask set lsw */
133void itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw); 137void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw);
134 138
135/* set interrupt register reset disable */ 139/* set interrupt register reset disable */
136void itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis); 140void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis);
137 141
138/* set interrupt status clear lsw */ 142/* set interrupt status clear lsw */
139void itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw, 143void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
140 u32 irq_status_clearlsw); 144 u32 irq_status_clearlsw);
141 145
142/* get interrupt status lsw */ 146/* get interrupt status lsw */
143u32 itr_irq_statuslsw_get(struct aq_hw_s *aq_hw); 147u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw);
144 148
145/* get reset interrupt */ 149/* get reset interrupt */
146u32 itr_res_irq_get(struct aq_hw_s *aq_hw); 150u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw);
147 151
148/* set reset interrupt */ 152/* set reset interrupt */
149void itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq); 153void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq);
150 154
151/* rdm */ 155/* rdm */
152 156
153/* set cpu id */ 157/* set cpu id */
154void rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca); 158void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca);
155 159
156/* set rx dca enable */ 160/* set rx dca enable */
157void rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en); 161void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en);
158 162
159/* set rx dca mode */ 163/* set rx dca mode */
160void rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode); 164void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode);
161 165
162/* set rx descriptor data buffer size */ 166/* set rx descriptor data buffer size */
163void rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw, 167void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
164 u32 rx_desc_data_buff_size, 168 u32 rx_desc_data_buff_size,
165 u32 descriptor); 169 u32 descriptor);
166 170
167/* set rx descriptor dca enable */ 171/* set rx descriptor dca enable */
168void rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en, 172void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
169 u32 dca); 173 u32 dca);
170 174
171/* set rx descriptor enable */ 175/* set rx descriptor enable */
172void rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en, 176void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
173 u32 descriptor); 177 u32 descriptor);
174 178
175/* set rx descriptor header splitting */ 179/* set rx descriptor header splitting */
176void rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw, 180void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
177 u32 rx_desc_head_splitting, 181 u32 rx_desc_head_splitting,
178 u32 descriptor); 182 u32 descriptor);
179 183
180/* get rx descriptor head pointer */ 184/* get rx descriptor head pointer */
181u32 rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor); 185u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor);
182 186
183/* set rx descriptor length */ 187/* set rx descriptor length */
184void rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len, 188void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
185 u32 descriptor); 189 u32 descriptor);
186 190
187/* set rx descriptor write-back interrupt enable */ 191/* set rx descriptor write-back interrupt enable */
188void rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, 192void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
189 u32 rx_desc_wr_wb_irq_en); 193 u32 rx_desc_wr_wb_irq_en);
190 194
191/* set rx header dca enable */ 195/* set rx header dca enable */
192void rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en, 196void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
193 u32 dca); 197 u32 dca);
194 198
195/* set rx payload dca enable */ 199/* set rx payload dca enable */
196void rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, u32 dca); 200void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en,
201 u32 dca);
197 202
198/* set rx descriptor header buffer size */ 203/* set rx descriptor header buffer size */
199void rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw, 204void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
200 u32 rx_desc_head_buff_size, 205 u32 rx_desc_head_buff_size,
201 u32 descriptor); 206 u32 descriptor);
202 207
203/* set rx descriptor reset */ 208/* set rx descriptor reset */
204void rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res, 209void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
205 u32 descriptor); 210 u32 descriptor);
206 211
207/* Set RDM Interrupt Moderation Enable */ 212/* Set RDM Interrupt Moderation Enable */
208void rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, u32 rdm_intr_moder_en); 213void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
214 u32 rdm_intr_moder_en);
209 215
210/* reg */ 216/* reg */
211 217
212/* set general interrupt mapping register */ 218/* set general interrupt mapping register */
213void reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map, u32 regidx); 219void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map,
220 u32 regidx);
214 221
215/* get general interrupt status register */ 222/* get general interrupt status register */
216u32 reg_gen_irq_status_get(struct aq_hw_s *aq_hw); 223u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw);
217 224
218/* set interrupt global control register */ 225/* set interrupt global control register */
219void reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl); 226void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl);
220 227
221/* set interrupt throttle register */ 228/* set interrupt throttle register */
222void reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle); 229void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle);
223 230
224/* set rx dma descriptor base address lsw */ 231/* set rx dma descriptor base address lsw */
225void reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, 232void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
226 u32 rx_dma_desc_base_addrlsw, 233 u32 rx_dma_desc_base_addrlsw,
227 u32 descriptor); 234 u32 descriptor);
228 235
229/* set rx dma descriptor base address msw */ 236/* set rx dma descriptor base address msw */
230void reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, 237void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
231 u32 rx_dma_desc_base_addrmsw, 238 u32 rx_dma_desc_base_addrmsw,
232 u32 descriptor); 239 u32 descriptor);
233 240
234/* get rx dma descriptor status register */ 241/* get rx dma descriptor status register */
235u32 reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor); 242u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor);
236 243
237/* set rx dma descriptor tail pointer register */ 244/* set rx dma descriptor tail pointer register */
238void reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, 245void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
239 u32 rx_dma_desc_tail_ptr, 246 u32 rx_dma_desc_tail_ptr,
240 u32 descriptor); 247 u32 descriptor);
241 248
242/* set rx filter multicast filter mask register */ 249/* set rx filter multicast filter mask register */
243void reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw, 250void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
244 u32 rx_flr_mcst_flr_msk); 251 u32 rx_flr_mcst_flr_msk);
245 252
246/* set rx filter multicast filter register */ 253/* set rx filter multicast filter register */
247void reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr, 254void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
248 u32 filter); 255 u32 filter);
249 256
250/* set rx filter rss control register 1 */ 257/* set rx filter rss control register 1 */
251void reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw, 258void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,
252 u32 rx_flr_rss_control1); 259 u32 rx_flr_rss_control1);
253 260
254/* Set RX Filter Control Register 2 */ 261/* Set RX Filter Control Register 2 */
255void reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_flr_control2); 262void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_flr_control2);
256 263
257/* Set RX Interrupt Moderation Control Register */ 264/* Set RX Interrupt Moderation Control Register */
258void reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, 265void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
259 u32 rx_intr_moderation_ctl, 266 u32 rx_intr_moderation_ctl,
260 u32 queue); 267 u32 queue);
261 268
262/* set tx dma debug control */ 269/* set tx dma debug control */
263void reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw, u32 tx_dma_debug_ctl); 270void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw,
271 u32 tx_dma_debug_ctl);
264 272
265/* set tx dma descriptor base address lsw */ 273/* set tx dma descriptor base address lsw */
266void reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, 274void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
267 u32 tx_dma_desc_base_addrlsw, 275 u32 tx_dma_desc_base_addrlsw,
268 u32 descriptor); 276 u32 descriptor);
269 277
270/* set tx dma descriptor base address msw */ 278/* set tx dma descriptor base address msw */
271void reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, 279void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
272 u32 tx_dma_desc_base_addrmsw, 280 u32 tx_dma_desc_base_addrmsw,
273 u32 descriptor); 281 u32 descriptor);
274 282
275/* set tx dma descriptor tail pointer register */ 283/* set tx dma descriptor tail pointer register */
276void reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, 284void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
277 u32 tx_dma_desc_tail_ptr, 285 u32 tx_dma_desc_tail_ptr,
278 u32 descriptor); 286 u32 descriptor);
279 287
280/* Set TX Interrupt Moderation Control Register */ 288/* Set TX Interrupt Moderation Control Register */
281void reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, 289void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
282 u32 tx_intr_moderation_ctl, 290 u32 tx_intr_moderation_ctl,
283 u32 queue); 291 u32 queue);
284 292
285/* set global microprocessor scratch pad */ 293/* set global microprocessor scratch pad */
286void reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw, 294void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
287 u32 glb_cpu_scratch_scp, u32 scratch_scp); 295 u32 glb_cpu_scratch_scp,
296 u32 scratch_scp);
288 297
289/* rpb */ 298/* rpb */
290 299
291/* set dma system loopback */ 300/* set dma system loopback */
292void rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk); 301void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk);
293 302
294/* set rx traffic class mode */ 303/* set rx traffic class mode */
295void rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw, 304void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
296 u32 rx_traf_class_mode); 305 u32 rx_traf_class_mode);
297 306
298/* set rx buffer enable */ 307/* set rx buffer enable */
299void rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en); 308void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en);
300 309
301/* set rx buffer high threshold (per tc) */ 310/* set rx buffer high threshold (per tc) */
302void rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, 311void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
303 u32 rx_buff_hi_threshold_per_tc, 312 u32 rx_buff_hi_threshold_per_tc,
304 u32 buffer); 313 u32 buffer);
305 314
306/* set rx buffer low threshold (per tc) */ 315/* set rx buffer low threshold (per tc) */
307void rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, 316void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
308 u32 rx_buff_lo_threshold_per_tc, 317 u32 rx_buff_lo_threshold_per_tc,
309 u32 buffer); 318 u32 buffer);
310 319
311/* set rx flow control mode */ 320/* set rx flow control mode */
312void rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode); 321void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode);
313 322
314/* set rx packet buffer size (per tc) */ 323/* set rx packet buffer size (per tc) */
315void rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, 324void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
316 u32 rx_pkt_buff_size_per_tc, 325 u32 rx_pkt_buff_size_per_tc,
317 u32 buffer); 326 u32 buffer);
318 327
319/* set rx xoff enable (per tc) */ 328/* set rx xoff enable (per tc) */
320void rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc, 329void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
321 u32 buffer); 330 u32 buffer);
322 331
323/* rpf */ 332/* rpf */
324 333
325/* set l2 broadcast count threshold */ 334/* set l2 broadcast count threshold */
326void rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw, 335void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
327 u32 l2broadcast_count_threshold); 336 u32 l2broadcast_count_threshold);
328 337
329/* set l2 broadcast enable */ 338/* set l2 broadcast enable */
330void rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en); 339void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en);
331 340
332/* set l2 broadcast filter action */ 341/* set l2 broadcast filter action */
333void rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw, 342void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,
334 u32 l2broadcast_flr_act); 343 u32 l2broadcast_flr_act);
335 344
336/* set l2 multicast filter enable */ 345/* set l2 multicast filter enable */
337void rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, u32 l2multicast_flr_en, 346void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,
338 u32 filter); 347 u32 l2multicast_flr_en,
348 u32 filter);
339 349
340/* set l2 promiscuous mode enable */ 350/* set l2 promiscuous mode enable */
341void rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw, 351void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
342 u32 l2promiscuous_mode_en); 352 u32 l2promiscuous_mode_en);
343 353
344/* set l2 unicast filter action */ 354/* set l2 unicast filter action */
345void rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_act, 355void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw,
346 u32 filter); 356 u32 l2unicast_flr_act,
357 u32 filter);
347 358
348/* set l2 unicast filter enable */ 359/* set l2 unicast filter enable */
349void rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en, 360void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
350 u32 filter); 361 u32 filter);
351 362
352/* set l2 unicast destination address lsw */ 363/* set l2 unicast destination address lsw */
353void rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw, 364void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
354 u32 l2unicast_dest_addresslsw, 365 u32 l2unicast_dest_addresslsw,
355 u32 filter); 366 u32 filter);
356 367
357/* set l2 unicast destination address msw */ 368/* set l2 unicast destination address msw */
358void rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw, 369void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
359 u32 l2unicast_dest_addressmsw, 370 u32 l2unicast_dest_addressmsw,
360 u32 filter); 371 u32 filter);
361 372
362/* Set L2 Accept all Multicast packets */ 373/* Set L2 Accept all Multicast packets */
363void rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw, 374void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
364 u32 l2_accept_all_mc_packets); 375 u32 l2_accept_all_mc_packets);
365 376
366/* set user-priority tc mapping */ 377/* set user-priority tc mapping */
367void rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw, 378void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
368 u32 user_priority_tc_map, u32 tc); 379 u32 user_priority_tc_map, u32 tc);
369 380
370/* set rss key address */ 381/* set rss key address */
371void rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr); 382void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr);
372 383
373/* set rss key write data */ 384/* set rss key write data */
374void rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data); 385void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data);
375 386
376/* get rss key write enable */ 387/* get rss key write enable */
377u32 rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw); 388u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw);
378 389
379/* set rss key write enable */ 390/* set rss key write enable */
380void rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en); 391void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en);
381 392
382/* set rss redirection table address */ 393/* set rss redirection table address */
383void rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw, 394void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,
384 u32 rss_redir_tbl_addr); 395 u32 rss_redir_tbl_addr);
385 396
386/* set rss redirection table write data */ 397/* set rss redirection table write data */
387void rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw, 398void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
388 u32 rss_redir_tbl_wr_data); 399 u32 rss_redir_tbl_wr_data);
389 400
390/* get rss redirection write enable */ 401/* get rss redirection write enable */
391u32 rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw); 402u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw);
392 403
393/* set rss redirection write enable */ 404/* set rss redirection write enable */
394void rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en); 405void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en);
395 406
396/* set tpo to rpf system loopback */ 407/* set tpo to rpf system loopback */
397void rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw, 408void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,
398 u32 tpo_to_rpf_sys_lbk); 409 u32 tpo_to_rpf_sys_lbk);
399 410
400/* set vlan inner ethertype */ 411/* set vlan inner ethertype */
401void rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht); 412void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht);
402 413
403/* set vlan outer ethertype */ 414/* set vlan outer ethertype */
404void rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht); 415void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht);
405 416
406/* set vlan promiscuous mode enable */ 417/* set vlan promiscuous mode enable */
407void rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, u32 vlan_prom_mode_en); 418void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,
419 u32 vlan_prom_mode_en);
408 420
409/* Set VLAN untagged action */ 421/* Set VLAN untagged action */
410void rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, u32 vlan_untagged_act); 422void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,
423 u32 vlan_untagged_act);
411 424
412/* Set VLAN accept untagged packets */ 425/* Set VLAN accept untagged packets */
413void rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw, 426void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
414 u32 vlan_accept_untagged_packets); 427 u32 vlan_acc_untagged_packets);
415 428
416/* Set VLAN filter enable */ 429/* Set VLAN filter enable */
417void rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en, u32 filter); 430void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en,
431 u32 filter);
418 432
419/* Set VLAN Filter Action */ 433/* Set VLAN Filter Action */
420void rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_filter_act, 434void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_filter_act,
421 u32 filter); 435 u32 filter);
422 436
423/* Set VLAN ID Filter */ 437/* Set VLAN ID Filter */
424void rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, u32 filter); 438void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
439 u32 filter);
425 440
426/* set ethertype filter enable */ 441/* set ethertype filter enable */
427void rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en, u32 filter); 442void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
443 u32 filter);
428 444
429/* set ethertype user-priority enable */ 445/* set ethertype user-priority enable */
430void rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw, 446void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
431 u32 etht_user_priority_en, u32 filter); 447 u32 etht_user_priority_en,
448 u32 filter);
432 449
433/* set ethertype rx queue enable */ 450/* set ethertype rx queue enable */
434void rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue_en, 451void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,
435 u32 filter); 452 u32 etht_rx_queue_en,
453 u32 filter);
436 454
437/* set ethertype rx queue */ 455/* set ethertype rx queue */
438void rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue, 456void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
439 u32 filter); 457 u32 filter);
440 458
441/* set ethertype user-priority */ 459/* set ethertype user-priority */
442void rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, u32 etht_user_priority, 460void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,
443 u32 filter); 461 u32 etht_user_priority,
462 u32 filter);
444 463
445/* set ethertype management queue */ 464/* set ethertype management queue */
446void rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue, 465void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
447 u32 filter); 466 u32 filter);
448 467
449/* set ethertype filter action */ 468/* set ethertype filter action */
450void rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act, 469void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
451 u32 filter); 470 u32 filter);
452 471
453/* set ethertype filter */ 472/* set ethertype filter */
454void rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter); 473void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter);
455 474
456/* rpo */ 475/* rpo */
457 476
458/* set ipv4 header checksum offload enable */ 477/* set ipv4 header checksum offload enable */
459void rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, 478void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
460 u32 ipv4header_crc_offload_en); 479 u32 ipv4header_crc_offload_en);
461 480
462/* set rx descriptor vlan stripping */ 481/* set rx descriptor vlan stripping */
463void rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw, 482void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
464 u32 rx_desc_vlan_stripping, 483 u32 rx_desc_vlan_stripping,
465 u32 descriptor); 484 u32 descriptor);
466 485
467/* set tcp/udp checksum offload enable */ 486/* set tcp/udp checksum offload enable */
468void rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, 487void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
469 u32 tcp_udp_crc_offload_en); 488 u32 tcp_udp_crc_offload_en);
470 489
471/* Set LRO Patch Optimization Enable. */ 490/* Set LRO Patch Optimization Enable. */
472void rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw, 491void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
473 u32 lro_patch_optimization_en); 492 u32 lro_patch_optimization_en);
474 493
475/* Set Large Receive Offload Enable */ 494/* Set Large Receive Offload Enable */
476void rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en); 495void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en);
477 496
478/* Set LRO Q Sessions Limit */ 497/* Set LRO Q Sessions Limit */
479void rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw, u32 lro_qsessions_lim); 498void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
499 u32 lro_qsessions_lim);
480 500
481/* Set LRO Total Descriptor Limit */ 501/* Set LRO Total Descriptor Limit */
482void rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw, u32 lro_total_desc_lim); 502void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw,
503 u32 lro_total_desc_lim);
483 504
484/* Set LRO Min Payload of First Packet */ 505/* Set LRO Min Payload of First Packet */
485void rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw, 506void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
486 u32 lro_min_pld_of_first_pkt); 507 u32 lro_min_pld_of_first_pkt);
487 508
488/* Set LRO Packet Limit */ 509/* Set LRO Packet Limit */
489void rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_packet_lim); 510void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_packet_lim);
490 511
491/* Set LRO Max Number of Descriptors */ 512/* Set LRO Max Number of Descriptors */
492void rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw, 513void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
493 u32 lro_max_desc_num, u32 lro); 514 u32 lro_max_desc_num, u32 lro);
494 515
495/* Set LRO Time Base Divider */ 516/* Set LRO Time Base Divider */
496void rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw, 517void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
497 u32 lro_time_base_divider); 518 u32 lro_time_base_divider);
498 519
499/*Set LRO Inactive Interval */ 520/*Set LRO Inactive Interval */
500void rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw, 521void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
501 u32 lro_inactive_interval); 522 u32 lro_inactive_interval);
502 523
503/*Set LRO Max Coalescing Interval */ 524/*Set LRO Max Coalescing Interval */
504void rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw, 525void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
505 u32 lro_max_coalescing_interval); 526 u32 lro_max_coal_interval);
506 527
507/* rx */ 528/* rx */
508 529
509/* set rx register reset disable */ 530/* set rx register reset disable */
510void rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis); 531void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis);
511 532
512/* tdm */ 533/* tdm */
513 534
514/* set cpu id */ 535/* set cpu id */
515void tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca); 536void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca);
516 537
517/* set large send offload enable */ 538/* set large send offload enable */
518void tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw, 539void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
519 u32 large_send_offload_en); 540 u32 large_send_offload_en);
520 541
521/* set tx descriptor enable */ 542/* set tx descriptor enable */
522void tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en, u32 descriptor); 543void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en,
544 u32 descriptor);
523 545
524/* set tx dca enable */ 546/* set tx dca enable */
525void tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en); 547void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en);
526 548
527/* set tx dca mode */ 549/* set tx dca mode */
528void tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode); 550void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode);
529 551
530/* set tx descriptor dca enable */ 552/* set tx descriptor dca enable */
531void tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en, u32 dca); 553void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en,
554 u32 dca);
532 555
533/* get tx descriptor head pointer */ 556/* get tx descriptor head pointer */
534u32 tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor); 557u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor);
535 558
536/* set tx descriptor length */ 559/* set tx descriptor length */
537void tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len, 560void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
538 u32 descriptor); 561 u32 descriptor);
539 562
540/* set tx descriptor write-back interrupt enable */ 563/* set tx descriptor write-back interrupt enable */
541void tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, 564void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
542 u32 tx_desc_wr_wb_irq_en); 565 u32 tx_desc_wr_wb_irq_en);
543 566
544/* set tx descriptor write-back threshold */ 567/* set tx descriptor write-back threshold */
545void tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw, 568void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
546 u32 tx_desc_wr_wb_threshold, 569 u32 tx_desc_wr_wb_threshold,
547 u32 descriptor); 570 u32 descriptor);
548 571
549/* Set TDM Interrupt Moderation Enable */ 572/* Set TDM Interrupt Moderation Enable */
550void tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw, 573void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
551 u32 tdm_irq_moderation_en); 574 u32 tdm_irq_moderation_en);
552/* thm */ 575/* thm */
553 576
554/* set lso tcp flag of first packet */ 577/* set lso tcp flag of first packet */
555void thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw, 578void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
556 u32 lso_tcp_flag_of_first_pkt); 579 u32 lso_tcp_flag_of_first_pkt);
557 580
558/* set lso tcp flag of last packet */ 581/* set lso tcp flag of last packet */
559void thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw, 582void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
560 u32 lso_tcp_flag_of_last_pkt); 583 u32 lso_tcp_flag_of_last_pkt);
561 584
562/* set lso tcp flag of middle packet */ 585/* set lso tcp flag of middle packet */
563void thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw, 586void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
564 u32 lso_tcp_flag_of_middle_pkt); 587 u32 lso_tcp_flag_of_middle_pkt);
565 588
566/* tpb */ 589/* tpb */
567 590
568/* set tx buffer enable */ 591/* set tx buffer enable */
569void tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en); 592void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en);
570 593
571/* set tx buffer high threshold (per tc) */ 594/* set tx buffer high threshold (per tc) */
572void tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, 595void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
573 u32 tx_buff_hi_threshold_per_tc, 596 u32 tx_buff_hi_threshold_per_tc,
574 u32 buffer); 597 u32 buffer);
575 598
576/* set tx buffer low threshold (per tc) */ 599/* set tx buffer low threshold (per tc) */
577void tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, 600void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
578 u32 tx_buff_lo_threshold_per_tc, 601 u32 tx_buff_lo_threshold_per_tc,
579 u32 buffer); 602 u32 buffer);
580 603
581/* set tx dma system loopback enable */ 604/* set tx dma system loopback enable */
582void tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en); 605void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en);
583 606
584/* set tx packet buffer size (per tc) */ 607/* set tx packet buffer size (per tc) */
585void tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, 608void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
586 u32 tx_pkt_buff_size_per_tc, u32 buffer); 609 u32 tx_pkt_buff_size_per_tc, u32 buffer);
587 610
588/* set tx path pad insert enable */ 611/* set tx path pad insert enable */
589void tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en); 612void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en);
590 613
591/* tpo */ 614/* tpo */
592 615
593/* set ipv4 header checksum offload enable */ 616/* set ipv4 header checksum offload enable */
594void tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, 617void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
595 u32 ipv4header_crc_offload_en); 618 u32 ipv4header_crc_offload_en);
596 619
597/* set tcp/udp checksum offload enable */ 620/* set tcp/udp checksum offload enable */
598void tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, 621void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
599 u32 tcp_udp_crc_offload_en); 622 u32 tcp_udp_crc_offload_en);
600 623
601/* set tx pkt system loopback enable */ 624/* set tx pkt system loopback enable */
602void tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_pkt_sys_lbk_en); 625void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw,
626 u32 tx_pkt_sys_lbk_en);
603 627
604/* tps */ 628/* tps */
605 629
606/* set tx packet scheduler data arbitration mode */ 630/* set tx packet scheduler data arbitration mode */
607void tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw, 631void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
608 u32 tx_pkt_shed_data_arb_mode); 632 u32 tx_pkt_shed_data_arb_mode);
609 633
610/* set tx packet scheduler descriptor rate current time reset */ 634/* set tx packet scheduler descriptor rate current time reset */
611void tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw, 635void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
612 u32 curr_time_res); 636 u32 curr_time_res);
613 637
614/* set tx packet scheduler descriptor rate limit */ 638/* set tx packet scheduler descriptor rate limit */
615void tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw, 639void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
616 u32 tx_pkt_shed_desc_rate_lim); 640 u32 tx_pkt_shed_desc_rate_lim);
617 641
618/* set tx packet scheduler descriptor tc arbitration mode */ 642/* set tx packet scheduler descriptor tc arbitration mode */
619void tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw, 643void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
620 u32 tx_pkt_shed_desc_tc_arb_mode); 644 u32 arb_mode);
621 645
622/* set tx packet scheduler descriptor tc max credit */ 646/* set tx packet scheduler descriptor tc max credit */
623void tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw, 647void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
624 u32 tx_pkt_shed_desc_tc_max_credit, 648 u32 max_credit,
625 u32 tc); 649 u32 tc);
626 650
627/* set tx packet scheduler descriptor tc weight */ 651/* set tx packet scheduler descriptor tc weight */
628void tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw, 652void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
629 u32 tx_pkt_shed_desc_tc_weight, 653 u32 tx_pkt_shed_desc_tc_weight,
630 u32 tc); 654 u32 tc);
631 655
632/* set tx packet scheduler descriptor vm arbitration mode */ 656/* set tx packet scheduler descriptor vm arbitration mode */
633void tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw, 657void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
634 u32 tx_pkt_shed_desc_vm_arb_mode); 658 u32 arb_mode);
635 659
636/* set tx packet scheduler tc data max credit */ 660/* set tx packet scheduler tc data max credit */
637void tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw, 661void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
638 u32 tx_pkt_shed_tc_data_max_credit, 662 u32 max_credit,
639 u32 tc); 663 u32 tc);
640 664
641/* set tx packet scheduler tc data weight */ 665/* set tx packet scheduler tc data weight */
642void tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw, 666void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
643 u32 tx_pkt_shed_tc_data_weight, 667 u32 tx_pkt_shed_tc_data_weight,
644 u32 tc); 668 u32 tc);
645 669
646/* tx */ 670/* tx */
647 671
648/* set tx register reset disable */ 672/* set tx register reset disable */
649void tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis); 673void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis);
650 674
651/* msm */ 675/* msm */
652 676
653/* get register access status */ 677/* get register access status */
654u32 msm_reg_access_status_get(struct aq_hw_s *aq_hw); 678u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw);
655 679
656/* set register address for indirect address */ 680/* set register address for indirect address */
657void msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw, 681void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
658 u32 reg_addr_for_indirect_addr); 682 u32 reg_addr_for_indirect_addr);
659 683
660/* set register read strobe */ 684/* set register read strobe */
661void msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe); 685void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe);
662 686
663/* get register read data */ 687/* get register read data */
664u32 msm_reg_rd_data_get(struct aq_hw_s *aq_hw); 688u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw);
665 689
666/* set register write data */ 690/* set register write data */
667void msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data); 691void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data);
668 692
669/* set register write strobe */ 693/* set register write strobe */
670void msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe); 694void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe);
671 695
672/* pci */ 696/* pci */
673 697
674/* set pci register reset disable */ 698/* set pci register reset disable */
675void pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis); 699void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis);
676 700
677#endif /* HW_ATL_LLH_H */ 701#endif /* HW_ATL_LLH_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h
index 93450ec930e8..e0cf70120f1d 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h
@@ -18,91 +18,91 @@
18 * base address: 0x000003a0 18 * base address: 0x000003a0
19 * parameter: semaphore {s} | stride size 0x4 | range [0, 15] 19 * parameter: semaphore {s} | stride size 0x4 | range [0, 15]
20 */ 20 */
21#define glb_cpu_sem_adr(semaphore) (0x000003a0u + (semaphore) * 0x4) 21#define HW_ATL_GLB_CPU_SEM_ADR(semaphore) (0x000003a0u + (semaphore) * 0x4)
22/* register address for bitfield rx dma good octet counter lsw [1f:0] */ 22/* register address for bitfield rx dma good octet counter lsw [1f:0] */
23#define stats_rx_dma_good_octet_counterlsw__adr 0x00006808 23#define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW 0x00006808
24/* register address for bitfield rx dma good packet counter lsw [1f:0] */ 24/* register address for bitfield rx dma good packet counter lsw [1f:0] */
25#define stats_rx_dma_good_pkt_counterlsw__adr 0x00006800 25#define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW 0x00006800
26/* register address for bitfield tx dma good octet counter lsw [1f:0] */ 26/* register address for bitfield tx dma good octet counter lsw [1f:0] */
27#define stats_tx_dma_good_octet_counterlsw__adr 0x00008808 27#define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW 0x00008808
28/* register address for bitfield tx dma good packet counter lsw [1f:0] */ 28/* register address for bitfield tx dma good packet counter lsw [1f:0] */
29#define stats_tx_dma_good_pkt_counterlsw__adr 0x00008800 29#define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW 0x00008800
30 30
31/* register address for bitfield rx dma good octet counter msw [3f:20] */ 31/* register address for bitfield rx dma good octet counter msw [3f:20] */
32#define stats_rx_dma_good_octet_countermsw__adr 0x0000680c 32#define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW 0x0000680c
33/* register address for bitfield rx dma good packet counter msw [3f:20] */ 33/* register address for bitfield rx dma good packet counter msw [3f:20] */
34#define stats_rx_dma_good_pkt_countermsw__adr 0x00006804 34#define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW 0x00006804
35/* register address for bitfield tx dma good octet counter msw [3f:20] */ 35/* register address for bitfield tx dma good octet counter msw [3f:20] */
36#define stats_tx_dma_good_octet_countermsw__adr 0x0000880c 36#define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW 0x0000880c
37/* register address for bitfield tx dma good packet counter msw [3f:20] */ 37/* register address for bitfield tx dma good packet counter msw [3f:20] */
38#define stats_tx_dma_good_pkt_countermsw__adr 0x00008804 38#define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW 0x00008804
39 39
40/* preprocessor definitions for msm rx errors counter register */ 40/* preprocessor definitions for msm rx errors counter register */
41#define mac_msm_rx_errs_cnt_adr 0x00000120u 41#define HW_ATL_MAC_MSM_RX_ERRS_CNT_ADR 0x00000120u
42 42
43/* preprocessor definitions for msm rx unicast frames counter register */ 43/* preprocessor definitions for msm rx unicast frames counter register */
44#define mac_msm_rx_ucst_frm_cnt_adr 0x000000e0u 44#define HW_ATL_MAC_MSM_RX_UCST_FRM_CNT_ADR 0x000000e0u
45 45
46/* preprocessor definitions for msm rx multicast frames counter register */ 46/* preprocessor definitions for msm rx multicast frames counter register */
47#define mac_msm_rx_mcst_frm_cnt_adr 0x000000e8u 47#define HW_ATL_MAC_MSM_RX_MCST_FRM_CNT_ADR 0x000000e8u
48 48
49/* preprocessor definitions for msm rx broadcast frames counter register */ 49/* preprocessor definitions for msm rx broadcast frames counter register */
50#define mac_msm_rx_bcst_frm_cnt_adr 0x000000f0u 50#define HW_ATL_MAC_MSM_RX_BCST_FRM_CNT_ADR 0x000000f0u
51 51
52/* preprocessor definitions for msm rx broadcast octets counter register 1 */ 52/* preprocessor definitions for msm rx broadcast octets counter register 1 */
53#define mac_msm_rx_bcst_octets_counter1_adr 0x000001b0u 53#define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER1_ADR 0x000001b0u
54 54
55/* preprocessor definitions for msm rx broadcast octets counter register 2 */ 55/* preprocessor definitions for msm rx broadcast octets counter register 2 */
56#define mac_msm_rx_bcst_octets_counter2_adr 0x000001b4u 56#define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER2_ADR 0x000001b4u
57 57
58/* preprocessor definitions for msm rx unicast octets counter register 0 */ 58/* preprocessor definitions for msm rx unicast octets counter register 0 */
59#define mac_msm_rx_ucst_octets_counter0_adr 0x000001b8u 59#define HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR 0x000001b8u
60 60
61/* preprocessor definitions for rx dma statistics counter 7 */ 61/* preprocessor definitions for rx dma statistics counter 7 */
62#define rx_dma_stat_counter7_adr 0x00006818u 62#define HW_ATL_RX_DMA_STAT_COUNTER7_ADR 0x00006818u
63 63
64/* preprocessor definitions for msm tx unicast frames counter register */ 64/* preprocessor definitions for msm tx unicast frames counter register */
65#define mac_msm_tx_ucst_frm_cnt_adr 0x00000108u 65#define HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR 0x00000108u
66 66
67/* preprocessor definitions for msm tx multicast frames counter register */ 67/* preprocessor definitions for msm tx multicast frames counter register */
68#define mac_msm_tx_mcst_frm_cnt_adr 0x00000110u 68#define HW_ATL_MAC_MSM_TX_MCST_FRM_CNT_ADR 0x00000110u
69 69
70/* preprocessor definitions for global mif identification */ 70/* preprocessor definitions for global mif identification */
71#define glb_mif_id_adr 0x0000001cu 71#define HW_ATL_GLB_MIF_ID_ADR 0x0000001cu
72 72
73/* register address for bitfield iamr_lsw[1f:0] */ 73/* register address for bitfield iamr_lsw[1f:0] */
74#define itr_iamrlsw_adr 0x00002090 74#define HW_ATL_ITR_IAMRLSW_ADR 0x00002090
75/* register address for bitfield rx dma drop packet counter [1f:0] */ 75/* register address for bitfield rx dma drop packet counter [1f:0] */
76#define rpb_rx_dma_drop_pkt_cnt_adr 0x00006818 76#define HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR 0x00006818
77 77
78/* register address for bitfield imcr_lsw[1f:0] */ 78/* register address for bitfield imcr_lsw[1f:0] */
79#define itr_imcrlsw_adr 0x00002070 79#define HW_ATL_ITR_IMCRLSW_ADR 0x00002070
80/* register address for bitfield imsr_lsw[1f:0] */ 80/* register address for bitfield imsr_lsw[1f:0] */
81#define itr_imsrlsw_adr 0x00002060 81#define HW_ATL_ITR_IMSRLSW_ADR 0x00002060
82/* register address for bitfield itr_reg_res_dsbl */ 82/* register address for bitfield itr_reg_res_dsbl */
83#define itr_reg_res_dsbl_adr 0x00002300 83#define HW_ATL_ITR_REG_RES_DSBL_ADR 0x00002300
84/* bitmask for bitfield itr_reg_res_dsbl */ 84/* bitmask for bitfield itr_reg_res_dsbl */
85#define itr_reg_res_dsbl_msk 0x20000000 85#define HW_ATL_ITR_REG_RES_DSBL_MSK 0x20000000
86/* lower bit position of bitfield itr_reg_res_dsbl */ 86/* lower bit position of bitfield itr_reg_res_dsbl */
87#define itr_reg_res_dsbl_shift 29 87#define HW_ATL_ITR_REG_RES_DSBL_SHIFT 29
88/* register address for bitfield iscr_lsw[1f:0] */ 88/* register address for bitfield iscr_lsw[1f:0] */
89#define itr_iscrlsw_adr 0x00002050 89#define HW_ATL_ITR_ISCRLSW_ADR 0x00002050
90/* register address for bitfield isr_lsw[1f:0] */ 90/* register address for bitfield isr_lsw[1f:0] */
91#define itr_isrlsw_adr 0x00002000 91#define HW_ATL_ITR_ISRLSW_ADR 0x00002000
92/* register address for bitfield itr_reset */ 92/* register address for bitfield itr_reset */
93#define itr_res_adr 0x00002300 93#define HW_ATL_ITR_RES_ADR 0x00002300
94/* bitmask for bitfield itr_reset */ 94/* bitmask for bitfield itr_reset */
95#define itr_res_msk 0x80000000 95#define HW_ATL_ITR_RES_MSK 0x80000000
96/* lower bit position of bitfield itr_reset */ 96/* lower bit position of bitfield itr_reset */
97#define itr_res_shift 31 97#define HW_ATL_ITR_RES_SHIFT 31
98/* register address for bitfield dca{d}_cpuid[7:0] */ 98/* register address for bitfield dca{d}_cpuid[7:0] */
99#define rdm_dcadcpuid_adr(dca) (0x00006100 + (dca) * 0x4) 99#define HW_ATL_RDM_DCADCPUID_ADR(dca) (0x00006100 + (dca) * 0x4)
100/* bitmask for bitfield dca{d}_cpuid[7:0] */ 100/* bitmask for bitfield dca{d}_cpuid[7:0] */
101#define rdm_dcadcpuid_msk 0x000000ff 101#define HW_ATL_RDM_DCADCPUID_MSK 0x000000ff
102/* lower bit position of bitfield dca{d}_cpuid[7:0] */ 102/* lower bit position of bitfield dca{d}_cpuid[7:0] */
103#define rdm_dcadcpuid_shift 0 103#define HW_ATL_RDM_DCADCPUID_SHIFT 0
104/* register address for bitfield dca_en */ 104/* register address for bitfield dca_en */
105#define rdm_dca_en_adr 0x00006180 105#define HW_ATL_RDM_DCA_EN_ADR 0x00006180
106 106
107/* rx dca_en bitfield definitions 107/* rx dca_en bitfield definitions
108 * preprocessor definitions for the bitfield "dca_en". 108 * preprocessor definitions for the bitfield "dca_en".
@@ -110,17 +110,17 @@
110 */ 110 */
111 111
112/* register address for bitfield dca_en */ 112/* register address for bitfield dca_en */
113#define rdm_dca_en_adr 0x00006180 113#define HW_ATL_RDM_DCA_EN_ADR 0x00006180
114/* bitmask for bitfield dca_en */ 114/* bitmask for bitfield dca_en */
115#define rdm_dca_en_msk 0x80000000 115#define HW_ATL_RDM_DCA_EN_MSK 0x80000000
116/* inverted bitmask for bitfield dca_en */ 116/* inverted bitmask for bitfield dca_en */
117#define rdm_dca_en_mskn 0x7fffffff 117#define HW_ATL_RDM_DCA_EN_MSKN 0x7fffffff
118/* lower bit position of bitfield dca_en */ 118/* lower bit position of bitfield dca_en */
119#define rdm_dca_en_shift 31 119#define HW_ATL_RDM_DCA_EN_SHIFT 31
120/* width of bitfield dca_en */ 120/* width of bitfield dca_en */
121#define rdm_dca_en_width 1 121#define HW_ATL_RDM_DCA_EN_WIDTH 1
122/* default value of bitfield dca_en */ 122/* default value of bitfield dca_en */
123#define rdm_dca_en_default 0x1 123#define HW_ATL_RDM_DCA_EN_DEFAULT 0x1
124 124
125/* rx dca_mode[3:0] bitfield definitions 125/* rx dca_mode[3:0] bitfield definitions
126 * preprocessor definitions for the bitfield "dca_mode[3:0]". 126 * preprocessor definitions for the bitfield "dca_mode[3:0]".
@@ -128,17 +128,17 @@
128 */ 128 */
129 129
130/* register address for bitfield dca_mode[3:0] */ 130/* register address for bitfield dca_mode[3:0] */
131#define rdm_dca_mode_adr 0x00006180 131#define HW_ATL_RDM_DCA_MODE_ADR 0x00006180
132/* bitmask for bitfield dca_mode[3:0] */ 132/* bitmask for bitfield dca_mode[3:0] */
133#define rdm_dca_mode_msk 0x0000000f 133#define HW_ATL_RDM_DCA_MODE_MSK 0x0000000f
134/* inverted bitmask for bitfield dca_mode[3:0] */ 134/* inverted bitmask for bitfield dca_mode[3:0] */
135#define rdm_dca_mode_mskn 0xfffffff0 135#define HW_ATL_RDM_DCA_MODE_MSKN 0xfffffff0
136/* lower bit position of bitfield dca_mode[3:0] */ 136/* lower bit position of bitfield dca_mode[3:0] */
137#define rdm_dca_mode_shift 0 137#define HW_ATL_RDM_DCA_MODE_SHIFT 0
138/* width of bitfield dca_mode[3:0] */ 138/* width of bitfield dca_mode[3:0] */
139#define rdm_dca_mode_width 4 139#define HW_ATL_RDM_DCA_MODE_WIDTH 4
140/* default value of bitfield dca_mode[3:0] */ 140/* default value of bitfield dca_mode[3:0] */
141#define rdm_dca_mode_default 0x0 141#define HW_ATL_RDM_DCA_MODE_DEFAULT 0x0
142 142
143/* rx desc{d}_data_size[4:0] bitfield definitions 143/* rx desc{d}_data_size[4:0] bitfield definitions
144 * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]". 144 * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]".
@@ -147,17 +147,18 @@
147 */ 147 */
148 148
149/* register address for bitfield desc{d}_data_size[4:0] */ 149/* register address for bitfield desc{d}_data_size[4:0] */
150#define rdm_descddata_size_adr(descriptor) (0x00005b18 + (descriptor) * 0x20) 150#define HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor) \
151 (0x00005b18 + (descriptor) * 0x20)
151/* bitmask for bitfield desc{d}_data_size[4:0] */ 152/* bitmask for bitfield desc{d}_data_size[4:0] */
152#define rdm_descddata_size_msk 0x0000001f 153#define HW_ATL_RDM_DESCDDATA_SIZE_MSK 0x0000001f
153/* inverted bitmask for bitfield desc{d}_data_size[4:0] */ 154/* inverted bitmask for bitfield desc{d}_data_size[4:0] */
154#define rdm_descddata_size_mskn 0xffffffe0 155#define HW_ATL_RDM_DESCDDATA_SIZE_MSKN 0xffffffe0
155/* lower bit position of bitfield desc{d}_data_size[4:0] */ 156/* lower bit position of bitfield desc{d}_data_size[4:0] */
156#define rdm_descddata_size_shift 0 157#define HW_ATL_RDM_DESCDDATA_SIZE_SHIFT 0
157/* width of bitfield desc{d}_data_size[4:0] */ 158/* width of bitfield desc{d}_data_size[4:0] */
158#define rdm_descddata_size_width 5 159#define HW_ATL_RDM_DESCDDATA_SIZE_WIDTH 5
159/* default value of bitfield desc{d}_data_size[4:0] */ 160/* default value of bitfield desc{d}_data_size[4:0] */
160#define rdm_descddata_size_default 0x0 161#define HW_ATL_RDM_DESCDDATA_SIZE_DEFAULT 0x0
161 162
162/* rx dca{d}_desc_en bitfield definitions 163/* rx dca{d}_desc_en bitfield definitions
163 * preprocessor definitions for the bitfield "dca{d}_desc_en". 164 * preprocessor definitions for the bitfield "dca{d}_desc_en".
@@ -166,17 +167,17 @@
166 */ 167 */
167 168
168/* register address for bitfield dca{d}_desc_en */ 169/* register address for bitfield dca{d}_desc_en */
169#define rdm_dcaddesc_en_adr(dca) (0x00006100 + (dca) * 0x4) 170#define HW_ATL_RDM_DCADDESC_EN_ADR(dca) (0x00006100 + (dca) * 0x4)
170/* bitmask for bitfield dca{d}_desc_en */ 171/* bitmask for bitfield dca{d}_desc_en */
171#define rdm_dcaddesc_en_msk 0x80000000 172#define HW_ATL_RDM_DCADDESC_EN_MSK 0x80000000
172/* inverted bitmask for bitfield dca{d}_desc_en */ 173/* inverted bitmask for bitfield dca{d}_desc_en */
173#define rdm_dcaddesc_en_mskn 0x7fffffff 174#define HW_ATL_RDM_DCADDESC_EN_MSKN 0x7fffffff
174/* lower bit position of bitfield dca{d}_desc_en */ 175/* lower bit position of bitfield dca{d}_desc_en */
175#define rdm_dcaddesc_en_shift 31 176#define HW_ATL_RDM_DCADDESC_EN_SHIFT 31
176/* width of bitfield dca{d}_desc_en */ 177/* width of bitfield dca{d}_desc_en */
177#define rdm_dcaddesc_en_width 1 178#define HW_ATL_RDM_DCADDESC_EN_WIDTH 1
178/* default value of bitfield dca{d}_desc_en */ 179/* default value of bitfield dca{d}_desc_en */
179#define rdm_dcaddesc_en_default 0x0 180#define HW_ATL_RDM_DCADDESC_EN_DEFAULT 0x0
180 181
181/* rx desc{d}_en bitfield definitions 182/* rx desc{d}_en bitfield definitions
182 * preprocessor definitions for the bitfield "desc{d}_en". 183 * preprocessor definitions for the bitfield "desc{d}_en".
@@ -185,17 +186,17 @@
185 */ 186 */
186 187
187/* register address for bitfield desc{d}_en */ 188/* register address for bitfield desc{d}_en */
188#define rdm_descden_adr(descriptor) (0x00005b08 + (descriptor) * 0x20) 189#define HW_ATL_RDM_DESCDEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20)
189/* bitmask for bitfield desc{d}_en */ 190/* bitmask for bitfield desc{d}_en */
190#define rdm_descden_msk 0x80000000 191#define HW_ATL_RDM_DESCDEN_MSK 0x80000000
191/* inverted bitmask for bitfield desc{d}_en */ 192/* inverted bitmask for bitfield desc{d}_en */
192#define rdm_descden_mskn 0x7fffffff 193#define HW_ATL_RDM_DESCDEN_MSKN 0x7fffffff
193/* lower bit position of bitfield desc{d}_en */ 194/* lower bit position of bitfield desc{d}_en */
194#define rdm_descden_shift 31 195#define HW_ATL_RDM_DESCDEN_SHIFT 31
195/* width of bitfield desc{d}_en */ 196/* width of bitfield desc{d}_en */
196#define rdm_descden_width 1 197#define HW_ATL_RDM_DESCDEN_WIDTH 1
197/* default value of bitfield desc{d}_en */ 198/* default value of bitfield desc{d}_en */
198#define rdm_descden_default 0x0 199#define HW_ATL_RDM_DESCDEN_DEFAULT 0x0
199 200
200/* rx desc{d}_hdr_size[4:0] bitfield definitions 201/* rx desc{d}_hdr_size[4:0] bitfield definitions
201 * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]". 202 * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]".
@@ -204,17 +205,18 @@
204 */ 205 */
205 206
206/* register address for bitfield desc{d}_hdr_size[4:0] */ 207/* register address for bitfield desc{d}_hdr_size[4:0] */
207#define rdm_descdhdr_size_adr(descriptor) (0x00005b18 + (descriptor) * 0x20) 208#define HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor) \
209 (0x00005b18 + (descriptor) * 0x20)
208/* bitmask for bitfield desc{d}_hdr_size[4:0] */ 210/* bitmask for bitfield desc{d}_hdr_size[4:0] */
209#define rdm_descdhdr_size_msk 0x00001f00 211#define HW_ATL_RDM_DESCDHDR_SIZE_MSK 0x00001f00
210/* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */ 212/* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */
211#define rdm_descdhdr_size_mskn 0xffffe0ff 213#define HW_ATL_RDM_DESCDHDR_SIZE_MSKN 0xffffe0ff
212/* lower bit position of bitfield desc{d}_hdr_size[4:0] */ 214/* lower bit position of bitfield desc{d}_hdr_size[4:0] */
213#define rdm_descdhdr_size_shift 8 215#define HW_ATL_RDM_DESCDHDR_SIZE_SHIFT 8
214/* width of bitfield desc{d}_hdr_size[4:0] */ 216/* width of bitfield desc{d}_hdr_size[4:0] */
215#define rdm_descdhdr_size_width 5 217#define HW_ATL_RDM_DESCDHDR_SIZE_WIDTH 5
216/* default value of bitfield desc{d}_hdr_size[4:0] */ 218/* default value of bitfield desc{d}_hdr_size[4:0] */
217#define rdm_descdhdr_size_default 0x0 219#define HW_ATL_RDM_DESCDHDR_SIZE_DEFAULT 0x0
218 220
219/* rx desc{d}_hdr_split bitfield definitions 221/* rx desc{d}_hdr_split bitfield definitions
220 * preprocessor definitions for the bitfield "desc{d}_hdr_split". 222 * preprocessor definitions for the bitfield "desc{d}_hdr_split".
@@ -223,17 +225,18 @@
223 */ 225 */
224 226
225/* register address for bitfield desc{d}_hdr_split */ 227/* register address for bitfield desc{d}_hdr_split */
226#define rdm_descdhdr_split_adr(descriptor) (0x00005b08 + (descriptor) * 0x20) 228#define HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor) \
229 (0x00005b08 + (descriptor) * 0x20)
227/* bitmask for bitfield desc{d}_hdr_split */ 230/* bitmask for bitfield desc{d}_hdr_split */
228#define rdm_descdhdr_split_msk 0x10000000 231#define HW_ATL_RDM_DESCDHDR_SPLIT_MSK 0x10000000
229/* inverted bitmask for bitfield desc{d}_hdr_split */ 232/* inverted bitmask for bitfield desc{d}_hdr_split */
230#define rdm_descdhdr_split_mskn 0xefffffff 233#define HW_ATL_RDM_DESCDHDR_SPLIT_MSKN 0xefffffff
231/* lower bit position of bitfield desc{d}_hdr_split */ 234/* lower bit position of bitfield desc{d}_hdr_split */
232#define rdm_descdhdr_split_shift 28 235#define HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT 28
233/* width of bitfield desc{d}_hdr_split */ 236/* width of bitfield desc{d}_hdr_split */
234#define rdm_descdhdr_split_width 1 237#define HW_ATL_RDM_DESCDHDR_SPLIT_WIDTH 1
235/* default value of bitfield desc{d}_hdr_split */ 238/* default value of bitfield desc{d}_hdr_split */
236#define rdm_descdhdr_split_default 0x0 239#define HW_ATL_RDM_DESCDHDR_SPLIT_DEFAULT 0x0
237 240
238/* rx desc{d}_hd[c:0] bitfield definitions 241/* rx desc{d}_hd[c:0] bitfield definitions
239 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 242 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]".
@@ -242,15 +245,15 @@
242 */ 245 */
243 246
244/* register address for bitfield desc{d}_hd[c:0] */ 247/* register address for bitfield desc{d}_hd[c:0] */
245#define rdm_descdhd_adr(descriptor) (0x00005b0c + (descriptor) * 0x20) 248#define HW_ATL_RDM_DESCDHD_ADR(descriptor) (0x00005b0c + (descriptor) * 0x20)
246/* bitmask for bitfield desc{d}_hd[c:0] */ 249/* bitmask for bitfield desc{d}_hd[c:0] */
247#define rdm_descdhd_msk 0x00001fff 250#define HW_ATL_RDM_DESCDHD_MSK 0x00001fff
248/* inverted bitmask for bitfield desc{d}_hd[c:0] */ 251/* inverted bitmask for bitfield desc{d}_hd[c:0] */
249#define rdm_descdhd_mskn 0xffffe000 252#define HW_ATL_RDM_DESCDHD_MSKN 0xffffe000
250/* lower bit position of bitfield desc{d}_hd[c:0] */ 253/* lower bit position of bitfield desc{d}_hd[c:0] */
251#define rdm_descdhd_shift 0 254#define HW_ATL_RDM_DESCDHD_SHIFT 0
252/* width of bitfield desc{d}_hd[c:0] */ 255/* width of bitfield desc{d}_hd[c:0] */
253#define rdm_descdhd_width 13 256#define HW_ATL_RDM_DESCDHD_WIDTH 13
254 257
255/* rx desc{d}_len[9:0] bitfield definitions 258/* rx desc{d}_len[9:0] bitfield definitions
256 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 259 * preprocessor definitions for the bitfield "desc{d}_len[9:0]".
@@ -259,17 +262,17 @@
259 */ 262 */
260 263
261/* register address for bitfield desc{d}_len[9:0] */ 264/* register address for bitfield desc{d}_len[9:0] */
262#define rdm_descdlen_adr(descriptor) (0x00005b08 + (descriptor) * 0x20) 265#define HW_ATL_RDM_DESCDLEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20)
263/* bitmask for bitfield desc{d}_len[9:0] */ 266/* bitmask for bitfield desc{d}_len[9:0] */
264#define rdm_descdlen_msk 0x00001ff8 267#define HW_ATL_RDM_DESCDLEN_MSK 0x00001ff8
265/* inverted bitmask for bitfield desc{d}_len[9:0] */ 268/* inverted bitmask for bitfield desc{d}_len[9:0] */
266#define rdm_descdlen_mskn 0xffffe007 269#define HW_ATL_RDM_DESCDLEN_MSKN 0xffffe007
267/* lower bit position of bitfield desc{d}_len[9:0] */ 270/* lower bit position of bitfield desc{d}_len[9:0] */
268#define rdm_descdlen_shift 3 271#define HW_ATL_RDM_DESCDLEN_SHIFT 3
269/* width of bitfield desc{d}_len[9:0] */ 272/* width of bitfield desc{d}_len[9:0] */
270#define rdm_descdlen_width 10 273#define HW_ATL_RDM_DESCDLEN_WIDTH 10
271/* default value of bitfield desc{d}_len[9:0] */ 274/* default value of bitfield desc{d}_len[9:0] */
272#define rdm_descdlen_default 0x0 275#define HW_ATL_RDM_DESCDLEN_DEFAULT 0x0
273 276
274/* rx desc{d}_reset bitfield definitions 277/* rx desc{d}_reset bitfield definitions
275 * preprocessor definitions for the bitfield "desc{d}_reset". 278 * preprocessor definitions for the bitfield "desc{d}_reset".
@@ -278,17 +281,17 @@
278 */ 281 */
279 282
280/* register address for bitfield desc{d}_reset */ 283/* register address for bitfield desc{d}_reset */
281#define rdm_descdreset_adr(descriptor) (0x00005b08 + (descriptor) * 0x20) 284#define HW_ATL_RDM_DESCDRESET_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20)
282/* bitmask for bitfield desc{d}_reset */ 285/* bitmask for bitfield desc{d}_reset */
283#define rdm_descdreset_msk 0x02000000 286#define HW_ATL_RDM_DESCDRESET_MSK 0x02000000
284/* inverted bitmask for bitfield desc{d}_reset */ 287/* inverted bitmask for bitfield desc{d}_reset */
285#define rdm_descdreset_mskn 0xfdffffff 288#define HW_ATL_RDM_DESCDRESET_MSKN 0xfdffffff
286/* lower bit position of bitfield desc{d}_reset */ 289/* lower bit position of bitfield desc{d}_reset */
287#define rdm_descdreset_shift 25 290#define HW_ATL_RDM_DESCDRESET_SHIFT 25
288/* width of bitfield desc{d}_reset */ 291/* width of bitfield desc{d}_reset */
289#define rdm_descdreset_width 1 292#define HW_ATL_RDM_DESCDRESET_WIDTH 1
290/* default value of bitfield desc{d}_reset */ 293/* default value of bitfield desc{d}_reset */
291#define rdm_descdreset_default 0x0 294#define HW_ATL_RDM_DESCDRESET_DEFAULT 0x0
292 295
293/* rx int_desc_wrb_en bitfield definitions 296/* rx int_desc_wrb_en bitfield definitions
294 * preprocessor definitions for the bitfield "int_desc_wrb_en". 297 * preprocessor definitions for the bitfield "int_desc_wrb_en".
@@ -296,17 +299,17 @@
296 */ 299 */
297 300
298/* register address for bitfield int_desc_wrb_en */ 301/* register address for bitfield int_desc_wrb_en */
299#define rdm_int_desc_wrb_en_adr 0x00005a30 302#define HW_ATL_RDM_INT_DESC_WRB_EN_ADR 0x00005a30
300/* bitmask for bitfield int_desc_wrb_en */ 303/* bitmask for bitfield int_desc_wrb_en */
301#define rdm_int_desc_wrb_en_msk 0x00000004 304#define HW_ATL_RDM_INT_DESC_WRB_EN_MSK 0x00000004
302/* inverted bitmask for bitfield int_desc_wrb_en */ 305/* inverted bitmask for bitfield int_desc_wrb_en */
303#define rdm_int_desc_wrb_en_mskn 0xfffffffb 306#define HW_ATL_RDM_INT_DESC_WRB_EN_MSKN 0xfffffffb
304/* lower bit position of bitfield int_desc_wrb_en */ 307/* lower bit position of bitfield int_desc_wrb_en */
305#define rdm_int_desc_wrb_en_shift 2 308#define HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT 2
306/* width of bitfield int_desc_wrb_en */ 309/* width of bitfield int_desc_wrb_en */
307#define rdm_int_desc_wrb_en_width 1 310#define HW_ATL_RDM_INT_DESC_WRB_EN_WIDTH 1
308/* default value of bitfield int_desc_wrb_en */ 311/* default value of bitfield int_desc_wrb_en */
309#define rdm_int_desc_wrb_en_default 0x0 312#define HW_ATL_RDM_INT_DESC_WRB_EN_DEFAULT 0x0
310 313
311/* rx dca{d}_hdr_en bitfield definitions 314/* rx dca{d}_hdr_en bitfield definitions
312 * preprocessor definitions for the bitfield "dca{d}_hdr_en". 315 * preprocessor definitions for the bitfield "dca{d}_hdr_en".
@@ -315,17 +318,17 @@
315 */ 318 */
316 319
317/* register address for bitfield dca{d}_hdr_en */ 320/* register address for bitfield dca{d}_hdr_en */
318#define rdm_dcadhdr_en_adr(dca) (0x00006100 + (dca) * 0x4) 321#define HW_ATL_RDM_DCADHDR_EN_ADR(dca) (0x00006100 + (dca) * 0x4)
319/* bitmask for bitfield dca{d}_hdr_en */ 322/* bitmask for bitfield dca{d}_hdr_en */
320#define rdm_dcadhdr_en_msk 0x40000000 323#define HW_ATL_RDM_DCADHDR_EN_MSK 0x40000000
321/* inverted bitmask for bitfield dca{d}_hdr_en */ 324/* inverted bitmask for bitfield dca{d}_hdr_en */
322#define rdm_dcadhdr_en_mskn 0xbfffffff 325#define HW_ATL_RDM_DCADHDR_EN_MSKN 0xbfffffff
323/* lower bit position of bitfield dca{d}_hdr_en */ 326/* lower bit position of bitfield dca{d}_hdr_en */
324#define rdm_dcadhdr_en_shift 30 327#define HW_ATL_RDM_DCADHDR_EN_SHIFT 30
325/* width of bitfield dca{d}_hdr_en */ 328/* width of bitfield dca{d}_hdr_en */
326#define rdm_dcadhdr_en_width 1 329#define HW_ATL_RDM_DCADHDR_EN_WIDTH 1
327/* default value of bitfield dca{d}_hdr_en */ 330/* default value of bitfield dca{d}_hdr_en */
328#define rdm_dcadhdr_en_default 0x0 331#define HW_ATL_RDM_DCADHDR_EN_DEFAULT 0x0
329 332
330/* rx dca{d}_pay_en bitfield definitions 333/* rx dca{d}_pay_en bitfield definitions
331 * preprocessor definitions for the bitfield "dca{d}_pay_en". 334 * preprocessor definitions for the bitfield "dca{d}_pay_en".
@@ -334,17 +337,17 @@
334 */ 337 */
335 338
336/* register address for bitfield dca{d}_pay_en */ 339/* register address for bitfield dca{d}_pay_en */
337#define rdm_dcadpay_en_adr(dca) (0x00006100 + (dca) * 0x4) 340#define HW_ATL_RDM_DCADPAY_EN_ADR(dca) (0x00006100 + (dca) * 0x4)
338/* bitmask for bitfield dca{d}_pay_en */ 341/* bitmask for bitfield dca{d}_pay_en */
339#define rdm_dcadpay_en_msk 0x20000000 342#define HW_ATL_RDM_DCADPAY_EN_MSK 0x20000000
340/* inverted bitmask for bitfield dca{d}_pay_en */ 343/* inverted bitmask for bitfield dca{d}_pay_en */
341#define rdm_dcadpay_en_mskn 0xdfffffff 344#define HW_ATL_RDM_DCADPAY_EN_MSKN 0xdfffffff
342/* lower bit position of bitfield dca{d}_pay_en */ 345/* lower bit position of bitfield dca{d}_pay_en */
343#define rdm_dcadpay_en_shift 29 346#define HW_ATL_RDM_DCADPAY_EN_SHIFT 29
344/* width of bitfield dca{d}_pay_en */ 347/* width of bitfield dca{d}_pay_en */
345#define rdm_dcadpay_en_width 1 348#define HW_ATL_RDM_DCADPAY_EN_WIDTH 1
346/* default value of bitfield dca{d}_pay_en */ 349/* default value of bitfield dca{d}_pay_en */
347#define rdm_dcadpay_en_default 0x0 350#define HW_ATL_RDM_DCADPAY_EN_DEFAULT 0x0
348 351
349/* RX rdm_int_rim_en Bitfield Definitions 352/* RX rdm_int_rim_en Bitfield Definitions
350 * Preprocessor definitions for the bitfield "rdm_int_rim_en". 353 * Preprocessor definitions for the bitfield "rdm_int_rim_en".
@@ -352,51 +355,51 @@
352 */ 355 */
353 356
354/* Register address for bitfield rdm_int_rim_en */ 357/* Register address for bitfield rdm_int_rim_en */
355#define rdm_int_rim_en_adr 0x00005A30 358#define HW_ATL_RDM_INT_RIM_EN_ADR 0x00005A30
356/* Bitmask for bitfield rdm_int_rim_en */ 359/* Bitmask for bitfield rdm_int_rim_en */
357#define rdm_int_rim_en_msk 0x00000008 360#define HW_ATL_RDM_INT_RIM_EN_MSK 0x00000008
358/* Inverted bitmask for bitfield rdm_int_rim_en */ 361/* Inverted bitmask for bitfield rdm_int_rim_en */
359#define rdm_int_rim_en_mskn 0xFFFFFFF7 362#define HW_ATL_RDM_INT_RIM_EN_MSKN 0xFFFFFFF7
360/* Lower bit position of bitfield rdm_int_rim_en */ 363/* Lower bit position of bitfield rdm_int_rim_en */
361#define rdm_int_rim_en_shift 3 364#define HW_ATL_RDM_INT_RIM_EN_SHIFT 3
362/* Width of bitfield rdm_int_rim_en */ 365/* Width of bitfield rdm_int_rim_en */
363#define rdm_int_rim_en_width 1 366#define HW_ATL_RDM_INT_RIM_EN_WIDTH 1
364/* Default value of bitfield rdm_int_rim_en */ 367/* Default value of bitfield rdm_int_rim_en */
365#define rdm_int_rim_en_default 0x0 368#define HW_ATL_RDM_INT_RIM_EN_DEFAULT 0x0
366 369
367/* general interrupt mapping register definitions 370/* general interrupt mapping register definitions
368 * preprocessor definitions for general interrupt mapping register 371 * preprocessor definitions for general interrupt mapping register
369 * base address: 0x00002180 372 * base address: 0x00002180
370 * parameter: regidx {f} | stride size 0x4 | range [0, 3] 373 * parameter: regidx {f} | stride size 0x4 | range [0, 3]
371 */ 374 */
372#define gen_intr_map_adr(regidx) (0x00002180u + (regidx) * 0x4) 375#define HW_ATL_GEN_INTR_MAP_ADR(regidx) (0x00002180u + (regidx) * 0x4)
373 376
374/* general interrupt status register definitions 377/* general interrupt status register definitions
375 * preprocessor definitions for general interrupt status register 378 * preprocessor definitions for general interrupt status register
376 * address: 0x000021A0 379 * address: 0x000021A0
377 */ 380 */
378 381
379#define gen_intr_stat_adr 0x000021A4U 382#define HW_ATL_GEN_INTR_STAT_ADR 0x000021A4U
380 383
381/* interrupt global control register definitions 384/* interrupt global control register definitions
382 * preprocessor definitions for interrupt global control register 385 * preprocessor definitions for interrupt global control register
383 * address: 0x00002300 386 * address: 0x00002300
384 */ 387 */
385#define intr_glb_ctl_adr 0x00002300u 388#define HW_ATL_INTR_GLB_CTL_ADR 0x00002300u
386 389
387/* interrupt throttle register definitions 390/* interrupt throttle register definitions
388 * preprocessor definitions for interrupt throttle register 391 * preprocessor definitions for interrupt throttle register
389 * base address: 0x00002800 392 * base address: 0x00002800
390 * parameter: throttle {t} | stride size 0x4 | range [0, 31] 393 * parameter: throttle {t} | stride size 0x4 | range [0, 31]
391 */ 394 */
392#define intr_thr_adr(throttle) (0x00002800u + (throttle) * 0x4) 395#define HW_ATL_INTR_THR_ADR(throttle) (0x00002800u + (throttle) * 0x4)
393 396
394/* rx dma descriptor base address lsw definitions 397/* rx dma descriptor base address lsw definitions
395 * preprocessor definitions for rx dma descriptor base address lsw 398 * preprocessor definitions for rx dma descriptor base address lsw
396 * base address: 0x00005b00 399 * base address: 0x00005b00
397 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 400 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
398 */ 401 */
399#define rx_dma_desc_base_addrlsw_adr(descriptor) \ 402#define HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \
400(0x00005b00u + (descriptor) * 0x20) 403(0x00005b00u + (descriptor) * 0x20)
401 404
402/* rx dma descriptor base address msw definitions 405/* rx dma descriptor base address msw definitions
@@ -404,7 +407,7 @@
404 * base address: 0x00005b04 407 * base address: 0x00005b04
405 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 408 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
406 */ 409 */
407#define rx_dma_desc_base_addrmsw_adr(descriptor) \ 410#define HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \
408(0x00005b04u + (descriptor) * 0x20) 411(0x00005b04u + (descriptor) * 0x20)
409 412
410/* rx dma descriptor status register definitions 413/* rx dma descriptor status register definitions
@@ -412,46 +415,48 @@
412 * base address: 0x00005b14 415 * base address: 0x00005b14
413 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 416 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
414 */ 417 */
415#define rx_dma_desc_stat_adr(descriptor) (0x00005b14u + (descriptor) * 0x20) 418#define HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor) \
419 (0x00005b14u + (descriptor) * 0x20)
416 420
417/* rx dma descriptor tail pointer register definitions 421/* rx dma descriptor tail pointer register definitions
418 * preprocessor definitions for rx dma descriptor tail pointer register 422 * preprocessor definitions for rx dma descriptor tail pointer register
419 * base address: 0x00005b10 423 * base address: 0x00005b10
420 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 424 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
421 */ 425 */
422#define rx_dma_desc_tail_ptr_adr(descriptor) (0x00005b10u + (descriptor) * 0x20) 426#define HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor) \
427 (0x00005b10u + (descriptor) * 0x20)
423 428
424/* rx interrupt moderation control register definitions 429/* rx interrupt moderation control register definitions
425 * Preprocessor definitions for RX Interrupt Moderation Control Register 430 * Preprocessor definitions for RX Interrupt Moderation Control Register
426 * Base Address: 0x00005A40 431 * Base Address: 0x00005A40
427 * Parameter: RIM {R} | stride size 0x4 | range [0, 31] 432 * Parameter: RIM {R} | stride size 0x4 | range [0, 31]
428 */ 433 */
429#define rx_intr_moderation_ctl_adr(rim) (0x00005A40u + (rim) * 0x4) 434#define HW_ATL_RX_INTR_MODERATION_CTL_ADR(rim) (0x00005A40u + (rim) * 0x4)
430 435
431/* rx filter multicast filter mask register definitions 436/* rx filter multicast filter mask register definitions
432 * preprocessor definitions for rx filter multicast filter mask register 437 * preprocessor definitions for rx filter multicast filter mask register
433 * address: 0x00005270 438 * address: 0x00005270
434 */ 439 */
435#define rx_flr_mcst_flr_msk_adr 0x00005270u 440#define HW_ATL_RX_FLR_MCST_FLR_MSK_ADR 0x00005270u
436 441
437/* rx filter multicast filter register definitions 442/* rx filter multicast filter register definitions
438 * preprocessor definitions for rx filter multicast filter register 443 * preprocessor definitions for rx filter multicast filter register
439 * base address: 0x00005250 444 * base address: 0x00005250
440 * parameter: filter {f} | stride size 0x4 | range [0, 7] 445 * parameter: filter {f} | stride size 0x4 | range [0, 7]
441 */ 446 */
442#define rx_flr_mcst_flr_adr(filter) (0x00005250u + (filter) * 0x4) 447#define HW_ATL_RX_FLR_MCST_FLR_ADR(filter) (0x00005250u + (filter) * 0x4)
443 448
444/* RX Filter RSS Control Register 1 Definitions 449/* RX Filter RSS Control Register 1 Definitions
445 * Preprocessor definitions for RX Filter RSS Control Register 1 450 * Preprocessor definitions for RX Filter RSS Control Register 1
446 * Address: 0x000054C0 451 * Address: 0x000054C0
447 */ 452 */
448#define rx_flr_rss_control1_adr 0x000054C0u 453#define HW_ATL_RX_FLR_RSS_CONTROL1_ADR 0x000054C0u
449 454
450/* RX Filter Control Register 2 Definitions 455/* RX Filter Control Register 2 Definitions
451 * Preprocessor definitions for RX Filter Control Register 2 456 * Preprocessor definitions for RX Filter Control Register 2
452 * Address: 0x00005104 457 * Address: 0x00005104
453 */ 458 */
454#define rx_flr_control2_adr 0x00005104u 459#define HW_ATL_RX_FLR_CONTROL2_ADR 0x00005104u
455 460
456/* tx tx dma debug control [1f:0] bitfield definitions 461/* tx tx dma debug control [1f:0] bitfield definitions
457 * preprocessor definitions for the bitfield "tx dma debug control [1f:0]". 462 * preprocessor definitions for the bitfield "tx dma debug control [1f:0]".
@@ -459,24 +464,24 @@
459 */ 464 */
460 465
461/* register address for bitfield tx dma debug control [1f:0] */ 466/* register address for bitfield tx dma debug control [1f:0] */
462#define tdm_tx_dma_debug_ctl_adr 0x00008920 467#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_ADR 0x00008920
463/* bitmask for bitfield tx dma debug control [1f:0] */ 468/* bitmask for bitfield tx dma debug control [1f:0] */
464#define tdm_tx_dma_debug_ctl_msk 0xffffffff 469#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSK 0xffffffff
465/* inverted bitmask for bitfield tx dma debug control [1f:0] */ 470/* inverted bitmask for bitfield tx dma debug control [1f:0] */
466#define tdm_tx_dma_debug_ctl_mskn 0x00000000 471#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSKN 0x00000000
467/* lower bit position of bitfield tx dma debug control [1f:0] */ 472/* lower bit position of bitfield tx dma debug control [1f:0] */
468#define tdm_tx_dma_debug_ctl_shift 0 473#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_SHIFT 0
469/* width of bitfield tx dma debug control [1f:0] */ 474/* width of bitfield tx dma debug control [1f:0] */
470#define tdm_tx_dma_debug_ctl_width 32 475#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_WIDTH 32
471/* default value of bitfield tx dma debug control [1f:0] */ 476/* default value of bitfield tx dma debug control [1f:0] */
472#define tdm_tx_dma_debug_ctl_default 0x0 477#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_DEFAULT 0x0
473 478
474/* tx dma descriptor base address lsw definitions 479/* tx dma descriptor base address lsw definitions
475 * preprocessor definitions for tx dma descriptor base address lsw 480 * preprocessor definitions for tx dma descriptor base address lsw
476 * base address: 0x00007c00 481 * base address: 0x00007c00
477 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 482 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
478 */ 483 */
479#define tx_dma_desc_base_addrlsw_adr(descriptor) \ 484#define HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \
480 (0x00007c00u + (descriptor) * 0x40) 485 (0x00007c00u + (descriptor) * 0x40)
481 486
482/* tx dma descriptor tail pointer register definitions 487/* tx dma descriptor tail pointer register definitions
@@ -484,7 +489,8 @@
484 * base address: 0x00007c10 489 * base address: 0x00007c10
485 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 490 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
486 */ 491 */
487#define tx_dma_desc_tail_ptr_adr(descriptor) (0x00007c10u + (descriptor) * 0x40) 492#define HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor) \
493 (0x00007c10u + (descriptor) * 0x40)
488 494
489/* rx dma_sys_loopback bitfield definitions 495/* rx dma_sys_loopback bitfield definitions
490 * preprocessor definitions for the bitfield "dma_sys_loopback". 496 * preprocessor definitions for the bitfield "dma_sys_loopback".
@@ -492,17 +498,17 @@
492 */ 498 */
493 499
494/* register address for bitfield dma_sys_loopback */ 500/* register address for bitfield dma_sys_loopback */
495#define rpb_dma_sys_lbk_adr 0x00005000 501#define HW_ATL_RPB_DMA_SYS_LBK_ADR 0x00005000
496/* bitmask for bitfield dma_sys_loopback */ 502/* bitmask for bitfield dma_sys_loopback */
497#define rpb_dma_sys_lbk_msk 0x00000040 503#define HW_ATL_RPB_DMA_SYS_LBK_MSK 0x00000040
498/* inverted bitmask for bitfield dma_sys_loopback */ 504/* inverted bitmask for bitfield dma_sys_loopback */
499#define rpb_dma_sys_lbk_mskn 0xffffffbf 505#define HW_ATL_RPB_DMA_SYS_LBK_MSKN 0xffffffbf
500/* lower bit position of bitfield dma_sys_loopback */ 506/* lower bit position of bitfield dma_sys_loopback */
501#define rpb_dma_sys_lbk_shift 6 507#define HW_ATL_RPB_DMA_SYS_LBK_SHIFT 6
502/* width of bitfield dma_sys_loopback */ 508/* width of bitfield dma_sys_loopback */
503#define rpb_dma_sys_lbk_width 1 509#define HW_ATL_RPB_DMA_SYS_LBK_WIDTH 1
504/* default value of bitfield dma_sys_loopback */ 510/* default value of bitfield dma_sys_loopback */
505#define rpb_dma_sys_lbk_default 0x0 511#define HW_ATL_RPB_DMA_SYS_LBK_DEFAULT 0x0
506 512
507/* rx rx_tc_mode bitfield definitions 513/* rx rx_tc_mode bitfield definitions
508 * preprocessor definitions for the bitfield "rx_tc_mode". 514 * preprocessor definitions for the bitfield "rx_tc_mode".
@@ -510,17 +516,17 @@
510 */ 516 */
511 517
512/* register address for bitfield rx_tc_mode */ 518/* register address for bitfield rx_tc_mode */
513#define rpb_rpf_rx_tc_mode_adr 0x00005700 519#define HW_ATL_RPB_RPF_RX_TC_MODE_ADR 0x00005700
514/* bitmask for bitfield rx_tc_mode */ 520/* bitmask for bitfield rx_tc_mode */
515#define rpb_rpf_rx_tc_mode_msk 0x00000100 521#define HW_ATL_RPB_RPF_RX_TC_MODE_MSK 0x00000100
516/* inverted bitmask for bitfield rx_tc_mode */ 522/* inverted bitmask for bitfield rx_tc_mode */
517#define rpb_rpf_rx_tc_mode_mskn 0xfffffeff 523#define HW_ATL_RPB_RPF_RX_TC_MODE_MSKN 0xfffffeff
518/* lower bit position of bitfield rx_tc_mode */ 524/* lower bit position of bitfield rx_tc_mode */
519#define rpb_rpf_rx_tc_mode_shift 8 525#define HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT 8
520/* width of bitfield rx_tc_mode */ 526/* width of bitfield rx_tc_mode */
521#define rpb_rpf_rx_tc_mode_width 1 527#define HW_ATL_RPB_RPF_RX_TC_MODE_WIDTH 1
522/* default value of bitfield rx_tc_mode */ 528/* default value of bitfield rx_tc_mode */
523#define rpb_rpf_rx_tc_mode_default 0x0 529#define HW_ATL_RPB_RPF_RX_TC_MODE_DEFAULT 0x0
524 530
525/* rx rx_buf_en bitfield definitions 531/* rx rx_buf_en bitfield definitions
526 * preprocessor definitions for the bitfield "rx_buf_en". 532 * preprocessor definitions for the bitfield "rx_buf_en".
@@ -528,17 +534,17 @@
528 */ 534 */
529 535
530/* register address for bitfield rx_buf_en */ 536/* register address for bitfield rx_buf_en */
531#define rpb_rx_buf_en_adr 0x00005700 537#define HW_ATL_RPB_RX_BUF_EN_ADR 0x00005700
532/* bitmask for bitfield rx_buf_en */ 538/* bitmask for bitfield rx_buf_en */
533#define rpb_rx_buf_en_msk 0x00000001 539#define HW_ATL_RPB_RX_BUF_EN_MSK 0x00000001
534/* inverted bitmask for bitfield rx_buf_en */ 540/* inverted bitmask for bitfield rx_buf_en */
535#define rpb_rx_buf_en_mskn 0xfffffffe 541#define HW_ATL_RPB_RX_BUF_EN_MSKN 0xfffffffe
536/* lower bit position of bitfield rx_buf_en */ 542/* lower bit position of bitfield rx_buf_en */
537#define rpb_rx_buf_en_shift 0 543#define HW_ATL_RPB_RX_BUF_EN_SHIFT 0
538/* width of bitfield rx_buf_en */ 544/* width of bitfield rx_buf_en */
539#define rpb_rx_buf_en_width 1 545#define HW_ATL_RPB_RX_BUF_EN_WIDTH 1
540/* default value of bitfield rx_buf_en */ 546/* default value of bitfield rx_buf_en */
541#define rpb_rx_buf_en_default 0x0 547#define HW_ATL_RPB_RX_BUF_EN_DEFAULT 0x0
542 548
543/* rx rx{b}_hi_thresh[d:0] bitfield definitions 549/* rx rx{b}_hi_thresh[d:0] bitfield definitions
544 * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]". 550 * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]".
@@ -547,17 +553,17 @@
547 */ 553 */
548 554
549/* register address for bitfield rx{b}_hi_thresh[d:0] */ 555/* register address for bitfield rx{b}_hi_thresh[d:0] */
550#define rpb_rxbhi_thresh_adr(buffer) (0x00005714 + (buffer) * 0x10) 556#define HW_ATL_RPB_RXBHI_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10)
551/* bitmask for bitfield rx{b}_hi_thresh[d:0] */ 557/* bitmask for bitfield rx{b}_hi_thresh[d:0] */
552#define rpb_rxbhi_thresh_msk 0x3fff0000 558#define HW_ATL_RPB_RXBHI_THRESH_MSK 0x3fff0000
553/* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */ 559/* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */
554#define rpb_rxbhi_thresh_mskn 0xc000ffff 560#define HW_ATL_RPB_RXBHI_THRESH_MSKN 0xc000ffff
555/* lower bit position of bitfield rx{b}_hi_thresh[d:0] */ 561/* lower bit position of bitfield rx{b}_hi_thresh[d:0] */
556#define rpb_rxbhi_thresh_shift 16 562#define HW_ATL_RPB_RXBHI_THRESH_SHIFT 16
557/* width of bitfield rx{b}_hi_thresh[d:0] */ 563/* width of bitfield rx{b}_hi_thresh[d:0] */
558#define rpb_rxbhi_thresh_width 14 564#define HW_ATL_RPB_RXBHI_THRESH_WIDTH 14
559/* default value of bitfield rx{b}_hi_thresh[d:0] */ 565/* default value of bitfield rx{b}_hi_thresh[d:0] */
560#define rpb_rxbhi_thresh_default 0x0 566#define HW_ATL_RPB_RXBHI_THRESH_DEFAULT 0x0
561 567
562/* rx rx{b}_lo_thresh[d:0] bitfield definitions 568/* rx rx{b}_lo_thresh[d:0] bitfield definitions
563 * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]". 569 * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]".
@@ -566,17 +572,17 @@
566 */ 572 */
567 573
568/* register address for bitfield rx{b}_lo_thresh[d:0] */ 574/* register address for bitfield rx{b}_lo_thresh[d:0] */
569#define rpb_rxblo_thresh_adr(buffer) (0x00005714 + (buffer) * 0x10) 575#define HW_ATL_RPB_RXBLO_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10)
570/* bitmask for bitfield rx{b}_lo_thresh[d:0] */ 576/* bitmask for bitfield rx{b}_lo_thresh[d:0] */
571#define rpb_rxblo_thresh_msk 0x00003fff 577#define HW_ATL_RPB_RXBLO_THRESH_MSK 0x00003fff
572/* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */ 578/* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */
573#define rpb_rxblo_thresh_mskn 0xffffc000 579#define HW_ATL_RPB_RXBLO_THRESH_MSKN 0xffffc000
574/* lower bit position of bitfield rx{b}_lo_thresh[d:0] */ 580/* lower bit position of bitfield rx{b}_lo_thresh[d:0] */
575#define rpb_rxblo_thresh_shift 0 581#define HW_ATL_RPB_RXBLO_THRESH_SHIFT 0
576/* width of bitfield rx{b}_lo_thresh[d:0] */ 582/* width of bitfield rx{b}_lo_thresh[d:0] */
577#define rpb_rxblo_thresh_width 14 583#define HW_ATL_RPB_RXBLO_THRESH_WIDTH 14
578/* default value of bitfield rx{b}_lo_thresh[d:0] */ 584/* default value of bitfield rx{b}_lo_thresh[d:0] */
579#define rpb_rxblo_thresh_default 0x0 585#define HW_ATL_RPB_RXBLO_THRESH_DEFAULT 0x0
580 586
581/* rx rx_fc_mode[1:0] bitfield definitions 587/* rx rx_fc_mode[1:0] bitfield definitions
582 * preprocessor definitions for the bitfield "rx_fc_mode[1:0]". 588 * preprocessor definitions for the bitfield "rx_fc_mode[1:0]".
@@ -584,17 +590,17 @@
584 */ 590 */
585 591
586/* register address for bitfield rx_fc_mode[1:0] */ 592/* register address for bitfield rx_fc_mode[1:0] */
587#define rpb_rx_fc_mode_adr 0x00005700 593#define HW_ATL_RPB_RX_FC_MODE_ADR 0x00005700
588/* bitmask for bitfield rx_fc_mode[1:0] */ 594/* bitmask for bitfield rx_fc_mode[1:0] */
589#define rpb_rx_fc_mode_msk 0x00000030 595#define HW_ATL_RPB_RX_FC_MODE_MSK 0x00000030
590/* inverted bitmask for bitfield rx_fc_mode[1:0] */ 596/* inverted bitmask for bitfield rx_fc_mode[1:0] */
591#define rpb_rx_fc_mode_mskn 0xffffffcf 597#define HW_ATL_RPB_RX_FC_MODE_MSKN 0xffffffcf
592/* lower bit position of bitfield rx_fc_mode[1:0] */ 598/* lower bit position of bitfield rx_fc_mode[1:0] */
593#define rpb_rx_fc_mode_shift 4 599#define HW_ATL_RPB_RX_FC_MODE_SHIFT 4
594/* width of bitfield rx_fc_mode[1:0] */ 600/* width of bitfield rx_fc_mode[1:0] */
595#define rpb_rx_fc_mode_width 2 601#define HW_ATL_RPB_RX_FC_MODE_WIDTH 2
596/* default value of bitfield rx_fc_mode[1:0] */ 602/* default value of bitfield rx_fc_mode[1:0] */
597#define rpb_rx_fc_mode_default 0x0 603#define HW_ATL_RPB_RX_FC_MODE_DEFAULT 0x0
598 604
599/* rx rx{b}_buf_size[8:0] bitfield definitions 605/* rx rx{b}_buf_size[8:0] bitfield definitions
600 * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]". 606 * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]".
@@ -603,17 +609,17 @@
603 */ 609 */
604 610
605/* register address for bitfield rx{b}_buf_size[8:0] */ 611/* register address for bitfield rx{b}_buf_size[8:0] */
606#define rpb_rxbbuf_size_adr(buffer) (0x00005710 + (buffer) * 0x10) 612#define HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer) (0x00005710 + (buffer) * 0x10)
607/* bitmask for bitfield rx{b}_buf_size[8:0] */ 613/* bitmask for bitfield rx{b}_buf_size[8:0] */
608#define rpb_rxbbuf_size_msk 0x000001ff 614#define HW_ATL_RPB_RXBBUF_SIZE_MSK 0x000001ff
609/* inverted bitmask for bitfield rx{b}_buf_size[8:0] */ 615/* inverted bitmask for bitfield rx{b}_buf_size[8:0] */
610#define rpb_rxbbuf_size_mskn 0xfffffe00 616#define HW_ATL_RPB_RXBBUF_SIZE_MSKN 0xfffffe00
611/* lower bit position of bitfield rx{b}_buf_size[8:0] */ 617/* lower bit position of bitfield rx{b}_buf_size[8:0] */
612#define rpb_rxbbuf_size_shift 0 618#define HW_ATL_RPB_RXBBUF_SIZE_SHIFT 0
613/* width of bitfield rx{b}_buf_size[8:0] */ 619/* width of bitfield rx{b}_buf_size[8:0] */
614#define rpb_rxbbuf_size_width 9 620#define HW_ATL_RPB_RXBBUF_SIZE_WIDTH 9
615/* default value of bitfield rx{b}_buf_size[8:0] */ 621/* default value of bitfield rx{b}_buf_size[8:0] */
616#define rpb_rxbbuf_size_default 0x0 622#define HW_ATL_RPB_RXBBUF_SIZE_DEFAULT 0x0
617 623
618/* rx rx{b}_xoff_en bitfield definitions 624/* rx rx{b}_xoff_en bitfield definitions
619 * preprocessor definitions for the bitfield "rx{b}_xoff_en". 625 * preprocessor definitions for the bitfield "rx{b}_xoff_en".
@@ -622,17 +628,17 @@
622 */ 628 */
623 629
624/* register address for bitfield rx{b}_xoff_en */ 630/* register address for bitfield rx{b}_xoff_en */
625#define rpb_rxbxoff_en_adr(buffer) (0x00005714 + (buffer) * 0x10) 631#define HW_ATL_RPB_RXBXOFF_EN_ADR(buffer) (0x00005714 + (buffer) * 0x10)
626/* bitmask for bitfield rx{b}_xoff_en */ 632/* bitmask for bitfield rx{b}_xoff_en */
627#define rpb_rxbxoff_en_msk 0x80000000 633#define HW_ATL_RPB_RXBXOFF_EN_MSK 0x80000000
628/* inverted bitmask for bitfield rx{b}_xoff_en */ 634/* inverted bitmask for bitfield rx{b}_xoff_en */
629#define rpb_rxbxoff_en_mskn 0x7fffffff 635#define HW_ATL_RPB_RXBXOFF_EN_MSKN 0x7fffffff
630/* lower bit position of bitfield rx{b}_xoff_en */ 636/* lower bit position of bitfield rx{b}_xoff_en */
631#define rpb_rxbxoff_en_shift 31 637#define HW_ATL_RPB_RXBXOFF_EN_SHIFT 31
632/* width of bitfield rx{b}_xoff_en */ 638/* width of bitfield rx{b}_xoff_en */
633#define rpb_rxbxoff_en_width 1 639#define HW_ATL_RPB_RXBXOFF_EN_WIDTH 1
634/* default value of bitfield rx{b}_xoff_en */ 640/* default value of bitfield rx{b}_xoff_en */
635#define rpb_rxbxoff_en_default 0x0 641#define HW_ATL_RPB_RXBXOFF_EN_DEFAULT 0x0
636 642
637/* rx l2_bc_thresh[f:0] bitfield definitions 643/* rx l2_bc_thresh[f:0] bitfield definitions
638 * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]". 644 * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]".
@@ -640,17 +646,17 @@
640 */ 646 */
641 647
642/* register address for bitfield l2_bc_thresh[f:0] */ 648/* register address for bitfield l2_bc_thresh[f:0] */
643#define rpfl2bc_thresh_adr 0x00005100 649#define HW_ATL_RPFL2BC_THRESH_ADR 0x00005100
644/* bitmask for bitfield l2_bc_thresh[f:0] */ 650/* bitmask for bitfield l2_bc_thresh[f:0] */
645#define rpfl2bc_thresh_msk 0xffff0000 651#define HW_ATL_RPFL2BC_THRESH_MSK 0xffff0000
646/* inverted bitmask for bitfield l2_bc_thresh[f:0] */ 652/* inverted bitmask for bitfield l2_bc_thresh[f:0] */
647#define rpfl2bc_thresh_mskn 0x0000ffff 653#define HW_ATL_RPFL2BC_THRESH_MSKN 0x0000ffff
648/* lower bit position of bitfield l2_bc_thresh[f:0] */ 654/* lower bit position of bitfield l2_bc_thresh[f:0] */
649#define rpfl2bc_thresh_shift 16 655#define HW_ATL_RPFL2BC_THRESH_SHIFT 16
650/* width of bitfield l2_bc_thresh[f:0] */ 656/* width of bitfield l2_bc_thresh[f:0] */
651#define rpfl2bc_thresh_width 16 657#define HW_ATL_RPFL2BC_THRESH_WIDTH 16
652/* default value of bitfield l2_bc_thresh[f:0] */ 658/* default value of bitfield l2_bc_thresh[f:0] */
653#define rpfl2bc_thresh_default 0x0 659#define HW_ATL_RPFL2BC_THRESH_DEFAULT 0x0
654 660
655/* rx l2_bc_en bitfield definitions 661/* rx l2_bc_en bitfield definitions
656 * preprocessor definitions for the bitfield "l2_bc_en". 662 * preprocessor definitions for the bitfield "l2_bc_en".
@@ -658,17 +664,17 @@
658 */ 664 */
659 665
660/* register address for bitfield l2_bc_en */ 666/* register address for bitfield l2_bc_en */
661#define rpfl2bc_en_adr 0x00005100 667#define HW_ATL_RPFL2BC_EN_ADR 0x00005100
662/* bitmask for bitfield l2_bc_en */ 668/* bitmask for bitfield l2_bc_en */
663#define rpfl2bc_en_msk 0x00000001 669#define HW_ATL_RPFL2BC_EN_MSK 0x00000001
664/* inverted bitmask for bitfield l2_bc_en */ 670/* inverted bitmask for bitfield l2_bc_en */
665#define rpfl2bc_en_mskn 0xfffffffe 671#define HW_ATL_RPFL2BC_EN_MSKN 0xfffffffe
666/* lower bit position of bitfield l2_bc_en */ 672/* lower bit position of bitfield l2_bc_en */
667#define rpfl2bc_en_shift 0 673#define HW_ATL_RPFL2BC_EN_SHIFT 0
668/* width of bitfield l2_bc_en */ 674/* width of bitfield l2_bc_en */
669#define rpfl2bc_en_width 1 675#define HW_ATL_RPFL2BC_EN_WIDTH 1
670/* default value of bitfield l2_bc_en */ 676/* default value of bitfield l2_bc_en */
671#define rpfl2bc_en_default 0x0 677#define HW_ATL_RPFL2BC_EN_DEFAULT 0x0
672 678
673/* rx l2_bc_act[2:0] bitfield definitions 679/* rx l2_bc_act[2:0] bitfield definitions
674 * preprocessor definitions for the bitfield "l2_bc_act[2:0]". 680 * preprocessor definitions for the bitfield "l2_bc_act[2:0]".
@@ -676,17 +682,17 @@
676 */ 682 */
677 683
678/* register address for bitfield l2_bc_act[2:0] */ 684/* register address for bitfield l2_bc_act[2:0] */
679#define rpfl2bc_act_adr 0x00005100 685#define HW_ATL_RPFL2BC_ACT_ADR 0x00005100
680/* bitmask for bitfield l2_bc_act[2:0] */ 686/* bitmask for bitfield l2_bc_act[2:0] */
681#define rpfl2bc_act_msk 0x00007000 687#define HW_ATL_RPFL2BC_ACT_MSK 0x00007000
682/* inverted bitmask for bitfield l2_bc_act[2:0] */ 688/* inverted bitmask for bitfield l2_bc_act[2:0] */
683#define rpfl2bc_act_mskn 0xffff8fff 689#define HW_ATL_RPFL2BC_ACT_MSKN 0xffff8fff
684/* lower bit position of bitfield l2_bc_act[2:0] */ 690/* lower bit position of bitfield l2_bc_act[2:0] */
685#define rpfl2bc_act_shift 12 691#define HW_ATL_RPFL2BC_ACT_SHIFT 12
686/* width of bitfield l2_bc_act[2:0] */ 692/* width of bitfield l2_bc_act[2:0] */
687#define rpfl2bc_act_width 3 693#define HW_ATL_RPFL2BC_ACT_WIDTH 3
688/* default value of bitfield l2_bc_act[2:0] */ 694/* default value of bitfield l2_bc_act[2:0] */
689#define rpfl2bc_act_default 0x0 695#define HW_ATL_RPFL2BC_ACT_DEFAULT 0x0
690 696
691/* rx l2_mc_en{f} bitfield definitions 697/* rx l2_mc_en{f} bitfield definitions
692 * preprocessor definitions for the bitfield "l2_mc_en{f}". 698 * preprocessor definitions for the bitfield "l2_mc_en{f}".
@@ -695,17 +701,17 @@
695 */ 701 */
696 702
697/* register address for bitfield l2_mc_en{f} */ 703/* register address for bitfield l2_mc_en{f} */
698#define rpfl2mc_enf_adr(filter) (0x00005250 + (filter) * 0x4) 704#define HW_ATL_RPFL2MC_ENF_ADR(filter) (0x00005250 + (filter) * 0x4)
699/* bitmask for bitfield l2_mc_en{f} */ 705/* bitmask for bitfield l2_mc_en{f} */
700#define rpfl2mc_enf_msk 0x80000000 706#define HW_ATL_RPFL2MC_ENF_MSK 0x80000000
701/* inverted bitmask for bitfield l2_mc_en{f} */ 707/* inverted bitmask for bitfield l2_mc_en{f} */
702#define rpfl2mc_enf_mskn 0x7fffffff 708#define HW_ATL_RPFL2MC_ENF_MSKN 0x7fffffff
703/* lower bit position of bitfield l2_mc_en{f} */ 709/* lower bit position of bitfield l2_mc_en{f} */
704#define rpfl2mc_enf_shift 31 710#define HW_ATL_RPFL2MC_ENF_SHIFT 31
705/* width of bitfield l2_mc_en{f} */ 711/* width of bitfield l2_mc_en{f} */
706#define rpfl2mc_enf_width 1 712#define HW_ATL_RPFL2MC_ENF_WIDTH 1
707/* default value of bitfield l2_mc_en{f} */ 713/* default value of bitfield l2_mc_en{f} */
708#define rpfl2mc_enf_default 0x0 714#define HW_ATL_RPFL2MC_ENF_DEFAULT 0x0
709 715
710/* rx l2_promis_mode bitfield definitions 716/* rx l2_promis_mode bitfield definitions
711 * preprocessor definitions for the bitfield "l2_promis_mode". 717 * preprocessor definitions for the bitfield "l2_promis_mode".
@@ -713,17 +719,17 @@
713 */ 719 */
714 720
715/* register address for bitfield l2_promis_mode */ 721/* register address for bitfield l2_promis_mode */
716#define rpfl2promis_mode_adr 0x00005100 722#define HW_ATL_RPFL2PROMIS_MODE_ADR 0x00005100
717/* bitmask for bitfield l2_promis_mode */ 723/* bitmask for bitfield l2_promis_mode */
718#define rpfl2promis_mode_msk 0x00000008 724#define HW_ATL_RPFL2PROMIS_MODE_MSK 0x00000008
719/* inverted bitmask for bitfield l2_promis_mode */ 725/* inverted bitmask for bitfield l2_promis_mode */
720#define rpfl2promis_mode_mskn 0xfffffff7 726#define HW_ATL_RPFL2PROMIS_MODE_MSKN 0xfffffff7
721/* lower bit position of bitfield l2_promis_mode */ 727/* lower bit position of bitfield l2_promis_mode */
722#define rpfl2promis_mode_shift 3 728#define HW_ATL_RPFL2PROMIS_MODE_SHIFT 3
723/* width of bitfield l2_promis_mode */ 729/* width of bitfield l2_promis_mode */
724#define rpfl2promis_mode_width 1 730#define HW_ATL_RPFL2PROMIS_MODE_WIDTH 1
725/* default value of bitfield l2_promis_mode */ 731/* default value of bitfield l2_promis_mode */
726#define rpfl2promis_mode_default 0x0 732#define HW_ATL_RPFL2PROMIS_MODE_DEFAULT 0x0
727 733
728/* rx l2_uc_act{f}[2:0] bitfield definitions 734/* rx l2_uc_act{f}[2:0] bitfield definitions
729 * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]". 735 * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]".
@@ -732,17 +738,17 @@
732 */ 738 */
733 739
734/* register address for bitfield l2_uc_act{f}[2:0] */ 740/* register address for bitfield l2_uc_act{f}[2:0] */
735#define rpfl2uc_actf_adr(filter) (0x00005114 + (filter) * 0x8) 741#define HW_ATL_RPFL2UC_ACTF_ADR(filter) (0x00005114 + (filter) * 0x8)
736/* bitmask for bitfield l2_uc_act{f}[2:0] */ 742/* bitmask for bitfield l2_uc_act{f}[2:0] */
737#define rpfl2uc_actf_msk 0x00070000 743#define HW_ATL_RPFL2UC_ACTF_MSK 0x00070000
738/* inverted bitmask for bitfield l2_uc_act{f}[2:0] */ 744/* inverted bitmask for bitfield l2_uc_act{f}[2:0] */
739#define rpfl2uc_actf_mskn 0xfff8ffff 745#define HW_ATL_RPFL2UC_ACTF_MSKN 0xfff8ffff
740/* lower bit position of bitfield l2_uc_act{f}[2:0] */ 746/* lower bit position of bitfield l2_uc_act{f}[2:0] */
741#define rpfl2uc_actf_shift 16 747#define HW_ATL_RPFL2UC_ACTF_SHIFT 16
742/* width of bitfield l2_uc_act{f}[2:0] */ 748/* width of bitfield l2_uc_act{f}[2:0] */
743#define rpfl2uc_actf_width 3 749#define HW_ATL_RPFL2UC_ACTF_WIDTH 3
744/* default value of bitfield l2_uc_act{f}[2:0] */ 750/* default value of bitfield l2_uc_act{f}[2:0] */
745#define rpfl2uc_actf_default 0x0 751#define HW_ATL_RPFL2UC_ACTF_DEFAULT 0x0
746 752
747/* rx l2_uc_en{f} bitfield definitions 753/* rx l2_uc_en{f} bitfield definitions
748 * preprocessor definitions for the bitfield "l2_uc_en{f}". 754 * preprocessor definitions for the bitfield "l2_uc_en{f}".
@@ -751,26 +757,26 @@
751 */ 757 */
752 758
753/* register address for bitfield l2_uc_en{f} */ 759/* register address for bitfield l2_uc_en{f} */
754#define rpfl2uc_enf_adr(filter) (0x00005114 + (filter) * 0x8) 760#define HW_ATL_RPFL2UC_ENF_ADR(filter) (0x00005114 + (filter) * 0x8)
755/* bitmask for bitfield l2_uc_en{f} */ 761/* bitmask for bitfield l2_uc_en{f} */
756#define rpfl2uc_enf_msk 0x80000000 762#define HW_ATL_RPFL2UC_ENF_MSK 0x80000000
757/* inverted bitmask for bitfield l2_uc_en{f} */ 763/* inverted bitmask for bitfield l2_uc_en{f} */
758#define rpfl2uc_enf_mskn 0x7fffffff 764#define HW_ATL_RPFL2UC_ENF_MSKN 0x7fffffff
759/* lower bit position of bitfield l2_uc_en{f} */ 765/* lower bit position of bitfield l2_uc_en{f} */
760#define rpfl2uc_enf_shift 31 766#define HW_ATL_RPFL2UC_ENF_SHIFT 31
761/* width of bitfield l2_uc_en{f} */ 767/* width of bitfield l2_uc_en{f} */
762#define rpfl2uc_enf_width 1 768#define HW_ATL_RPFL2UC_ENF_WIDTH 1
763/* default value of bitfield l2_uc_en{f} */ 769/* default value of bitfield l2_uc_en{f} */
764#define rpfl2uc_enf_default 0x0 770#define HW_ATL_RPFL2UC_ENF_DEFAULT 0x0
765 771
766/* register address for bitfield l2_uc_da{f}_lsw[1f:0] */ 772/* register address for bitfield l2_uc_da{f}_lsw[1f:0] */
767#define rpfl2uc_daflsw_adr(filter) (0x00005110 + (filter) * 0x8) 773#define HW_ATL_RPFL2UC_DAFLSW_ADR(filter) (0x00005110 + (filter) * 0x8)
768/* register address for bitfield l2_uc_da{f}_msw[f:0] */ 774/* register address for bitfield l2_uc_da{f}_msw[f:0] */
769#define rpfl2uc_dafmsw_adr(filter) (0x00005114 + (filter) * 0x8) 775#define HW_ATL_RPFL2UC_DAFMSW_ADR(filter) (0x00005114 + (filter) * 0x8)
770/* bitmask for bitfield l2_uc_da{f}_msw[f:0] */ 776/* bitmask for bitfield l2_uc_da{f}_msw[f:0] */
771#define rpfl2uc_dafmsw_msk 0x0000ffff 777#define HW_ATL_RPFL2UC_DAFMSW_MSK 0x0000ffff
772/* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */ 778/* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */
773#define rpfl2uc_dafmsw_shift 0 779#define HW_ATL_RPFL2UC_DAFMSW_SHIFT 0
774 780
775/* rx l2_mc_accept_all bitfield definitions 781/* rx l2_mc_accept_all bitfield definitions
776 * Preprocessor definitions for the bitfield "l2_mc_accept_all". 782 * Preprocessor definitions for the bitfield "l2_mc_accept_all".
@@ -778,22 +784,22 @@
778 */ 784 */
779 785
780/* Register address for bitfield l2_mc_accept_all */ 786/* Register address for bitfield l2_mc_accept_all */
781#define rpfl2mc_accept_all_adr 0x00005270 787#define HW_ATL_RPFL2MC_ACCEPT_ALL_ADR 0x00005270
782/* Bitmask for bitfield l2_mc_accept_all */ 788/* Bitmask for bitfield l2_mc_accept_all */
783#define rpfl2mc_accept_all_msk 0x00004000 789#define HW_ATL_RPFL2MC_ACCEPT_ALL_MSK 0x00004000
784/* Inverted bitmask for bitfield l2_mc_accept_all */ 790/* Inverted bitmask for bitfield l2_mc_accept_all */
785#define rpfl2mc_accept_all_mskn 0xFFFFBFFF 791#define HW_ATL_RPFL2MC_ACCEPT_ALL_MSKN 0xFFFFBFFF
786/* Lower bit position of bitfield l2_mc_accept_all */ 792/* Lower bit position of bitfield l2_mc_accept_all */
787#define rpfl2mc_accept_all_shift 14 793#define HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT 14
788/* Width of bitfield l2_mc_accept_all */ 794/* Width of bitfield l2_mc_accept_all */
789#define rpfl2mc_accept_all_width 1 795#define HW_ATL_RPFL2MC_ACCEPT_ALL_WIDTH 1
790/* Default value of bitfield l2_mc_accept_all */ 796/* Default value of bitfield l2_mc_accept_all */
791#define rpfl2mc_accept_all_default 0x0 797#define HW_ATL_RPFL2MC_ACCEPT_ALL_DEFAULT 0x0
792 798
793/* width of bitfield rx_tc_up{t}[2:0] */ 799/* width of bitfield rx_tc_up{t}[2:0] */
794#define rpf_rpb_rx_tc_upt_width 3 800#define HW_ATL_RPF_RPB_RX_TC_UPT_WIDTH 3
795/* default value of bitfield rx_tc_up{t}[2:0] */ 801/* default value of bitfield rx_tc_up{t}[2:0] */
796#define rpf_rpb_rx_tc_upt_default 0x0 802#define HW_ATL_RPF_RPB_RX_TC_UPT_DEFAULT 0x0
797 803
798/* rx rss_key_addr[4:0] bitfield definitions 804/* rx rss_key_addr[4:0] bitfield definitions
799 * preprocessor definitions for the bitfield "rss_key_addr[4:0]". 805 * preprocessor definitions for the bitfield "rss_key_addr[4:0]".
@@ -801,17 +807,17 @@
801 */ 807 */
802 808
803/* register address for bitfield rss_key_addr[4:0] */ 809/* register address for bitfield rss_key_addr[4:0] */
804#define rpf_rss_key_addr_adr 0x000054d0 810#define HW_ATL_RPF_RSS_KEY_ADDR_ADR 0x000054d0
805/* bitmask for bitfield rss_key_addr[4:0] */ 811/* bitmask for bitfield rss_key_addr[4:0] */
806#define rpf_rss_key_addr_msk 0x0000001f 812#define HW_ATL_RPF_RSS_KEY_ADDR_MSK 0x0000001f
807/* inverted bitmask for bitfield rss_key_addr[4:0] */ 813/* inverted bitmask for bitfield rss_key_addr[4:0] */
808#define rpf_rss_key_addr_mskn 0xffffffe0 814#define HW_ATL_RPF_RSS_KEY_ADDR_MSKN 0xffffffe0
809/* lower bit position of bitfield rss_key_addr[4:0] */ 815/* lower bit position of bitfield rss_key_addr[4:0] */
810#define rpf_rss_key_addr_shift 0 816#define HW_ATL_RPF_RSS_KEY_ADDR_SHIFT 0
811/* width of bitfield rss_key_addr[4:0] */ 817/* width of bitfield rss_key_addr[4:0] */
812#define rpf_rss_key_addr_width 5 818#define HW_ATL_RPF_RSS_KEY_ADDR_WIDTH 5
813/* default value of bitfield rss_key_addr[4:0] */ 819/* default value of bitfield rss_key_addr[4:0] */
814#define rpf_rss_key_addr_default 0x0 820#define HW_ATL_RPF_RSS_KEY_ADDR_DEFAULT 0x0
815 821
816/* rx rss_key_wr_data[1f:0] bitfield definitions 822/* rx rss_key_wr_data[1f:0] bitfield definitions
817 * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]". 823 * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]".
@@ -819,17 +825,17 @@
819 */ 825 */
820 826
821/* register address for bitfield rss_key_wr_data[1f:0] */ 827/* register address for bitfield rss_key_wr_data[1f:0] */
822#define rpf_rss_key_wr_data_adr 0x000054d4 828#define HW_ATL_RPF_RSS_KEY_WR_DATA_ADR 0x000054d4
823/* bitmask for bitfield rss_key_wr_data[1f:0] */ 829/* bitmask for bitfield rss_key_wr_data[1f:0] */
824#define rpf_rss_key_wr_data_msk 0xffffffff 830#define HW_ATL_RPF_RSS_KEY_WR_DATA_MSK 0xffffffff
825/* inverted bitmask for bitfield rss_key_wr_data[1f:0] */ 831/* inverted bitmask for bitfield rss_key_wr_data[1f:0] */
826#define rpf_rss_key_wr_data_mskn 0x00000000 832#define HW_ATL_RPF_RSS_KEY_WR_DATA_MSKN 0x00000000
827/* lower bit position of bitfield rss_key_wr_data[1f:0] */ 833/* lower bit position of bitfield rss_key_wr_data[1f:0] */
828#define rpf_rss_key_wr_data_shift 0 834#define HW_ATL_RPF_RSS_KEY_WR_DATA_SHIFT 0
829/* width of bitfield rss_key_wr_data[1f:0] */ 835/* width of bitfield rss_key_wr_data[1f:0] */
830#define rpf_rss_key_wr_data_width 32 836#define HW_ATL_RPF_RSS_KEY_WR_DATA_WIDTH 32
831/* default value of bitfield rss_key_wr_data[1f:0] */ 837/* default value of bitfield rss_key_wr_data[1f:0] */
832#define rpf_rss_key_wr_data_default 0x0 838#define HW_ATL_RPF_RSS_KEY_WR_DATA_DEFAULT 0x0
833 839
834/* rx rss_key_wr_en_i bitfield definitions 840/* rx rss_key_wr_en_i bitfield definitions
835 * preprocessor definitions for the bitfield "rss_key_wr_en_i". 841 * preprocessor definitions for the bitfield "rss_key_wr_en_i".
@@ -837,17 +843,17 @@
837 */ 843 */
838 844
839/* register address for bitfield rss_key_wr_en_i */ 845/* register address for bitfield rss_key_wr_en_i */
840#define rpf_rss_key_wr_eni_adr 0x000054d0 846#define HW_ATL_RPF_RSS_KEY_WR_ENI_ADR 0x000054d0
841/* bitmask for bitfield rss_key_wr_en_i */ 847/* bitmask for bitfield rss_key_wr_en_i */
842#define rpf_rss_key_wr_eni_msk 0x00000020 848#define HW_ATL_RPF_RSS_KEY_WR_ENI_MSK 0x00000020
843/* inverted bitmask for bitfield rss_key_wr_en_i */ 849/* inverted bitmask for bitfield rss_key_wr_en_i */
844#define rpf_rss_key_wr_eni_mskn 0xffffffdf 850#define HW_ATL_RPF_RSS_KEY_WR_ENI_MSKN 0xffffffdf
845/* lower bit position of bitfield rss_key_wr_en_i */ 851/* lower bit position of bitfield rss_key_wr_en_i */
846#define rpf_rss_key_wr_eni_shift 5 852#define HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT 5
847/* width of bitfield rss_key_wr_en_i */ 853/* width of bitfield rss_key_wr_en_i */
848#define rpf_rss_key_wr_eni_width 1 854#define HW_ATL_RPF_RSS_KEY_WR_ENI_WIDTH 1
849/* default value of bitfield rss_key_wr_en_i */ 855/* default value of bitfield rss_key_wr_en_i */
850#define rpf_rss_key_wr_eni_default 0x0 856#define HW_ATL_RPF_RSS_KEY_WR_ENI_DEFAULT 0x0
851 857
852/* rx rss_redir_addr[3:0] bitfield definitions 858/* rx rss_redir_addr[3:0] bitfield definitions
853 * preprocessor definitions for the bitfield "rss_redir_addr[3:0]". 859 * preprocessor definitions for the bitfield "rss_redir_addr[3:0]".
@@ -855,17 +861,17 @@
855 */ 861 */
856 862
857/* register address for bitfield rss_redir_addr[3:0] */ 863/* register address for bitfield rss_redir_addr[3:0] */
858#define rpf_rss_redir_addr_adr 0x000054e0 864#define HW_ATL_RPF_RSS_REDIR_ADDR_ADR 0x000054e0
859/* bitmask for bitfield rss_redir_addr[3:0] */ 865/* bitmask for bitfield rss_redir_addr[3:0] */
860#define rpf_rss_redir_addr_msk 0x0000000f 866#define HW_ATL_RPF_RSS_REDIR_ADDR_MSK 0x0000000f
861/* inverted bitmask for bitfield rss_redir_addr[3:0] */ 867/* inverted bitmask for bitfield rss_redir_addr[3:0] */
862#define rpf_rss_redir_addr_mskn 0xfffffff0 868#define HW_ATL_RPF_RSS_REDIR_ADDR_MSKN 0xfffffff0
863/* lower bit position of bitfield rss_redir_addr[3:0] */ 869/* lower bit position of bitfield rss_redir_addr[3:0] */
864#define rpf_rss_redir_addr_shift 0 870#define HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT 0
865/* width of bitfield rss_redir_addr[3:0] */ 871/* width of bitfield rss_redir_addr[3:0] */
866#define rpf_rss_redir_addr_width 4 872#define HW_ATL_RPF_RSS_REDIR_ADDR_WIDTH 4
867/* default value of bitfield rss_redir_addr[3:0] */ 873/* default value of bitfield rss_redir_addr[3:0] */
868#define rpf_rss_redir_addr_default 0x0 874#define HW_ATL_RPF_RSS_REDIR_ADDR_DEFAULT 0x0
869 875
870/* rx rss_redir_wr_data[f:0] bitfield definitions 876/* rx rss_redir_wr_data[f:0] bitfield definitions
871 * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]". 877 * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]".
@@ -873,17 +879,17 @@
873 */ 879 */
874 880
875/* register address for bitfield rss_redir_wr_data[f:0] */ 881/* register address for bitfield rss_redir_wr_data[f:0] */
876#define rpf_rss_redir_wr_data_adr 0x000054e4 882#define HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR 0x000054e4
877/* bitmask for bitfield rss_redir_wr_data[f:0] */ 883/* bitmask for bitfield rss_redir_wr_data[f:0] */
878#define rpf_rss_redir_wr_data_msk 0x0000ffff 884#define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK 0x0000ffff
879/* inverted bitmask for bitfield rss_redir_wr_data[f:0] */ 885/* inverted bitmask for bitfield rss_redir_wr_data[f:0] */
880#define rpf_rss_redir_wr_data_mskn 0xffff0000 886#define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSKN 0xffff0000
881/* lower bit position of bitfield rss_redir_wr_data[f:0] */ 887/* lower bit position of bitfield rss_redir_wr_data[f:0] */
882#define rpf_rss_redir_wr_data_shift 0 888#define HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT 0
883/* width of bitfield rss_redir_wr_data[f:0] */ 889/* width of bitfield rss_redir_wr_data[f:0] */
884#define rpf_rss_redir_wr_data_width 16 890#define HW_ATL_RPF_RSS_REDIR_WR_DATA_WIDTH 16
885/* default value of bitfield rss_redir_wr_data[f:0] */ 891/* default value of bitfield rss_redir_wr_data[f:0] */
886#define rpf_rss_redir_wr_data_default 0x0 892#define HW_ATL_RPF_RSS_REDIR_WR_DATA_DEFAULT 0x0
887 893
888/* rx rss_redir_wr_en_i bitfield definitions 894/* rx rss_redir_wr_en_i bitfield definitions
889 * preprocessor definitions for the bitfield "rss_redir_wr_en_i". 895 * preprocessor definitions for the bitfield "rss_redir_wr_en_i".
@@ -891,17 +897,17 @@
891 */ 897 */
892 898
893/* register address for bitfield rss_redir_wr_en_i */ 899/* register address for bitfield rss_redir_wr_en_i */
894#define rpf_rss_redir_wr_eni_adr 0x000054e0 900#define HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR 0x000054e0
895/* bitmask for bitfield rss_redir_wr_en_i */ 901/* bitmask for bitfield rss_redir_wr_en_i */
896#define rpf_rss_redir_wr_eni_msk 0x00000010 902#define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK 0x00000010
897/* inverted bitmask for bitfield rss_redir_wr_en_i */ 903/* inverted bitmask for bitfield rss_redir_wr_en_i */
898#define rpf_rss_redir_wr_eni_mskn 0xffffffef 904#define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSKN 0xffffffef
899/* lower bit position of bitfield rss_redir_wr_en_i */ 905/* lower bit position of bitfield rss_redir_wr_en_i */
900#define rpf_rss_redir_wr_eni_shift 4 906#define HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT 4
901/* width of bitfield rss_redir_wr_en_i */ 907/* width of bitfield rss_redir_wr_en_i */
902#define rpf_rss_redir_wr_eni_width 1 908#define HW_ATL_RPF_RSS_REDIR_WR_ENI_WIDTH 1
903/* default value of bitfield rss_redir_wr_en_i */ 909/* default value of bitfield rss_redir_wr_en_i */
904#define rpf_rss_redir_wr_eni_default 0x0 910#define HW_ATL_RPF_RSS_REDIR_WR_ENI_DEFAULT 0x0
905 911
906/* rx tpo_rpf_sys_loopback bitfield definitions 912/* rx tpo_rpf_sys_loopback bitfield definitions
907 * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback". 913 * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback".
@@ -909,17 +915,17 @@
909 */ 915 */
910 916
911/* register address for bitfield tpo_rpf_sys_loopback */ 917/* register address for bitfield tpo_rpf_sys_loopback */
912#define rpf_tpo_rpf_sys_lbk_adr 0x00005000 918#define HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR 0x00005000
913/* bitmask for bitfield tpo_rpf_sys_loopback */ 919/* bitmask for bitfield tpo_rpf_sys_loopback */
914#define rpf_tpo_rpf_sys_lbk_msk 0x00000100 920#define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK 0x00000100
915/* inverted bitmask for bitfield tpo_rpf_sys_loopback */ 921/* inverted bitmask for bitfield tpo_rpf_sys_loopback */
916#define rpf_tpo_rpf_sys_lbk_mskn 0xfffffeff 922#define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSKN 0xfffffeff
917/* lower bit position of bitfield tpo_rpf_sys_loopback */ 923/* lower bit position of bitfield tpo_rpf_sys_loopback */
918#define rpf_tpo_rpf_sys_lbk_shift 8 924#define HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT 8
919/* width of bitfield tpo_rpf_sys_loopback */ 925/* width of bitfield tpo_rpf_sys_loopback */
920#define rpf_tpo_rpf_sys_lbk_width 1 926#define HW_ATL_RPF_TPO_RPF_SYS_LBK_WIDTH 1
921/* default value of bitfield tpo_rpf_sys_loopback */ 927/* default value of bitfield tpo_rpf_sys_loopback */
922#define rpf_tpo_rpf_sys_lbk_default 0x0 928#define HW_ATL_RPF_TPO_RPF_SYS_LBK_DEFAULT 0x0
923 929
924/* rx vl_inner_tpid[f:0] bitfield definitions 930/* rx vl_inner_tpid[f:0] bitfield definitions
925 * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]". 931 * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]".
@@ -927,17 +933,17 @@
927 */ 933 */
928 934
929/* register address for bitfield vl_inner_tpid[f:0] */ 935/* register address for bitfield vl_inner_tpid[f:0] */
930#define rpf_vl_inner_tpid_adr 0x00005284 936#define HW_ATL_RPF_VL_INNER_TPID_ADR 0x00005284
931/* bitmask for bitfield vl_inner_tpid[f:0] */ 937/* bitmask for bitfield vl_inner_tpid[f:0] */
932#define rpf_vl_inner_tpid_msk 0x0000ffff 938#define HW_ATL_RPF_VL_INNER_TPID_MSK 0x0000ffff
933/* inverted bitmask for bitfield vl_inner_tpid[f:0] */ 939/* inverted bitmask for bitfield vl_inner_tpid[f:0] */
934#define rpf_vl_inner_tpid_mskn 0xffff0000 940#define HW_ATL_RPF_VL_INNER_TPID_MSKN 0xffff0000
935/* lower bit position of bitfield vl_inner_tpid[f:0] */ 941/* lower bit position of bitfield vl_inner_tpid[f:0] */
936#define rpf_vl_inner_tpid_shift 0 942#define HW_ATL_RPF_VL_INNER_TPID_SHIFT 0
937/* width of bitfield vl_inner_tpid[f:0] */ 943/* width of bitfield vl_inner_tpid[f:0] */
938#define rpf_vl_inner_tpid_width 16 944#define HW_ATL_RPF_VL_INNER_TPID_WIDTH 16
939/* default value of bitfield vl_inner_tpid[f:0] */ 945/* default value of bitfield vl_inner_tpid[f:0] */
940#define rpf_vl_inner_tpid_default 0x8100 946#define HW_ATL_RPF_VL_INNER_TPID_DEFAULT 0x8100
941 947
942/* rx vl_outer_tpid[f:0] bitfield definitions 948/* rx vl_outer_tpid[f:0] bitfield definitions
943 * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]". 949 * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]".
@@ -945,17 +951,17 @@
945 */ 951 */
946 952
947/* register address for bitfield vl_outer_tpid[f:0] */ 953/* register address for bitfield vl_outer_tpid[f:0] */
948#define rpf_vl_outer_tpid_adr 0x00005284 954#define HW_ATL_RPF_VL_OUTER_TPID_ADR 0x00005284
949/* bitmask for bitfield vl_outer_tpid[f:0] */ 955/* bitmask for bitfield vl_outer_tpid[f:0] */
950#define rpf_vl_outer_tpid_msk 0xffff0000 956#define HW_ATL_RPF_VL_OUTER_TPID_MSK 0xffff0000
951/* inverted bitmask for bitfield vl_outer_tpid[f:0] */ 957/* inverted bitmask for bitfield vl_outer_tpid[f:0] */
952#define rpf_vl_outer_tpid_mskn 0x0000ffff 958#define HW_ATL_RPF_VL_OUTER_TPID_MSKN 0x0000ffff
953/* lower bit position of bitfield vl_outer_tpid[f:0] */ 959/* lower bit position of bitfield vl_outer_tpid[f:0] */
954#define rpf_vl_outer_tpid_shift 16 960#define HW_ATL_RPF_VL_OUTER_TPID_SHIFT 16
955/* width of bitfield vl_outer_tpid[f:0] */ 961/* width of bitfield vl_outer_tpid[f:0] */
956#define rpf_vl_outer_tpid_width 16 962#define HW_ATL_RPF_VL_OUTER_TPID_WIDTH 16
957/* default value of bitfield vl_outer_tpid[f:0] */ 963/* default value of bitfield vl_outer_tpid[f:0] */
958#define rpf_vl_outer_tpid_default 0x88a8 964#define HW_ATL_RPF_VL_OUTER_TPID_DEFAULT 0x88a8
959 965
960/* rx vl_promis_mode bitfield definitions 966/* rx vl_promis_mode bitfield definitions
961 * preprocessor definitions for the bitfield "vl_promis_mode". 967 * preprocessor definitions for the bitfield "vl_promis_mode".
@@ -963,17 +969,17 @@
963 */ 969 */
964 970
965/* register address for bitfield vl_promis_mode */ 971/* register address for bitfield vl_promis_mode */
966#define rpf_vl_promis_mode_adr 0x00005280 972#define HW_ATL_RPF_VL_PROMIS_MODE_ADR 0x00005280
967/* bitmask for bitfield vl_promis_mode */ 973/* bitmask for bitfield vl_promis_mode */
968#define rpf_vl_promis_mode_msk 0x00000002 974#define HW_ATL_RPF_VL_PROMIS_MODE_MSK 0x00000002
969/* inverted bitmask for bitfield vl_promis_mode */ 975/* inverted bitmask for bitfield vl_promis_mode */
970#define rpf_vl_promis_mode_mskn 0xfffffffd 976#define HW_ATL_RPF_VL_PROMIS_MODE_MSKN 0xfffffffd
971/* lower bit position of bitfield vl_promis_mode */ 977/* lower bit position of bitfield vl_promis_mode */
972#define rpf_vl_promis_mode_shift 1 978#define HW_ATL_RPF_VL_PROMIS_MODE_SHIFT 1
973/* width of bitfield vl_promis_mode */ 979/* width of bitfield vl_promis_mode */
974#define rpf_vl_promis_mode_width 1 980#define HW_ATL_RPF_VL_PROMIS_MODE_WIDTH 1
975/* default value of bitfield vl_promis_mode */ 981/* default value of bitfield vl_promis_mode */
976#define rpf_vl_promis_mode_default 0x0 982#define HW_ATL_RPF_VL_PROMIS_MODE_DEFAULT 0x0
977 983
978/* RX vl_accept_untagged_mode Bitfield Definitions 984/* RX vl_accept_untagged_mode Bitfield Definitions
979 * Preprocessor definitions for the bitfield "vl_accept_untagged_mode". 985 * Preprocessor definitions for the bitfield "vl_accept_untagged_mode".
@@ -981,17 +987,17 @@
981 */ 987 */
982 988
983/* Register address for bitfield vl_accept_untagged_mode */ 989/* Register address for bitfield vl_accept_untagged_mode */
984#define rpf_vl_accept_untagged_mode_adr 0x00005280 990#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR 0x00005280
985/* Bitmask for bitfield vl_accept_untagged_mode */ 991/* Bitmask for bitfield vl_accept_untagged_mode */
986#define rpf_vl_accept_untagged_mode_msk 0x00000004 992#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK 0x00000004
987/* Inverted bitmask for bitfield vl_accept_untagged_mode */ 993/* Inverted bitmask for bitfield vl_accept_untagged_mode */
988#define rpf_vl_accept_untagged_mode_mskn 0xFFFFFFFB 994#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSKN 0xFFFFFFFB
989/* Lower bit position of bitfield vl_accept_untagged_mode */ 995/* Lower bit position of bitfield vl_accept_untagged_mode */
990#define rpf_vl_accept_untagged_mode_shift 2 996#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT 2
991/* Width of bitfield vl_accept_untagged_mode */ 997/* Width of bitfield vl_accept_untagged_mode */
992#define rpf_vl_accept_untagged_mode_width 1 998#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_WIDTH 1
993/* Default value of bitfield vl_accept_untagged_mode */ 999/* Default value of bitfield vl_accept_untagged_mode */
994#define rpf_vl_accept_untagged_mode_default 0x0 1000#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_DEFAULT 0x0
995 1001
996/* rX vl_untagged_act[2:0] Bitfield Definitions 1002/* rX vl_untagged_act[2:0] Bitfield Definitions
997 * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]". 1003 * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]".
@@ -999,17 +1005,17 @@
999 */ 1005 */
1000 1006
1001/* Register address for bitfield vl_untagged_act[2:0] */ 1007/* Register address for bitfield vl_untagged_act[2:0] */
1002#define rpf_vl_untagged_act_adr 0x00005280 1008#define HW_ATL_RPF_VL_UNTAGGED_ACT_ADR 0x00005280
1003/* Bitmask for bitfield vl_untagged_act[2:0] */ 1009/* Bitmask for bitfield vl_untagged_act[2:0] */
1004#define rpf_vl_untagged_act_msk 0x00000038 1010#define HW_ATL_RPF_VL_UNTAGGED_ACT_MSK 0x00000038
1005/* Inverted bitmask for bitfield vl_untagged_act[2:0] */ 1011/* Inverted bitmask for bitfield vl_untagged_act[2:0] */
1006#define rpf_vl_untagged_act_mskn 0xFFFFFFC7 1012#define HW_ATL_RPF_VL_UNTAGGED_ACT_MSKN 0xFFFFFFC7
1007/* Lower bit position of bitfield vl_untagged_act[2:0] */ 1013/* Lower bit position of bitfield vl_untagged_act[2:0] */
1008#define rpf_vl_untagged_act_shift 3 1014#define HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT 3
1009/* Width of bitfield vl_untagged_act[2:0] */ 1015/* Width of bitfield vl_untagged_act[2:0] */
1010#define rpf_vl_untagged_act_width 3 1016#define HW_ATL_RPF_VL_UNTAGGED_ACT_WIDTH 3
1011/* Default value of bitfield vl_untagged_act[2:0] */ 1017/* Default value of bitfield vl_untagged_act[2:0] */
1012#define rpf_vl_untagged_act_default 0x0 1018#define HW_ATL_RPF_VL_UNTAGGED_ACT_DEFAULT 0x0
1013 1019
1014/* RX vl_en{F} Bitfield Definitions 1020/* RX vl_en{F} Bitfield Definitions
1015 * Preprocessor definitions for the bitfield "vl_en{F}". 1021 * Preprocessor definitions for the bitfield "vl_en{F}".
@@ -1018,17 +1024,17 @@
1018 */ 1024 */
1019 1025
1020/* Register address for bitfield vl_en{F} */ 1026/* Register address for bitfield vl_en{F} */
1021#define rpf_vl_en_f_adr(filter) (0x00005290 + (filter) * 0x4) 1027#define HW_ATL_RPF_VL_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4)
1022/* Bitmask for bitfield vl_en{F} */ 1028/* Bitmask for bitfield vl_en{F} */
1023#define rpf_vl_en_f_msk 0x80000000 1029#define HW_ATL_RPF_VL_EN_F_MSK 0x80000000
1024/* Inverted bitmask for bitfield vl_en{F} */ 1030/* Inverted bitmask for bitfield vl_en{F} */
1025#define rpf_vl_en_f_mskn 0x7FFFFFFF 1031#define HW_ATL_RPF_VL_EN_F_MSKN 0x7FFFFFFF
1026/* Lower bit position of bitfield vl_en{F} */ 1032/* Lower bit position of bitfield vl_en{F} */
1027#define rpf_vl_en_f_shift 31 1033#define HW_ATL_RPF_VL_EN_F_SHIFT 31
1028/* Width of bitfield vl_en{F} */ 1034/* Width of bitfield vl_en{F} */
1029#define rpf_vl_en_f_width 1 1035#define HW_ATL_RPF_VL_EN_F_WIDTH 1
1030/* Default value of bitfield vl_en{F} */ 1036/* Default value of bitfield vl_en{F} */
1031#define rpf_vl_en_f_default 0x0 1037#define HW_ATL_RPF_VL_EN_F_DEFAULT 0x0
1032 1038
1033/* RX vl_act{F}[2:0] Bitfield Definitions 1039/* RX vl_act{F}[2:0] Bitfield Definitions
1034 * Preprocessor definitions for the bitfield "vl_act{F}[2:0]". 1040 * Preprocessor definitions for the bitfield "vl_act{F}[2:0]".
@@ -1037,17 +1043,17 @@
1037 */ 1043 */
1038 1044
1039/* Register address for bitfield vl_act{F}[2:0] */ 1045/* Register address for bitfield vl_act{F}[2:0] */
1040#define rpf_vl_act_f_adr(filter) (0x00005290 + (filter) * 0x4) 1046#define HW_ATL_RPF_VL_ACT_F_ADR(filter) (0x00005290 + (filter) * 0x4)
1041/* Bitmask for bitfield vl_act{F}[2:0] */ 1047/* Bitmask for bitfield vl_act{F}[2:0] */
1042#define rpf_vl_act_f_msk 0x00070000 1048#define HW_ATL_RPF_VL_ACT_F_MSK 0x00070000
1043/* Inverted bitmask for bitfield vl_act{F}[2:0] */ 1049/* Inverted bitmask for bitfield vl_act{F}[2:0] */
1044#define rpf_vl_act_f_mskn 0xFFF8FFFF 1050#define HW_ATL_RPF_VL_ACT_F_MSKN 0xFFF8FFFF
1045/* Lower bit position of bitfield vl_act{F}[2:0] */ 1051/* Lower bit position of bitfield vl_act{F}[2:0] */
1046#define rpf_vl_act_f_shift 16 1052#define HW_ATL_RPF_VL_ACT_F_SHIFT 16
1047/* Width of bitfield vl_act{F}[2:0] */ 1053/* Width of bitfield vl_act{F}[2:0] */
1048#define rpf_vl_act_f_width 3 1054#define HW_ATL_RPF_VL_ACT_F_WIDTH 3
1049/* Default value of bitfield vl_act{F}[2:0] */ 1055/* Default value of bitfield vl_act{F}[2:0] */
1050#define rpf_vl_act_f_default 0x0 1056#define HW_ATL_RPF_VL_ACT_F_DEFAULT 0x0
1051 1057
1052/* RX vl_id{F}[B:0] Bitfield Definitions 1058/* RX vl_id{F}[B:0] Bitfield Definitions
1053 * Preprocessor definitions for the bitfield "vl_id{F}[B:0]". 1059 * Preprocessor definitions for the bitfield "vl_id{F}[B:0]".
@@ -1056,17 +1062,17 @@
1056 */ 1062 */
1057 1063
1058/* Register address for bitfield vl_id{F}[B:0] */ 1064/* Register address for bitfield vl_id{F}[B:0] */
1059#define rpf_vl_id_f_adr(filter) (0x00005290 + (filter) * 0x4) 1065#define HW_ATL_RPF_VL_ID_F_ADR(filter) (0x00005290 + (filter) * 0x4)
1060/* Bitmask for bitfield vl_id{F}[B:0] */ 1066/* Bitmask for bitfield vl_id{F}[B:0] */
1061#define rpf_vl_id_f_msk 0x00000FFF 1067#define HW_ATL_RPF_VL_ID_F_MSK 0x00000FFF
1062/* Inverted bitmask for bitfield vl_id{F}[B:0] */ 1068/* Inverted bitmask for bitfield vl_id{F}[B:0] */
1063#define rpf_vl_id_f_mskn 0xFFFFF000 1069#define HW_ATL_RPF_VL_ID_F_MSKN 0xFFFFF000
1064/* Lower bit position of bitfield vl_id{F}[B:0] */ 1070/* Lower bit position of bitfield vl_id{F}[B:0] */
1065#define rpf_vl_id_f_shift 0 1071#define HW_ATL_RPF_VL_ID_F_SHIFT 0
1066/* Width of bitfield vl_id{F}[B:0] */ 1072/* Width of bitfield vl_id{F}[B:0] */
1067#define rpf_vl_id_f_width 12 1073#define HW_ATL_RPF_VL_ID_F_WIDTH 12
1068/* Default value of bitfield vl_id{F}[B:0] */ 1074/* Default value of bitfield vl_id{F}[B:0] */
1069#define rpf_vl_id_f_default 0x0 1075#define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0
1070 1076
1071/* RX et_en{F} Bitfield Definitions 1077/* RX et_en{F} Bitfield Definitions
1072 * Preprocessor definitions for the bitfield "et_en{F}". 1078 * Preprocessor definitions for the bitfield "et_en{F}".
@@ -1075,17 +1081,17 @@
1075 */ 1081 */
1076 1082
1077/* Register address for bitfield et_en{F} */ 1083/* Register address for bitfield et_en{F} */
1078#define rpf_et_en_f_adr(filter) (0x00005300 + (filter) * 0x4) 1084#define HW_ATL_RPF_ET_EN_F_ADR(filter) (0x00005300 + (filter) * 0x4)
1079/* Bitmask for bitfield et_en{F} */ 1085/* Bitmask for bitfield et_en{F} */
1080#define rpf_et_en_f_msk 0x80000000 1086#define HW_ATL_RPF_ET_EN_F_MSK 0x80000000
1081/* Inverted bitmask for bitfield et_en{F} */ 1087/* Inverted bitmask for bitfield et_en{F} */
1082#define rpf_et_en_f_mskn 0x7FFFFFFF 1088#define HW_ATL_RPF_ET_EN_F_MSKN 0x7FFFFFFF
1083/* Lower bit position of bitfield et_en{F} */ 1089/* Lower bit position of bitfield et_en{F} */
1084#define rpf_et_en_f_shift 31 1090#define HW_ATL_RPF_ET_EN_F_SHIFT 31
1085/* Width of bitfield et_en{F} */ 1091/* Width of bitfield et_en{F} */
1086#define rpf_et_en_f_width 1 1092#define HW_ATL_RPF_ET_EN_F_WIDTH 1
1087/* Default value of bitfield et_en{F} */ 1093/* Default value of bitfield et_en{F} */
1088#define rpf_et_en_f_default 0x0 1094#define HW_ATL_RPF_ET_EN_F_DEFAULT 0x0
1089 1095
1090/* rx et_en{f} bitfield definitions 1096/* rx et_en{f} bitfield definitions
1091 * preprocessor definitions for the bitfield "et_en{f}". 1097 * preprocessor definitions for the bitfield "et_en{f}".
@@ -1094,17 +1100,17 @@
1094 */ 1100 */
1095 1101
1096/* register address for bitfield et_en{f} */ 1102/* register address for bitfield et_en{f} */
1097#define rpf_et_enf_adr(filter) (0x00005300 + (filter) * 0x4) 1103#define HW_ATL_RPF_ET_ENF_ADR(filter) (0x00005300 + (filter) * 0x4)
1098/* bitmask for bitfield et_en{f} */ 1104/* bitmask for bitfield et_en{f} */
1099#define rpf_et_enf_msk 0x80000000 1105#define HW_ATL_RPF_ET_ENF_MSK 0x80000000
1100/* inverted bitmask for bitfield et_en{f} */ 1106/* inverted bitmask for bitfield et_en{f} */
1101#define rpf_et_enf_mskn 0x7fffffff 1107#define HW_ATL_RPF_ET_ENF_MSKN 0x7fffffff
1102/* lower bit position of bitfield et_en{f} */ 1108/* lower bit position of bitfield et_en{f} */
1103#define rpf_et_enf_shift 31 1109#define HW_ATL_RPF_ET_ENF_SHIFT 31
1104/* width of bitfield et_en{f} */ 1110/* width of bitfield et_en{f} */
1105#define rpf_et_enf_width 1 1111#define HW_ATL_RPF_ET_ENF_WIDTH 1
1106/* default value of bitfield et_en{f} */ 1112/* default value of bitfield et_en{f} */
1107#define rpf_et_enf_default 0x0 1113#define HW_ATL_RPF_ET_ENF_DEFAULT 0x0
1108 1114
1109/* rx et_up{f}_en bitfield definitions 1115/* rx et_up{f}_en bitfield definitions
1110 * preprocessor definitions for the bitfield "et_up{f}_en". 1116 * preprocessor definitions for the bitfield "et_up{f}_en".
@@ -1113,17 +1119,17 @@
1113 */ 1119 */
1114 1120
1115/* register address for bitfield et_up{f}_en */ 1121/* register address for bitfield et_up{f}_en */
1116#define rpf_et_upfen_adr(filter) (0x00005300 + (filter) * 0x4) 1122#define HW_ATL_RPF_ET_UPFEN_ADR(filter) (0x00005300 + (filter) * 0x4)
1117/* bitmask for bitfield et_up{f}_en */ 1123/* bitmask for bitfield et_up{f}_en */
1118#define rpf_et_upfen_msk 0x40000000 1124#define HW_ATL_RPF_ET_UPFEN_MSK 0x40000000
1119/* inverted bitmask for bitfield et_up{f}_en */ 1125/* inverted bitmask for bitfield et_up{f}_en */
1120#define rpf_et_upfen_mskn 0xbfffffff 1126#define HW_ATL_RPF_ET_UPFEN_MSKN 0xbfffffff
1121/* lower bit position of bitfield et_up{f}_en */ 1127/* lower bit position of bitfield et_up{f}_en */
1122#define rpf_et_upfen_shift 30 1128#define HW_ATL_RPF_ET_UPFEN_SHIFT 30
1123/* width of bitfield et_up{f}_en */ 1129/* width of bitfield et_up{f}_en */
1124#define rpf_et_upfen_width 1 1130#define HW_ATL_RPF_ET_UPFEN_WIDTH 1
1125/* default value of bitfield et_up{f}_en */ 1131/* default value of bitfield et_up{f}_en */
1126#define rpf_et_upfen_default 0x0 1132#define HW_ATL_RPF_ET_UPFEN_DEFAULT 0x0
1127 1133
1128/* rx et_rxq{f}_en bitfield definitions 1134/* rx et_rxq{f}_en bitfield definitions
1129 * preprocessor definitions for the bitfield "et_rxq{f}_en". 1135 * preprocessor definitions for the bitfield "et_rxq{f}_en".
@@ -1132,17 +1138,17 @@
1132 */ 1138 */
1133 1139
1134/* register address for bitfield et_rxq{f}_en */ 1140/* register address for bitfield et_rxq{f}_en */
1135#define rpf_et_rxqfen_adr(filter) (0x00005300 + (filter) * 0x4) 1141#define HW_ATL_RPF_ET_RXQFEN_ADR(filter) (0x00005300 + (filter) * 0x4)
1136/* bitmask for bitfield et_rxq{f}_en */ 1142/* bitmask for bitfield et_rxq{f}_en */
1137#define rpf_et_rxqfen_msk 0x20000000 1143#define HW_ATL_RPF_ET_RXQFEN_MSK 0x20000000
1138/* inverted bitmask for bitfield et_rxq{f}_en */ 1144/* inverted bitmask for bitfield et_rxq{f}_en */
1139#define rpf_et_rxqfen_mskn 0xdfffffff 1145#define HW_ATL_RPF_ET_RXQFEN_MSKN 0xdfffffff
1140/* lower bit position of bitfield et_rxq{f}_en */ 1146/* lower bit position of bitfield et_rxq{f}_en */
1141#define rpf_et_rxqfen_shift 29 1147#define HW_ATL_RPF_ET_RXQFEN_SHIFT 29
1142/* width of bitfield et_rxq{f}_en */ 1148/* width of bitfield et_rxq{f}_en */
1143#define rpf_et_rxqfen_width 1 1149#define HW_ATL_RPF_ET_RXQFEN_WIDTH 1
1144/* default value of bitfield et_rxq{f}_en */ 1150/* default value of bitfield et_rxq{f}_en */
1145#define rpf_et_rxqfen_default 0x0 1151#define HW_ATL_RPF_ET_RXQFEN_DEFAULT 0x0
1146 1152
1147/* rx et_up{f}[2:0] bitfield definitions 1153/* rx et_up{f}[2:0] bitfield definitions
1148 * preprocessor definitions for the bitfield "et_up{f}[2:0]". 1154 * preprocessor definitions for the bitfield "et_up{f}[2:0]".
@@ -1151,17 +1157,17 @@
1151 */ 1157 */
1152 1158
1153/* register address for bitfield et_up{f}[2:0] */ 1159/* register address for bitfield et_up{f}[2:0] */
1154#define rpf_et_upf_adr(filter) (0x00005300 + (filter) * 0x4) 1160#define HW_ATL_RPF_ET_UPF_ADR(filter) (0x00005300 + (filter) * 0x4)
1155/* bitmask for bitfield et_up{f}[2:0] */ 1161/* bitmask for bitfield et_up{f}[2:0] */
1156#define rpf_et_upf_msk 0x1c000000 1162#define HW_ATL_RPF_ET_UPF_MSK 0x1c000000
1157/* inverted bitmask for bitfield et_up{f}[2:0] */ 1163/* inverted bitmask for bitfield et_up{f}[2:0] */
1158#define rpf_et_upf_mskn 0xe3ffffff 1164#define HW_ATL_RPF_ET_UPF_MSKN 0xe3ffffff
1159/* lower bit position of bitfield et_up{f}[2:0] */ 1165/* lower bit position of bitfield et_up{f}[2:0] */
1160#define rpf_et_upf_shift 26 1166#define HW_ATL_RPF_ET_UPF_SHIFT 26
1161/* width of bitfield et_up{f}[2:0] */ 1167/* width of bitfield et_up{f}[2:0] */
1162#define rpf_et_upf_width 3 1168#define HW_ATL_RPF_ET_UPF_WIDTH 3
1163/* default value of bitfield et_up{f}[2:0] */ 1169/* default value of bitfield et_up{f}[2:0] */
1164#define rpf_et_upf_default 0x0 1170#define HW_ATL_RPF_ET_UPF_DEFAULT 0x0
1165 1171
1166/* rx et_rxq{f}[4:0] bitfield definitions 1172/* rx et_rxq{f}[4:0] bitfield definitions
1167 * preprocessor definitions for the bitfield "et_rxq{f}[4:0]". 1173 * preprocessor definitions for the bitfield "et_rxq{f}[4:0]".
@@ -1170,17 +1176,17 @@
1170 */ 1176 */
1171 1177
1172/* register address for bitfield et_rxq{f}[4:0] */ 1178/* register address for bitfield et_rxq{f}[4:0] */
1173#define rpf_et_rxqf_adr(filter) (0x00005300 + (filter) * 0x4) 1179#define HW_ATL_RPF_ET_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4)
1174/* bitmask for bitfield et_rxq{f}[4:0] */ 1180/* bitmask for bitfield et_rxq{f}[4:0] */
1175#define rpf_et_rxqf_msk 0x01f00000 1181#define HW_ATL_RPF_ET_RXQF_MSK 0x01f00000
1176/* inverted bitmask for bitfield et_rxq{f}[4:0] */ 1182/* inverted bitmask for bitfield et_rxq{f}[4:0] */
1177#define rpf_et_rxqf_mskn 0xfe0fffff 1183#define HW_ATL_RPF_ET_RXQF_MSKN 0xfe0fffff
1178/* lower bit position of bitfield et_rxq{f}[4:0] */ 1184/* lower bit position of bitfield et_rxq{f}[4:0] */
1179#define rpf_et_rxqf_shift 20 1185#define HW_ATL_RPF_ET_RXQF_SHIFT 20
1180/* width of bitfield et_rxq{f}[4:0] */ 1186/* width of bitfield et_rxq{f}[4:0] */
1181#define rpf_et_rxqf_width 5 1187#define HW_ATL_RPF_ET_RXQF_WIDTH 5
1182/* default value of bitfield et_rxq{f}[4:0] */ 1188/* default value of bitfield et_rxq{f}[4:0] */
1183#define rpf_et_rxqf_default 0x0 1189#define HW_ATL_RPF_ET_RXQF_DEFAULT 0x0
1184 1190
1185/* rx et_mng_rxq{f} bitfield definitions 1191/* rx et_mng_rxq{f} bitfield definitions
1186 * preprocessor definitions for the bitfield "et_mng_rxq{f}". 1192 * preprocessor definitions for the bitfield "et_mng_rxq{f}".
@@ -1189,17 +1195,17 @@
1189 */ 1195 */
1190 1196
1191/* register address for bitfield et_mng_rxq{f} */ 1197/* register address for bitfield et_mng_rxq{f} */
1192#define rpf_et_mng_rxqf_adr(filter) (0x00005300 + (filter) * 0x4) 1198#define HW_ATL_RPF_ET_MNG_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4)
1193/* bitmask for bitfield et_mng_rxq{f} */ 1199/* bitmask for bitfield et_mng_rxq{f} */
1194#define rpf_et_mng_rxqf_msk 0x00080000 1200#define HW_ATL_RPF_ET_MNG_RXQF_MSK 0x00080000
1195/* inverted bitmask for bitfield et_mng_rxq{f} */ 1201/* inverted bitmask for bitfield et_mng_rxq{f} */
1196#define rpf_et_mng_rxqf_mskn 0xfff7ffff 1202#define HW_ATL_RPF_ET_MNG_RXQF_MSKN 0xfff7ffff
1197/* lower bit position of bitfield et_mng_rxq{f} */ 1203/* lower bit position of bitfield et_mng_rxq{f} */
1198#define rpf_et_mng_rxqf_shift 19 1204#define HW_ATL_RPF_ET_MNG_RXQF_SHIFT 19
1199/* width of bitfield et_mng_rxq{f} */ 1205/* width of bitfield et_mng_rxq{f} */
1200#define rpf_et_mng_rxqf_width 1 1206#define HW_ATL_RPF_ET_MNG_RXQF_WIDTH 1
1201/* default value of bitfield et_mng_rxq{f} */ 1207/* default value of bitfield et_mng_rxq{f} */
1202#define rpf_et_mng_rxqf_default 0x0 1208#define HW_ATL_RPF_ET_MNG_RXQF_DEFAULT 0x0
1203 1209
1204/* rx et_act{f}[2:0] bitfield definitions 1210/* rx et_act{f}[2:0] bitfield definitions
1205 * preprocessor definitions for the bitfield "et_act{f}[2:0]". 1211 * preprocessor definitions for the bitfield "et_act{f}[2:0]".
@@ -1208,17 +1214,17 @@
1208 */ 1214 */
1209 1215
1210/* register address for bitfield et_act{f}[2:0] */ 1216/* register address for bitfield et_act{f}[2:0] */
1211#define rpf_et_actf_adr(filter) (0x00005300 + (filter) * 0x4) 1217#define HW_ATL_RPF_ET_ACTF_ADR(filter) (0x00005300 + (filter) * 0x4)
1212/* bitmask for bitfield et_act{f}[2:0] */ 1218/* bitmask for bitfield et_act{f}[2:0] */
1213#define rpf_et_actf_msk 0x00070000 1219#define HW_ATL_RPF_ET_ACTF_MSK 0x00070000
1214/* inverted bitmask for bitfield et_act{f}[2:0] */ 1220/* inverted bitmask for bitfield et_act{f}[2:0] */
1215#define rpf_et_actf_mskn 0xfff8ffff 1221#define HW_ATL_RPF_ET_ACTF_MSKN 0xfff8ffff
1216/* lower bit position of bitfield et_act{f}[2:0] */ 1222/* lower bit position of bitfield et_act{f}[2:0] */
1217#define rpf_et_actf_shift 16 1223#define HW_ATL_RPF_ET_ACTF_SHIFT 16
1218/* width of bitfield et_act{f}[2:0] */ 1224/* width of bitfield et_act{f}[2:0] */
1219#define rpf_et_actf_width 3 1225#define HW_ATL_RPF_ET_ACTF_WIDTH 3
1220/* default value of bitfield et_act{f}[2:0] */ 1226/* default value of bitfield et_act{f}[2:0] */
1221#define rpf_et_actf_default 0x0 1227#define HW_ATL_RPF_ET_ACTF_DEFAULT 0x0
1222 1228
1223/* rx et_val{f}[f:0] bitfield definitions 1229/* rx et_val{f}[f:0] bitfield definitions
1224 * preprocessor definitions for the bitfield "et_val{f}[f:0]". 1230 * preprocessor definitions for the bitfield "et_val{f}[f:0]".
@@ -1227,17 +1233,17 @@
1227 */ 1233 */
1228 1234
1229/* register address for bitfield et_val{f}[f:0] */ 1235/* register address for bitfield et_val{f}[f:0] */
1230#define rpf_et_valf_adr(filter) (0x00005300 + (filter) * 0x4) 1236#define HW_ATL_RPF_ET_VALF_ADR(filter) (0x00005300 + (filter) * 0x4)
1231/* bitmask for bitfield et_val{f}[f:0] */ 1237/* bitmask for bitfield et_val{f}[f:0] */
1232#define rpf_et_valf_msk 0x0000ffff 1238#define HW_ATL_RPF_ET_VALF_MSK 0x0000ffff
1233/* inverted bitmask for bitfield et_val{f}[f:0] */ 1239/* inverted bitmask for bitfield et_val{f}[f:0] */
1234#define rpf_et_valf_mskn 0xffff0000 1240#define HW_ATL_RPF_ET_VALF_MSKN 0xffff0000
1235/* lower bit position of bitfield et_val{f}[f:0] */ 1241/* lower bit position of bitfield et_val{f}[f:0] */
1236#define rpf_et_valf_shift 0 1242#define HW_ATL_RPF_ET_VALF_SHIFT 0
1237/* width of bitfield et_val{f}[f:0] */ 1243/* width of bitfield et_val{f}[f:0] */
1238#define rpf_et_valf_width 16 1244#define HW_ATL_RPF_ET_VALF_WIDTH 16
1239/* default value of bitfield et_val{f}[f:0] */ 1245/* default value of bitfield et_val{f}[f:0] */
1240#define rpf_et_valf_default 0x0 1246#define HW_ATL_RPF_ET_VALF_DEFAULT 0x0
1241 1247
1242/* rx ipv4_chk_en bitfield definitions 1248/* rx ipv4_chk_en bitfield definitions
1243 * preprocessor definitions for the bitfield "ipv4_chk_en". 1249 * preprocessor definitions for the bitfield "ipv4_chk_en".
@@ -1245,17 +1251,17 @@
1245 */ 1251 */
1246 1252
1247/* register address for bitfield ipv4_chk_en */ 1253/* register address for bitfield ipv4_chk_en */
1248#define rpo_ipv4chk_en_adr 0x00005580 1254#define HW_ATL_RPO_IPV4CHK_EN_ADR 0x00005580
1249/* bitmask for bitfield ipv4_chk_en */ 1255/* bitmask for bitfield ipv4_chk_en */
1250#define rpo_ipv4chk_en_msk 0x00000002 1256#define HW_ATL_RPO_IPV4CHK_EN_MSK 0x00000002
1251/* inverted bitmask for bitfield ipv4_chk_en */ 1257/* inverted bitmask for bitfield ipv4_chk_en */
1252#define rpo_ipv4chk_en_mskn 0xfffffffd 1258#define HW_ATL_RPO_IPV4CHK_EN_MSKN 0xfffffffd
1253/* lower bit position of bitfield ipv4_chk_en */ 1259/* lower bit position of bitfield ipv4_chk_en */
1254#define rpo_ipv4chk_en_shift 1 1260#define HW_ATL_RPO_IPV4CHK_EN_SHIFT 1
1255/* width of bitfield ipv4_chk_en */ 1261/* width of bitfield ipv4_chk_en */
1256#define rpo_ipv4chk_en_width 1 1262#define HW_ATL_RPO_IPV4CHK_EN_WIDTH 1
1257/* default value of bitfield ipv4_chk_en */ 1263/* default value of bitfield ipv4_chk_en */
1258#define rpo_ipv4chk_en_default 0x0 1264#define HW_ATL_RPO_IPV4CHK_EN_DEFAULT 0x0
1259 1265
1260/* rx desc{d}_vl_strip bitfield definitions 1266/* rx desc{d}_vl_strip bitfield definitions
1261 * preprocessor definitions for the bitfield "desc{d}_vl_strip". 1267 * preprocessor definitions for the bitfield "desc{d}_vl_strip".
@@ -1264,17 +1270,18 @@
1264 */ 1270 */
1265 1271
1266/* register address for bitfield desc{d}_vl_strip */ 1272/* register address for bitfield desc{d}_vl_strip */
1267#define rpo_descdvl_strip_adr(descriptor) (0x00005b08 + (descriptor) * 0x20) 1273#define HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor) \
1274 (0x00005b08 + (descriptor) * 0x20)
1268/* bitmask for bitfield desc{d}_vl_strip */ 1275/* bitmask for bitfield desc{d}_vl_strip */
1269#define rpo_descdvl_strip_msk 0x20000000 1276#define HW_ATL_RPO_DESCDVL_STRIP_MSK 0x20000000
1270/* inverted bitmask for bitfield desc{d}_vl_strip */ 1277/* inverted bitmask for bitfield desc{d}_vl_strip */
1271#define rpo_descdvl_strip_mskn 0xdfffffff 1278#define HW_ATL_RPO_DESCDVL_STRIP_MSKN 0xdfffffff
1272/* lower bit position of bitfield desc{d}_vl_strip */ 1279/* lower bit position of bitfield desc{d}_vl_strip */
1273#define rpo_descdvl_strip_shift 29 1280#define HW_ATL_RPO_DESCDVL_STRIP_SHIFT 29
1274/* width of bitfield desc{d}_vl_strip */ 1281/* width of bitfield desc{d}_vl_strip */
1275#define rpo_descdvl_strip_width 1 1282#define HW_ATL_RPO_DESCDVL_STRIP_WIDTH 1
1276/* default value of bitfield desc{d}_vl_strip */ 1283/* default value of bitfield desc{d}_vl_strip */
1277#define rpo_descdvl_strip_default 0x0 1284#define HW_ATL_RPO_DESCDVL_STRIP_DEFAULT 0x0
1278 1285
1279/* rx l4_chk_en bitfield definitions 1286/* rx l4_chk_en bitfield definitions
1280 * preprocessor definitions for the bitfield "l4_chk_en". 1287 * preprocessor definitions for the bitfield "l4_chk_en".
@@ -1282,17 +1289,17 @@
1282 */ 1289 */
1283 1290
1284/* register address for bitfield l4_chk_en */ 1291/* register address for bitfield l4_chk_en */
1285#define rpol4chk_en_adr 0x00005580 1292#define HW_ATL_RPOL4CHK_EN_ADR 0x00005580
1286/* bitmask for bitfield l4_chk_en */ 1293/* bitmask for bitfield l4_chk_en */
1287#define rpol4chk_en_msk 0x00000001 1294#define HW_ATL_RPOL4CHK_EN_MSK 0x00000001
1288/* inverted bitmask for bitfield l4_chk_en */ 1295/* inverted bitmask for bitfield l4_chk_en */
1289#define rpol4chk_en_mskn 0xfffffffe 1296#define HW_ATL_RPOL4CHK_EN_MSKN 0xfffffffe
1290/* lower bit position of bitfield l4_chk_en */ 1297/* lower bit position of bitfield l4_chk_en */
1291#define rpol4chk_en_shift 0 1298#define HW_ATL_RPOL4CHK_EN_SHIFT 0
1292/* width of bitfield l4_chk_en */ 1299/* width of bitfield l4_chk_en */
1293#define rpol4chk_en_width 1 1300#define HW_ATL_RPOL4CHK_EN_WIDTH 1
1294/* default value of bitfield l4_chk_en */ 1301/* default value of bitfield l4_chk_en */
1295#define rpol4chk_en_default 0x0 1302#define HW_ATL_RPOL4CHK_EN_DEFAULT 0x0
1296 1303
1297/* rx reg_res_dsbl bitfield definitions 1304/* rx reg_res_dsbl bitfield definitions
1298 * preprocessor definitions for the bitfield "reg_res_dsbl". 1305 * preprocessor definitions for the bitfield "reg_res_dsbl".
@@ -1300,17 +1307,17 @@
1300 */ 1307 */
1301 1308
1302/* register address for bitfield reg_res_dsbl */ 1309/* register address for bitfield reg_res_dsbl */
1303#define rx_reg_res_dsbl_adr 0x00005000 1310#define HW_ATL_RX_REG_RES_DSBL_ADR 0x00005000
1304/* bitmask for bitfield reg_res_dsbl */ 1311/* bitmask for bitfield reg_res_dsbl */
1305#define rx_reg_res_dsbl_msk 0x20000000 1312#define HW_ATL_RX_REG_RES_DSBL_MSK 0x20000000
1306/* inverted bitmask for bitfield reg_res_dsbl */ 1313/* inverted bitmask for bitfield reg_res_dsbl */
1307#define rx_reg_res_dsbl_mskn 0xdfffffff 1314#define HW_ATL_RX_REG_RES_DSBL_MSKN 0xdfffffff
1308/* lower bit position of bitfield reg_res_dsbl */ 1315/* lower bit position of bitfield reg_res_dsbl */
1309#define rx_reg_res_dsbl_shift 29 1316#define HW_ATL_RX_REG_RES_DSBL_SHIFT 29
1310/* width of bitfield reg_res_dsbl */ 1317/* width of bitfield reg_res_dsbl */
1311#define rx_reg_res_dsbl_width 1 1318#define HW_ATL_RX_REG_RES_DSBL_WIDTH 1
1312/* default value of bitfield reg_res_dsbl */ 1319/* default value of bitfield reg_res_dsbl */
1313#define rx_reg_res_dsbl_default 0x1 1320#define HW_ATL_RX_REG_RES_DSBL_DEFAULT 0x1
1314 1321
1315/* tx dca{d}_cpuid[7:0] bitfield definitions 1322/* tx dca{d}_cpuid[7:0] bitfield definitions
1316 * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]". 1323 * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]".
@@ -1319,17 +1326,17 @@
1319 */ 1326 */
1320 1327
1321/* register address for bitfield dca{d}_cpuid[7:0] */ 1328/* register address for bitfield dca{d}_cpuid[7:0] */
1322#define tdm_dcadcpuid_adr(dca) (0x00008400 + (dca) * 0x4) 1329#define HW_ATL_TDM_DCADCPUID_ADR(dca) (0x00008400 + (dca) * 0x4)
1323/* bitmask for bitfield dca{d}_cpuid[7:0] */ 1330/* bitmask for bitfield dca{d}_cpuid[7:0] */
1324#define tdm_dcadcpuid_msk 0x000000ff 1331#define HW_ATL_TDM_DCADCPUID_MSK 0x000000ff
1325/* inverted bitmask for bitfield dca{d}_cpuid[7:0] */ 1332/* inverted bitmask for bitfield dca{d}_cpuid[7:0] */
1326#define tdm_dcadcpuid_mskn 0xffffff00 1333#define HW_ATL_TDM_DCADCPUID_MSKN 0xffffff00
1327/* lower bit position of bitfield dca{d}_cpuid[7:0] */ 1334/* lower bit position of bitfield dca{d}_cpuid[7:0] */
1328#define tdm_dcadcpuid_shift 0 1335#define HW_ATL_TDM_DCADCPUID_SHIFT 0
1329/* width of bitfield dca{d}_cpuid[7:0] */ 1336/* width of bitfield dca{d}_cpuid[7:0] */
1330#define tdm_dcadcpuid_width 8 1337#define HW_ATL_TDM_DCADCPUID_WIDTH 8
1331/* default value of bitfield dca{d}_cpuid[7:0] */ 1338/* default value of bitfield dca{d}_cpuid[7:0] */
1332#define tdm_dcadcpuid_default 0x0 1339#define HW_ATL_TDM_DCADCPUID_DEFAULT 0x0
1333 1340
1334/* tx lso_en[1f:0] bitfield definitions 1341/* tx lso_en[1f:0] bitfield definitions
1335 * preprocessor definitions for the bitfield "lso_en[1f:0]". 1342 * preprocessor definitions for the bitfield "lso_en[1f:0]".
@@ -1337,17 +1344,17 @@
1337 */ 1344 */
1338 1345
1339/* register address for bitfield lso_en[1f:0] */ 1346/* register address for bitfield lso_en[1f:0] */
1340#define tdm_lso_en_adr 0x00007810 1347#define HW_ATL_TDM_LSO_EN_ADR 0x00007810
1341/* bitmask for bitfield lso_en[1f:0] */ 1348/* bitmask for bitfield lso_en[1f:0] */
1342#define tdm_lso_en_msk 0xffffffff 1349#define HW_ATL_TDM_LSO_EN_MSK 0xffffffff
1343/* inverted bitmask for bitfield lso_en[1f:0] */ 1350/* inverted bitmask for bitfield lso_en[1f:0] */
1344#define tdm_lso_en_mskn 0x00000000 1351#define HW_ATL_TDM_LSO_EN_MSKN 0x00000000
1345/* lower bit position of bitfield lso_en[1f:0] */ 1352/* lower bit position of bitfield lso_en[1f:0] */
1346#define tdm_lso_en_shift 0 1353#define HW_ATL_TDM_LSO_EN_SHIFT 0
1347/* width of bitfield lso_en[1f:0] */ 1354/* width of bitfield lso_en[1f:0] */
1348#define tdm_lso_en_width 32 1355#define HW_ATL_TDM_LSO_EN_WIDTH 32
1349/* default value of bitfield lso_en[1f:0] */ 1356/* default value of bitfield lso_en[1f:0] */
1350#define tdm_lso_en_default 0x0 1357#define HW_ATL_TDM_LSO_EN_DEFAULT 0x0
1351 1358
1352/* tx dca_en bitfield definitions 1359/* tx dca_en bitfield definitions
1353 * preprocessor definitions for the bitfield "dca_en". 1360 * preprocessor definitions for the bitfield "dca_en".
@@ -1355,17 +1362,17 @@
1355 */ 1362 */
1356 1363
1357/* register address for bitfield dca_en */ 1364/* register address for bitfield dca_en */
1358#define tdm_dca_en_adr 0x00008480 1365#define HW_ATL_TDM_DCA_EN_ADR 0x00008480
1359/* bitmask for bitfield dca_en */ 1366/* bitmask for bitfield dca_en */
1360#define tdm_dca_en_msk 0x80000000 1367#define HW_ATL_TDM_DCA_EN_MSK 0x80000000
1361/* inverted bitmask for bitfield dca_en */ 1368/* inverted bitmask for bitfield dca_en */
1362#define tdm_dca_en_mskn 0x7fffffff 1369#define HW_ATL_TDM_DCA_EN_MSKN 0x7fffffff
1363/* lower bit position of bitfield dca_en */ 1370/* lower bit position of bitfield dca_en */
1364#define tdm_dca_en_shift 31 1371#define HW_ATL_TDM_DCA_EN_SHIFT 31
1365/* width of bitfield dca_en */ 1372/* width of bitfield dca_en */
1366#define tdm_dca_en_width 1 1373#define HW_ATL_TDM_DCA_EN_WIDTH 1
1367/* default value of bitfield dca_en */ 1374/* default value of bitfield dca_en */
1368#define tdm_dca_en_default 0x1 1375#define HW_ATL_TDM_DCA_EN_DEFAULT 0x1
1369 1376
1370/* tx dca_mode[3:0] bitfield definitions 1377/* tx dca_mode[3:0] bitfield definitions
1371 * preprocessor definitions for the bitfield "dca_mode[3:0]". 1378 * preprocessor definitions for the bitfield "dca_mode[3:0]".
@@ -1373,17 +1380,17 @@
1373 */ 1380 */
1374 1381
1375/* register address for bitfield dca_mode[3:0] */ 1382/* register address for bitfield dca_mode[3:0] */
1376#define tdm_dca_mode_adr 0x00008480 1383#define HW_ATL_TDM_DCA_MODE_ADR 0x00008480
1377/* bitmask for bitfield dca_mode[3:0] */ 1384/* bitmask for bitfield dca_mode[3:0] */
1378#define tdm_dca_mode_msk 0x0000000f 1385#define HW_ATL_TDM_DCA_MODE_MSK 0x0000000f
1379/* inverted bitmask for bitfield dca_mode[3:0] */ 1386/* inverted bitmask for bitfield dca_mode[3:0] */
1380#define tdm_dca_mode_mskn 0xfffffff0 1387#define HW_ATL_TDM_DCA_MODE_MSKN 0xfffffff0
1381/* lower bit position of bitfield dca_mode[3:0] */ 1388/* lower bit position of bitfield dca_mode[3:0] */
1382#define tdm_dca_mode_shift 0 1389#define HW_ATL_TDM_DCA_MODE_SHIFT 0
1383/* width of bitfield dca_mode[3:0] */ 1390/* width of bitfield dca_mode[3:0] */
1384#define tdm_dca_mode_width 4 1391#define HW_ATL_TDM_DCA_MODE_WIDTH 4
1385/* default value of bitfield dca_mode[3:0] */ 1392/* default value of bitfield dca_mode[3:0] */
1386#define tdm_dca_mode_default 0x0 1393#define HW_ATL_TDM_DCA_MODE_DEFAULT 0x0
1387 1394
1388/* tx dca{d}_desc_en bitfield definitions 1395/* tx dca{d}_desc_en bitfield definitions
1389 * preprocessor definitions for the bitfield "dca{d}_desc_en". 1396 * preprocessor definitions for the bitfield "dca{d}_desc_en".
@@ -1392,17 +1399,17 @@
1392 */ 1399 */
1393 1400
1394/* register address for bitfield dca{d}_desc_en */ 1401/* register address for bitfield dca{d}_desc_en */
1395#define tdm_dcaddesc_en_adr(dca) (0x00008400 + (dca) * 0x4) 1402#define HW_ATL_TDM_DCADDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4)
1396/* bitmask for bitfield dca{d}_desc_en */ 1403/* bitmask for bitfield dca{d}_desc_en */
1397#define tdm_dcaddesc_en_msk 0x80000000 1404#define HW_ATL_TDM_DCADDESC_EN_MSK 0x80000000
1398/* inverted bitmask for bitfield dca{d}_desc_en */ 1405/* inverted bitmask for bitfield dca{d}_desc_en */
1399#define tdm_dcaddesc_en_mskn 0x7fffffff 1406#define HW_ATL_TDM_DCADDESC_EN_MSKN 0x7fffffff
1400/* lower bit position of bitfield dca{d}_desc_en */ 1407/* lower bit position of bitfield dca{d}_desc_en */
1401#define tdm_dcaddesc_en_shift 31 1408#define HW_ATL_TDM_DCADDESC_EN_SHIFT 31
1402/* width of bitfield dca{d}_desc_en */ 1409/* width of bitfield dca{d}_desc_en */
1403#define tdm_dcaddesc_en_width 1 1410#define HW_ATL_TDM_DCADDESC_EN_WIDTH 1
1404/* default value of bitfield dca{d}_desc_en */ 1411/* default value of bitfield dca{d}_desc_en */
1405#define tdm_dcaddesc_en_default 0x0 1412#define HW_ATL_TDM_DCADDESC_EN_DEFAULT 0x0
1406 1413
1407/* tx desc{d}_en bitfield definitions 1414/* tx desc{d}_en bitfield definitions
1408 * preprocessor definitions for the bitfield "desc{d}_en". 1415 * preprocessor definitions for the bitfield "desc{d}_en".
@@ -1411,17 +1418,17 @@
1411 */ 1418 */
1412 1419
1413/* register address for bitfield desc{d}_en */ 1420/* register address for bitfield desc{d}_en */
1414#define tdm_descden_adr(descriptor) (0x00007c08 + (descriptor) * 0x40) 1421#define HW_ATL_TDM_DESCDEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40)
1415/* bitmask for bitfield desc{d}_en */ 1422/* bitmask for bitfield desc{d}_en */
1416#define tdm_descden_msk 0x80000000 1423#define HW_ATL_TDM_DESCDEN_MSK 0x80000000
1417/* inverted bitmask for bitfield desc{d}_en */ 1424/* inverted bitmask for bitfield desc{d}_en */
1418#define tdm_descden_mskn 0x7fffffff 1425#define HW_ATL_TDM_DESCDEN_MSKN 0x7fffffff
1419/* lower bit position of bitfield desc{d}_en */ 1426/* lower bit position of bitfield desc{d}_en */
1420#define tdm_descden_shift 31 1427#define HW_ATL_TDM_DESCDEN_SHIFT 31
1421/* width of bitfield desc{d}_en */ 1428/* width of bitfield desc{d}_en */
1422#define tdm_descden_width 1 1429#define HW_ATL_TDM_DESCDEN_WIDTH 1
1423/* default value of bitfield desc{d}_en */ 1430/* default value of bitfield desc{d}_en */
1424#define tdm_descden_default 0x0 1431#define HW_ATL_TDM_DESCDEN_DEFAULT 0x0
1425 1432
1426/* tx desc{d}_hd[c:0] bitfield definitions 1433/* tx desc{d}_hd[c:0] bitfield definitions
1427 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 1434 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]".
@@ -1430,15 +1437,15 @@
1430 */ 1437 */
1431 1438
1432/* register address for bitfield desc{d}_hd[c:0] */ 1439/* register address for bitfield desc{d}_hd[c:0] */
1433#define tdm_descdhd_adr(descriptor) (0x00007c0c + (descriptor) * 0x40) 1440#define HW_ATL_TDM_DESCDHD_ADR(descriptor) (0x00007c0c + (descriptor) * 0x40)
1434/* bitmask for bitfield desc{d}_hd[c:0] */ 1441/* bitmask for bitfield desc{d}_hd[c:0] */
1435#define tdm_descdhd_msk 0x00001fff 1442#define HW_ATL_TDM_DESCDHD_MSK 0x00001fff
1436/* inverted bitmask for bitfield desc{d}_hd[c:0] */ 1443/* inverted bitmask for bitfield desc{d}_hd[c:0] */
1437#define tdm_descdhd_mskn 0xffffe000 1444#define HW_ATL_TDM_DESCDHD_MSKN 0xffffe000
1438/* lower bit position of bitfield desc{d}_hd[c:0] */ 1445/* lower bit position of bitfield desc{d}_hd[c:0] */
1439#define tdm_descdhd_shift 0 1446#define HW_ATL_TDM_DESCDHD_SHIFT 0
1440/* width of bitfield desc{d}_hd[c:0] */ 1447/* width of bitfield desc{d}_hd[c:0] */
1441#define tdm_descdhd_width 13 1448#define HW_ATL_TDM_DESCDHD_WIDTH 13
1442 1449
1443/* tx desc{d}_len[9:0] bitfield definitions 1450/* tx desc{d}_len[9:0] bitfield definitions
1444 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 1451 * preprocessor definitions for the bitfield "desc{d}_len[9:0]".
@@ -1447,17 +1454,17 @@
1447 */ 1454 */
1448 1455
1449/* register address for bitfield desc{d}_len[9:0] */ 1456/* register address for bitfield desc{d}_len[9:0] */
1450#define tdm_descdlen_adr(descriptor) (0x00007c08 + (descriptor) * 0x40) 1457#define HW_ATL_TDM_DESCDLEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40)
1451/* bitmask for bitfield desc{d}_len[9:0] */ 1458/* bitmask for bitfield desc{d}_len[9:0] */
1452#define tdm_descdlen_msk 0x00001ff8 1459#define HW_ATL_TDM_DESCDLEN_MSK 0x00001ff8
1453/* inverted bitmask for bitfield desc{d}_len[9:0] */ 1460/* inverted bitmask for bitfield desc{d}_len[9:0] */
1454#define tdm_descdlen_mskn 0xffffe007 1461#define HW_ATL_TDM_DESCDLEN_MSKN 0xffffe007
1455/* lower bit position of bitfield desc{d}_len[9:0] */ 1462/* lower bit position of bitfield desc{d}_len[9:0] */
1456#define tdm_descdlen_shift 3 1463#define HW_ATL_TDM_DESCDLEN_SHIFT 3
1457/* width of bitfield desc{d}_len[9:0] */ 1464/* width of bitfield desc{d}_len[9:0] */
1458#define tdm_descdlen_width 10 1465#define HW_ATL_TDM_DESCDLEN_WIDTH 10
1459/* default value of bitfield desc{d}_len[9:0] */ 1466/* default value of bitfield desc{d}_len[9:0] */
1460#define tdm_descdlen_default 0x0 1467#define HW_ATL_TDM_DESCDLEN_DEFAULT 0x0
1461 1468
1462/* tx int_desc_wrb_en bitfield definitions 1469/* tx int_desc_wrb_en bitfield definitions
1463 * preprocessor definitions for the bitfield "int_desc_wrb_en". 1470 * preprocessor definitions for the bitfield "int_desc_wrb_en".
@@ -1465,17 +1472,17 @@
1465 */ 1472 */
1466 1473
1467/* register address for bitfield int_desc_wrb_en */ 1474/* register address for bitfield int_desc_wrb_en */
1468#define tdm_int_desc_wrb_en_adr 0x00007b40 1475#define HW_ATL_TDM_INT_DESC_WRB_EN_ADR 0x00007b40
1469/* bitmask for bitfield int_desc_wrb_en */ 1476/* bitmask for bitfield int_desc_wrb_en */
1470#define tdm_int_desc_wrb_en_msk 0x00000002 1477#define HW_ATL_TDM_INT_DESC_WRB_EN_MSK 0x00000002
1471/* inverted bitmask for bitfield int_desc_wrb_en */ 1478/* inverted bitmask for bitfield int_desc_wrb_en */
1472#define tdm_int_desc_wrb_en_mskn 0xfffffffd 1479#define HW_ATL_TDM_INT_DESC_WRB_EN_MSKN 0xfffffffd
1473/* lower bit position of bitfield int_desc_wrb_en */ 1480/* lower bit position of bitfield int_desc_wrb_en */
1474#define tdm_int_desc_wrb_en_shift 1 1481#define HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT 1
1475/* width of bitfield int_desc_wrb_en */ 1482/* width of bitfield int_desc_wrb_en */
1476#define tdm_int_desc_wrb_en_width 1 1483#define HW_ATL_TDM_INT_DESC_WRB_EN_WIDTH 1
1477/* default value of bitfield int_desc_wrb_en */ 1484/* default value of bitfield int_desc_wrb_en */
1478#define tdm_int_desc_wrb_en_default 0x0 1485#define HW_ATL_TDM_INT_DESC_WRB_EN_DEFAULT 0x0
1479 1486
1480/* tx desc{d}_wrb_thresh[6:0] bitfield definitions 1487/* tx desc{d}_wrb_thresh[6:0] bitfield definitions
1481 * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]". 1488 * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]".
@@ -1484,17 +1491,18 @@
1484 */ 1491 */
1485 1492
1486/* register address for bitfield desc{d}_wrb_thresh[6:0] */ 1493/* register address for bitfield desc{d}_wrb_thresh[6:0] */
1487#define tdm_descdwrb_thresh_adr(descriptor) (0x00007c18 + (descriptor) * 0x40) 1494#define HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor) \
1495 (0x00007c18 + (descriptor) * 0x40)
1488/* bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1496/* bitmask for bitfield desc{d}_wrb_thresh[6:0] */
1489#define tdm_descdwrb_thresh_msk 0x00007f00 1497#define HW_ATL_TDM_DESCDWRB_THRESH_MSK 0x00007f00
1490/* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1498/* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */
1491#define tdm_descdwrb_thresh_mskn 0xffff80ff 1499#define HW_ATL_TDM_DESCDWRB_THRESH_MSKN 0xffff80ff
1492/* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */ 1500/* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */
1493#define tdm_descdwrb_thresh_shift 8 1501#define HW_ATL_TDM_DESCDWRB_THRESH_SHIFT 8
1494/* width of bitfield desc{d}_wrb_thresh[6:0] */ 1502/* width of bitfield desc{d}_wrb_thresh[6:0] */
1495#define tdm_descdwrb_thresh_width 7 1503#define HW_ATL_TDM_DESCDWRB_THRESH_WIDTH 7
1496/* default value of bitfield desc{d}_wrb_thresh[6:0] */ 1504/* default value of bitfield desc{d}_wrb_thresh[6:0] */
1497#define tdm_descdwrb_thresh_default 0x0 1505#define HW_ATL_TDM_DESCDWRB_THRESH_DEFAULT 0x0
1498 1506
1499/* tx lso_tcp_flag_first[b:0] bitfield definitions 1507/* tx lso_tcp_flag_first[b:0] bitfield definitions
1500 * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]". 1508 * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]".
@@ -1502,17 +1510,17 @@
1502 */ 1510 */
1503 1511
1504/* register address for bitfield lso_tcp_flag_first[b:0] */ 1512/* register address for bitfield lso_tcp_flag_first[b:0] */
1505#define thm_lso_tcp_flag_first_adr 0x00007820 1513#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR 0x00007820
1506/* bitmask for bitfield lso_tcp_flag_first[b:0] */ 1514/* bitmask for bitfield lso_tcp_flag_first[b:0] */
1507#define thm_lso_tcp_flag_first_msk 0x00000fff 1515#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK 0x00000fff
1508/* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */ 1516/* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */
1509#define thm_lso_tcp_flag_first_mskn 0xfffff000 1517#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSKN 0xfffff000
1510/* lower bit position of bitfield lso_tcp_flag_first[b:0] */ 1518/* lower bit position of bitfield lso_tcp_flag_first[b:0] */
1511#define thm_lso_tcp_flag_first_shift 0 1519#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT 0
1512/* width of bitfield lso_tcp_flag_first[b:0] */ 1520/* width of bitfield lso_tcp_flag_first[b:0] */
1513#define thm_lso_tcp_flag_first_width 12 1521#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_WIDTH 12
1514/* default value of bitfield lso_tcp_flag_first[b:0] */ 1522/* default value of bitfield lso_tcp_flag_first[b:0] */
1515#define thm_lso_tcp_flag_first_default 0x0 1523#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_DEFAULT 0x0
1516 1524
1517/* tx lso_tcp_flag_last[b:0] bitfield definitions 1525/* tx lso_tcp_flag_last[b:0] bitfield definitions
1518 * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]". 1526 * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]".
@@ -1520,17 +1528,17 @@
1520 */ 1528 */
1521 1529
1522/* register address for bitfield lso_tcp_flag_last[b:0] */ 1530/* register address for bitfield lso_tcp_flag_last[b:0] */
1523#define thm_lso_tcp_flag_last_adr 0x00007824 1531#define HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR 0x00007824
1524/* bitmask for bitfield lso_tcp_flag_last[b:0] */ 1532/* bitmask for bitfield lso_tcp_flag_last[b:0] */
1525#define thm_lso_tcp_flag_last_msk 0x00000fff 1533#define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK 0x00000fff
1526/* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */ 1534/* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */
1527#define thm_lso_tcp_flag_last_mskn 0xfffff000 1535#define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSKN 0xfffff000
1528/* lower bit position of bitfield lso_tcp_flag_last[b:0] */ 1536/* lower bit position of bitfield lso_tcp_flag_last[b:0] */
1529#define thm_lso_tcp_flag_last_shift 0 1537#define HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT 0
1530/* width of bitfield lso_tcp_flag_last[b:0] */ 1538/* width of bitfield lso_tcp_flag_last[b:0] */
1531#define thm_lso_tcp_flag_last_width 12 1539#define HW_ATL_THM_LSO_TCP_FLAG_LAST_WIDTH 12
1532/* default value of bitfield lso_tcp_flag_last[b:0] */ 1540/* default value of bitfield lso_tcp_flag_last[b:0] */
1533#define thm_lso_tcp_flag_last_default 0x0 1541#define HW_ATL_THM_LSO_TCP_FLAG_LAST_DEFAULT 0x0
1534 1542
1535/* tx lso_tcp_flag_mid[b:0] bitfield definitions 1543/* tx lso_tcp_flag_mid[b:0] bitfield definitions
1536 * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]". 1544 * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]".
@@ -1538,17 +1546,17 @@
1538 */ 1546 */
1539 1547
1540/* Register address for bitfield lro_rsc_max[1F:0] */ 1548/* Register address for bitfield lro_rsc_max[1F:0] */
1541#define rpo_lro_rsc_max_adr 0x00005598 1549#define HW_ATL_RPO_LRO_RSC_MAX_ADR 0x00005598
1542/* Bitmask for bitfield lro_rsc_max[1F:0] */ 1550/* Bitmask for bitfield lro_rsc_max[1F:0] */
1543#define rpo_lro_rsc_max_msk 0xFFFFFFFF 1551#define HW_ATL_RPO_LRO_RSC_MAX_MSK 0xFFFFFFFF
1544/* Inverted bitmask for bitfield lro_rsc_max[1F:0] */ 1552/* Inverted bitmask for bitfield lro_rsc_max[1F:0] */
1545#define rpo_lro_rsc_max_mskn 0x00000000 1553#define HW_ATL_RPO_LRO_RSC_MAX_MSKN 0x00000000
1546/* Lower bit position of bitfield lro_rsc_max[1F:0] */ 1554/* Lower bit position of bitfield lro_rsc_max[1F:0] */
1547#define rpo_lro_rsc_max_shift 0 1555#define HW_ATL_RPO_LRO_RSC_MAX_SHIFT 0
1548/* Width of bitfield lro_rsc_max[1F:0] */ 1556/* Width of bitfield lro_rsc_max[1F:0] */
1549#define rpo_lro_rsc_max_width 32 1557#define HW_ATL_RPO_LRO_RSC_MAX_WIDTH 32
1550/* Default value of bitfield lro_rsc_max[1F:0] */ 1558/* Default value of bitfield lro_rsc_max[1F:0] */
1551#define rpo_lro_rsc_max_default 0x0 1559#define HW_ATL_RPO_LRO_RSC_MAX_DEFAULT 0x0
1552 1560
1553/* RX lro_en[1F:0] Bitfield Definitions 1561/* RX lro_en[1F:0] Bitfield Definitions
1554 * Preprocessor definitions for the bitfield "lro_en[1F:0]". 1562 * Preprocessor definitions for the bitfield "lro_en[1F:0]".
@@ -1556,17 +1564,17 @@
1556 */ 1564 */
1557 1565
1558/* Register address for bitfield lro_en[1F:0] */ 1566/* Register address for bitfield lro_en[1F:0] */
1559#define rpo_lro_en_adr 0x00005590 1567#define HW_ATL_RPO_LRO_EN_ADR 0x00005590
1560/* Bitmask for bitfield lro_en[1F:0] */ 1568/* Bitmask for bitfield lro_en[1F:0] */
1561#define rpo_lro_en_msk 0xFFFFFFFF 1569#define HW_ATL_RPO_LRO_EN_MSK 0xFFFFFFFF
1562/* Inverted bitmask for bitfield lro_en[1F:0] */ 1570/* Inverted bitmask for bitfield lro_en[1F:0] */
1563#define rpo_lro_en_mskn 0x00000000 1571#define HW_ATL_RPO_LRO_EN_MSKN 0x00000000
1564/* Lower bit position of bitfield lro_en[1F:0] */ 1572/* Lower bit position of bitfield lro_en[1F:0] */
1565#define rpo_lro_en_shift 0 1573#define HW_ATL_RPO_LRO_EN_SHIFT 0
1566/* Width of bitfield lro_en[1F:0] */ 1574/* Width of bitfield lro_en[1F:0] */
1567#define rpo_lro_en_width 32 1575#define HW_ATL_RPO_LRO_EN_WIDTH 32
1568/* Default value of bitfield lro_en[1F:0] */ 1576/* Default value of bitfield lro_en[1F:0] */
1569#define rpo_lro_en_default 0x0 1577#define HW_ATL_RPO_LRO_EN_DEFAULT 0x0
1570 1578
1571/* RX lro_ptopt_en Bitfield Definitions 1579/* RX lro_ptopt_en Bitfield Definitions
1572 * Preprocessor definitions for the bitfield "lro_ptopt_en". 1580 * Preprocessor definitions for the bitfield "lro_ptopt_en".
@@ -1574,17 +1582,17 @@
1574 */ 1582 */
1575 1583
1576/* Register address for bitfield lro_ptopt_en */ 1584/* Register address for bitfield lro_ptopt_en */
1577#define rpo_lro_ptopt_en_adr 0x00005594 1585#define HW_ATL_RPO_LRO_PTOPT_EN_ADR 0x00005594
1578/* Bitmask for bitfield lro_ptopt_en */ 1586/* Bitmask for bitfield lro_ptopt_en */
1579#define rpo_lro_ptopt_en_msk 0x00008000 1587#define HW_ATL_RPO_LRO_PTOPT_EN_MSK 0x00008000
1580/* Inverted bitmask for bitfield lro_ptopt_en */ 1588/* Inverted bitmask for bitfield lro_ptopt_en */
1581#define rpo_lro_ptopt_en_mskn 0xFFFF7FFF 1589#define HW_ATL_RPO_LRO_PTOPT_EN_MSKN 0xFFFF7FFF
1582/* Lower bit position of bitfield lro_ptopt_en */ 1590/* Lower bit position of bitfield lro_ptopt_en */
1583#define rpo_lro_ptopt_en_shift 15 1591#define HW_ATL_RPO_LRO_PTOPT_EN_SHIFT 15
1584/* Width of bitfield lro_ptopt_en */ 1592/* Width of bitfield lro_ptopt_en */
1585#define rpo_lro_ptopt_en_width 1 1593#define HW_ATL_RPO_LRO_PTOPT_EN_WIDTH 1
1586/* Default value of bitfield lro_ptopt_en */ 1594/* Default value of bitfield lro_ptopt_en */
1587#define rpo_lro_ptopt_en_defalt 0x1 1595#define HW_ATL_RPO_LRO_PTOPT_EN_DEFALT 0x1
1588 1596
1589/* RX lro_q_ses_lmt Bitfield Definitions 1597/* RX lro_q_ses_lmt Bitfield Definitions
1590 * Preprocessor definitions for the bitfield "lro_q_ses_lmt". 1598 * Preprocessor definitions for the bitfield "lro_q_ses_lmt".
@@ -1592,17 +1600,17 @@
1592 */ 1600 */
1593 1601
1594/* Register address for bitfield lro_q_ses_lmt */ 1602/* Register address for bitfield lro_q_ses_lmt */
1595#define rpo_lro_qses_lmt_adr 0x00005594 1603#define HW_ATL_RPO_LRO_QSES_LMT_ADR 0x00005594
1596/* Bitmask for bitfield lro_q_ses_lmt */ 1604/* Bitmask for bitfield lro_q_ses_lmt */
1597#define rpo_lro_qses_lmt_msk 0x00003000 1605#define HW_ATL_RPO_LRO_QSES_LMT_MSK 0x00003000
1598/* Inverted bitmask for bitfield lro_q_ses_lmt */ 1606/* Inverted bitmask for bitfield lro_q_ses_lmt */
1599#define rpo_lro_qses_lmt_mskn 0xFFFFCFFF 1607#define HW_ATL_RPO_LRO_QSES_LMT_MSKN 0xFFFFCFFF
1600/* Lower bit position of bitfield lro_q_ses_lmt */ 1608/* Lower bit position of bitfield lro_q_ses_lmt */
1601#define rpo_lro_qses_lmt_shift 12 1609#define HW_ATL_RPO_LRO_QSES_LMT_SHIFT 12
1602/* Width of bitfield lro_q_ses_lmt */ 1610/* Width of bitfield lro_q_ses_lmt */
1603#define rpo_lro_qses_lmt_width 2 1611#define HW_ATL_RPO_LRO_QSES_LMT_WIDTH 2
1604/* Default value of bitfield lro_q_ses_lmt */ 1612/* Default value of bitfield lro_q_ses_lmt */
1605#define rpo_lro_qses_lmt_default 0x1 1613#define HW_ATL_RPO_LRO_QSES_LMT_DEFAULT 0x1
1606 1614
1607/* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions 1615/* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions
1608 * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]". 1616 * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]".
@@ -1610,17 +1618,17 @@
1610 */ 1618 */
1611 1619
1612/* Register address for bitfield lro_tot_dsc_lmt[1:0] */ 1620/* Register address for bitfield lro_tot_dsc_lmt[1:0] */
1613#define rpo_lro_tot_dsc_lmt_adr 0x00005594 1621#define HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR 0x00005594
1614/* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1622/* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */
1615#define rpo_lro_tot_dsc_lmt_msk 0x00000060 1623#define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK 0x00000060
1616/* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1624/* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */
1617#define rpo_lro_tot_dsc_lmt_mskn 0xFFFFFF9F 1625#define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSKN 0xFFFFFF9F
1618/* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */ 1626/* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */
1619#define rpo_lro_tot_dsc_lmt_shift 5 1627#define HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT 5
1620/* Width of bitfield lro_tot_dsc_lmt[1:0] */ 1628/* Width of bitfield lro_tot_dsc_lmt[1:0] */
1621#define rpo_lro_tot_dsc_lmt_width 2 1629#define HW_ATL_RPO_LRO_TOT_DSC_LMT_WIDTH 2
1622/* Default value of bitfield lro_tot_dsc_lmt[1:0] */ 1630/* Default value of bitfield lro_tot_dsc_lmt[1:0] */
1623#define rpo_lro_tot_dsc_lmt_defalt 0x1 1631#define HW_ATL_RPO_LRO_TOT_DSC_LMT_DEFALT 0x1
1624 1632
1625/* RX lro_pkt_min[4:0] Bitfield Definitions 1633/* RX lro_pkt_min[4:0] Bitfield Definitions
1626 * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]". 1634 * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]".
@@ -1628,22 +1636,22 @@
1628 */ 1636 */
1629 1637
1630/* Register address for bitfield lro_pkt_min[4:0] */ 1638/* Register address for bitfield lro_pkt_min[4:0] */
1631#define rpo_lro_pkt_min_adr 0x00005594 1639#define HW_ATL_RPO_LRO_PKT_MIN_ADR 0x00005594
1632/* Bitmask for bitfield lro_pkt_min[4:0] */ 1640/* Bitmask for bitfield lro_pkt_min[4:0] */
1633#define rpo_lro_pkt_min_msk 0x0000001F 1641#define HW_ATL_RPO_LRO_PKT_MIN_MSK 0x0000001F
1634/* Inverted bitmask for bitfield lro_pkt_min[4:0] */ 1642/* Inverted bitmask for bitfield lro_pkt_min[4:0] */
1635#define rpo_lro_pkt_min_mskn 0xFFFFFFE0 1643#define HW_ATL_RPO_LRO_PKT_MIN_MSKN 0xFFFFFFE0
1636/* Lower bit position of bitfield lro_pkt_min[4:0] */ 1644/* Lower bit position of bitfield lro_pkt_min[4:0] */
1637#define rpo_lro_pkt_min_shift 0 1645#define HW_ATL_RPO_LRO_PKT_MIN_SHIFT 0
1638/* Width of bitfield lro_pkt_min[4:0] */ 1646/* Width of bitfield lro_pkt_min[4:0] */
1639#define rpo_lro_pkt_min_width 5 1647#define HW_ATL_RPO_LRO_PKT_MIN_WIDTH 5
1640/* Default value of bitfield lro_pkt_min[4:0] */ 1648/* Default value of bitfield lro_pkt_min[4:0] */
1641#define rpo_lro_pkt_min_default 0x8 1649#define HW_ATL_RPO_LRO_PKT_MIN_DEFAULT 0x8
1642 1650
1643/* Width of bitfield lro{L}_des_max[1:0] */ 1651/* Width of bitfield lro{L}_des_max[1:0] */
1644#define rpo_lro_ldes_max_width 2 1652#define HW_ATL_RPO_LRO_LDES_MAX_WIDTH 2
1645/* Default value of bitfield lro{L}_des_max[1:0] */ 1653/* Default value of bitfield lro{L}_des_max[1:0] */
1646#define rpo_lro_ldes_max_default 0x0 1654#define HW_ATL_RPO_LRO_LDES_MAX_DEFAULT 0x0
1647 1655
1648/* RX lro_tb_div[11:0] Bitfield Definitions 1656/* RX lro_tb_div[11:0] Bitfield Definitions
1649 * Preprocessor definitions for the bitfield "lro_tb_div[11:0]". 1657 * Preprocessor definitions for the bitfield "lro_tb_div[11:0]".
@@ -1651,17 +1659,17 @@
1651 */ 1659 */
1652 1660
1653/* Register address for bitfield lro_tb_div[11:0] */ 1661/* Register address for bitfield lro_tb_div[11:0] */
1654#define rpo_lro_tb_div_adr 0x00005620 1662#define HW_ATL_RPO_LRO_TB_DIV_ADR 0x00005620
1655/* Bitmask for bitfield lro_tb_div[11:0] */ 1663/* Bitmask for bitfield lro_tb_div[11:0] */
1656#define rpo_lro_tb_div_msk 0xFFF00000 1664#define HW_ATL_RPO_LRO_TB_DIV_MSK 0xFFF00000
1657/* Inverted bitmask for bitfield lro_tb_div[11:0] */ 1665/* Inverted bitmask for bitfield lro_tb_div[11:0] */
1658#define rpo_lro_tb_div_mskn 0x000FFFFF 1666#define HW_ATL_RPO_LRO_TB_DIV_MSKN 0x000FFFFF
1659/* Lower bit position of bitfield lro_tb_div[11:0] */ 1667/* Lower bit position of bitfield lro_tb_div[11:0] */
1660#define rpo_lro_tb_div_shift 20 1668#define HW_ATL_RPO_LRO_TB_DIV_SHIFT 20
1661/* Width of bitfield lro_tb_div[11:0] */ 1669/* Width of bitfield lro_tb_div[11:0] */
1662#define rpo_lro_tb_div_width 12 1670#define HW_ATL_RPO_LRO_TB_DIV_WIDTH 12
1663/* Default value of bitfield lro_tb_div[11:0] */ 1671/* Default value of bitfield lro_tb_div[11:0] */
1664#define rpo_lro_tb_div_default 0xC35 1672#define HW_ATL_RPO_LRO_TB_DIV_DEFAULT 0xC35
1665 1673
1666/* RX lro_ina_ival[9:0] Bitfield Definitions 1674/* RX lro_ina_ival[9:0] Bitfield Definitions
1667 * Preprocessor definitions for the bitfield "lro_ina_ival[9:0]". 1675 * Preprocessor definitions for the bitfield "lro_ina_ival[9:0]".
@@ -1669,17 +1677,17 @@
1669 */ 1677 */
1670 1678
1671/* Register address for bitfield lro_ina_ival[9:0] */ 1679/* Register address for bitfield lro_ina_ival[9:0] */
1672#define rpo_lro_ina_ival_adr 0x00005620 1680#define HW_ATL_RPO_LRO_INA_IVAL_ADR 0x00005620
1673/* Bitmask for bitfield lro_ina_ival[9:0] */ 1681/* Bitmask for bitfield lro_ina_ival[9:0] */
1674#define rpo_lro_ina_ival_msk 0x000FFC00 1682#define HW_ATL_RPO_LRO_INA_IVAL_MSK 0x000FFC00
1675/* Inverted bitmask for bitfield lro_ina_ival[9:0] */ 1683/* Inverted bitmask for bitfield lro_ina_ival[9:0] */
1676#define rpo_lro_ina_ival_mskn 0xFFF003FF 1684#define HW_ATL_RPO_LRO_INA_IVAL_MSKN 0xFFF003FF
1677/* Lower bit position of bitfield lro_ina_ival[9:0] */ 1685/* Lower bit position of bitfield lro_ina_ival[9:0] */
1678#define rpo_lro_ina_ival_shift 10 1686#define HW_ATL_RPO_LRO_INA_IVAL_SHIFT 10
1679/* Width of bitfield lro_ina_ival[9:0] */ 1687/* Width of bitfield lro_ina_ival[9:0] */
1680#define rpo_lro_ina_ival_width 10 1688#define HW_ATL_RPO_LRO_INA_IVAL_WIDTH 10
1681/* Default value of bitfield lro_ina_ival[9:0] */ 1689/* Default value of bitfield lro_ina_ival[9:0] */
1682#define rpo_lro_ina_ival_default 0xA 1690#define HW_ATL_RPO_LRO_INA_IVAL_DEFAULT 0xA
1683 1691
1684/* RX lro_max_ival[9:0] Bitfield Definitions 1692/* RX lro_max_ival[9:0] Bitfield Definitions
1685 * Preprocessor definitions for the bitfield "lro_max_ival[9:0]". 1693 * Preprocessor definitions for the bitfield "lro_max_ival[9:0]".
@@ -1687,17 +1695,17 @@
1687 */ 1695 */
1688 1696
1689/* Register address for bitfield lro_max_ival[9:0] */ 1697/* Register address for bitfield lro_max_ival[9:0] */
1690#define rpo_lro_max_ival_adr 0x00005620 1698#define HW_ATL_RPO_LRO_MAX_IVAL_ADR 0x00005620
1691/* Bitmask for bitfield lro_max_ival[9:0] */ 1699/* Bitmask for bitfield lro_max_ival[9:0] */
1692#define rpo_lro_max_ival_msk 0x000003FF 1700#define HW_ATL_RPO_LRO_MAX_IVAL_MSK 0x000003FF
1693/* Inverted bitmask for bitfield lro_max_ival[9:0] */ 1701/* Inverted bitmask for bitfield lro_max_ival[9:0] */
1694#define rpo_lro_max_ival_mskn 0xFFFFFC00 1702#define HW_ATL_RPO_LRO_MAX_IVAL_MSKN 0xFFFFFC00
1695/* Lower bit position of bitfield lro_max_ival[9:0] */ 1703/* Lower bit position of bitfield lro_max_ival[9:0] */
1696#define rpo_lro_max_ival_shift 0 1704#define HW_ATL_RPO_LRO_MAX_IVAL_SHIFT 0
1697/* Width of bitfield lro_max_ival[9:0] */ 1705/* Width of bitfield lro_max_ival[9:0] */
1698#define rpo_lro_max_ival_width 10 1706#define HW_ATL_RPO_LRO_MAX_IVAL_WIDTH 10
1699/* Default value of bitfield lro_max_ival[9:0] */ 1707/* Default value of bitfield lro_max_ival[9:0] */
1700#define rpo_lro_max_ival_default 0x19 1708#define HW_ATL_RPO_LRO_MAX_IVAL_DEFAULT 0x19
1701 1709
1702/* TX dca{D}_cpuid[7:0] Bitfield Definitions 1710/* TX dca{D}_cpuid[7:0] Bitfield Definitions
1703 * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]". 1711 * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]".
@@ -1706,17 +1714,17 @@
1706 */ 1714 */
1707 1715
1708/* Register address for bitfield dca{D}_cpuid[7:0] */ 1716/* Register address for bitfield dca{D}_cpuid[7:0] */
1709#define tdm_dca_dcpuid_adr(dca) (0x00008400 + (dca) * 0x4) 1717#define HW_ATL_TDM_DCA_DCPUID_ADR(dca) (0x00008400 + (dca) * 0x4)
1710/* Bitmask for bitfield dca{D}_cpuid[7:0] */ 1718/* Bitmask for bitfield dca{D}_cpuid[7:0] */
1711#define tdm_dca_dcpuid_msk 0x000000FF 1719#define HW_ATL_TDM_DCA_DCPUID_MSK 0x000000FF
1712/* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */ 1720/* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */
1713#define tdm_dca_dcpuid_mskn 0xFFFFFF00 1721#define HW_ATL_TDM_DCA_DCPUID_MSKN 0xFFFFFF00
1714/* Lower bit position of bitfield dca{D}_cpuid[7:0] */ 1722/* Lower bit position of bitfield dca{D}_cpuid[7:0] */
1715#define tdm_dca_dcpuid_shift 0 1723#define HW_ATL_TDM_DCA_DCPUID_SHIFT 0
1716/* Width of bitfield dca{D}_cpuid[7:0] */ 1724/* Width of bitfield dca{D}_cpuid[7:0] */
1717#define tdm_dca_dcpuid_width 8 1725#define HW_ATL_TDM_DCA_DCPUID_WIDTH 8
1718/* Default value of bitfield dca{D}_cpuid[7:0] */ 1726/* Default value of bitfield dca{D}_cpuid[7:0] */
1719#define tdm_dca_dcpuid_default 0x0 1727#define HW_ATL_TDM_DCA_DCPUID_DEFAULT 0x0
1720 1728
1721/* TX dca{D}_desc_en Bitfield Definitions 1729/* TX dca{D}_desc_en Bitfield Definitions
1722 * Preprocessor definitions for the bitfield "dca{D}_desc_en". 1730 * Preprocessor definitions for the bitfield "dca{D}_desc_en".
@@ -1725,17 +1733,17 @@
1725 */ 1733 */
1726 1734
1727/* Register address for bitfield dca{D}_desc_en */ 1735/* Register address for bitfield dca{D}_desc_en */
1728#define tdm_dca_ddesc_en_adr(dca) (0x00008400 + (dca) * 0x4) 1736#define HW_ATL_TDM_DCA_DDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4)
1729/* Bitmask for bitfield dca{D}_desc_en */ 1737/* Bitmask for bitfield dca{D}_desc_en */
1730#define tdm_dca_ddesc_en_msk 0x80000000 1738#define HW_ATL_TDM_DCA_DDESC_EN_MSK 0x80000000
1731/* Inverted bitmask for bitfield dca{D}_desc_en */ 1739/* Inverted bitmask for bitfield dca{D}_desc_en */
1732#define tdm_dca_ddesc_en_mskn 0x7FFFFFFF 1740#define HW_ATL_TDM_DCA_DDESC_EN_MSKN 0x7FFFFFFF
1733/* Lower bit position of bitfield dca{D}_desc_en */ 1741/* Lower bit position of bitfield dca{D}_desc_en */
1734#define tdm_dca_ddesc_en_shift 31 1742#define HW_ATL_TDM_DCA_DDESC_EN_SHIFT 31
1735/* Width of bitfield dca{D}_desc_en */ 1743/* Width of bitfield dca{D}_desc_en */
1736#define tdm_dca_ddesc_en_width 1 1744#define HW_ATL_TDM_DCA_DDESC_EN_WIDTH 1
1737/* Default value of bitfield dca{D}_desc_en */ 1745/* Default value of bitfield dca{D}_desc_en */
1738#define tdm_dca_ddesc_en_default 0x0 1746#define HW_ATL_TDM_DCA_DDESC_EN_DEFAULT 0x0
1739 1747
1740/* TX desc{D}_en Bitfield Definitions 1748/* TX desc{D}_en Bitfield Definitions
1741 * Preprocessor definitions for the bitfield "desc{D}_en". 1749 * Preprocessor definitions for the bitfield "desc{D}_en".
@@ -1744,17 +1752,17 @@
1744 */ 1752 */
1745 1753
1746/* Register address for bitfield desc{D}_en */ 1754/* Register address for bitfield desc{D}_en */
1747#define tdm_desc_den_adr(descriptor) (0x00007C08 + (descriptor) * 0x40) 1755#define HW_ATL_TDM_DESC_DEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40)
1748/* Bitmask for bitfield desc{D}_en */ 1756/* Bitmask for bitfield desc{D}_en */
1749#define tdm_desc_den_msk 0x80000000 1757#define HW_ATL_TDM_DESC_DEN_MSK 0x80000000
1750/* Inverted bitmask for bitfield desc{D}_en */ 1758/* Inverted bitmask for bitfield desc{D}_en */
1751#define tdm_desc_den_mskn 0x7FFFFFFF 1759#define HW_ATL_TDM_DESC_DEN_MSKN 0x7FFFFFFF
1752/* Lower bit position of bitfield desc{D}_en */ 1760/* Lower bit position of bitfield desc{D}_en */
1753#define tdm_desc_den_shift 31 1761#define HW_ATL_TDM_DESC_DEN_SHIFT 31
1754/* Width of bitfield desc{D}_en */ 1762/* Width of bitfield desc{D}_en */
1755#define tdm_desc_den_width 1 1763#define HW_ATL_TDM_DESC_DEN_WIDTH 1
1756/* Default value of bitfield desc{D}_en */ 1764/* Default value of bitfield desc{D}_en */
1757#define tdm_desc_den_default 0x0 1765#define HW_ATL_TDM_DESC_DEN_DEFAULT 0x0
1758 1766
1759/* TX desc{D}_hd[C:0] Bitfield Definitions 1767/* TX desc{D}_hd[C:0] Bitfield Definitions
1760 * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]". 1768 * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]".
@@ -1763,15 +1771,15 @@
1763 */ 1771 */
1764 1772
1765/* Register address for bitfield desc{D}_hd[C:0] */ 1773/* Register address for bitfield desc{D}_hd[C:0] */
1766#define tdm_desc_dhd_adr(descriptor) (0x00007C0C + (descriptor) * 0x40) 1774#define HW_ATL_TDM_DESC_DHD_ADR(descriptor) (0x00007C0C + (descriptor) * 0x40)
1767/* Bitmask for bitfield desc{D}_hd[C:0] */ 1775/* Bitmask for bitfield desc{D}_hd[C:0] */
1768#define tdm_desc_dhd_msk 0x00001FFF 1776#define HW_ATL_TDM_DESC_DHD_MSK 0x00001FFF
1769/* Inverted bitmask for bitfield desc{D}_hd[C:0] */ 1777/* Inverted bitmask for bitfield desc{D}_hd[C:0] */
1770#define tdm_desc_dhd_mskn 0xFFFFE000 1778#define HW_ATL_TDM_DESC_DHD_MSKN 0xFFFFE000
1771/* Lower bit position of bitfield desc{D}_hd[C:0] */ 1779/* Lower bit position of bitfield desc{D}_hd[C:0] */
1772#define tdm_desc_dhd_shift 0 1780#define HW_ATL_TDM_DESC_DHD_SHIFT 0
1773/* Width of bitfield desc{D}_hd[C:0] */ 1781/* Width of bitfield desc{D}_hd[C:0] */
1774#define tdm_desc_dhd_width 13 1782#define HW_ATL_TDM_DESC_DHD_WIDTH 13
1775 1783
1776/* TX desc{D}_len[9:0] Bitfield Definitions 1784/* TX desc{D}_len[9:0] Bitfield Definitions
1777 * Preprocessor definitions for the bitfield "desc{D}_len[9:0]". 1785 * Preprocessor definitions for the bitfield "desc{D}_len[9:0]".
@@ -1780,17 +1788,17 @@
1780 */ 1788 */
1781 1789
1782/* Register address for bitfield desc{D}_len[9:0] */ 1790/* Register address for bitfield desc{D}_len[9:0] */
1783#define tdm_desc_dlen_adr(descriptor) (0x00007C08 + (descriptor) * 0x40) 1791#define HW_ATL_TDM_DESC_DLEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40)
1784/* Bitmask for bitfield desc{D}_len[9:0] */ 1792/* Bitmask for bitfield desc{D}_len[9:0] */
1785#define tdm_desc_dlen_msk 0x00001FF8 1793#define HW_ATL_TDM_DESC_DLEN_MSK 0x00001FF8
1786/* Inverted bitmask for bitfield desc{D}_len[9:0] */ 1794/* Inverted bitmask for bitfield desc{D}_len[9:0] */
1787#define tdm_desc_dlen_mskn 0xFFFFE007 1795#define HW_ATL_TDM_DESC_DLEN_MSKN 0xFFFFE007
1788/* Lower bit position of bitfield desc{D}_len[9:0] */ 1796/* Lower bit position of bitfield desc{D}_len[9:0] */
1789#define tdm_desc_dlen_shift 3 1797#define HW_ATL_TDM_DESC_DLEN_SHIFT 3
1790/* Width of bitfield desc{D}_len[9:0] */ 1798/* Width of bitfield desc{D}_len[9:0] */
1791#define tdm_desc_dlen_width 10 1799#define HW_ATL_TDM_DESC_DLEN_WIDTH 10
1792/* Default value of bitfield desc{D}_len[9:0] */ 1800/* Default value of bitfield desc{D}_len[9:0] */
1793#define tdm_desc_dlen_default 0x0 1801#define HW_ATL_TDM_DESC_DLEN_DEFAULT 0x0
1794 1802
1795/* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions 1803/* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions
1796 * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]". 1804 * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]".
@@ -1799,18 +1807,18 @@
1799 */ 1807 */
1800 1808
1801/* Register address for bitfield desc{D}_wrb_thresh[6:0] */ 1809/* Register address for bitfield desc{D}_wrb_thresh[6:0] */
1802#define tdm_desc_dwrb_thresh_adr(descriptor) \ 1810#define HW_ATL_TDM_DESC_DWRB_THRESH_ADR(descriptor) \
1803 (0x00007C18 + (descriptor) * 0x40) 1811 (0x00007C18 + (descriptor) * 0x40)
1804/* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 1812/* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */
1805#define tdm_desc_dwrb_thresh_msk 0x00007F00 1813#define HW_ATL_TDM_DESC_DWRB_THRESH_MSK 0x00007F00
1806/* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 1814/* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */
1807#define tdm_desc_dwrb_thresh_mskn 0xFFFF80FF 1815#define HW_ATL_TDM_DESC_DWRB_THRESH_MSKN 0xFFFF80FF
1808/* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */ 1816/* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */
1809#define tdm_desc_dwrb_thresh_shift 8 1817#define HW_ATL_TDM_DESC_DWRB_THRESH_SHIFT 8
1810/* Width of bitfield desc{D}_wrb_thresh[6:0] */ 1818/* Width of bitfield desc{D}_wrb_thresh[6:0] */
1811#define tdm_desc_dwrb_thresh_width 7 1819#define HW_ATL_TDM_DESC_DWRB_THRESH_WIDTH 7
1812/* Default value of bitfield desc{D}_wrb_thresh[6:0] */ 1820/* Default value of bitfield desc{D}_wrb_thresh[6:0] */
1813#define tdm_desc_dwrb_thresh_default 0x0 1821#define HW_ATL_TDM_DESC_DWRB_THRESH_DEFAULT 0x0
1814 1822
1815/* TX tdm_int_mod_en Bitfield Definitions 1823/* TX tdm_int_mod_en Bitfield Definitions
1816 * Preprocessor definitions for the bitfield "tdm_int_mod_en". 1824 * Preprocessor definitions for the bitfield "tdm_int_mod_en".
@@ -1818,34 +1826,34 @@
1818 */ 1826 */
1819 1827
1820/* Register address for bitfield tdm_int_mod_en */ 1828/* Register address for bitfield tdm_int_mod_en */
1821#define tdm_int_mod_en_adr 0x00007B40 1829#define HW_ATL_TDM_INT_MOD_EN_ADR 0x00007B40
1822/* Bitmask for bitfield tdm_int_mod_en */ 1830/* Bitmask for bitfield tdm_int_mod_en */
1823#define tdm_int_mod_en_msk 0x00000010 1831#define HW_ATL_TDM_INT_MOD_EN_MSK 0x00000010
1824/* Inverted bitmask for bitfield tdm_int_mod_en */ 1832/* Inverted bitmask for bitfield tdm_int_mod_en */
1825#define tdm_int_mod_en_mskn 0xFFFFFFEF 1833#define HW_ATL_TDM_INT_MOD_EN_MSKN 0xFFFFFFEF
1826/* Lower bit position of bitfield tdm_int_mod_en */ 1834/* Lower bit position of bitfield tdm_int_mod_en */
1827#define tdm_int_mod_en_shift 4 1835#define HW_ATL_TDM_INT_MOD_EN_SHIFT 4
1828/* Width of bitfield tdm_int_mod_en */ 1836/* Width of bitfield tdm_int_mod_en */
1829#define tdm_int_mod_en_width 1 1837#define HW_ATL_TDM_INT_MOD_EN_WIDTH 1
1830/* Default value of bitfield tdm_int_mod_en */ 1838/* Default value of bitfield tdm_int_mod_en */
1831#define tdm_int_mod_en_default 0x0 1839#define HW_ATL_TDM_INT_MOD_EN_DEFAULT 0x0
1832 1840
1833/* TX lso_tcp_flag_mid[B:0] Bitfield Definitions 1841/* TX lso_tcp_flag_mid[B:0] Bitfield Definitions
1834 * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]". 1842 * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]".
1835 * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]" 1843 * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]"
1836 */ 1844 */
1837/* register address for bitfield lso_tcp_flag_mid[b:0] */ 1845/* register address for bitfield lso_tcp_flag_mid[b:0] */
1838#define thm_lso_tcp_flag_mid_adr 0x00007820 1846#define HW_ATL_THM_LSO_TCP_FLAG_MID_ADR 0x00007820
1839/* bitmask for bitfield lso_tcp_flag_mid[b:0] */ 1847/* bitmask for bitfield lso_tcp_flag_mid[b:0] */
1840#define thm_lso_tcp_flag_mid_msk 0x0fff0000 1848#define HW_ATL_THM_LSO_TCP_FLAG_MID_MSK 0x0fff0000
1841/* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */ 1849/* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */
1842#define thm_lso_tcp_flag_mid_mskn 0xf000ffff 1850#define HW_ATL_THM_LSO_TCP_FLAG_MID_MSKN 0xf000ffff
1843/* lower bit position of bitfield lso_tcp_flag_mid[b:0] */ 1851/* lower bit position of bitfield lso_tcp_flag_mid[b:0] */
1844#define thm_lso_tcp_flag_mid_shift 16 1852#define HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT 16
1845/* width of bitfield lso_tcp_flag_mid[b:0] */ 1853/* width of bitfield lso_tcp_flag_mid[b:0] */
1846#define thm_lso_tcp_flag_mid_width 12 1854#define HW_ATL_THM_LSO_TCP_FLAG_MID_WIDTH 12
1847/* default value of bitfield lso_tcp_flag_mid[b:0] */ 1855/* default value of bitfield lso_tcp_flag_mid[b:0] */
1848#define thm_lso_tcp_flag_mid_default 0x0 1856#define HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT 0x0
1849 1857
1850/* tx tx_buf_en bitfield definitions 1858/* tx tx_buf_en bitfield definitions
1851 * preprocessor definitions for the bitfield "tx_buf_en". 1859 * preprocessor definitions for the bitfield "tx_buf_en".
@@ -1853,17 +1861,17 @@
1853 */ 1861 */
1854 1862
1855/* register address for bitfield tx_buf_en */ 1863/* register address for bitfield tx_buf_en */
1856#define tpb_tx_buf_en_adr 0x00007900 1864#define HW_ATL_TPB_TX_BUF_EN_ADR 0x00007900
1857/* bitmask for bitfield tx_buf_en */ 1865/* bitmask for bitfield tx_buf_en */
1858#define tpb_tx_buf_en_msk 0x00000001 1866#define HW_ATL_TPB_TX_BUF_EN_MSK 0x00000001
1859/* inverted bitmask for bitfield tx_buf_en */ 1867/* inverted bitmask for bitfield tx_buf_en */
1860#define tpb_tx_buf_en_mskn 0xfffffffe 1868#define HW_ATL_TPB_TX_BUF_EN_MSKN 0xfffffffe
1861/* lower bit position of bitfield tx_buf_en */ 1869/* lower bit position of bitfield tx_buf_en */
1862#define tpb_tx_buf_en_shift 0 1870#define HW_ATL_TPB_TX_BUF_EN_SHIFT 0
1863/* width of bitfield tx_buf_en */ 1871/* width of bitfield tx_buf_en */
1864#define tpb_tx_buf_en_width 1 1872#define HW_ATL_TPB_TX_BUF_EN_WIDTH 1
1865/* default value of bitfield tx_buf_en */ 1873/* default value of bitfield tx_buf_en */
1866#define tpb_tx_buf_en_default 0x0 1874#define HW_ATL_TPB_TX_BUF_EN_DEFAULT 0x0
1867 1875
1868/* tx tx{b}_hi_thresh[c:0] bitfield definitions 1876/* tx tx{b}_hi_thresh[c:0] bitfield definitions
1869 * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]". 1877 * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]".
@@ -1872,17 +1880,17 @@
1872 */ 1880 */
1873 1881
1874/* register address for bitfield tx{b}_hi_thresh[c:0] */ 1882/* register address for bitfield tx{b}_hi_thresh[c:0] */
1875#define tpb_txbhi_thresh_adr(buffer) (0x00007914 + (buffer) * 0x10) 1883#define HW_ATL_TPB_TXBHI_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10)
1876/* bitmask for bitfield tx{b}_hi_thresh[c:0] */ 1884/* bitmask for bitfield tx{b}_hi_thresh[c:0] */
1877#define tpb_txbhi_thresh_msk 0x1fff0000 1885#define HW_ATL_TPB_TXBHI_THRESH_MSK 0x1fff0000
1878/* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */ 1886/* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */
1879#define tpb_txbhi_thresh_mskn 0xe000ffff 1887#define HW_ATL_TPB_TXBHI_THRESH_MSKN 0xe000ffff
1880/* lower bit position of bitfield tx{b}_hi_thresh[c:0] */ 1888/* lower bit position of bitfield tx{b}_hi_thresh[c:0] */
1881#define tpb_txbhi_thresh_shift 16 1889#define HW_ATL_TPB_TXBHI_THRESH_SHIFT 16
1882/* width of bitfield tx{b}_hi_thresh[c:0] */ 1890/* width of bitfield tx{b}_hi_thresh[c:0] */
1883#define tpb_txbhi_thresh_width 13 1891#define HW_ATL_TPB_TXBHI_THRESH_WIDTH 13
1884/* default value of bitfield tx{b}_hi_thresh[c:0] */ 1892/* default value of bitfield tx{b}_hi_thresh[c:0] */
1885#define tpb_txbhi_thresh_default 0x0 1893#define HW_ATL_TPB_TXBHI_THRESH_DEFAULT 0x0
1886 1894
1887/* tx tx{b}_lo_thresh[c:0] bitfield definitions 1895/* tx tx{b}_lo_thresh[c:0] bitfield definitions
1888 * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]". 1896 * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]".
@@ -1891,17 +1899,17 @@
1891 */ 1899 */
1892 1900
1893/* register address for bitfield tx{b}_lo_thresh[c:0] */ 1901/* register address for bitfield tx{b}_lo_thresh[c:0] */
1894#define tpb_txblo_thresh_adr(buffer) (0x00007914 + (buffer) * 0x10) 1902#define HW_ATL_TPB_TXBLO_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10)
1895/* bitmask for bitfield tx{b}_lo_thresh[c:0] */ 1903/* bitmask for bitfield tx{b}_lo_thresh[c:0] */
1896#define tpb_txblo_thresh_msk 0x00001fff 1904#define HW_ATL_TPB_TXBLO_THRESH_MSK 0x00001fff
1897/* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */ 1905/* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */
1898#define tpb_txblo_thresh_mskn 0xffffe000 1906#define HW_ATL_TPB_TXBLO_THRESH_MSKN 0xffffe000
1899/* lower bit position of bitfield tx{b}_lo_thresh[c:0] */ 1907/* lower bit position of bitfield tx{b}_lo_thresh[c:0] */
1900#define tpb_txblo_thresh_shift 0 1908#define HW_ATL_TPB_TXBLO_THRESH_SHIFT 0
1901/* width of bitfield tx{b}_lo_thresh[c:0] */ 1909/* width of bitfield tx{b}_lo_thresh[c:0] */
1902#define tpb_txblo_thresh_width 13 1910#define HW_ATL_TPB_TXBLO_THRESH_WIDTH 13
1903/* default value of bitfield tx{b}_lo_thresh[c:0] */ 1911/* default value of bitfield tx{b}_lo_thresh[c:0] */
1904#define tpb_txblo_thresh_default 0x0 1912#define HW_ATL_TPB_TXBLO_THRESH_DEFAULT 0x0
1905 1913
1906/* tx dma_sys_loopback bitfield definitions 1914/* tx dma_sys_loopback bitfield definitions
1907 * preprocessor definitions for the bitfield "dma_sys_loopback". 1915 * preprocessor definitions for the bitfield "dma_sys_loopback".
@@ -1909,17 +1917,17 @@
1909 */ 1917 */
1910 1918
1911/* register address for bitfield dma_sys_loopback */ 1919/* register address for bitfield dma_sys_loopback */
1912#define tpb_dma_sys_lbk_adr 0x00007000 1920#define HW_ATL_TPB_DMA_SYS_LBK_ADR 0x00007000
1913/* bitmask for bitfield dma_sys_loopback */ 1921/* bitmask for bitfield dma_sys_loopback */
1914#define tpb_dma_sys_lbk_msk 0x00000040 1922#define HW_ATL_TPB_DMA_SYS_LBK_MSK 0x00000040
1915/* inverted bitmask for bitfield dma_sys_loopback */ 1923/* inverted bitmask for bitfield dma_sys_loopback */
1916#define tpb_dma_sys_lbk_mskn 0xffffffbf 1924#define HW_ATL_TPB_DMA_SYS_LBK_MSKN 0xffffffbf
1917/* lower bit position of bitfield dma_sys_loopback */ 1925/* lower bit position of bitfield dma_sys_loopback */
1918#define tpb_dma_sys_lbk_shift 6 1926#define HW_ATL_TPB_DMA_SYS_LBK_SHIFT 6
1919/* width of bitfield dma_sys_loopback */ 1927/* width of bitfield dma_sys_loopback */
1920#define tpb_dma_sys_lbk_width 1 1928#define HW_ATL_TPB_DMA_SYS_LBK_WIDTH 1
1921/* default value of bitfield dma_sys_loopback */ 1929/* default value of bitfield dma_sys_loopback */
1922#define tpb_dma_sys_lbk_default 0x0 1930#define HW_ATL_TPB_DMA_SYS_LBK_DEFAULT 0x0
1923 1931
1924/* tx tx{b}_buf_size[7:0] bitfield definitions 1932/* tx tx{b}_buf_size[7:0] bitfield definitions
1925 * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]". 1933 * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]".
@@ -1928,17 +1936,17 @@
1928 */ 1936 */
1929 1937
1930/* register address for bitfield tx{b}_buf_size[7:0] */ 1938/* register address for bitfield tx{b}_buf_size[7:0] */
1931#define tpb_txbbuf_size_adr(buffer) (0x00007910 + (buffer) * 0x10) 1939#define HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer) (0x00007910 + (buffer) * 0x10)
1932/* bitmask for bitfield tx{b}_buf_size[7:0] */ 1940/* bitmask for bitfield tx{b}_buf_size[7:0] */
1933#define tpb_txbbuf_size_msk 0x000000ff 1941#define HW_ATL_TPB_TXBBUF_SIZE_MSK 0x000000ff
1934/* inverted bitmask for bitfield tx{b}_buf_size[7:0] */ 1942/* inverted bitmask for bitfield tx{b}_buf_size[7:0] */
1935#define tpb_txbbuf_size_mskn 0xffffff00 1943#define HW_ATL_TPB_TXBBUF_SIZE_MSKN 0xffffff00
1936/* lower bit position of bitfield tx{b}_buf_size[7:0] */ 1944/* lower bit position of bitfield tx{b}_buf_size[7:0] */
1937#define tpb_txbbuf_size_shift 0 1945#define HW_ATL_TPB_TXBBUF_SIZE_SHIFT 0
1938/* width of bitfield tx{b}_buf_size[7:0] */ 1946/* width of bitfield tx{b}_buf_size[7:0] */
1939#define tpb_txbbuf_size_width 8 1947#define HW_ATL_TPB_TXBBUF_SIZE_WIDTH 8
1940/* default value of bitfield tx{b}_buf_size[7:0] */ 1948/* default value of bitfield tx{b}_buf_size[7:0] */
1941#define tpb_txbbuf_size_default 0x0 1949#define HW_ATL_TPB_TXBBUF_SIZE_DEFAULT 0x0
1942 1950
1943/* tx tx_scp_ins_en bitfield definitions 1951/* tx tx_scp_ins_en bitfield definitions
1944 * preprocessor definitions for the bitfield "tx_scp_ins_en". 1952 * preprocessor definitions for the bitfield "tx_scp_ins_en".
@@ -1946,17 +1954,17 @@
1946 */ 1954 */
1947 1955
1948/* register address for bitfield tx_scp_ins_en */ 1956/* register address for bitfield tx_scp_ins_en */
1949#define tpb_tx_scp_ins_en_adr 0x00007900 1957#define HW_ATL_TPB_TX_SCP_INS_EN_ADR 0x00007900
1950/* bitmask for bitfield tx_scp_ins_en */ 1958/* bitmask for bitfield tx_scp_ins_en */
1951#define tpb_tx_scp_ins_en_msk 0x00000004 1959#define HW_ATL_TPB_TX_SCP_INS_EN_MSK 0x00000004
1952/* inverted bitmask for bitfield tx_scp_ins_en */ 1960/* inverted bitmask for bitfield tx_scp_ins_en */
1953#define tpb_tx_scp_ins_en_mskn 0xfffffffb 1961#define HW_ATL_TPB_TX_SCP_INS_EN_MSKN 0xfffffffb
1954/* lower bit position of bitfield tx_scp_ins_en */ 1962/* lower bit position of bitfield tx_scp_ins_en */
1955#define tpb_tx_scp_ins_en_shift 2 1963#define HW_ATL_TPB_TX_SCP_INS_EN_SHIFT 2
1956/* width of bitfield tx_scp_ins_en */ 1964/* width of bitfield tx_scp_ins_en */
1957#define tpb_tx_scp_ins_en_width 1 1965#define HW_ATL_TPB_TX_SCP_INS_EN_WIDTH 1
1958/* default value of bitfield tx_scp_ins_en */ 1966/* default value of bitfield tx_scp_ins_en */
1959#define tpb_tx_scp_ins_en_default 0x0 1967#define HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT 0x0
1960 1968
1961/* tx ipv4_chk_en bitfield definitions 1969/* tx ipv4_chk_en bitfield definitions
1962 * preprocessor definitions for the bitfield "ipv4_chk_en". 1970 * preprocessor definitions for the bitfield "ipv4_chk_en".
@@ -1964,17 +1972,17 @@
1964 */ 1972 */
1965 1973
1966/* register address for bitfield ipv4_chk_en */ 1974/* register address for bitfield ipv4_chk_en */
1967#define tpo_ipv4chk_en_adr 0x00007800 1975#define HW_ATL_TPO_IPV4CHK_EN_ADR 0x00007800
1968/* bitmask for bitfield ipv4_chk_en */ 1976/* bitmask for bitfield ipv4_chk_en */
1969#define tpo_ipv4chk_en_msk 0x00000002 1977#define HW_ATL_TPO_IPV4CHK_EN_MSK 0x00000002
1970/* inverted bitmask for bitfield ipv4_chk_en */ 1978/* inverted bitmask for bitfield ipv4_chk_en */
1971#define tpo_ipv4chk_en_mskn 0xfffffffd 1979#define HW_ATL_TPO_IPV4CHK_EN_MSKN 0xfffffffd
1972/* lower bit position of bitfield ipv4_chk_en */ 1980/* lower bit position of bitfield ipv4_chk_en */
1973#define tpo_ipv4chk_en_shift 1 1981#define HW_ATL_TPO_IPV4CHK_EN_SHIFT 1
1974/* width of bitfield ipv4_chk_en */ 1982/* width of bitfield ipv4_chk_en */
1975#define tpo_ipv4chk_en_width 1 1983#define HW_ATL_TPO_IPV4CHK_EN_WIDTH 1
1976/* default value of bitfield ipv4_chk_en */ 1984/* default value of bitfield ipv4_chk_en */
1977#define tpo_ipv4chk_en_default 0x0 1985#define HW_ATL_TPO_IPV4CHK_EN_DEFAULT 0x0
1978 1986
1979/* tx l4_chk_en bitfield definitions 1987/* tx l4_chk_en bitfield definitions
1980 * preprocessor definitions for the bitfield "l4_chk_en". 1988 * preprocessor definitions for the bitfield "l4_chk_en".
@@ -1982,17 +1990,17 @@
1982 */ 1990 */
1983 1991
1984/* register address for bitfield l4_chk_en */ 1992/* register address for bitfield l4_chk_en */
1985#define tpol4chk_en_adr 0x00007800 1993#define HW_ATL_TPOL4CHK_EN_ADR 0x00007800
1986/* bitmask for bitfield l4_chk_en */ 1994/* bitmask for bitfield l4_chk_en */
1987#define tpol4chk_en_msk 0x00000001 1995#define HW_ATL_TPOL4CHK_EN_MSK 0x00000001
1988/* inverted bitmask for bitfield l4_chk_en */ 1996/* inverted bitmask for bitfield l4_chk_en */
1989#define tpol4chk_en_mskn 0xfffffffe 1997#define HW_ATL_TPOL4CHK_EN_MSKN 0xfffffffe
1990/* lower bit position of bitfield l4_chk_en */ 1998/* lower bit position of bitfield l4_chk_en */
1991#define tpol4chk_en_shift 0 1999#define HW_ATL_TPOL4CHK_EN_SHIFT 0
1992/* width of bitfield l4_chk_en */ 2000/* width of bitfield l4_chk_en */
1993#define tpol4chk_en_width 1 2001#define HW_ATL_TPOL4CHK_EN_WIDTH 1
1994/* default value of bitfield l4_chk_en */ 2002/* default value of bitfield l4_chk_en */
1995#define tpol4chk_en_default 0x0 2003#define HW_ATL_TPOL4CHK_EN_DEFAULT 0x0
1996 2004
1997/* tx pkt_sys_loopback bitfield definitions 2005/* tx pkt_sys_loopback bitfield definitions
1998 * preprocessor definitions for the bitfield "pkt_sys_loopback". 2006 * preprocessor definitions for the bitfield "pkt_sys_loopback".
@@ -2000,17 +2008,17 @@
2000 */ 2008 */
2001 2009
2002/* register address for bitfield pkt_sys_loopback */ 2010/* register address for bitfield pkt_sys_loopback */
2003#define tpo_pkt_sys_lbk_adr 0x00007000 2011#define HW_ATL_TPO_PKT_SYS_LBK_ADR 0x00007000
2004/* bitmask for bitfield pkt_sys_loopback */ 2012/* bitmask for bitfield pkt_sys_loopback */
2005#define tpo_pkt_sys_lbk_msk 0x00000080 2013#define HW_ATL_TPO_PKT_SYS_LBK_MSK 0x00000080
2006/* inverted bitmask for bitfield pkt_sys_loopback */ 2014/* inverted bitmask for bitfield pkt_sys_loopback */
2007#define tpo_pkt_sys_lbk_mskn 0xffffff7f 2015#define HW_ATL_TPO_PKT_SYS_LBK_MSKN 0xffffff7f
2008/* lower bit position of bitfield pkt_sys_loopback */ 2016/* lower bit position of bitfield pkt_sys_loopback */
2009#define tpo_pkt_sys_lbk_shift 7 2017#define HW_ATL_TPO_PKT_SYS_LBK_SHIFT 7
2010/* width of bitfield pkt_sys_loopback */ 2018/* width of bitfield pkt_sys_loopback */
2011#define tpo_pkt_sys_lbk_width 1 2019#define HW_ATL_TPO_PKT_SYS_LBK_WIDTH 1
2012/* default value of bitfield pkt_sys_loopback */ 2020/* default value of bitfield pkt_sys_loopback */
2013#define tpo_pkt_sys_lbk_default 0x0 2021#define HW_ATL_TPO_PKT_SYS_LBK_DEFAULT 0x0
2014 2022
2015/* tx data_tc_arb_mode bitfield definitions 2023/* tx data_tc_arb_mode bitfield definitions
2016 * preprocessor definitions for the bitfield "data_tc_arb_mode". 2024 * preprocessor definitions for the bitfield "data_tc_arb_mode".
@@ -2018,17 +2026,17 @@
2018 */ 2026 */
2019 2027
2020/* register address for bitfield data_tc_arb_mode */ 2028/* register address for bitfield data_tc_arb_mode */
2021#define tps_data_tc_arb_mode_adr 0x00007100 2029#define HW_ATL_TPS_DATA_TC_ARB_MODE_ADR 0x00007100
2022/* bitmask for bitfield data_tc_arb_mode */ 2030/* bitmask for bitfield data_tc_arb_mode */
2023#define tps_data_tc_arb_mode_msk 0x00000001 2031#define HW_ATL_TPS_DATA_TC_ARB_MODE_MSK 0x00000001
2024/* inverted bitmask for bitfield data_tc_arb_mode */ 2032/* inverted bitmask for bitfield data_tc_arb_mode */
2025#define tps_data_tc_arb_mode_mskn 0xfffffffe 2033#define HW_ATL_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffe
2026/* lower bit position of bitfield data_tc_arb_mode */ 2034/* lower bit position of bitfield data_tc_arb_mode */
2027#define tps_data_tc_arb_mode_shift 0 2035#define HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT 0
2028/* width of bitfield data_tc_arb_mode */ 2036/* width of bitfield data_tc_arb_mode */
2029#define tps_data_tc_arb_mode_width 1 2037#define HW_ATL_TPS_DATA_TC_ARB_MODE_WIDTH 1
2030/* default value of bitfield data_tc_arb_mode */ 2038/* default value of bitfield data_tc_arb_mode */
2031#define tps_data_tc_arb_mode_default 0x0 2039#define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0
2032 2040
2033/* tx desc_rate_ta_rst bitfield definitions 2041/* tx desc_rate_ta_rst bitfield definitions
2034 * preprocessor definitions for the bitfield "desc_rate_ta_rst". 2042 * preprocessor definitions for the bitfield "desc_rate_ta_rst".
@@ -2036,17 +2044,17 @@
2036 */ 2044 */
2037 2045
2038/* register address for bitfield desc_rate_ta_rst */ 2046/* register address for bitfield desc_rate_ta_rst */
2039#define tps_desc_rate_ta_rst_adr 0x00007310 2047#define HW_ATL_TPS_DESC_RATE_TA_RST_ADR 0x00007310
2040/* bitmask for bitfield desc_rate_ta_rst */ 2048/* bitmask for bitfield desc_rate_ta_rst */
2041#define tps_desc_rate_ta_rst_msk 0x80000000 2049#define HW_ATL_TPS_DESC_RATE_TA_RST_MSK 0x80000000
2042/* inverted bitmask for bitfield desc_rate_ta_rst */ 2050/* inverted bitmask for bitfield desc_rate_ta_rst */
2043#define tps_desc_rate_ta_rst_mskn 0x7fffffff 2051#define HW_ATL_TPS_DESC_RATE_TA_RST_MSKN 0x7fffffff
2044/* lower bit position of bitfield desc_rate_ta_rst */ 2052/* lower bit position of bitfield desc_rate_ta_rst */
2045#define tps_desc_rate_ta_rst_shift 31 2053#define HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT 31
2046/* width of bitfield desc_rate_ta_rst */ 2054/* width of bitfield desc_rate_ta_rst */
2047#define tps_desc_rate_ta_rst_width 1 2055#define HW_ATL_TPS_DESC_RATE_TA_RST_WIDTH 1
2048/* default value of bitfield desc_rate_ta_rst */ 2056/* default value of bitfield desc_rate_ta_rst */
2049#define tps_desc_rate_ta_rst_default 0x0 2057#define HW_ATL_TPS_DESC_RATE_TA_RST_DEFAULT 0x0
2050 2058
2051/* tx desc_rate_limit[a:0] bitfield definitions 2059/* tx desc_rate_limit[a:0] bitfield definitions
2052 * preprocessor definitions for the bitfield "desc_rate_limit[a:0]". 2060 * preprocessor definitions for the bitfield "desc_rate_limit[a:0]".
@@ -2054,17 +2062,17 @@
2054 */ 2062 */
2055 2063
2056/* register address for bitfield desc_rate_limit[a:0] */ 2064/* register address for bitfield desc_rate_limit[a:0] */
2057#define tps_desc_rate_lim_adr 0x00007310 2065#define HW_ATL_TPS_DESC_RATE_LIM_ADR 0x00007310
2058/* bitmask for bitfield desc_rate_limit[a:0] */ 2066/* bitmask for bitfield desc_rate_limit[a:0] */
2059#define tps_desc_rate_lim_msk 0x000007ff 2067#define HW_ATL_TPS_DESC_RATE_LIM_MSK 0x000007ff
2060/* inverted bitmask for bitfield desc_rate_limit[a:0] */ 2068/* inverted bitmask for bitfield desc_rate_limit[a:0] */
2061#define tps_desc_rate_lim_mskn 0xfffff800 2069#define HW_ATL_TPS_DESC_RATE_LIM_MSKN 0xfffff800
2062/* lower bit position of bitfield desc_rate_limit[a:0] */ 2070/* lower bit position of bitfield desc_rate_limit[a:0] */
2063#define tps_desc_rate_lim_shift 0 2071#define HW_ATL_TPS_DESC_RATE_LIM_SHIFT 0
2064/* width of bitfield desc_rate_limit[a:0] */ 2072/* width of bitfield desc_rate_limit[a:0] */
2065#define tps_desc_rate_lim_width 11 2073#define HW_ATL_TPS_DESC_RATE_LIM_WIDTH 11
2066/* default value of bitfield desc_rate_limit[a:0] */ 2074/* default value of bitfield desc_rate_limit[a:0] */
2067#define tps_desc_rate_lim_default 0x0 2075#define HW_ATL_TPS_DESC_RATE_LIM_DEFAULT 0x0
2068 2076
2069/* tx desc_tc_arb_mode[1:0] bitfield definitions 2077/* tx desc_tc_arb_mode[1:0] bitfield definitions
2070 * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]". 2078 * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]".
@@ -2072,17 +2080,17 @@
2072 */ 2080 */
2073 2081
2074/* register address for bitfield desc_tc_arb_mode[1:0] */ 2082/* register address for bitfield desc_tc_arb_mode[1:0] */
2075#define tps_desc_tc_arb_mode_adr 0x00007200 2083#define HW_ATL_TPS_DESC_TC_ARB_MODE_ADR 0x00007200
2076/* bitmask for bitfield desc_tc_arb_mode[1:0] */ 2084/* bitmask for bitfield desc_tc_arb_mode[1:0] */
2077#define tps_desc_tc_arb_mode_msk 0x00000003 2085#define HW_ATL_TPS_DESC_TC_ARB_MODE_MSK 0x00000003
2078/* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */ 2086/* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */
2079#define tps_desc_tc_arb_mode_mskn 0xfffffffc 2087#define HW_ATL_TPS_DESC_TC_ARB_MODE_MSKN 0xfffffffc
2080/* lower bit position of bitfield desc_tc_arb_mode[1:0] */ 2088/* lower bit position of bitfield desc_tc_arb_mode[1:0] */
2081#define tps_desc_tc_arb_mode_shift 0 2089#define HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT 0
2082/* width of bitfield desc_tc_arb_mode[1:0] */ 2090/* width of bitfield desc_tc_arb_mode[1:0] */
2083#define tps_desc_tc_arb_mode_width 2 2091#define HW_ATL_TPS_DESC_TC_ARB_MODE_WIDTH 2
2084/* default value of bitfield desc_tc_arb_mode[1:0] */ 2092/* default value of bitfield desc_tc_arb_mode[1:0] */
2085#define tps_desc_tc_arb_mode_default 0x0 2093#define HW_ATL_TPS_DESC_TC_ARB_MODE_DEFAULT 0x0
2086 2094
2087/* tx desc_tc{t}_credit_max[b:0] bitfield definitions 2095/* tx desc_tc{t}_credit_max[b:0] bitfield definitions
2088 * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]". 2096 * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]".
@@ -2091,17 +2099,17 @@
2091 */ 2099 */
2092 2100
2093/* register address for bitfield desc_tc{t}_credit_max[b:0] */ 2101/* register address for bitfield desc_tc{t}_credit_max[b:0] */
2094#define tps_desc_tctcredit_max_adr(tc) (0x00007210 + (tc) * 0x4) 2102#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc) (0x00007210 + (tc) * 0x4)
2095/* bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2103/* bitmask for bitfield desc_tc{t}_credit_max[b:0] */
2096#define tps_desc_tctcredit_max_msk 0x0fff0000 2104#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK 0x0fff0000
2097/* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2105/* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */
2098#define tps_desc_tctcredit_max_mskn 0xf000ffff 2106#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSKN 0xf000ffff
2099/* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */ 2107/* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */
2100#define tps_desc_tctcredit_max_shift 16 2108#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT 16
2101/* width of bitfield desc_tc{t}_credit_max[b:0] */ 2109/* width of bitfield desc_tc{t}_credit_max[b:0] */
2102#define tps_desc_tctcredit_max_width 12 2110#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_WIDTH 12
2103/* default value of bitfield desc_tc{t}_credit_max[b:0] */ 2111/* default value of bitfield desc_tc{t}_credit_max[b:0] */
2104#define tps_desc_tctcredit_max_default 0x0 2112#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_DEFAULT 0x0
2105 2113
2106/* tx desc_tc{t}_weight[8:0] bitfield definitions 2114/* tx desc_tc{t}_weight[8:0] bitfield definitions
2107 * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]". 2115 * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]".
@@ -2110,17 +2118,17 @@
2110 */ 2118 */
2111 2119
2112/* register address for bitfield desc_tc{t}_weight[8:0] */ 2120/* register address for bitfield desc_tc{t}_weight[8:0] */
2113#define tps_desc_tctweight_adr(tc) (0x00007210 + (tc) * 0x4) 2121#define HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc) (0x00007210 + (tc) * 0x4)
2114/* bitmask for bitfield desc_tc{t}_weight[8:0] */ 2122/* bitmask for bitfield desc_tc{t}_weight[8:0] */
2115#define tps_desc_tctweight_msk 0x000001ff 2123#define HW_ATL_TPS_DESC_TCTWEIGHT_MSK 0x000001ff
2116/* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */ 2124/* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */
2117#define tps_desc_tctweight_mskn 0xfffffe00 2125#define HW_ATL_TPS_DESC_TCTWEIGHT_MSKN 0xfffffe00
2118/* lower bit position of bitfield desc_tc{t}_weight[8:0] */ 2126/* lower bit position of bitfield desc_tc{t}_weight[8:0] */
2119#define tps_desc_tctweight_shift 0 2127#define HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT 0
2120/* width of bitfield desc_tc{t}_weight[8:0] */ 2128/* width of bitfield desc_tc{t}_weight[8:0] */
2121#define tps_desc_tctweight_width 9 2129#define HW_ATL_TPS_DESC_TCTWEIGHT_WIDTH 9
2122/* default value of bitfield desc_tc{t}_weight[8:0] */ 2130/* default value of bitfield desc_tc{t}_weight[8:0] */
2123#define tps_desc_tctweight_default 0x0 2131#define HW_ATL_TPS_DESC_TCTWEIGHT_DEFAULT 0x0
2124 2132
2125/* tx desc_vm_arb_mode bitfield definitions 2133/* tx desc_vm_arb_mode bitfield definitions
2126 * preprocessor definitions for the bitfield "desc_vm_arb_mode". 2134 * preprocessor definitions for the bitfield "desc_vm_arb_mode".
@@ -2128,17 +2136,17 @@
2128 */ 2136 */
2129 2137
2130/* register address for bitfield desc_vm_arb_mode */ 2138/* register address for bitfield desc_vm_arb_mode */
2131#define tps_desc_vm_arb_mode_adr 0x00007300 2139#define HW_ATL_TPS_DESC_VM_ARB_MODE_ADR 0x00007300
2132/* bitmask for bitfield desc_vm_arb_mode */ 2140/* bitmask for bitfield desc_vm_arb_mode */
2133#define tps_desc_vm_arb_mode_msk 0x00000001 2141#define HW_ATL_TPS_DESC_VM_ARB_MODE_MSK 0x00000001
2134/* inverted bitmask for bitfield desc_vm_arb_mode */ 2142/* inverted bitmask for bitfield desc_vm_arb_mode */
2135#define tps_desc_vm_arb_mode_mskn 0xfffffffe 2143#define HW_ATL_TPS_DESC_VM_ARB_MODE_MSKN 0xfffffffe
2136/* lower bit position of bitfield desc_vm_arb_mode */ 2144/* lower bit position of bitfield desc_vm_arb_mode */
2137#define tps_desc_vm_arb_mode_shift 0 2145#define HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT 0
2138/* width of bitfield desc_vm_arb_mode */ 2146/* width of bitfield desc_vm_arb_mode */
2139#define tps_desc_vm_arb_mode_width 1 2147#define HW_ATL_TPS_DESC_VM_ARB_MODE_WIDTH 1
2140/* default value of bitfield desc_vm_arb_mode */ 2148/* default value of bitfield desc_vm_arb_mode */
2141#define tps_desc_vm_arb_mode_default 0x0 2149#define HW_ATL_TPS_DESC_VM_ARB_MODE_DEFAULT 0x0
2142 2150
2143/* tx data_tc{t}_credit_max[b:0] bitfield definitions 2151/* tx data_tc{t}_credit_max[b:0] bitfield definitions
2144 * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]". 2152 * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]".
@@ -2147,17 +2155,17 @@
2147 */ 2155 */
2148 2156
2149/* register address for bitfield data_tc{t}_credit_max[b:0] */ 2157/* register address for bitfield data_tc{t}_credit_max[b:0] */
2150#define tps_data_tctcredit_max_adr(tc) (0x00007110 + (tc) * 0x4) 2158#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4)
2151/* bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2159/* bitmask for bitfield data_tc{t}_credit_max[b:0] */
2152#define tps_data_tctcredit_max_msk 0x0fff0000 2160#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK 0x0fff0000
2153/* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2161/* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */
2154#define tps_data_tctcredit_max_mskn 0xf000ffff 2162#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSKN 0xf000ffff
2155/* lower bit position of bitfield data_tc{t}_credit_max[b:0] */ 2163/* lower bit position of bitfield data_tc{t}_credit_max[b:0] */
2156#define tps_data_tctcredit_max_shift 16 2164#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT 16
2157/* width of bitfield data_tc{t}_credit_max[b:0] */ 2165/* width of bitfield data_tc{t}_credit_max[b:0] */
2158#define tps_data_tctcredit_max_width 12 2166#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_WIDTH 12
2159/* default value of bitfield data_tc{t}_credit_max[b:0] */ 2167/* default value of bitfield data_tc{t}_credit_max[b:0] */
2160#define tps_data_tctcredit_max_default 0x0 2168#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0
2161 2169
2162/* tx data_tc{t}_weight[8:0] bitfield definitions 2170/* tx data_tc{t}_weight[8:0] bitfield definitions
2163 * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]". 2171 * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]".
@@ -2166,17 +2174,17 @@
2166 */ 2174 */
2167 2175
2168/* register address for bitfield data_tc{t}_weight[8:0] */ 2176/* register address for bitfield data_tc{t}_weight[8:0] */
2169#define tps_data_tctweight_adr(tc) (0x00007110 + (tc) * 0x4) 2177#define HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4)
2170/* bitmask for bitfield data_tc{t}_weight[8:0] */ 2178/* bitmask for bitfield data_tc{t}_weight[8:0] */
2171#define tps_data_tctweight_msk 0x000001ff 2179#define HW_ATL_TPS_DATA_TCTWEIGHT_MSK 0x000001ff
2172/* inverted bitmask for bitfield data_tc{t}_weight[8:0] */ 2180/* inverted bitmask for bitfield data_tc{t}_weight[8:0] */
2173#define tps_data_tctweight_mskn 0xfffffe00 2181#define HW_ATL_TPS_DATA_TCTWEIGHT_MSKN 0xfffffe00
2174/* lower bit position of bitfield data_tc{t}_weight[8:0] */ 2182/* lower bit position of bitfield data_tc{t}_weight[8:0] */
2175#define tps_data_tctweight_shift 0 2183#define HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT 0
2176/* width of bitfield data_tc{t}_weight[8:0] */ 2184/* width of bitfield data_tc{t}_weight[8:0] */
2177#define tps_data_tctweight_width 9 2185#define HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH 9
2178/* default value of bitfield data_tc{t}_weight[8:0] */ 2186/* default value of bitfield data_tc{t}_weight[8:0] */
2179#define tps_data_tctweight_default 0x0 2187#define HW_ATL_TPS_DATA_TCTWEIGHT_DEFAULT 0x0
2180 2188
2181/* tx reg_res_dsbl bitfield definitions 2189/* tx reg_res_dsbl bitfield definitions
2182 * preprocessor definitions for the bitfield "reg_res_dsbl". 2190 * preprocessor definitions for the bitfield "reg_res_dsbl".
@@ -2184,17 +2192,17 @@
2184 */ 2192 */
2185 2193
2186/* register address for bitfield reg_res_dsbl */ 2194/* register address for bitfield reg_res_dsbl */
2187#define tx_reg_res_dsbl_adr 0x00007000 2195#define HW_ATL_TX_REG_RES_DSBL_ADR 0x00007000
2188/* bitmask for bitfield reg_res_dsbl */ 2196/* bitmask for bitfield reg_res_dsbl */
2189#define tx_reg_res_dsbl_msk 0x20000000 2197#define HW_ATL_TX_REG_RES_DSBL_MSK 0x20000000
2190/* inverted bitmask for bitfield reg_res_dsbl */ 2198/* inverted bitmask for bitfield reg_res_dsbl */
2191#define tx_reg_res_dsbl_mskn 0xdfffffff 2199#define HW_ATL_TX_REG_RES_DSBL_MSKN 0xdfffffff
2192/* lower bit position of bitfield reg_res_dsbl */ 2200/* lower bit position of bitfield reg_res_dsbl */
2193#define tx_reg_res_dsbl_shift 29 2201#define HW_ATL_TX_REG_RES_DSBL_SHIFT 29
2194/* width of bitfield reg_res_dsbl */ 2202/* width of bitfield reg_res_dsbl */
2195#define tx_reg_res_dsbl_width 1 2203#define HW_ATL_TX_REG_RES_DSBL_WIDTH 1
2196/* default value of bitfield reg_res_dsbl */ 2204/* default value of bitfield reg_res_dsbl */
2197#define tx_reg_res_dsbl_default 0x1 2205#define HW_ATL_TX_REG_RES_DSBL_DEFAULT 0x1
2198 2206
2199/* mac_phy register access busy bitfield definitions 2207/* mac_phy register access busy bitfield definitions
2200 * preprocessor definitions for the bitfield "register access busy". 2208 * preprocessor definitions for the bitfield "register access busy".
@@ -2202,15 +2210,15 @@
2202 */ 2210 */
2203 2211
2204/* register address for bitfield register access busy */ 2212/* register address for bitfield register access busy */
2205#define msm_reg_access_busy_adr 0x00004400 2213#define HW_ATL_MSM_REG_ACCESS_BUSY_ADR 0x00004400
2206/* bitmask for bitfield register access busy */ 2214/* bitmask for bitfield register access busy */
2207#define msm_reg_access_busy_msk 0x00001000 2215#define HW_ATL_MSM_REG_ACCESS_BUSY_MSK 0x00001000
2208/* inverted bitmask for bitfield register access busy */ 2216/* inverted bitmask for bitfield register access busy */
2209#define msm_reg_access_busy_mskn 0xffffefff 2217#define HW_ATL_MSM_REG_ACCESS_BUSY_MSKN 0xffffefff
2210/* lower bit position of bitfield register access busy */ 2218/* lower bit position of bitfield register access busy */
2211#define msm_reg_access_busy_shift 12 2219#define HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT 12
2212/* width of bitfield register access busy */ 2220/* width of bitfield register access busy */
2213#define msm_reg_access_busy_width 1 2221#define HW_ATL_MSM_REG_ACCESS_BUSY_WIDTH 1
2214 2222
2215/* mac_phy msm register address[7:0] bitfield definitions 2223/* mac_phy msm register address[7:0] bitfield definitions
2216 * preprocessor definitions for the bitfield "msm register address[7:0]". 2224 * preprocessor definitions for the bitfield "msm register address[7:0]".
@@ -2218,17 +2226,17 @@
2218 */ 2226 */
2219 2227
2220/* register address for bitfield msm register address[7:0] */ 2228/* register address for bitfield msm register address[7:0] */
2221#define msm_reg_addr_adr 0x00004400 2229#define HW_ATL_MSM_REG_ADDR_ADR 0x00004400
2222/* bitmask for bitfield msm register address[7:0] */ 2230/* bitmask for bitfield msm register address[7:0] */
2223#define msm_reg_addr_msk 0x000000ff 2231#define HW_ATL_MSM_REG_ADDR_MSK 0x000000ff
2224/* inverted bitmask for bitfield msm register address[7:0] */ 2232/* inverted bitmask for bitfield msm register address[7:0] */
2225#define msm_reg_addr_mskn 0xffffff00 2233#define HW_ATL_MSM_REG_ADDR_MSKN 0xffffff00
2226/* lower bit position of bitfield msm register address[7:0] */ 2234/* lower bit position of bitfield msm register address[7:0] */
2227#define msm_reg_addr_shift 0 2235#define HW_ATL_MSM_REG_ADDR_SHIFT 0
2228/* width of bitfield msm register address[7:0] */ 2236/* width of bitfield msm register address[7:0] */
2229#define msm_reg_addr_width 8 2237#define HW_ATL_MSM_REG_ADDR_WIDTH 8
2230/* default value of bitfield msm register address[7:0] */ 2238/* default value of bitfield msm register address[7:0] */
2231#define msm_reg_addr_default 0x0 2239#define HW_ATL_MSM_REG_ADDR_DEFAULT 0x0
2232 2240
2233/* mac_phy register read strobe bitfield definitions 2241/* mac_phy register read strobe bitfield definitions
2234 * preprocessor definitions for the bitfield "register read strobe". 2242 * preprocessor definitions for the bitfield "register read strobe".
@@ -2236,17 +2244,17 @@
2236 */ 2244 */
2237 2245
2238/* register address for bitfield register read strobe */ 2246/* register address for bitfield register read strobe */
2239#define msm_reg_rd_strobe_adr 0x00004400 2247#define HW_ATL_MSM_REG_RD_STROBE_ADR 0x00004400
2240/* bitmask for bitfield register read strobe */ 2248/* bitmask for bitfield register read strobe */
2241#define msm_reg_rd_strobe_msk 0x00000200 2249#define HW_ATL_MSM_REG_RD_STROBE_MSK 0x00000200
2242/* inverted bitmask for bitfield register read strobe */ 2250/* inverted bitmask for bitfield register read strobe */
2243#define msm_reg_rd_strobe_mskn 0xfffffdff 2251#define HW_ATL_MSM_REG_RD_STROBE_MSKN 0xfffffdff
2244/* lower bit position of bitfield register read strobe */ 2252/* lower bit position of bitfield register read strobe */
2245#define msm_reg_rd_strobe_shift 9 2253#define HW_ATL_MSM_REG_RD_STROBE_SHIFT 9
2246/* width of bitfield register read strobe */ 2254/* width of bitfield register read strobe */
2247#define msm_reg_rd_strobe_width 1 2255#define HW_ATL_MSM_REG_RD_STROBE_WIDTH 1
2248/* default value of bitfield register read strobe */ 2256/* default value of bitfield register read strobe */
2249#define msm_reg_rd_strobe_default 0x0 2257#define HW_ATL_MSM_REG_RD_STROBE_DEFAULT 0x0
2250 2258
2251/* mac_phy msm register read data[31:0] bitfield definitions 2259/* mac_phy msm register read data[31:0] bitfield definitions
2252 * preprocessor definitions for the bitfield "msm register read data[31:0]". 2260 * preprocessor definitions for the bitfield "msm register read data[31:0]".
@@ -2254,15 +2262,15 @@
2254 */ 2262 */
2255 2263
2256/* register address for bitfield msm register read data[31:0] */ 2264/* register address for bitfield msm register read data[31:0] */
2257#define msm_reg_rd_data_adr 0x00004408 2265#define HW_ATL_MSM_REG_RD_DATA_ADR 0x00004408
2258/* bitmask for bitfield msm register read data[31:0] */ 2266/* bitmask for bitfield msm register read data[31:0] */
2259#define msm_reg_rd_data_msk 0xffffffff 2267#define HW_ATL_MSM_REG_RD_DATA_MSK 0xffffffff
2260/* inverted bitmask for bitfield msm register read data[31:0] */ 2268/* inverted bitmask for bitfield msm register read data[31:0] */
2261#define msm_reg_rd_data_mskn 0x00000000 2269#define HW_ATL_MSM_REG_RD_DATA_MSKN 0x00000000
2262/* lower bit position of bitfield msm register read data[31:0] */ 2270/* lower bit position of bitfield msm register read data[31:0] */
2263#define msm_reg_rd_data_shift 0 2271#define HW_ATL_MSM_REG_RD_DATA_SHIFT 0
2264/* width of bitfield msm register read data[31:0] */ 2272/* width of bitfield msm register read data[31:0] */
2265#define msm_reg_rd_data_width 32 2273#define HW_ATL_MSM_REG_RD_DATA_WIDTH 32
2266 2274
2267/* mac_phy msm register write data[31:0] bitfield definitions 2275/* mac_phy msm register write data[31:0] bitfield definitions
2268 * preprocessor definitions for the bitfield "msm register write data[31:0]". 2276 * preprocessor definitions for the bitfield "msm register write data[31:0]".
@@ -2270,17 +2278,17 @@
2270 */ 2278 */
2271 2279
2272/* register address for bitfield msm register write data[31:0] */ 2280/* register address for bitfield msm register write data[31:0] */
2273#define msm_reg_wr_data_adr 0x00004404 2281#define HW_ATL_MSM_REG_WR_DATA_ADR 0x00004404
2274/* bitmask for bitfield msm register write data[31:0] */ 2282/* bitmask for bitfield msm register write data[31:0] */
2275#define msm_reg_wr_data_msk 0xffffffff 2283#define HW_ATL_MSM_REG_WR_DATA_MSK 0xffffffff
2276/* inverted bitmask for bitfield msm register write data[31:0] */ 2284/* inverted bitmask for bitfield msm register write data[31:0] */
2277#define msm_reg_wr_data_mskn 0x00000000 2285#define HW_ATL_MSM_REG_WR_DATA_MSKN 0x00000000
2278/* lower bit position of bitfield msm register write data[31:0] */ 2286/* lower bit position of bitfield msm register write data[31:0] */
2279#define msm_reg_wr_data_shift 0 2287#define HW_ATL_MSM_REG_WR_DATA_SHIFT 0
2280/* width of bitfield msm register write data[31:0] */ 2288/* width of bitfield msm register write data[31:0] */
2281#define msm_reg_wr_data_width 32 2289#define HW_ATL_MSM_REG_WR_DATA_WIDTH 32
2282/* default value of bitfield msm register write data[31:0] */ 2290/* default value of bitfield msm register write data[31:0] */
2283#define msm_reg_wr_data_default 0x0 2291#define HW_ATL_MSM_REG_WR_DATA_DEFAULT 0x0
2284 2292
2285/* mac_phy register write strobe bitfield definitions 2293/* mac_phy register write strobe bitfield definitions
2286 * preprocessor definitions for the bitfield "register write strobe". 2294 * preprocessor definitions for the bitfield "register write strobe".
@@ -2288,17 +2296,17 @@
2288 */ 2296 */
2289 2297
2290/* register address for bitfield register write strobe */ 2298/* register address for bitfield register write strobe */
2291#define msm_reg_wr_strobe_adr 0x00004400 2299#define HW_ATL_MSM_REG_WR_STROBE_ADR 0x00004400
2292/* bitmask for bitfield register write strobe */ 2300/* bitmask for bitfield register write strobe */
2293#define msm_reg_wr_strobe_msk 0x00000100 2301#define HW_ATL_MSM_REG_WR_STROBE_MSK 0x00000100
2294/* inverted bitmask for bitfield register write strobe */ 2302/* inverted bitmask for bitfield register write strobe */
2295#define msm_reg_wr_strobe_mskn 0xfffffeff 2303#define HW_ATL_MSM_REG_WR_STROBE_MSKN 0xfffffeff
2296/* lower bit position of bitfield register write strobe */ 2304/* lower bit position of bitfield register write strobe */
2297#define msm_reg_wr_strobe_shift 8 2305#define HW_ATL_MSM_REG_WR_STROBE_SHIFT 8
2298/* width of bitfield register write strobe */ 2306/* width of bitfield register write strobe */
2299#define msm_reg_wr_strobe_width 1 2307#define HW_ATL_MSM_REG_WR_STROBE_WIDTH 1
2300/* default value of bitfield register write strobe */ 2308/* default value of bitfield register write strobe */
2301#define msm_reg_wr_strobe_default 0x0 2309#define HW_ATL_MSM_REG_WR_STROBE_DEFAULT 0x0
2302 2310
2303/* mif soft reset bitfield definitions 2311/* mif soft reset bitfield definitions
2304 * preprocessor definitions for the bitfield "soft reset". 2312 * preprocessor definitions for the bitfield "soft reset".
@@ -2306,17 +2314,17 @@
2306 */ 2314 */
2307 2315
2308/* register address for bitfield soft reset */ 2316/* register address for bitfield soft reset */
2309#define glb_soft_res_adr 0x00000000 2317#define HW_ATL_GLB_SOFT_RES_ADR 0x00000000
2310/* bitmask for bitfield soft reset */ 2318/* bitmask for bitfield soft reset */
2311#define glb_soft_res_msk 0x00008000 2319#define HW_ATL_GLB_SOFT_RES_MSK 0x00008000
2312/* inverted bitmask for bitfield soft reset */ 2320/* inverted bitmask for bitfield soft reset */
2313#define glb_soft_res_mskn 0xffff7fff 2321#define HW_ATL_GLB_SOFT_RES_MSKN 0xffff7fff
2314/* lower bit position of bitfield soft reset */ 2322/* lower bit position of bitfield soft reset */
2315#define glb_soft_res_shift 15 2323#define HW_ATL_GLB_SOFT_RES_SHIFT 15
2316/* width of bitfield soft reset */ 2324/* width of bitfield soft reset */
2317#define glb_soft_res_width 1 2325#define HW_ATL_GLB_SOFT_RES_WIDTH 1
2318/* default value of bitfield soft reset */ 2326/* default value of bitfield soft reset */
2319#define glb_soft_res_default 0x0 2327#define HW_ATL_GLB_SOFT_RES_DEFAULT 0x0
2320 2328
2321/* mif register reset disable bitfield definitions 2329/* mif register reset disable bitfield definitions
2322 * preprocessor definitions for the bitfield "register reset disable". 2330 * preprocessor definitions for the bitfield "register reset disable".
@@ -2324,27 +2332,27 @@
2324 */ 2332 */
2325 2333
2326/* register address for bitfield register reset disable */ 2334/* register address for bitfield register reset disable */
2327#define glb_reg_res_dis_adr 0x00000000 2335#define HW_ATL_GLB_REG_RES_DIS_ADR 0x00000000
2328/* bitmask for bitfield register reset disable */ 2336/* bitmask for bitfield register reset disable */
2329#define glb_reg_res_dis_msk 0x00004000 2337#define HW_ATL_GLB_REG_RES_DIS_MSK 0x00004000
2330/* inverted bitmask for bitfield register reset disable */ 2338/* inverted bitmask for bitfield register reset disable */
2331#define glb_reg_res_dis_mskn 0xffffbfff 2339#define HW_ATL_GLB_REG_RES_DIS_MSKN 0xffffbfff
2332/* lower bit position of bitfield register reset disable */ 2340/* lower bit position of bitfield register reset disable */
2333#define glb_reg_res_dis_shift 14 2341#define HW_ATL_GLB_REG_RES_DIS_SHIFT 14
2334/* width of bitfield register reset disable */ 2342/* width of bitfield register reset disable */
2335#define glb_reg_res_dis_width 1 2343#define HW_ATL_GLB_REG_RES_DIS_WIDTH 1
2336/* default value of bitfield register reset disable */ 2344/* default value of bitfield register reset disable */
2337#define glb_reg_res_dis_default 0x1 2345#define HW_ATL_GLB_REG_RES_DIS_DEFAULT 0x1
2338 2346
2339/* tx dma debug control definitions */ 2347/* tx dma debug control definitions */
2340#define tx_dma_debug_ctl_adr 0x00008920u 2348#define HW_ATL_TX_DMA_DEBUG_CTL_ADR 0x00008920u
2341 2349
2342/* tx dma descriptor base address msw definitions */ 2350/* tx dma descriptor base address msw definitions */
2343#define tx_dma_desc_base_addrmsw_adr(descriptor) \ 2351#define HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \
2344 (0x00007c04u + (descriptor) * 0x40) 2352 (0x00007c04u + (descriptor) * 0x40)
2345 2353
2346/* tx dma total request limit */ 2354/* tx dma total request limit */
2347#define tx_dma_total_req_limit_adr 0x00007b20u 2355#define HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR 0x00007b20u
2348 2356
2349/* tx interrupt moderation control register definitions 2357/* tx interrupt moderation control register definitions
2350 * Preprocessor definitions for TX Interrupt Moderation Control Register 2358 * Preprocessor definitions for TX Interrupt Moderation Control Register
@@ -2352,7 +2360,7 @@
2352 * Parameter: queue {Q} | stride size 0x4 | range [0, 31] 2360 * Parameter: queue {Q} | stride size 0x4 | range [0, 31]
2353 */ 2361 */
2354 2362
2355#define tx_intr_moderation_ctl_adr(queue) (0x00008980u + (queue) * 0x4) 2363#define HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue) (0x00008980u + (queue) * 0x4)
2356 2364
2357/* pcie reg_res_dsbl bitfield definitions 2365/* pcie reg_res_dsbl bitfield definitions
2358 * preprocessor definitions for the bitfield "reg_res_dsbl". 2366 * preprocessor definitions for the bitfield "reg_res_dsbl".
@@ -2360,22 +2368,23 @@
2360 */ 2368 */
2361 2369
2362/* register address for bitfield reg_res_dsbl */ 2370/* register address for bitfield reg_res_dsbl */
2363#define pci_reg_res_dsbl_adr 0x00001000 2371#define HW_ATL_PCI_REG_RES_DSBL_ADR 0x00001000
2364/* bitmask for bitfield reg_res_dsbl */ 2372/* bitmask for bitfield reg_res_dsbl */
2365#define pci_reg_res_dsbl_msk 0x20000000 2373#define HW_ATL_PCI_REG_RES_DSBL_MSK 0x20000000
2366/* inverted bitmask for bitfield reg_res_dsbl */ 2374/* inverted bitmask for bitfield reg_res_dsbl */
2367#define pci_reg_res_dsbl_mskn 0xdfffffff 2375#define HW_ATL_PCI_REG_RES_DSBL_MSKN 0xdfffffff
2368/* lower bit position of bitfield reg_res_dsbl */ 2376/* lower bit position of bitfield reg_res_dsbl */
2369#define pci_reg_res_dsbl_shift 29 2377#define HW_ATL_PCI_REG_RES_DSBL_SHIFT 29
2370/* width of bitfield reg_res_dsbl */ 2378/* width of bitfield reg_res_dsbl */
2371#define pci_reg_res_dsbl_width 1 2379#define HW_ATL_PCI_REG_RES_DSBL_WIDTH 1
2372/* default value of bitfield reg_res_dsbl */ 2380/* default value of bitfield reg_res_dsbl */
2373#define pci_reg_res_dsbl_default 0x1 2381#define HW_ATL_PCI_REG_RES_DSBL_DEFAULT 0x1
2374 2382
2375/* PCI core control register */ 2383/* PCI core control register */
2376#define pci_reg_control6_adr 0x1014u 2384#define HW_ATL_PCI_REG_CONTROL6_ADR 0x1014u
2377 2385
2378/* global microprocessor scratch pad definitions */ 2386/* global microprocessor scratch pad definitions */
2379#define glb_cpu_scratch_scp_adr(scratch_scp) (0x00000300u + (scratch_scp) * 0x4) 2387#define HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp) \
2388 (0x00000300u + (scratch_scp) * 0x4)
2380 2389
2381#endif /* HW_ATL_LLH_INTERNAL_H */ 2390#endif /* HW_ATL_LLH_INTERNAL_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
index f2ce12ed4218..9c7e9161b4db 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
@@ -11,11 +11,9 @@
11 * abstraction layer. 11 * abstraction layer.
12 */ 12 */
13 13
14#include "../aq_hw.h" 14#include "../aq_nic.h"
15#include "../aq_hw_utils.h" 15#include "../aq_hw_utils.h"
16#include "../aq_pci_func.h" 16#include "../aq_pci_func.h"
17#include "../aq_ring.h"
18#include "../aq_vec.h"
19#include "hw_atl_utils.h" 17#include "hw_atl_utils.h"
20#include "hw_atl_llh.h" 18#include "hw_atl_llh.h"
21 19
@@ -37,15 +35,15 @@ static int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
37{ 35{
38 int err = 0; 36 int err = 0;
39 37
40 AQ_HW_WAIT_FOR(reg_glb_cpu_sem_get(self, 38 AQ_HW_WAIT_FOR(hw_atl_reg_glb_cpu_sem_get(self,
41 HW_ATL_FW_SM_RAM) == 1U, 39 HW_ATL_FW_SM_RAM) == 1U,
42 1U, 10000U); 40 1U, 10000U);
43 41
44 if (err < 0) { 42 if (err < 0) {
45 bool is_locked; 43 bool is_locked;
46 44
47 reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM); 45 hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);
48 is_locked = reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM); 46 is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
49 if (!is_locked) { 47 if (!is_locked) {
50 err = -ETIME; 48 err = -ETIME;
51 goto err_exit; 49 goto err_exit;
@@ -66,7 +64,7 @@ static int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
66 *(p++) = aq_hw_read_reg(self, 0x0000020CU); 64 *(p++) = aq_hw_read_reg(self, 0x0000020CU);
67 } 65 }
68 66
69 reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM); 67 hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);
70 68
71err_exit: 69err_exit:
72 return err; 70 return err;
@@ -78,7 +76,7 @@ static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
78 int err = 0; 76 int err = 0;
79 bool is_locked; 77 bool is_locked;
80 78
81 is_locked = reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM); 79 is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
82 if (!is_locked) { 80 if (!is_locked) {
83 err = -ETIME; 81 err = -ETIME;
84 goto err_exit; 82 goto err_exit;
@@ -97,7 +95,7 @@ static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
97 } 95 }
98 } 96 }
99 97
100 reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM); 98 hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);
101 99
102err_exit: 100err_exit:
103 return err; 101 return err;
@@ -119,7 +117,7 @@ err_exit:
119} 117}
120 118
121static int hw_atl_utils_init_ucp(struct aq_hw_s *self, 119static int hw_atl_utils_init_ucp(struct aq_hw_s *self,
122 struct aq_hw_caps_s *aq_hw_caps) 120 const struct aq_hw_caps_s *aq_hw_caps)
123{ 121{
124 int err = 0; 122 int err = 0;
125 123
@@ -133,10 +131,10 @@ static int hw_atl_utils_init_ucp(struct aq_hw_s *self,
133 aq_hw_write_reg(self, HW_ATL_UCP_0X370_REG, ucp_0x370); 131 aq_hw_write_reg(self, HW_ATL_UCP_0X370_REG, ucp_0x370);
134 } 132 }
135 133
136 reg_glb_cpu_scratch_scp_set(self, 0x00000000U, 25U); 134 hw_atl_reg_glb_cpu_scratch_scp_set(self, 0x00000000U, 25U);
137 135
138 /* check 10 times by 1ms */ 136 /* check 10 times by 1ms */
139 AQ_HW_WAIT_FOR(0U != (PHAL_ATLANTIC_A0->mbox_addr = 137 AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
140 aq_hw_read_reg(self, 0x360U)), 1000U, 10U); 138 aq_hw_read_reg(self, 0x360U)), 1000U, 10U);
141 139
142 err = hw_atl_utils_ver_match(aq_hw_caps->fw_ver_expected, 140 err = hw_atl_utils_ver_match(aq_hw_caps->fw_ver_expected,
@@ -174,14 +172,14 @@ static int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size)
174 err = -1; 172 err = -1;
175 goto err_exit; 173 goto err_exit;
176 } 174 }
177 err = hw_atl_utils_fw_upload_dwords(self, PHAL_ATLANTIC->rpc_addr, 175 err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr,
178 (u32 *)(void *)&PHAL_ATLANTIC->rpc, 176 (u32 *)(void *)&self->rpc,
179 (rpc_size + sizeof(u32) - 177 (rpc_size + sizeof(u32) -
180 sizeof(u8)) / sizeof(u32)); 178 sizeof(u8)) / sizeof(u32));
181 if (err < 0) 179 if (err < 0)
182 goto err_exit; 180 goto err_exit;
183 181
184 sw.tid = 0xFFFFU & (++PHAL_ATLANTIC->rpc_tid); 182 sw.tid = 0xFFFFU & (++self->rpc_tid);
185 sw.len = (u16)rpc_size; 183 sw.len = (u16)rpc_size;
186 aq_hw_write_reg(self, HW_ATL_RPC_CONTROL_ADR, sw.val); 184 aq_hw_write_reg(self, HW_ATL_RPC_CONTROL_ADR, sw.val);
187 185
@@ -199,7 +197,7 @@ static int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
199 do { 197 do {
200 sw.val = aq_hw_read_reg(self, HW_ATL_RPC_CONTROL_ADR); 198 sw.val = aq_hw_read_reg(self, HW_ATL_RPC_CONTROL_ADR);
201 199
202 PHAL_ATLANTIC->rpc_tid = sw.tid; 200 self->rpc_tid = sw.tid;
203 201
204 AQ_HW_WAIT_FOR(sw.tid == 202 AQ_HW_WAIT_FOR(sw.tid ==
205 (fw.val = 203 (fw.val =
@@ -221,9 +219,9 @@ static int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
221 if (fw.len) { 219 if (fw.len) {
222 err = 220 err =
223 hw_atl_utils_fw_downld_dwords(self, 221 hw_atl_utils_fw_downld_dwords(self,
224 PHAL_ATLANTIC->rpc_addr, 222 self->rpc_addr,
225 (u32 *)(void *) 223 (u32 *)(void *)
226 &PHAL_ATLANTIC->rpc, 224 &self->rpc,
227 (fw.len + sizeof(u32) - 225 (fw.len + sizeof(u32) -
228 sizeof(u8)) / 226 sizeof(u8)) /
229 sizeof(u32)); 227 sizeof(u32));
@@ -231,19 +229,18 @@ static int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
231 goto err_exit; 229 goto err_exit;
232 } 230 }
233 231
234 *rpc = &PHAL_ATLANTIC->rpc; 232 *rpc = &self->rpc;
235 } 233 }
236 234
237err_exit: 235err_exit:
238 return err; 236 return err;
239} 237}
240 238
241static int hw_atl_utils_mpi_create(struct aq_hw_s *self, 239static int hw_atl_utils_mpi_create(struct aq_hw_s *self)
242 struct aq_hw_caps_s *aq_hw_caps)
243{ 240{
244 int err = 0; 241 int err = 0;
245 242
246 err = hw_atl_utils_init_ucp(self, aq_hw_caps); 243 err = hw_atl_utils_init_ucp(self, self->aq_nic_cfg->aq_hw_caps);
247 if (err < 0) 244 if (err < 0)
248 goto err_exit; 245 goto err_exit;
249 246
@@ -259,7 +256,7 @@ int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
259 struct hw_aq_atl_utils_mbox_header *pmbox) 256 struct hw_aq_atl_utils_mbox_header *pmbox)
260{ 257{
261 return hw_atl_utils_fw_downld_dwords(self, 258 return hw_atl_utils_fw_downld_dwords(self,
262 PHAL_ATLANTIC->mbox_addr, 259 self->mbox_addr,
263 (u32 *)(void *)pmbox, 260 (u32 *)(void *)pmbox,
264 sizeof(*pmbox) / sizeof(u32)); 261 sizeof(*pmbox) / sizeof(u32));
265} 262}
@@ -270,7 +267,7 @@ void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
270 int err = 0; 267 int err = 0;
271 268
272 err = hw_atl_utils_fw_downld_dwords(self, 269 err = hw_atl_utils_fw_downld_dwords(self,
273 PHAL_ATLANTIC->mbox_addr, 270 self->mbox_addr,
274 (u32 *)(void *)pmbox, 271 (u32 *)(void *)pmbox,
275 sizeof(*pmbox) / sizeof(u32)); 272 sizeof(*pmbox) / sizeof(u32));
276 if (err < 0) 273 if (err < 0)
@@ -281,9 +278,9 @@ void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
281 self->aq_nic_cfg->mtu : 1514U; 278 self->aq_nic_cfg->mtu : 1514U;
282 pmbox->stats.ubrc = pmbox->stats.uprc * mtu; 279 pmbox->stats.ubrc = pmbox->stats.uprc * mtu;
283 pmbox->stats.ubtc = pmbox->stats.uptc * mtu; 280 pmbox->stats.ubtc = pmbox->stats.uptc * mtu;
284 pmbox->stats.dpc = atomic_read(&PHAL_ATLANTIC_A0->dpc); 281 pmbox->stats.dpc = atomic_read(&self->dpc);
285 } else { 282 } else {
286 pmbox->stats.dpc = reg_rx_dma_stat_counter7get(self); 283 pmbox->stats.dpc = hw_atl_reg_rx_dma_stat_counter7get(self);
287 } 284 }
288 285
289err_exit:; 286err_exit:;
@@ -365,7 +362,6 @@ int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self)
365} 362}
366 363
367int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self, 364int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self,
368 struct aq_hw_caps_s *aq_hw_caps,
369 u8 *mac) 365 u8 *mac)
370{ 366{
371 int err = 0; 367 int err = 0;
@@ -376,9 +372,9 @@ int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self,
376 self->mmio = aq_pci_func_get_mmio(self->aq_pci_func); 372 self->mmio = aq_pci_func_get_mmio(self->aq_pci_func);
377 373
378 hw_atl_utils_hw_chip_features_init(self, 374 hw_atl_utils_hw_chip_features_init(self,
379 &PHAL_ATLANTIC_A0->chip_features); 375 &self->chip_features);
380 376
381 err = hw_atl_utils_mpi_create(self, aq_hw_caps); 377 err = hw_atl_utils_mpi_create(self);
382 if (err < 0) 378 if (err < 0)
383 goto err_exit; 379 goto err_exit;
384 380
@@ -396,7 +392,7 @@ int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self,
396 aq_hw_read_reg(self, 0x00000374U) + 392 aq_hw_read_reg(self, 0x00000374U) +
397 (40U * 4U), 393 (40U * 4U),
398 mac_addr, 394 mac_addr,
399 AQ_DIMOF(mac_addr)); 395 ARRAY_SIZE(mac_addr));
400 if (err < 0) { 396 if (err < 0) {
401 mac_addr[0] = 0U; 397 mac_addr[0] = 0U;
402 mac_addr[1] = 0U; 398 mac_addr[1] = 0U;
@@ -465,7 +461,7 @@ unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps)
465void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p) 461void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p)
466{ 462{
467 u32 chip_features = 0U; 463 u32 chip_features = 0U;
468 u32 val = reg_glb_mif_id_get(self); 464 u32 val = hw_atl_reg_glb_mif_id_get(self);
469 u32 mif_rev = val & 0xFFU; 465 u32 mif_rev = val & 0xFFU;
470 466
471 if ((3U & mif_rev) == 1U) { 467 if ((3U & mif_rev) == 1U) {
@@ -500,13 +496,13 @@ int hw_atl_utils_hw_set_power(struct aq_hw_s *self,
500 496
501int hw_atl_utils_update_stats(struct aq_hw_s *self) 497int hw_atl_utils_update_stats(struct aq_hw_s *self)
502{ 498{
503 struct hw_atl_s *hw_self = PHAL_ATLANTIC;
504 struct hw_aq_atl_utils_mbox mbox; 499 struct hw_aq_atl_utils_mbox mbox;
505 500
506 hw_atl_utils_mpi_read_stats(self, &mbox); 501 hw_atl_utils_mpi_read_stats(self, &mbox);
507 502
508#define AQ_SDELTA(_N_) (hw_self->curr_stats._N_ += \ 503#define AQ_SDELTA(_N_) (self->curr_stats._N_ += \
509 mbox.stats._N_ - hw_self->last_stats._N_) 504 mbox.stats._N_ - self->last_stats._N_)
505
510 if (self->aq_link_status.mbps) { 506 if (self->aq_link_status.mbps) {
511 AQ_SDELTA(uprc); 507 AQ_SDELTA(uprc);
512 AQ_SDELTA(mprc); 508 AQ_SDELTA(mprc);
@@ -527,19 +523,19 @@ int hw_atl_utils_update_stats(struct aq_hw_s *self)
527 AQ_SDELTA(dpc); 523 AQ_SDELTA(dpc);
528 } 524 }
529#undef AQ_SDELTA 525#undef AQ_SDELTA
530 hw_self->curr_stats.dma_pkt_rc = stats_rx_dma_good_pkt_counterlsw_get(self); 526 self->curr_stats.dma_pkt_rc = hw_atl_stats_rx_dma_good_pkt_counterlsw_get(self);
531 hw_self->curr_stats.dma_pkt_tc = stats_tx_dma_good_pkt_counterlsw_get(self); 527 self->curr_stats.dma_pkt_tc = hw_atl_stats_tx_dma_good_pkt_counterlsw_get(self);
532 hw_self->curr_stats.dma_oct_rc = stats_rx_dma_good_octet_counterlsw_get(self); 528 self->curr_stats.dma_oct_rc = hw_atl_stats_rx_dma_good_octet_counterlsw_get(self);
533 hw_self->curr_stats.dma_oct_tc = stats_tx_dma_good_octet_counterlsw_get(self); 529 self->curr_stats.dma_oct_tc = hw_atl_stats_tx_dma_good_octet_counterlsw_get(self);
534 530
535 memcpy(&hw_self->last_stats, &mbox.stats, sizeof(mbox.stats)); 531 memcpy(&self->last_stats, &mbox.stats, sizeof(mbox.stats));
536 532
537 return 0; 533 return 0;
538} 534}
539 535
540struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self) 536struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self)
541{ 537{
542 return &PHAL_ATLANTIC->curr_stats; 538 return &self->curr_stats;
543} 539}
544 540
545static const u32 hw_atl_utils_hw_mac_regs[] = { 541static const u32 hw_atl_utils_hw_mac_regs[] = {
@@ -568,7 +564,7 @@ static const u32 hw_atl_utils_hw_mac_regs[] = {
568}; 564};
569 565
570int hw_atl_utils_hw_get_regs(struct aq_hw_s *self, 566int hw_atl_utils_hw_get_regs(struct aq_hw_s *self,
571 struct aq_hw_caps_s *aq_hw_caps, 567 const struct aq_hw_caps_s *aq_hw_caps,
572 u32 *regs_buff) 568 u32 *regs_buff)
573{ 569{
574 unsigned int i = 0U; 570 unsigned int i = 0U;
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h
index 21aeca6908d3..40e2319c65d5 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h
@@ -14,10 +14,39 @@
14#ifndef HW_ATL_UTILS_H 14#ifndef HW_ATL_UTILS_H
15#define HW_ATL_UTILS_H 15#define HW_ATL_UTILS_H
16 16
17#include "../aq_common.h"
18
19#define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); } 17#define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); }
20 18
19/* Hardware tx descriptor */
20struct __packed hw_atl_txd_s {
21 u64 buf_addr;
22 u32 ctl;
23 u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */
24};
25
26/* Hardware tx context descriptor */
27struct __packed hw_atl_txc_s {
28 u32 rsvd;
29 u32 len;
30 u32 ctl;
31 u32 len2;
32};
33
34/* Hardware rx descriptor */
35struct __packed hw_atl_rxd_s {
36 u64 buf_addr;
37 u64 hdr_addr;
38};
39
40/* Hardware rx descriptor writeback */
41struct __packed hw_atl_rxd_wb_s {
42 u32 type;
43 u32 rss_hash;
44 u16 status;
45 u16 pkt_len;
46 u16 next_desc_ptr;
47 u16 vlan;
48};
49
21struct __packed hw_atl_stats_s { 50struct __packed hw_atl_stats_s {
22 u32 uprc; 51 u32 uprc;
23 u32 mprc; 52 u32 mprc;
@@ -126,26 +155,6 @@ struct __packed hw_aq_atl_utils_mbox {
126 struct hw_atl_stats_s stats; 155 struct hw_atl_stats_s stats;
127}; 156};
128 157
129struct __packed hw_atl_s {
130 struct aq_hw_s base;
131 struct hw_atl_stats_s last_stats;
132 struct aq_stats_s curr_stats;
133 u64 speed;
134 unsigned int chip_features;
135 u32 fw_ver_actual;
136 atomic_t dpc;
137 u32 mbox_addr;
138 u32 rpc_addr;
139 u32 rpc_tid;
140 struct hw_aq_atl_utils_fw_rpc rpc;
141};
142
143#define SELF ((struct hw_atl_s *)self)
144
145#define PHAL_ATLANTIC ((struct hw_atl_s *)((void *)(self)))
146#define PHAL_ATLANTIC_A0 ((struct hw_atl_s *)((void *)(self)))
147#define PHAL_ATLANTIC_B0 ((struct hw_atl_s *)((void *)(self)))
148
149#define HAL_ATLANTIC_UTILS_CHIP_MIPS 0x00000001U 158#define HAL_ATLANTIC_UTILS_CHIP_MIPS 0x00000001U
150#define HAL_ATLANTIC_UTILS_CHIP_TPO2 0x00000002U 159#define HAL_ATLANTIC_UTILS_CHIP_TPO2 0x00000002U
151#define HAL_ATLANTIC_UTILS_CHIP_RPF2 0x00000004U 160#define HAL_ATLANTIC_UTILS_CHIP_RPF2 0x00000004U
@@ -154,7 +163,7 @@ struct __packed hw_atl_s {
154#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 0x02000000U 163#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 0x02000000U
155 164
156#define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \ 165#define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \
157 PHAL_ATLANTIC->chip_features) 166 self->chip_features)
158 167
159enum hal_atl_utils_fw_state_e { 168enum hal_atl_utils_fw_state_e {
160 MPI_DEINIT = 0, 169 MPI_DEINIT = 0,
@@ -171,6 +180,10 @@ enum hal_atl_utils_fw_state_e {
171#define HAL_ATLANTIC_RATE_100M BIT(5) 180#define HAL_ATLANTIC_RATE_100M BIT(5)
172#define HAL_ATLANTIC_RATE_INVALID BIT(6) 181#define HAL_ATLANTIC_RATE_INVALID BIT(6)
173 182
183struct aq_hw_s;
184struct aq_hw_caps_s;
185struct aq_hw_link_status_s;
186
174void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p); 187void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p);
175 188
176int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self, 189int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
@@ -189,13 +202,12 @@ int hw_atl_utils_mpi_set_speed(struct aq_hw_s *self, u32 speed,
189int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self); 202int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self);
190 203
191int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self, 204int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self,
192 struct aq_hw_caps_s *aq_hw_caps,
193 u8 *mac); 205 u8 *mac);
194 206
195unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps); 207unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps);
196 208
197int hw_atl_utils_hw_get_regs(struct aq_hw_s *self, 209int hw_atl_utils_hw_get_regs(struct aq_hw_s *self,
198 struct aq_hw_caps_s *aq_hw_caps, 210 const struct aq_hw_caps_s *aq_hw_caps,
199 u32 *regs_buff); 211 u32 *regs_buff);
200 212
201int hw_atl_utils_hw_set_power(struct aq_hw_s *self, 213int hw_atl_utils_hw_set_power(struct aq_hw_s *self,
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 22:56:48 -0400