Merge branch 'pci/resource' into next

* pci/resource:
  PCI: Fail pci_map_rom() if the option ROM is invalid
  PCI: Move pci_map_rom() error path
  x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 00-1f, 30-3f, 60-7f)
  PCI: Add pci_resize_resource() for resizing BARs
  PCI: Add resizable BAR infrastructure
  PCI: Add PCI resource type mask #define

8 files changed, 380 insertions, 17 deletions

diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index f2228b150faa..e59378bf37d9 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -635,3 +635,88 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2030, quirk_no_aersid);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);
+
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
+
+#define AMD_141b_MMIO_BASE(x)   (0x80 + (x) * 0x8)
+#define AMD_141b_MMIO_BASE_RE_MASK              BIT(0)
+#define AMD_141b_MMIO_BASE_WE_MASK              BIT(1)
+#define AMD_141b_MMIO_BASE_MMIOBASE_MASK        GENMASK(31,8)
+
+#define AMD_141b_MMIO_LIMIT(x)  (0x84 + (x) * 0x8)
+#define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK      GENMASK(31,8)
+
+#define AMD_141b_MMIO_HIGH(x)   (0x180 + (x) * 0x4)
+#define AMD_141b_MMIO_HIGH_MMIOBASE_MASK        GENMASK(7,0)
+#define AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT      16
+#define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK       GENMASK(23,16)
+
+/*
+ * The PCI Firmware Spec, rev 3.2, notes that ACPI should optionally allow
+ * configuring host bridge windows using the _PRS and _SRS methods.
+ *
+ * But this is rarely implemented, so we manually enable a large 64bit BAR for
+ * PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh, 60h-7fh) Processors
+ * here.
+ */
+static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
+{
+        unsigned i;
+        u32 base, limit, high;
+        struct resource *res, *conflict;
+
+        for (i = 0; i < 8; i++) {
+                pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base);
+                pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high);
+
+                /* Is this slot free? */
+                if (!(base & (AMD_141b_MMIO_BASE_RE_MASK |
+                              AMD_141b_MMIO_BASE_WE_MASK)))
+                        break;
+
+                base >>= 8;
+                base |= high << 24;
+
+                /* Abort if a slot already configures a 64bit BAR. */
+                if (base > 0x10000)
+                        return;
+        }
+        if (i == 8)
+                return;
+
+        res = kzalloc(sizeof(*res), GFP_KERNEL);
+        if (!res)
+                return;
+
+        res->name = "PCI Bus 0000:00";
+        res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM |
+                IORESOURCE_MEM_64 | IORESOURCE_WINDOW;
+        res->start = 0x100000000ull;
+        res->end = 0xfd00000000ull - 1;
+
+        /* Just grab the free area behind system memory for this */
+        while ((conflict = request_resource_conflict(&iomem_resource, res)))
+                res->start = conflict->end + 1;
+
+        dev_info(&dev->dev, "adding root bus resource %pR\n", res);
+
+        base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) |
+                AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK;
+        limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK;
+        high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) |
+                ((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT)
+                 & AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK);
+
+        pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high);
+        pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit);
+        pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base);
+
+        pci_bus_add_resource(dev->bus, res, 0);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
+
+#endif
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index d50c58d6acd3..c5172b01164d 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -2966,6 +2966,107 @@ bool pci_acs_path_enabled(struct pci_dev *start,
 }
 
 /**
+ * pci_rebar_find_pos - find position of resize ctrl reg for BAR
+ * @pdev: PCI device
+ * @bar: BAR to find
+ *
+ * Helper to find the position of the ctrl register for a BAR.
+ * Returns -ENOTSUPP if resizable BARs are not supported at all.
+ * Returns -ENOENT if no ctrl register for the BAR could be found.
+ */
+static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
+{
+        unsigned int pos, nbars, i;
+        u32 ctrl;
+
+        pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
+        if (!pos)
+                return -ENOTSUPP;
+
+        pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
+        nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
+                    PCI_REBAR_CTRL_NBAR_SHIFT;
+
+        for (i = 0; i < nbars; i++, pos += 8) {
+                int bar_idx;
+
+                pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
+                bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
+                if (bar_idx == bar)
+                        return pos;
+        }
+
+        return -ENOENT;
+}
+
+/**
+ * pci_rebar_get_possible_sizes - get possible sizes for BAR
+ * @pdev: PCI device
+ * @bar: BAR to query
+ *
+ * Get the possible sizes of a resizable BAR as bitmask defined in the spec
+ * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
+ */
+u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
+{
+        int pos;
+        u32 cap;
+
+        pos = pci_rebar_find_pos(pdev, bar);
+        if (pos < 0)
+                return 0;
+
+        pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
+        return (cap & PCI_REBAR_CAP_SIZES) >> 4;
+}
+
+/**
+ * pci_rebar_get_current_size - get the current size of a BAR
+ * @pdev: PCI device
+ * @bar: BAR to set size to
+ *
+ * Read the size of a BAR from the resizable BAR config.
+ * Returns size if found or negative error code.
+ */
+int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
+{
+        int pos;
+        u32 ctrl;
+
+        pos = pci_rebar_find_pos(pdev, bar);
+        if (pos < 0)
+                return pos;
+
+        pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
+        return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> 8;
+}
+
+/**
+ * pci_rebar_set_size - set a new size for a BAR
+ * @pdev: PCI device
+ * @bar: BAR to set size to
+ * @size: new size as defined in the spec (0=1MB, 19=512GB)
+ *
+ * Set the new size of a BAR as defined in the spec.
+ * Returns zero if resizing was successful, error code otherwise.
+ */
+int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
+{
+        int pos;
+        u32 ctrl;
+
+        pos = pci_rebar_find_pos(pdev, bar);
+        if (pos < 0)
+                return pos;
+
+        pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
+        ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
+        ctrl |= size << 8;
+        pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
+        return 0;
+}
+
+/**
  * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
  * @dev: the PCI device
  * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)