aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorWei Ni <wni@nvidia.com>2016-05-11 06:20:21 -0400
committerZhang Rui <rui.zhang@intel.com>2016-09-27 02:02:32 -0400
commit0fa2bfcd1a0ee2f0465b769f37163b7e7d9c2e50 (patch)
tree0a731ecc9db7cea14f5c8baac68c8f62939ce854
parente12b048c3060975203225b6ebd30a4fe85082bab (diff)
arm64: tegra: use tegra132-soctherm for Tegra132
The Tegra132 has the specific settings for soctherm, so change to use campatible "nvidia,tegra132-soctherm" for it. And adds cpu, gpu, mem and pllx thermal zones. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra132.dtsi36
1 files changed, 34 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
index 2013f8916084..e41d8e82d7ed 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
@@ -4,6 +4,7 @@
4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/thermal/tegra124-soctherm.h>
7 8
8/ { 9/ {
9 compatible = "nvidia,tegra132", "nvidia,tegra124"; 10 compatible = "nvidia,tegra132", "nvidia,tegra124";
@@ -727,8 +728,8 @@
727 }; 728 };
728 729
729 soctherm: thermal-sensor@700e2000 { 730 soctherm: thermal-sensor@700e2000 {
730 compatible = "nvidia,tegra124-soctherm"; 731 compatible = "nvidia,tegra132-soctherm";
731 reg = <0x0 0x700e2000 0x0 0x1000>; 732 reg = <0x0 0x700e2000 0x0 0x600>;
732 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 733 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 734 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
734 <&tegra_car TEGRA124_CLK_SOC_THERM>; 735 <&tegra_car TEGRA124_CLK_SOC_THERM>;
@@ -738,6 +739,37 @@
738 #thermal-sensor-cells = <1>; 739 #thermal-sensor-cells = <1>;
739 }; 740 };
740 741
742 thermal-zones {
743 cpu {
744 polling-delay-passive = <1000>;
745 polling-delay = <0>;
746
747 thermal-sensors =
748 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
749 };
750 mem {
751 polling-delay-passive = <0>;
752 polling-delay = <0>;
753
754 thermal-sensors =
755 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
756 };
757 gpu {
758 polling-delay-passive = <1000>;
759 polling-delay = <0>;
760
761 thermal-sensors =
762 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
763 };
764 pllx {
765 polling-delay-passive = <0>;
766 polling-delay = <0>;
767
768 thermal-sensors =
769 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
770 };
771 };
772
741 ahub@70300000 { 773 ahub@70300000 {
742 compatible = "nvidia,tegra124-ahub"; 774 compatible = "nvidia,tegra124-ahub";
743 reg = <0x0 0x70300000 0x0 0x200>, 775 reg = <0x0 0x70300000 0x0 0x200>,