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authorJia Hongtao <hongtao.jia@nxp.com>2017-01-03 21:36:25 -0500
committerShawn Guo <shawnguo@kernel.org>2017-01-09 22:12:14 -0500
commit0f7a4bcbe51dfb7c39c39089486448ab0aac6c77 (patch)
tree62f90a3a301e3ce549fcd48ae26b019ed048fb06
parentba3213602d2824de358564ff391293f351ba1b1c (diff)
arm64: dts: ls1046a: Add TMU device tree support
Also add nodes and properties for thermal management support. Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi80
1 files changed, 80 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 38806ca53829..4a164b801882 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -45,6 +45,7 @@
45 */ 45 */
46 46
47#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/interrupt-controller/arm-gic.h>
48#include <dt-bindings/thermal/thermal.h>
48 49
49/ { 50/ {
50 compatible = "fsl,ls1046a"; 51 compatible = "fsl,ls1046a";
@@ -67,6 +68,7 @@
67 clocks = <&clockgen 1 0>; 68 clocks = <&clockgen 1 0>;
68 next-level-cache = <&l2>; 69 next-level-cache = <&l2>;
69 cpu-idle-states = <&CPU_PH20>; 70 cpu-idle-states = <&CPU_PH20>;
71 #cooling-cells = <2>;
70 }; 72 };
71 73
72 cpu1: cpu@1 { 74 cpu1: cpu@1 {
@@ -279,6 +281,84 @@
279 clocks = <&sysclk>; 281 clocks = <&sysclk>;
280 }; 282 };
281 283
284 tmu: tmu@1f00000 {
285 compatible = "fsl,qoriq-tmu";
286 reg = <0x0 0x1f00000 0x0 0x10000>;
287 interrupts = <0 33 0x4>;
288 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
289 fsl,tmu-calibration =
290 /* Calibration data group 1 */
291 <0x00000000 0x00000026
292 0x00000001 0x0000002d
293 0x00000002 0x00000032
294 0x00000003 0x00000039
295 0x00000004 0x0000003f
296 0x00000005 0x00000046
297 0x00000006 0x0000004d
298 0x00000007 0x00000054
299 0x00000008 0x0000005a
300 0x00000009 0x00000061
301 0x0000000a 0x0000006a
302 0x0000000b 0x00000071
303 /* Calibration data group 2 */
304 0x00010000 0x00000025
305 0x00010001 0x0000002c
306 0x00010002 0x00000035
307 0x00010003 0x0000003d
308 0x00010004 0x00000045
309 0x00010005 0x0000004e
310 0x00010006 0x00000057
311 0x00010007 0x00000061
312 0x00010008 0x0000006b
313 0x00010009 0x00000076
314 /* Calibration data group 3 */
315 0x00020000 0x00000029
316 0x00020001 0x00000033
317 0x00020002 0x0000003d
318 0x00020003 0x00000049
319 0x00020004 0x00000056
320 0x00020005 0x00000061
321 0x00020006 0x0000006d
322 /* Calibration data group 4 */
323 0x00030000 0x00000021
324 0x00030001 0x0000002a
325 0x00030002 0x0000003c
326 0x00030003 0x0000004e>;
327 big-endian;
328 #thermal-sensor-cells = <1>;
329 };
330
331 thermal-zones {
332 cpu_thermal: cpu-thermal {
333 polling-delay-passive = <1000>;
334 polling-delay = <5000>;
335 thermal-sensors = <&tmu 3>;
336
337 trips {
338 cpu_alert: cpu-alert {
339 temperature = <85000>;
340 hysteresis = <2000>;
341 type = "passive";
342 };
343
344 cpu_crit: cpu-crit {
345 temperature = <95000>;
346 hysteresis = <2000>;
347 type = "critical";
348 };
349 };
350
351 cooling-maps {
352 map0 {
353 trip = <&cpu_alert>;
354 cooling-device =
355 <&cpu0 THERMAL_NO_LIMIT
356 THERMAL_NO_LIMIT>;
357 };
358 };
359 };
360 };
361
282 dspi: dspi@2100000 { 362 dspi: dspi@2100000 {
283 compatible = "fsl,ls1021a-v1.0-dspi"; 363 compatible = "fsl,ls1021a-v1.0-dspi";
284 #address-cells = <1>; 364 #address-cells = <1>;