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authorTakeshi Kihara <takeshi.kihara.df@renesas.com>2017-11-16 09:59:21 -0500
committerGeert Uytterhoeven <geert+renesas@glider.be>2017-12-05 08:14:55 -0500
commit0f4713d71f22d3b0ec3de6ae4a126cceecdea82b (patch)
tree6c0b8f754e9a940d789d58f7be20670eb5f9a799
parent8714a9c1bdd388aa6cff6cd01e357c349300158e (diff)
pinctrl: sh-pfc: r8a7796: Rename RTS{0,1,3,4}# pin function definitions
This patch renames the pin function macro definitions of the GPSR5 and IPSR{0,3,5,6,12} registers value for the RTS{0,1,3,4}# pin. This is a correction because GPSR and IPSR register specification for R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7796.c48
1 files changed, 24 insertions, 24 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 954daaef2ec3..e5807d1ce0dc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -163,11 +163,11 @@
163#define GPSR5_11 F_(RX2_A, IP13_7_4) 163#define GPSR5_11 F_(RX2_A, IP13_7_4)
164#define GPSR5_10 F_(TX2_A, IP13_3_0) 164#define GPSR5_10 F_(TX2_A, IP13_3_0)
165#define GPSR5_9 F_(SCK2, IP12_31_28) 165#define GPSR5_9 F_(SCK2, IP12_31_28)
166#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24) 166#define GPSR5_8 F_(RTS1_N, IP12_27_24)
167#define GPSR5_7 F_(CTS1_N, IP12_23_20) 167#define GPSR5_7 F_(CTS1_N, IP12_23_20)
168#define GPSR5_6 F_(TX1_A, IP12_19_16) 168#define GPSR5_6 F_(TX1_A, IP12_19_16)
169#define GPSR5_5 F_(RX1_A, IP12_15_12) 169#define GPSR5_5 F_(RX1_A, IP12_15_12)
170#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8) 170#define GPSR5_4 F_(RTS0_N, IP12_11_8)
171#define GPSR5_3 F_(CTS0_N, IP12_7_4) 171#define GPSR5_3 F_(CTS0_N, IP12_7_4)
172#define GPSR5_2 F_(TX0, IP12_3_0) 172#define GPSR5_2 F_(TX0, IP12_3_0)
173#define GPSR5_1 F_(RX0, IP11_31_28) 173#define GPSR5_1 F_(RX0, IP11_31_28)
@@ -220,7 +220,7 @@
220#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 225#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 226#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -240,7 +240,7 @@
240#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 240#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 241#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 242#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 243#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 244#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 245
246/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 246/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
@@ -258,7 +258,7 @@
258#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -271,7 +271,7 @@
271#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 276
277/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 277/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
@@ -318,11 +318,11 @@
318#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 319#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 320#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -626,7 +626,7 @@ static const u16 pinmux_data[] = {
626 626
627 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), 627 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
628 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), 628 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
629 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0), 629 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
630 630
631 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 631 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
632 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 632 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -763,7 +763,7 @@ static const u16 pinmux_data[] = {
763 763
764 PINMUX_IPSR_GPSR(IP3_7_4, A10), 764 PINMUX_IPSR_GPSR(IP3_7_4, A10),
765 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 765 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
766 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1), 766 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
767 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 767 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
768 768
769 PINMUX_IPSR_GPSR(IP3_11_8, A11), 769 PINMUX_IPSR_GPSR(IP3_11_8, A11),
@@ -866,7 +866,7 @@ static const u16 pinmux_data[] = {
866 866
867 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 867 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
868 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 868 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
869 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS), 869 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
870 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 870 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
871 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 871 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
872 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 872 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
@@ -947,7 +947,7 @@ static const u16 pinmux_data[] = {
947 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 947 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
948 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 948 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
949 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 949 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
950 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), 950 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
951 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 951 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
952 952
953 PINMUX_IPSR_GPSR(IP6_31_28, D12), 953 PINMUX_IPSR_GPSR(IP6_31_28, D12),
@@ -1155,7 +1155,7 @@ static const u16 pinmux_data[] = {
1155 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1155 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1156 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1156 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1157 1157
1158 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS), 1158 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1159 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1159 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1160 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1160 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1161 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), 1161 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
@@ -1184,7 +1184,7 @@ static const u16 pinmux_data[] = {
1184 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1184 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1185 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1185 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1186 1186
1187 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS), 1187 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1188 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1188 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1189 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1189 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1190 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1190 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
@@ -3249,7 +3249,7 @@ static const unsigned int scif0_ctrl_pins[] = {
3249 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3249 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3250}; 3250};
3251static const unsigned int scif0_ctrl_mux[] = { 3251static const unsigned int scif0_ctrl_mux[] = {
3252 RTS0_N_TANS_MARK, CTS0_N_MARK, 3252 RTS0_N_MARK, CTS0_N_MARK,
3253}; 3253};
3254/* - SCIF1 ------------------------------------------------------------------ */ 3254/* - SCIF1 ------------------------------------------------------------------ */
3255static const unsigned int scif1_data_a_pins[] = { 3255static const unsigned int scif1_data_a_pins[] = {
@@ -3271,7 +3271,7 @@ static const unsigned int scif1_ctrl_pins[] = {
3271 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3271 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3272}; 3272};
3273static const unsigned int scif1_ctrl_mux[] = { 3273static const unsigned int scif1_ctrl_mux[] = {
3274 RTS1_N_TANS_MARK, CTS1_N_MARK, 3274 RTS1_N_MARK, CTS1_N_MARK,
3275}; 3275};
3276 3276
3277static const unsigned int scif1_data_b_pins[] = { 3277static const unsigned int scif1_data_b_pins[] = {
@@ -3323,7 +3323,7 @@ static const unsigned int scif3_ctrl_pins[] = {
3323 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3323 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3324}; 3324};
3325static const unsigned int scif3_ctrl_mux[] = { 3325static const unsigned int scif3_ctrl_mux[] = {
3326 RTS3_N_TANS_MARK, CTS3_N_MARK, 3326 RTS3_N_MARK, CTS3_N_MARK,
3327}; 3327};
3328static const unsigned int scif3_data_b_pins[] = { 3328static const unsigned int scif3_data_b_pins[] = {
3329 /* RX, TX */ 3329 /* RX, TX */
@@ -3352,7 +3352,7 @@ static const unsigned int scif4_ctrl_a_pins[] = {
3352 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3352 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3353}; 3353};
3354static const unsigned int scif4_ctrl_a_mux[] = { 3354static const unsigned int scif4_ctrl_a_mux[] = {
3355 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, 3355 RTS4_N_A_MARK, CTS4_N_A_MARK,
3356}; 3356};
3357static const unsigned int scif4_data_b_pins[] = { 3357static const unsigned int scif4_data_b_pins[] = {
3358 /* RX, TX */ 3358 /* RX, TX */
@@ -3373,7 +3373,7 @@ static const unsigned int scif4_ctrl_b_pins[] = {
3373 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3373 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3374}; 3374};
3375static const unsigned int scif4_ctrl_b_mux[] = { 3375static const unsigned int scif4_ctrl_b_mux[] = {
3376 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK, 3376 RTS4_N_B_MARK, CTS4_N_B_MARK,
3377}; 3377};
3378static const unsigned int scif4_data_c_pins[] = { 3378static const unsigned int scif4_data_c_pins[] = {
3379 /* RX, TX */ 3379 /* RX, TX */
@@ -3394,7 +3394,7 @@ static const unsigned int scif4_ctrl_c_pins[] = {
3394 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3394 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3395}; 3395};
3396static const unsigned int scif4_ctrl_c_mux[] = { 3396static const unsigned int scif4_ctrl_c_mux[] = {
3397 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, 3397 RTS4_N_C_MARK, CTS4_N_C_MARK,
3398}; 3398};
3399/* - SCIF5 ------------------------------------------------------------------ */ 3399/* - SCIF5 ------------------------------------------------------------------ */
3400static const unsigned int scif5_data_a_pins[] = { 3400static const unsigned int scif5_data_a_pins[] = {
@@ -5400,11 +5400,11 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5400 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 5400 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5401 } }, 5401 } },
5402 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 5402 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5403 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */ 5403 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5404 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 5404 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5405 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 5405 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5406 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 5406 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5407 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */ 5407 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5408 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 5408 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5409 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 5409 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5410 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 5410 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
@@ -5649,11 +5649,11 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5649 [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 5649 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5650 [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 5650 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5651 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 5651 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
5652 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */ 5652 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
5653 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 5653 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5654 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 5654 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5655 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 5655 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
5656 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */ 5656 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
5657 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 5657 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5658 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 5658 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5659 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 5659 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 03:14:09 -0400