diff options
author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2015-08-28 08:42:30 -0400 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2015-09-15 05:22:34 -0400 |
commit | 0f44de6cb8904e9a686188aaa51323280d37e127 (patch) | |
tree | a32511d90f535d0f95ffa282edc8cd3d9a6e02fe | |
parent | 654b7d6aec9e55ca5e67adb3bdf0fefd9533c900 (diff) |
ARM: tegra: apalis: Fix pin muxing
Fix pin muxing which got broken due to certain stuff having been fixed
or renamed since.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r-- | arch/arm/boot/dts/tegra30-apalis.dtsi | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index fd6c94e0eeac..84744dc446c4 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi | |||
@@ -66,7 +66,7 @@ | |||
66 | /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ | 66 | /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ |
67 | uart3_cts_n_pa1 { | 67 | uart3_cts_n_pa1 { |
68 | nvidia,pins = "uart3_cts_n_pa1"; | 68 | nvidia,pins = "uart3_cts_n_pa1"; |
69 | nvidia,function = "rsvd1"; | 69 | nvidia,function = "rsvd2"; |
70 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | 70 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
71 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 71 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
72 | }; | 72 | }; |
@@ -152,32 +152,32 @@ | |||
152 | }; | 152 | }; |
153 | 153 | ||
154 | /* Apalis PWM1 */ | 154 | /* Apalis PWM1 */ |
155 | gpio_pu6 { | 155 | pu6 { |
156 | nvidia,pins = "gpio_pu6"; | 156 | nvidia,pins = "pu6"; |
157 | nvidia,function = "pwm3"; | 157 | nvidia,function = "pwm3"; |
158 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 158 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
159 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 159 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
160 | }; | 160 | }; |
161 | 161 | ||
162 | /* Apalis PWM2 */ | 162 | /* Apalis PWM2 */ |
163 | gpio_pu5 { | 163 | pu5 { |
164 | nvidia,pins = "gpio_pu5"; | 164 | nvidia,pins = "pu5"; |
165 | nvidia,function = "pwm2"; | 165 | nvidia,function = "pwm2"; |
166 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 166 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
167 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 167 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
168 | }; | 168 | }; |
169 | 169 | ||
170 | /* Apalis PWM3 */ | 170 | /* Apalis PWM3 */ |
171 | gpio_pu4 { | 171 | pu4 { |
172 | nvidia,pins = "gpio_pu4"; | 172 | nvidia,pins = "pu4"; |
173 | nvidia,function = "pwm1"; | 173 | nvidia,function = "pwm1"; |
174 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 174 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
175 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 175 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
176 | }; | 176 | }; |
177 | 177 | ||
178 | /* Apalis PWM4 */ | 178 | /* Apalis PWM4 */ |
179 | gpio_pu3 { | 179 | pu3 { |
180 | nvidia,pins = "gpio_pu3"; | 180 | nvidia,pins = "pu3"; |
181 | nvidia,function = "pwm0"; | 181 | nvidia,function = "pwm0"; |
182 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 182 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
183 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 183 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |