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authorTero Kristo <t-kristo@ti.com>2017-08-24 08:33:01 -0400
committerTero Kristo <t-kristo@ti.com>2017-12-01 08:17:17 -0500
commit0ed266d7ae5e46de4730ddfb26fe9dde69fc5549 (patch)
tree867030e3fe0710c7d953358d0a2de71fd3eb3437
parent78aac8004615b685b418891f78379cd8477195ac (diff)
clk: ti: omap3: cleanup unnecessary clock aliases
Most of the clock aliases are no longer needed, only leave the ones required by OMAP timer code in place. Signed-off-by: Tero Kristo <t-kristo@ti.com>
-rw-r--r--drivers/clk/ti/clk-3xxx.c263
1 files changed, 2 insertions, 261 deletions
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
index b1251cae98b8..8aa5f5793835 100644
--- a/drivers/clk/ti/clk-3xxx.c
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -224,296 +224,43 @@ const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = {
224}; 224};
225 225
226static struct ti_dt_clk omap3xxx_clks[] = { 226static struct ti_dt_clk omap3xxx_clks[] = {
227 DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
228 DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
229 DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
230 DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
231 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
232 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
233 DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
234 DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
235 DT_CLK("twl", "fck", "osc_sys_ck"),
236 DT_CLK(NULL, "sys_ck", "sys_ck"),
237 DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
238 DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
239 DT_CLK(NULL, "sys_altclk", "sys_altclk"),
240 DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
241 DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
242 DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
243 DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
244 DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
245 DT_CLK(NULL, "core_ck", "core_ck"),
246 DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
247 DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
248 DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
249 DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
250 DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
251 DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
252 DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
253 DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
254 DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
255 DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
256 DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
257 DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
258 DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
259 DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
260 DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
261 DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
262 DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
263 DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
264 DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
265 DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
266 DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
267 DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
268 DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
269 DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
270 DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
271 DT_CLK(NULL, "corex2_fck", "corex2_fck"),
272 DT_CLK(NULL, "dpll1_fck", "dpll1_fck"),
273 DT_CLK(NULL, "mpu_ck", "mpu_ck"),
274 DT_CLK(NULL, "arm_fck", "arm_fck"),
275 DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
276 DT_CLK(NULL, "l3_ick", "l3_ick"),
277 DT_CLK(NULL, "l4_ick", "l4_ick"),
278 DT_CLK(NULL, "rm_ick", "rm_ick"),
279 DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
280 DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
281 DT_CLK(NULL, "core_96m_fck", "core_96m_fck"),
282 DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
283 DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
284 DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
285 DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
286 DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
287 DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
288 DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
289 DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
290 DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
291 DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
292 DT_CLK(NULL, "uart2_fck", "uart2_fck"),
293 DT_CLK(NULL, "uart1_fck", "uart1_fck"),
294 DT_CLK(NULL, "core_12m_fck", "core_12m_fck"),
295 DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
296 DT_CLK(NULL, "hdq_fck", "hdq_fck"),
297 DT_CLK(NULL, "core_l3_ick", "core_l3_ick"),
298 DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
299 DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
300 DT_CLK(NULL, "core_l4_ick", "core_l4_ick"),
301 DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
302 DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
303 DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
304 DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
305 DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
306 DT_CLK(NULL, "hdq_ick", "hdq_ick"),
307 DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
308 DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
309 DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
310 DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
311 DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"),
312 DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
313 DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
314 DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
315 DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
316 DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
317 DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
318 DT_CLK(NULL, "i2c3_ick", "i2c3_ick"),
319 DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
320 DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
321 DT_CLK(NULL, "uart2_ick", "uart2_ick"),
322 DT_CLK(NULL, "uart1_ick", "uart1_ick"),
323 DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
324 DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
325 DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
326 DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
327 DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
328 DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"),
329 DT_CLK(NULL, "init_60m_fclk", "dummy_ck"),
330 DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
331 DT_CLK(NULL, "aes2_ick", "aes2_ick"),
332 DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"),
333 DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"),
334 DT_CLK(NULL, "sha12_ick", "sha12_ick"),
335 DT_CLK(NULL, "wdt2_fck", "wdt2_fck"),
336 DT_CLK("omap_wdt", "ick", "wdt2_ick"),
337 DT_CLK(NULL, "wdt2_ick", "wdt2_ick"),
338 DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
339 DT_CLK(NULL, "gpio1_ick", "gpio1_ick"),
340 DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"),
341 DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
342 DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
343 DT_CLK(NULL, "per_96m_fck", "per_96m_fck"),
344 DT_CLK(NULL, "per_48m_fck", "per_48m_fck"),
345 DT_CLK(NULL, "uart3_fck", "uart3_fck"),
346 DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
347 DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
348 DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
349 DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
350 DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
351 DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
352 DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
353 DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
354 DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"),
355 DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"),
356 DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"),
357 DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"),
358 DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"),
359 DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"),
360 DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
361 DT_CLK(NULL, "per_l4_ick", "per_l4_ick"),
362 DT_CLK(NULL, "gpio6_ick", "gpio6_ick"),
363 DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
364 DT_CLK(NULL, "gpio4_ick", "gpio4_ick"),
365 DT_CLK(NULL, "gpio3_ick", "gpio3_ick"),
366 DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
367 DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
368 DT_CLK(NULL, "uart3_ick", "uart3_ick"),
369 DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
370 DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
371 DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
372 DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
373 DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
374 DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
375 DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
376 DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
377 DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
378 DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
379 DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
380 DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
381 DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
382 DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
383 DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
384 DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
385 DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
386 DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
387 DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
388 DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
389 DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
390 DT_CLK(NULL, "pclk_fck", "pclk_fck"),
391 DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"),
392 DT_CLK(NULL, "atclk_fck", "atclk_fck"),
393 DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"),
394 DT_CLK(NULL, "traceclk_fck", "traceclk_fck"),
395 DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"),
396 DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
397 DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
398 DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"), 227 DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
399 DT_CLK(NULL, "timer_sys_ck", "sys_ck"), 228 DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
400 DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
401 { .node_name = NULL },
402};
403
404static struct ti_dt_clk omap34xx_omap36xx_clks[] = {
405 DT_CLK(NULL, "aes1_ick", "aes1_ick"),
406 DT_CLK("omap_rng", "ick", "rng_ick"),
407 DT_CLK("omap3-rom-rng", "ick", "rng_ick"),
408 DT_CLK(NULL, "sha11_ick", "sha11_ick"),
409 DT_CLK(NULL, "des1_ick", "des1_ick"),
410 DT_CLK(NULL, "cam_mclk", "cam_mclk"),
411 DT_CLK(NULL, "cam_ick", "cam_ick"),
412 DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"),
413 DT_CLK(NULL, "security_l3_ick", "security_l3_ick"),
414 DT_CLK(NULL, "pka_ick", "pka_ick"),
415 DT_CLK(NULL, "icr_ick", "icr_ick"),
416 DT_CLK("omap-aes", "ick", "aes2_ick"),
417 DT_CLK("omap-sham", "ick", "sha12_ick"),
418 DT_CLK(NULL, "des2_ick", "des2_ick"),
419 DT_CLK(NULL, "mspro_ick", "mspro_ick"),
420 DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
421 DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
422 DT_CLK(NULL, "sr1_fck", "sr1_fck"),
423 DT_CLK(NULL, "sr2_fck", "sr2_fck"),
424 DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"),
425 DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"),
426 DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"),
427 DT_CLK(NULL, "dpll2_fck", "dpll2_fck"),
428 DT_CLK(NULL, "iva2_ck", "iva2_ck"),
429 DT_CLK(NULL, "modem_fck", "modem_fck"),
430 DT_CLK(NULL, "sad2d_ick", "sad2d_ick"),
431 DT_CLK(NULL, "mad2d_ick", "mad2d_ick"),
432 DT_CLK(NULL, "mspro_fck", "mspro_fck"),
433 DT_CLK(NULL, "dpll2_ck", "dpll2_ck"),
434 DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"),
435 { .node_name = NULL }, 229 { .node_name = NULL },
436}; 230};
437 231
438static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = { 232static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
439 DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"), 233 DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
440 DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"), 234 DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
441 DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"),
442 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"), 235 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
443 DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"), 236 DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
444 DT_CLK(NULL, "usim_fck", "usim_fck"),
445 DT_CLK(NULL, "usim_ick", "usim_ick"),
446 { .node_name = NULL }, 237 { .node_name = NULL },
447}; 238};
448 239
449static struct ti_dt_clk omap3430es1_clks[] = { 240static struct ti_dt_clk omap3430es1_clks[] = {
450 DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"),
451 DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"),
452 DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"),
453 DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"),
454 DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"),
455 DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"),
456 DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"),
457 DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"), 241 DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
458 DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"), 242 DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
459 DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"),
460 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"), 243 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
461 DT_CLK(NULL, "fac_ick", "fac_ick"),
462 DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"), 244 DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
463 DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
464 DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"), 245 DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
465 DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
466 DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"), 246 DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
467 { .node_name = NULL }, 247 { .node_name = NULL },
468}; 248};
469 249
470static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = { 250static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
471 DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"),
472 DT_CLK(NULL, "dpll5_ck", "dpll5_ck"),
473 DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"),
474 DT_CLK(NULL, "sgx_fck", "sgx_fck"),
475 DT_CLK(NULL, "sgx_ick", "sgx_ick"),
476 DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"),
477 DT_CLK(NULL, "ts_fck", "ts_fck"),
478 DT_CLK(NULL, "usbtll_fck", "usbtll_fck"),
479 DT_CLK(NULL, "usbtll_ick", "usbtll_ick"),
480 DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
481 DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"),
482 DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"),
483 DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"), 251 DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
484 DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
485 DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"), 252 DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
486 DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"),
487 DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"),
488 DT_CLK(NULL, "usbhost_ick", "usbhost_ick"),
489 { .node_name = NULL }, 253 { .node_name = NULL },
490}; 254};
491 255
492static struct ti_dt_clk am35xx_clks[] = { 256static struct ti_dt_clk am35xx_clks[] = {
493 DT_CLK(NULL, "ipss_ick", "ipss_ick"),
494 DT_CLK(NULL, "rmii_ck", "rmii_ck"),
495 DT_CLK(NULL, "pclk_ck", "pclk_ck"),
496 DT_CLK(NULL, "emac_ick", "emac_ick"),
497 DT_CLK(NULL, "emac_fck", "emac_fck"),
498 DT_CLK("davinci_emac.0", NULL, "emac_ick"),
499 DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
500 DT_CLK("vpfe-capture", "master", "vpfe_ick"),
501 DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
502 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"), 257 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
503 DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"), 258 DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
504 DT_CLK(NULL, "hecc_ck", "hecc_ck"),
505 DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"), 259 DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
506 DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"), 260 DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
507 { .node_name = NULL }, 261 { .node_name = NULL },
508}; 262};
509 263
510static struct ti_dt_clk omap36xx_clks[] = {
511 DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"),
512 DT_CLK(NULL, "uart4_fck", "uart4_fck"),
513 DT_CLK(NULL, "uart4_ick", "uart4_ick"),
514 { .node_name = NULL },
515};
516
517static const char *enable_init_clks[] = { 264static const char *enable_init_clks[] = {
518 "sdrc_ick", 265 "sdrc_ick",
519 "gpmc_fck", 266 "gpmc_fck",
@@ -579,16 +326,10 @@ static int __init omap3xxx_dt_clk_init(int soc_type)
579 soc_type == OMAP3_SOC_OMAP3630) 326 soc_type == OMAP3_SOC_OMAP3630)
580 ti_dt_clocks_register(omap36xx_omap3430es2plus_clks); 327 ti_dt_clocks_register(omap36xx_omap3430es2plus_clks);
581 328
582 if (soc_type == OMAP3_SOC_OMAP3430_ES1 ||
583 soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
584 soc_type == OMAP3_SOC_OMAP3630)
585 ti_dt_clocks_register(omap34xx_omap36xx_clks);
586
587 if (soc_type == OMAP3_SOC_OMAP3630)
588 ti_dt_clocks_register(omap36xx_clks);
589
590 omap2_clk_disable_autoidle_all(); 329 omap2_clk_disable_autoidle_all();
591 330
331 ti_clk_add_aliases();
332
592 omap2_clk_enable_init_clocks(enable_init_clks, 333 omap2_clk_enable_init_clocks(enable_init_clks,
593 ARRAY_SIZE(enable_init_clks)); 334 ARRAY_SIZE(enable_init_clks));
594 335