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authorOlof Johansson <olof@lixom.net>2018-09-23 09:33:56 -0400
committerOlof Johansson <olof@lixom.net>2018-09-23 09:33:56 -0400
commit0ecee767ce76c90985dfcd162845ff5d1a2778d4 (patch)
tree04a70efe2c591ed2248e3d1a2a9564413e805447
parentda4cf9cdec9bdc68aaac0f1f0d171d32b05fa342 (diff)
parent3be9349f38c7dd7f108a71f640908a727101d2db (diff)
Merge tag 'ux500-dts-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt
Ux500 DTS changes for the v4.20 kernel cycle. Assorted housekeeping DTS patches. * tag 'ux500-dts-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: ARM: dts: ux500: Mark PRCMU as syscon compatible arm: dts: ste: Update coresight bindings for hardware port ARM: dts: ste: Fix SPI controller node names ARM: dts: ux500: Get rid of DTC warnings ARM: dts: ux500: Fix LCDA clock line muxing dt-bindings: arm: scu: Correct example SCU unit addresses ARM: dts: ux500: Correct SCU unit address Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/scu.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/ux500/boards.txt2
-rw-r--r--arch/arm/boot/dts/ste-dbx5x0.dtsi80
-rw-r--r--arch/arm/boot/dts/ste-href-family-pinctrl.dtsi8
-rw-r--r--arch/arm/boot/dts/ste-href.dtsi1
-rw-r--r--arch/arm/boot/dts/ste-hrefprev60.dtsi2
-rw-r--r--arch/arm/boot/dts/ste-snowball.dts3
-rw-r--r--arch/arm/boot/dts/ste-u300.dts2
8 files changed, 56 insertions, 44 deletions
diff --git a/Documentation/devicetree/bindings/arm/scu.txt b/Documentation/devicetree/bindings/arm/scu.txt
index 08a587875996..74d0a780ce51 100644
--- a/Documentation/devicetree/bindings/arm/scu.txt
+++ b/Documentation/devicetree/bindings/arm/scu.txt
@@ -22,7 +22,7 @@ References:
22 22
23Example: 23Example:
24 24
25scu@a04100000 { 25scu@a0410000 {
26 compatible = "arm,cortex-a9-scu"; 26 compatible = "arm,cortex-a9-scu";
27 reg = <0xa0410000 0x100>; 27 reg = <0xa0410000 0x100>;
28}; 28};
diff --git a/Documentation/devicetree/bindings/arm/ux500/boards.txt b/Documentation/devicetree/bindings/arm/ux500/boards.txt
index 0fa429534f49..89408de55bfd 100644
--- a/Documentation/devicetree/bindings/arm/ux500/boards.txt
+++ b/Documentation/devicetree/bindings/arm/ux500/boards.txt
@@ -60,7 +60,7 @@ Example:
60 <0xa0410100 0x100>; 60 <0xa0410100 0x100>;
61 }; 61 };
62 62
63 scu@a04100000 { 63 scu@a0410000 {
64 compatible = "arm,cortex-a9-scu"; 64 compatible = "arm,cortex-a9-scu";
65 reg = <0xa0410000 0x100>; 65 reg = <0xa0410000 0x100>;
66 }; 66 };
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index 2310a4e97768..e6ed7c0354a2 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -15,9 +15,14 @@
15#include <dt-bindings/arm/ux500_pm_domains.h> 15#include <dt-bindings/arm/ux500_pm_domains.h>
16#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/clock/ste-ab8500.h> 17#include <dt-bindings/clock/ste-ab8500.h>
18#include "skeleton.dtsi"
19 18
20/ { 19/ {
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 chosen {
24 };
25
21 cpus { 26 cpus {
22 #address-cells = <1>; 27 #address-cells = <1>;
23 #size-cells = <0>; 28 #size-cells = <0>;
@@ -67,9 +72,11 @@
67 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 72 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
68 clock-names = "apb_pclk", "atclk"; 73 clock-names = "apb_pclk", "atclk";
69 cpu = <&CPU0>; 74 cpu = <&CPU0>;
70 port { 75 out-ports {
71 ptm0_out_port: endpoint { 76 port {
72 remote-endpoint = <&funnel_in_port0>; 77 ptm0_out_port: endpoint {
78 remote-endpoint = <&funnel_in_port0>;
79 };
73 }; 80 };
74 }; 81 };
75 }; 82 };
@@ -81,9 +88,11 @@
81 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 88 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
82 clock-names = "apb_pclk", "atclk"; 89 clock-names = "apb_pclk", "atclk";
83 cpu = <&CPU1>; 90 cpu = <&CPU1>;
84 port { 91 out-ports {
85 ptm1_out_port: endpoint { 92 port {
86 remote-endpoint = <&funnel_in_port1>; 93 ptm1_out_port: endpoint {
94 remote-endpoint = <&funnel_in_port1>;
95 };
87 }; 96 };
88 }; 97 };
89 }; 98 };
@@ -94,32 +103,29 @@
94 103
95 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 104 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
96 clock-names = "apb_pclk", "atclk"; 105 clock-names = "apb_pclk", "atclk";
97 ports { 106 out-ports {
98 #address-cells = <1>; 107 port {
99 #size-cells = <0>;
100
101 /* funnel output ports */
102 port@0 {
103 reg = <0>;
104 funnel_out_port: endpoint { 108 funnel_out_port: endpoint {
105 remote-endpoint = 109 remote-endpoint =
106 <&replicator_in_port0>; 110 <&replicator_in_port0>;
107 }; 111 };
108 }; 112 };
113 };
109 114
110 /* funnel input ports */ 115 in-ports {
111 port@1 { 116 #address-cells = <1>;
117 #size-cells = <0>;
118
119 port@0 {
112 reg = <0>; 120 reg = <0>;
113 funnel_in_port0: endpoint { 121 funnel_in_port0: endpoint {
114 slave-mode;
115 remote-endpoint = <&ptm0_out_port>; 122 remote-endpoint = <&ptm0_out_port>;
116 }; 123 };
117 }; 124 };
118 125
119 port@2 { 126 port@1 {
120 reg = <1>; 127 reg = <1>;
121 funnel_in_port1: endpoint { 128 funnel_in_port1: endpoint {
122 slave-mode;
123 remote-endpoint = <&ptm1_out_port>; 129 remote-endpoint = <&ptm1_out_port>;
124 }; 130 };
125 }; 131 };
@@ -131,11 +137,10 @@
131 clocks = <&prcmu_clk PRCMU_APEATCLK>; 137 clocks = <&prcmu_clk PRCMU_APEATCLK>;
132 clock-names = "atclk"; 138 clock-names = "atclk";
133 139
134 ports { 140 out-ports {
135 #address-cells = <1>; 141 #address-cells = <1>;
136 #size-cells = <0>; 142 #size-cells = <0>;
137 143
138 /* replicator output ports */
139 port@0 { 144 port@0 {
140 reg = <0>; 145 reg = <0>;
141 replicator_out_port0: endpoint { 146 replicator_out_port0: endpoint {
@@ -148,12 +153,11 @@
148 remote-endpoint = <&etb_in_port>; 153 remote-endpoint = <&etb_in_port>;
149 }; 154 };
150 }; 155 };
156 };
151 157
152 /* replicator input port */ 158 in-ports {
153 port@2 { 159 port {
154 reg = <0>;
155 replicator_in_port0: endpoint { 160 replicator_in_port0: endpoint {
156 slave-mode;
157 remote-endpoint = <&funnel_out_port>; 161 remote-endpoint = <&funnel_out_port>;
158 }; 162 };
159 }; 163 };
@@ -166,10 +170,11 @@
166 170
167 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 171 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
168 clock-names = "apb_pclk", "atclk"; 172 clock-names = "apb_pclk", "atclk";
169 port { 173 in-ports {
170 tpiu_in_port: endpoint { 174 port {
171 slave-mode; 175 tpiu_in_port: endpoint {
172 remote-endpoint = <&replicator_out_port0>; 176 remote-endpoint = <&replicator_out_port0>;
177 };
173 }; 178 };
174 }; 179 };
175 }; 180 };
@@ -180,10 +185,11 @@
180 185
181 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 186 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
182 clock-names = "apb_pclk", "atclk"; 187 clock-names = "apb_pclk", "atclk";
183 port { 188 in-ports {
184 etb_in_port: endpoint { 189 port {
185 slave-mode; 190 etb_in_port: endpoint {
186 remote-endpoint = <&replicator_out_port1>; 191 remote-endpoint = <&replicator_out_port1>;
192 };
187 }; 193 };
188 }; 194 };
189 }; 195 };
@@ -197,7 +203,7 @@
197 <0xa0410100 0x100>; 203 <0xa0410100 0x100>;
198 }; 204 };
199 205
200 scu@a04100000 { 206 scu@a0410000 {
201 compatible = "arm,cortex-a9-scu"; 207 compatible = "arm,cortex-a9-scu";
202 reg = <0xa0410000 0x100>; 208 reg = <0xa0410000 0x100>;
203 }; 209 };
@@ -487,7 +493,7 @@
487 }; 493 };
488 494
489 prcmu: prcmu@80157000 { 495 prcmu: prcmu@80157000 {
490 compatible = "stericsson,db8500-prcmu"; 496 compatible = "stericsson,db8500-prcmu", "syscon";
491 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; 497 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
492 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; 498 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
493 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 499 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
@@ -878,7 +884,7 @@
878 power-domains = <&pm_domains DOMAIN_VAPE>; 884 power-domains = <&pm_domains DOMAIN_VAPE>;
879 }; 885 };
880 886
881 ssp@80002000 { 887 spi@80002000 {
882 compatible = "arm,pl022", "arm,primecell"; 888 compatible = "arm,pl022", "arm,primecell";
883 reg = <0x80002000 0x1000>; 889 reg = <0x80002000 0x1000>;
884 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 890 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@@ -892,7 +898,7 @@
892 power-domains = <&pm_domains DOMAIN_VAPE>; 898 power-domains = <&pm_domains DOMAIN_VAPE>;
893 }; 899 };
894 900
895 ssp@80003000 { 901 spi@80003000 {
896 compatible = "arm,pl022", "arm,primecell"; 902 compatible = "arm,pl022", "arm,primecell";
897 reg = <0x80003000 0x1000>; 903 reg = <0x80003000 0x1000>;
898 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 904 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
index 5c5cea232743..1ec193b0c506 100644
--- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
@@ -607,16 +607,20 @@
607 607
608 mcde { 608 mcde {
609 lcd_default_mode: lcd_default { 609 lcd_default_mode: lcd_default {
610 default_mux { 610 default_mux1 {
611 /* Mux in VSI0 and all the data lines */ 611 /* Mux in VSI0 and all the data lines */
612 function = "lcd"; 612 function = "lcd";
613 groups = 613 groups =
614 "lcdvsi0_a_1", /* VSI0 for LCD */ 614 "lcdvsi0_a_1", /* VSI0 for LCD */
615 "lcd_d0_d7_a_1", /* Data lines */ 615 "lcd_d0_d7_a_1", /* Data lines */
616 "lcd_d8_d11_a_1", /* TV-out */ 616 "lcd_d8_d11_a_1", /* TV-out */
617 "lcdaclk_b_1", /* Clock line for TV-out */
618 "lcdvsi1_a_1"; /* VSI1 for HDMI */ 617 "lcdvsi1_a_1"; /* VSI1 for HDMI */
619 }; 618 };
619 default_mux2 {
620 function = "lcda";
621 groups =
622 "lcdaclk_b_1"; /* Clock line for TV-out */
623 };
620 default_cfg1 { 624 default_cfg1 {
621 pins = 625 pins =
622 "GPIO68_E1", /* VSI0 */ 626 "GPIO68_E1", /* VSI0 */
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index 9e359e4f342e..feb682a3d363 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -15,6 +15,7 @@
15 15
16/ { 16/ {
17 memory { 17 memory {
18 device_type = "memory";
18 reg = <0x00000000 0x20000000>; 19 reg = <0x00000000 0x20000000>;
19 }; 20 };
20 21
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi
index 3f14b4df69b4..94eeb7f1c947 100644
--- a/arch/arm/boot/dts/ste-hrefprev60.dtsi
+++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi
@@ -57,7 +57,7 @@
57 }; 57 };
58 }; 58 };
59 59
60 ssp@80002000 { 60 spi@80002000 {
61 /* 61 /*
62 * On the first generation boards, this SSP/SPI port was connected 62 * On the first generation boards, this SSP/SPI port was connected
63 * to the AB8500. 63 * to the AB8500.
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index b0b94d053098..2de3ce79e496 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -26,6 +26,7 @@
26 }; 26 };
27 27
28 memory { 28 memory {
29 device_type = "memory";
29 reg = <0x00000000 0x20000000>; 30 reg = <0x00000000 0x20000000>;
30 }; 31 };
31 32
@@ -376,7 +377,7 @@
376 pinctrl-1 = <&i2c3_sleep_mode>; 377 pinctrl-1 = <&i2c3_sleep_mode>;
377 }; 378 };
378 379
379 ssp@80002000 { 380 spi@80002000 {
380 pinctrl-names = "default"; 381 pinctrl-names = "default";
381 pinctrl-0 = <&ssp0_snowball_mode>; 382 pinctrl-0 = <&ssp0_snowball_mode>;
382 }; 383 };
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 62ecb6a2fa39..1bd1aba3322f 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -442,7 +442,7 @@
442 dma-names = "rx"; 442 dma-names = "rx";
443 }; 443 };
444 444
445 spi: ssp@c0006000 { 445 spi: spi@c0006000 {
446 compatible = "arm,pl022", "arm,primecell"; 446 compatible = "arm,pl022", "arm,primecell";
447 reg = <0xc0006000 0x1000>; 447 reg = <0xc0006000 0x1000>;
448 interrupt-parent = <&vica>; 448 interrupt-parent = <&vica>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 03:00:29 -0400