diff options
author | Stephen Boyd <sboyd@codeaurora.org> | 2016-02-08 16:50:32 -0500 |
---|---|---|
committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-02-08 16:51:04 -0500 |
commit | 0e954fea5be056d13945a124bdf2b7e358d1554d (patch) | |
tree | 25902a15765dd309f344948de74b35eb7a087b14 | |
parent | 60c7e2d2edc7a2a3613540e18760a713359946f6 (diff) | |
parent | 5a1d5eff3ede4de4482015a9999336051054283f (diff) |
Merge tag 'tegra-for-4.5-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-fixes
Pull tegra fixes from Thierry Reding:
clk: tegra: Fixes for v4.5-rc3
This set contains a bunch of miscellaneous fixes that have accumulated
over the past couple of weeks, primarily for the Tegra210 support added
in v4.5-rc1.
* tag 'tegra-for-4.5-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: super: Fix sparse warnings for functions not declared as static
clk: tegra: Fix sparse warnings for functions not declared as static
clk: tegra: Fix sparse warning for pll_m
clk: tegra: Use definition for pll_u override bit
clk: tegra: Fix warning caused by pll_u failing to lock
clk: tegra: Fix clock sources for Tegra210 EMC
clk: tegra: Add the APB2APE audio clock on Tegra210
clk: tegra: Add missing of_node_put()
clk: tegra: Fix PLLE SS coefficients
clk: tegra: Fix typos around clearing PLLE bits during enable
clk: tegra: Do not disable PLLE when under hardware control
clk: tegra: Fix pllx dyn step calculation
clk: tegra: pll: Fix potential sleeping-while-atomic
clk: tegra: Fix the misnaming of nvenc from msenc
clk: tegra: Fix naming of MISC registers
clk: tegra: Remove improper flags for lock_enable
clk: tegra: Fix divider on VI_I2C
-rw-r--r-- | drivers/clk/tegra/clk-emc.c | 6 | ||||
-rw-r--r-- | drivers/clk/tegra/clk-id.h | 1 | ||||
-rw-r--r-- | drivers/clk/tegra/clk-pll.c | 50 | ||||
-rw-r--r-- | drivers/clk/tegra/clk-tegra-periph.c | 5 | ||||
-rw-r--r-- | drivers/clk/tegra/clk-tegra-super-gen4.c | 6 | ||||
-rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 132 | ||||
-rw-r--r-- | include/dt-bindings/clock/tegra210-car.h | 2 |
7 files changed, 104 insertions, 98 deletions
diff --git a/drivers/clk/tegra/clk-emc.c b/drivers/clk/tegra/clk-emc.c index e1fe8f35d45c..74e7544f861b 100644 --- a/drivers/clk/tegra/clk-emc.c +++ b/drivers/clk/tegra/clk-emc.c | |||
@@ -450,8 +450,10 @@ static int load_timings_from_dt(struct tegra_clk_emc *tegra, | |||
450 | struct emc_timing *timing = tegra->timings + (i++); | 450 | struct emc_timing *timing = tegra->timings + (i++); |
451 | 451 | ||
452 | err = load_one_timing_from_dt(tegra, timing, child); | 452 | err = load_one_timing_from_dt(tegra, timing, child); |
453 | if (err) | 453 | if (err) { |
454 | of_node_put(child); | ||
454 | return err; | 455 | return err; |
456 | } | ||
455 | 457 | ||
456 | timing->ram_code = ram_code; | 458 | timing->ram_code = ram_code; |
457 | } | 459 | } |
@@ -499,9 +501,9 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, | |||
499 | * fuses until the apbmisc driver is loaded. | 501 | * fuses until the apbmisc driver is loaded. |
500 | */ | 502 | */ |
501 | err = load_timings_from_dt(tegra, node, node_ram_code); | 503 | err = load_timings_from_dt(tegra, node, node_ram_code); |
504 | of_node_put(node); | ||
502 | if (err) | 505 | if (err) |
503 | return ERR_PTR(err); | 506 | return ERR_PTR(err); |
504 | of_node_put(node); | ||
505 | break; | 507 | break; |
506 | } | 508 | } |
507 | 509 | ||
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h index 19ce0738ee76..62ea38187b71 100644 --- a/drivers/clk/tegra/clk-id.h +++ b/drivers/clk/tegra/clk-id.h | |||
@@ -11,6 +11,7 @@ enum clk_id { | |||
11 | tegra_clk_afi, | 11 | tegra_clk_afi, |
12 | tegra_clk_amx, | 12 | tegra_clk_amx, |
13 | tegra_clk_amx1, | 13 | tegra_clk_amx1, |
14 | tegra_clk_apb2ape, | ||
14 | tegra_clk_apbdma, | 15 | tegra_clk_apbdma, |
15 | tegra_clk_apbif, | 16 | tegra_clk_apbif, |
16 | tegra_clk_ape, | 17 | tegra_clk_ape, |
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index a534bfab30b3..6ac3f843e7ca 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c | |||
@@ -86,15 +86,21 @@ | |||
86 | #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\ | 86 | #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\ |
87 | PLLE_SS_CNTL_SSC_BYP) | 87 | PLLE_SS_CNTL_SSC_BYP) |
88 | #define PLLE_SS_MAX_MASK 0x1ff | 88 | #define PLLE_SS_MAX_MASK 0x1ff |
89 | #define PLLE_SS_MAX_VAL 0x25 | 89 | #define PLLE_SS_MAX_VAL_TEGRA114 0x25 |
90 | #define PLLE_SS_MAX_VAL_TEGRA210 0x21 | ||
90 | #define PLLE_SS_INC_MASK (0xff << 16) | 91 | #define PLLE_SS_INC_MASK (0xff << 16) |
91 | #define PLLE_SS_INC_VAL (0x1 << 16) | 92 | #define PLLE_SS_INC_VAL (0x1 << 16) |
92 | #define PLLE_SS_INCINTRV_MASK (0x3f << 24) | 93 | #define PLLE_SS_INCINTRV_MASK (0x3f << 24) |
93 | #define PLLE_SS_INCINTRV_VAL (0x20 << 24) | 94 | #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24) |
95 | #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24) | ||
94 | #define PLLE_SS_COEFFICIENTS_MASK \ | 96 | #define PLLE_SS_COEFFICIENTS_MASK \ |
95 | (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) | 97 | (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) |
96 | #define PLLE_SS_COEFFICIENTS_VAL \ | 98 | #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \ |
97 | (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL) | 99 | (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\ |
100 | PLLE_SS_INCINTRV_VAL_TEGRA114) | ||
101 | #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \ | ||
102 | (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\ | ||
103 | PLLE_SS_INCINTRV_VAL_TEGRA210) | ||
98 | 104 | ||
99 | #define PLLE_AUX_PLLP_SEL BIT(2) | 105 | #define PLLE_AUX_PLLP_SEL BIT(2) |
100 | #define PLLE_AUX_USE_LOCKDET BIT(3) | 106 | #define PLLE_AUX_USE_LOCKDET BIT(3) |
@@ -880,7 +886,7 @@ static int clk_plle_training(struct tegra_clk_pll *pll) | |||
880 | static int clk_plle_enable(struct clk_hw *hw) | 886 | static int clk_plle_enable(struct clk_hw *hw) |
881 | { | 887 | { |
882 | struct tegra_clk_pll *pll = to_clk_pll(hw); | 888 | struct tegra_clk_pll *pll = to_clk_pll(hw); |
883 | unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); | 889 | unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); |
884 | struct tegra_clk_pll_freq_table sel; | 890 | struct tegra_clk_pll_freq_table sel; |
885 | u32 val; | 891 | u32 val; |
886 | int err; | 892 | int err; |
@@ -1378,7 +1384,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) | |||
1378 | u32 val; | 1384 | u32 val; |
1379 | int ret; | 1385 | int ret; |
1380 | unsigned long flags = 0; | 1386 | unsigned long flags = 0; |
1381 | unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); | 1387 | unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); |
1382 | 1388 | ||
1383 | if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) | 1389 | if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) |
1384 | return -EINVAL; | 1390 | return -EINVAL; |
@@ -1401,7 +1407,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) | |||
1401 | val |= PLLE_MISC_IDDQ_SW_CTRL; | 1407 | val |= PLLE_MISC_IDDQ_SW_CTRL; |
1402 | val &= ~PLLE_MISC_IDDQ_SW_VALUE; | 1408 | val &= ~PLLE_MISC_IDDQ_SW_VALUE; |
1403 | val |= PLLE_MISC_PLLE_PTS; | 1409 | val |= PLLE_MISC_PLLE_PTS; |
1404 | val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; | 1410 | val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK); |
1405 | pll_writel_misc(val, pll); | 1411 | pll_writel_misc(val, pll); |
1406 | udelay(5); | 1412 | udelay(5); |
1407 | 1413 | ||
@@ -1428,7 +1434,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) | |||
1428 | val = pll_readl(PLLE_SS_CTRL, pll); | 1434 | val = pll_readl(PLLE_SS_CTRL, pll); |
1429 | val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); | 1435 | val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); |
1430 | val &= ~PLLE_SS_COEFFICIENTS_MASK; | 1436 | val &= ~PLLE_SS_COEFFICIENTS_MASK; |
1431 | val |= PLLE_SS_COEFFICIENTS_VAL; | 1437 | val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114; |
1432 | pll_writel(val, PLLE_SS_CTRL, pll); | 1438 | pll_writel(val, PLLE_SS_CTRL, pll); |
1433 | val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); | 1439 | val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); |
1434 | pll_writel(val, PLLE_SS_CTRL, pll); | 1440 | pll_writel(val, PLLE_SS_CTRL, pll); |
@@ -2012,9 +2018,9 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) | |||
2012 | struct tegra_clk_pll *pll = to_clk_pll(hw); | 2018 | struct tegra_clk_pll *pll = to_clk_pll(hw); |
2013 | struct tegra_clk_pll_freq_table sel; | 2019 | struct tegra_clk_pll_freq_table sel; |
2014 | u32 val; | 2020 | u32 val; |
2015 | int ret; | 2021 | int ret = 0; |
2016 | unsigned long flags = 0; | 2022 | unsigned long flags = 0; |
2017 | unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); | 2023 | unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); |
2018 | 2024 | ||
2019 | if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) | 2025 | if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) |
2020 | return -EINVAL; | 2026 | return -EINVAL; |
@@ -2022,22 +2028,20 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) | |||
2022 | if (pll->lock) | 2028 | if (pll->lock) |
2023 | spin_lock_irqsave(pll->lock, flags); | 2029 | spin_lock_irqsave(pll->lock, flags); |
2024 | 2030 | ||
2031 | val = pll_readl(pll->params->aux_reg, pll); | ||
2032 | if (val & PLLE_AUX_SEQ_ENABLE) | ||
2033 | goto out; | ||
2034 | |||
2025 | val = pll_readl_base(pll); | 2035 | val = pll_readl_base(pll); |
2026 | val &= ~BIT(30); /* Disable lock override */ | 2036 | val &= ~BIT(30); /* Disable lock override */ |
2027 | pll_writel_base(val, pll); | 2037 | pll_writel_base(val, pll); |
2028 | 2038 | ||
2029 | val = pll_readl(pll->params->aux_reg, pll); | ||
2030 | val |= PLLE_AUX_ENABLE_SWCTL; | ||
2031 | val &= ~PLLE_AUX_SEQ_ENABLE; | ||
2032 | pll_writel(val, pll->params->aux_reg, pll); | ||
2033 | udelay(1); | ||
2034 | |||
2035 | val = pll_readl_misc(pll); | 2039 | val = pll_readl_misc(pll); |
2036 | val |= PLLE_MISC_LOCK_ENABLE; | 2040 | val |= PLLE_MISC_LOCK_ENABLE; |
2037 | val |= PLLE_MISC_IDDQ_SW_CTRL; | 2041 | val |= PLLE_MISC_IDDQ_SW_CTRL; |
2038 | val &= ~PLLE_MISC_IDDQ_SW_VALUE; | 2042 | val &= ~PLLE_MISC_IDDQ_SW_VALUE; |
2039 | val |= PLLE_MISC_PLLE_PTS; | 2043 | val |= PLLE_MISC_PLLE_PTS; |
2040 | val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; | 2044 | val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK); |
2041 | pll_writel_misc(val, pll); | 2045 | pll_writel_misc(val, pll); |
2042 | udelay(5); | 2046 | udelay(5); |
2043 | 2047 | ||
@@ -2067,7 +2071,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) | |||
2067 | val = pll_readl(PLLE_SS_CTRL, pll); | 2071 | val = pll_readl(PLLE_SS_CTRL, pll); |
2068 | val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); | 2072 | val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); |
2069 | val &= ~PLLE_SS_COEFFICIENTS_MASK; | 2073 | val &= ~PLLE_SS_COEFFICIENTS_MASK; |
2070 | val |= PLLE_SS_COEFFICIENTS_VAL; | 2074 | val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210; |
2071 | pll_writel(val, PLLE_SS_CTRL, pll); | 2075 | pll_writel(val, PLLE_SS_CTRL, pll); |
2072 | val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); | 2076 | val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); |
2073 | pll_writel(val, PLLE_SS_CTRL, pll); | 2077 | pll_writel(val, PLLE_SS_CTRL, pll); |
@@ -2104,15 +2108,25 @@ static void clk_plle_tegra210_disable(struct clk_hw *hw) | |||
2104 | if (pll->lock) | 2108 | if (pll->lock) |
2105 | spin_lock_irqsave(pll->lock, flags); | 2109 | spin_lock_irqsave(pll->lock, flags); |
2106 | 2110 | ||
2111 | /* If PLLE HW sequencer is enabled, SW should not disable PLLE */ | ||
2112 | val = pll_readl(pll->params->aux_reg, pll); | ||
2113 | if (val & PLLE_AUX_SEQ_ENABLE) | ||
2114 | goto out; | ||
2115 | |||
2107 | val = pll_readl_base(pll); | 2116 | val = pll_readl_base(pll); |
2108 | val &= ~PLLE_BASE_ENABLE; | 2117 | val &= ~PLLE_BASE_ENABLE; |
2109 | pll_writel_base(val, pll); | 2118 | pll_writel_base(val, pll); |
2110 | 2119 | ||
2120 | val = pll_readl(pll->params->aux_reg, pll); | ||
2121 | val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL; | ||
2122 | pll_writel(val, pll->params->aux_reg, pll); | ||
2123 | |||
2111 | val = pll_readl_misc(pll); | 2124 | val = pll_readl_misc(pll); |
2112 | val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; | 2125 | val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; |
2113 | pll_writel_misc(val, pll); | 2126 | pll_writel_misc(val, pll); |
2114 | udelay(1); | 2127 | udelay(1); |
2115 | 2128 | ||
2129 | out: | ||
2116 | if (pll->lock) | 2130 | if (pll->lock) |
2117 | spin_unlock_irqrestore(pll->lock, flags); | 2131 | spin_unlock_irqrestore(pll->lock, flags); |
2118 | } | 2132 | } |
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index 6ad381a888a6..ea2b9cbf9e70 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c | |||
@@ -773,7 +773,7 @@ static struct tegra_periph_init_data periph_clks[] = { | |||
773 | XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src), | 773 | XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src), |
774 | XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8), | 774 | XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8), |
775 | MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb), | 775 | MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb), |
776 | MUX8("msenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc), | 776 | MUX8("nvenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc), |
777 | MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec), | 777 | MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec), |
778 | MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg), | 778 | MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg), |
779 | MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape), | 779 | MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape), |
@@ -782,7 +782,7 @@ static struct tegra_periph_init_data periph_clks[] = { | |||
782 | NODIV("sor1", mux_clkm_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 15, MASK(1), 183, 0, tegra_clk_sor1, &sor1_lock), | 782 | NODIV("sor1", mux_clkm_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 15, MASK(1), 183, 0, tegra_clk_sor1, &sor1_lock), |
783 | MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy), | 783 | MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy), |
784 | MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi), | 784 | MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi), |
785 | MUX("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, TEGRA_PERIPH_ON_APB, tegra_clk_vi_i2c), | 785 | I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c), |
786 | MUX("mipibif", mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif), | 786 | MUX("mipibif", mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif), |
787 | MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape), | 787 | MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape), |
788 | MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb), | 788 | MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb), |
@@ -829,6 +829,7 @@ static struct tegra_periph_init_data gate_clks[] = { | |||
829 | GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0), | 829 | GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0), |
830 | GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0), | 830 | GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0), |
831 | GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0), | 831 | GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0), |
832 | GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0), | ||
832 | }; | 833 | }; |
833 | 834 | ||
834 | static struct tegra_periph_init_data div_clks[] = { | 835 | static struct tegra_periph_init_data div_clks[] = { |
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c index 4559a20e3af6..474de0f0c26d 100644 --- a/drivers/clk/tegra/clk-tegra-super-gen4.c +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c | |||
@@ -67,7 +67,7 @@ static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", | |||
67 | "pll_p", "pll_p_out4", "unused", | 67 | "pll_p", "pll_p_out4", "unused", |
68 | "unused", "pll_x", "pll_x_out0" }; | 68 | "unused", "pll_x", "pll_x_out0" }; |
69 | 69 | ||
70 | const struct tegra_super_gen_info tegra_super_gen_info_gen4 = { | 70 | static const struct tegra_super_gen_info tegra_super_gen_info_gen4 = { |
71 | .gen = gen4, | 71 | .gen = gen4, |
72 | .sclk_parents = sclk_parents, | 72 | .sclk_parents = sclk_parents, |
73 | .cclk_g_parents = cclk_g_parents, | 73 | .cclk_g_parents = cclk_g_parents, |
@@ -93,7 +93,7 @@ static const char *cclk_lp_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unu | |||
93 | "unused", "unused", "unused", "unused", | 93 | "unused", "unused", "unused", "unused", |
94 | "dfllCPU_out" }; | 94 | "dfllCPU_out" }; |
95 | 95 | ||
96 | const struct tegra_super_gen_info tegra_super_gen_info_gen5 = { | 96 | static const struct tegra_super_gen_info tegra_super_gen_info_gen5 = { |
97 | .gen = gen5, | 97 | .gen = gen5, |
98 | .sclk_parents = sclk_parents_gen5, | 98 | .sclk_parents = sclk_parents_gen5, |
99 | .cclk_g_parents = cclk_g_parents_gen5, | 99 | .cclk_g_parents = cclk_g_parents_gen5, |
@@ -171,7 +171,7 @@ static void __init tegra_sclk_init(void __iomem *clk_base, | |||
171 | *dt_clk = clk; | 171 | *dt_clk = clk; |
172 | } | 172 | } |
173 | 173 | ||
174 | void __init tegra_super_clk_init(void __iomem *clk_base, | 174 | static void __init tegra_super_clk_init(void __iomem *clk_base, |
175 | void __iomem *pmc_base, | 175 | void __iomem *pmc_base, |
176 | struct tegra_clk *tegra_clks, | 176 | struct tegra_clk *tegra_clks, |
177 | struct tegra_clk_pll_params *params, | 177 | struct tegra_clk_pll_params *params, |
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 58514c44ea83..637041fd53ad 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c | |||
@@ -59,8 +59,8 @@ | |||
59 | #define PLLC3_MISC3 0x50c | 59 | #define PLLC3_MISC3 0x50c |
60 | 60 | ||
61 | #define PLLM_BASE 0x90 | 61 | #define PLLM_BASE 0x90 |
62 | #define PLLM_MISC0 0x9c | ||
63 | #define PLLM_MISC1 0x98 | 62 | #define PLLM_MISC1 0x98 |
63 | #define PLLM_MISC2 0x9c | ||
64 | #define PLLP_BASE 0xa0 | 64 | #define PLLP_BASE 0xa0 |
65 | #define PLLP_MISC0 0xac | 65 | #define PLLP_MISC0 0xac |
66 | #define PLLP_MISC1 0x680 | 66 | #define PLLP_MISC1 0x680 |
@@ -99,7 +99,7 @@ | |||
99 | #define PLLC4_MISC0 0x5a8 | 99 | #define PLLC4_MISC0 0x5a8 |
100 | #define PLLC4_OUT 0x5e4 | 100 | #define PLLC4_OUT 0x5e4 |
101 | #define PLLMB_BASE 0x5e8 | 101 | #define PLLMB_BASE 0x5e8 |
102 | #define PLLMB_MISC0 0x5ec | 102 | #define PLLMB_MISC1 0x5ec |
103 | #define PLLA1_BASE 0x6a4 | 103 | #define PLLA1_BASE 0x6a4 |
104 | #define PLLA1_MISC0 0x6a8 | 104 | #define PLLA1_MISC0 0x6a8 |
105 | #define PLLA1_MISC1 0x6ac | 105 | #define PLLA1_MISC1 0x6ac |
@@ -243,7 +243,8 @@ static unsigned long tegra210_input_freq[] = { | |||
243 | }; | 243 | }; |
244 | 244 | ||
245 | static const char *mux_pllmcp_clkm[] = { | 245 | static const char *mux_pllmcp_clkm[] = { |
246 | "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3", | 246 | "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb", |
247 | "pll_p", | ||
247 | }; | 248 | }; |
248 | #define mux_pllmcp_clkm_idx NULL | 249 | #define mux_pllmcp_clkm_idx NULL |
249 | 250 | ||
@@ -367,12 +368,12 @@ static const char *mux_pllmcp_clkm[] = { | |||
367 | /* PLLMB */ | 368 | /* PLLMB */ |
368 | #define PLLMB_BASE_LOCK (1 << 27) | 369 | #define PLLMB_BASE_LOCK (1 << 27) |
369 | 370 | ||
370 | #define PLLMB_MISC0_LOCK_OVERRIDE (1 << 18) | 371 | #define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18) |
371 | #define PLLMB_MISC0_IDDQ (1 << 17) | 372 | #define PLLMB_MISC1_IDDQ (1 << 17) |
372 | #define PLLMB_MISC0_LOCK_ENABLE (1 << 16) | 373 | #define PLLMB_MISC1_LOCK_ENABLE (1 << 16) |
373 | 374 | ||
374 | #define PLLMB_MISC0_DEFAULT_VALUE 0x00030000 | 375 | #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000 |
375 | #define PLLMB_MISC0_WRITE_MASK 0x0007ffff | 376 | #define PLLMB_MISC1_WRITE_MASK 0x0007ffff |
376 | 377 | ||
377 | /* PLLP */ | 378 | /* PLLP */ |
378 | #define PLLP_BASE_OVERRIDE (1 << 28) | 379 | #define PLLP_BASE_OVERRIDE (1 << 28) |
@@ -457,7 +458,8 @@ static void pllcx_check_defaults(struct tegra_clk_pll_params *params) | |||
457 | PLLCX_MISC3_WRITE_MASK); | 458 | PLLCX_MISC3_WRITE_MASK); |
458 | } | 459 | } |
459 | 460 | ||
460 | void tegra210_pllcx_set_defaults(const char *name, struct tegra_clk_pll *pllcx) | 461 | static void tegra210_pllcx_set_defaults(const char *name, |
462 | struct tegra_clk_pll *pllcx) | ||
461 | { | 463 | { |
462 | pllcx->params->defaults_set = true; | 464 | pllcx->params->defaults_set = true; |
463 | 465 | ||
@@ -482,22 +484,22 @@ void tegra210_pllcx_set_defaults(const char *name, struct tegra_clk_pll *pllcx) | |||
482 | udelay(1); | 484 | udelay(1); |
483 | } | 485 | } |
484 | 486 | ||
485 | void _pllc_set_defaults(struct tegra_clk_pll *pllcx) | 487 | static void _pllc_set_defaults(struct tegra_clk_pll *pllcx) |
486 | { | 488 | { |
487 | tegra210_pllcx_set_defaults("PLL_C", pllcx); | 489 | tegra210_pllcx_set_defaults("PLL_C", pllcx); |
488 | } | 490 | } |
489 | 491 | ||
490 | void _pllc2_set_defaults(struct tegra_clk_pll *pllcx) | 492 | static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx) |
491 | { | 493 | { |
492 | tegra210_pllcx_set_defaults("PLL_C2", pllcx); | 494 | tegra210_pllcx_set_defaults("PLL_C2", pllcx); |
493 | } | 495 | } |
494 | 496 | ||
495 | void _pllc3_set_defaults(struct tegra_clk_pll *pllcx) | 497 | static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx) |
496 | { | 498 | { |
497 | tegra210_pllcx_set_defaults("PLL_C3", pllcx); | 499 | tegra210_pllcx_set_defaults("PLL_C3", pllcx); |
498 | } | 500 | } |
499 | 501 | ||
500 | void _plla1_set_defaults(struct tegra_clk_pll *pllcx) | 502 | static void _plla1_set_defaults(struct tegra_clk_pll *pllcx) |
501 | { | 503 | { |
502 | tegra210_pllcx_set_defaults("PLL_A1", pllcx); | 504 | tegra210_pllcx_set_defaults("PLL_A1", pllcx); |
503 | } | 505 | } |
@@ -507,7 +509,7 @@ void _plla1_set_defaults(struct tegra_clk_pll *pllcx) | |||
507 | * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used. | 509 | * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used. |
508 | * Fractional SDM is allowed to provide exact audio rates. | 510 | * Fractional SDM is allowed to provide exact audio rates. |
509 | */ | 511 | */ |
510 | void tegra210_plla_set_defaults(struct tegra_clk_pll *plla) | 512 | static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla) |
511 | { | 513 | { |
512 | u32 mask; | 514 | u32 mask; |
513 | u32 val = readl_relaxed(clk_base + plla->params->base_reg); | 515 | u32 val = readl_relaxed(clk_base + plla->params->base_reg); |
@@ -559,7 +561,7 @@ void tegra210_plla_set_defaults(struct tegra_clk_pll *plla) | |||
559 | * PLLD | 561 | * PLLD |
560 | * PLL with fractional SDM. | 562 | * PLL with fractional SDM. |
561 | */ | 563 | */ |
562 | void tegra210_plld_set_defaults(struct tegra_clk_pll *plld) | 564 | static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld) |
563 | { | 565 | { |
564 | u32 val; | 566 | u32 val; |
565 | u32 mask = 0xffff; | 567 | u32 mask = 0xffff; |
@@ -698,7 +700,7 @@ static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss, | |||
698 | udelay(1); | 700 | udelay(1); |
699 | } | 701 | } |
700 | 702 | ||
701 | void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2) | 703 | static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2) |
702 | { | 704 | { |
703 | plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE, | 705 | plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE, |
704 | PLLD2_MISC1_CFG_DEFAULT_VALUE, | 706 | PLLD2_MISC1_CFG_DEFAULT_VALUE, |
@@ -706,7 +708,7 @@ void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2) | |||
706 | PLLD2_MISC3_CTRL2_DEFAULT_VALUE); | 708 | PLLD2_MISC3_CTRL2_DEFAULT_VALUE); |
707 | } | 709 | } |
708 | 710 | ||
709 | void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp) | 711 | static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp) |
710 | { | 712 | { |
711 | plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE, | 713 | plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE, |
712 | PLLDP_MISC1_CFG_DEFAULT_VALUE, | 714 | PLLDP_MISC1_CFG_DEFAULT_VALUE, |
@@ -719,7 +721,7 @@ void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp) | |||
719 | * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support. | 721 | * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support. |
720 | * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers. | 722 | * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers. |
721 | */ | 723 | */ |
722 | void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4) | 724 | static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4) |
723 | { | 725 | { |
724 | plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0); | 726 | plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0); |
725 | } | 727 | } |
@@ -728,7 +730,7 @@ void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4) | |||
728 | * PLLRE | 730 | * PLLRE |
729 | * VCO is exposed to the clock tree directly along with post-divider output | 731 | * VCO is exposed to the clock tree directly along with post-divider output |
730 | */ | 732 | */ |
731 | void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre) | 733 | static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre) |
732 | { | 734 | { |
733 | u32 mask; | 735 | u32 mask; |
734 | u32 val = readl_relaxed(clk_base + pllre->params->base_reg); | 736 | u32 val = readl_relaxed(clk_base + pllre->params->base_reg); |
@@ -780,13 +782,13 @@ static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b) | |||
780 | { | 782 | { |
781 | unsigned long input_rate; | 783 | unsigned long input_rate; |
782 | 784 | ||
783 | if (!IS_ERR_OR_NULL(hw->clk)) { | 785 | /* cf rate */ |
786 | if (!IS_ERR_OR_NULL(hw->clk)) | ||
784 | input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); | 787 | input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); |
785 | /* cf rate */ | 788 | else |
786 | input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); | ||
787 | } else { | ||
788 | input_rate = 38400000; | 789 | input_rate = 38400000; |
789 | } | 790 | |
791 | input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); | ||
790 | 792 | ||
791 | switch (input_rate) { | 793 | switch (input_rate) { |
792 | case 12000000: | 794 | case 12000000: |
@@ -841,7 +843,7 @@ static void pllx_check_defaults(struct tegra_clk_pll *pll) | |||
841 | PLLX_MISC5_WRITE_MASK); | 843 | PLLX_MISC5_WRITE_MASK); |
842 | } | 844 | } |
843 | 845 | ||
844 | void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx) | 846 | static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx) |
845 | { | 847 | { |
846 | u32 val; | 848 | u32 val; |
847 | u32 step_a, step_b; | 849 | u32 step_a, step_b; |
@@ -901,7 +903,7 @@ void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx) | |||
901 | } | 903 | } |
902 | 904 | ||
903 | /* PLLMB */ | 905 | /* PLLMB */ |
904 | void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb) | 906 | static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb) |
905 | { | 907 | { |
906 | u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg); | 908 | u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg); |
907 | 909 | ||
@@ -914,15 +916,15 @@ void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb) | |||
914 | * PLL is ON: check if defaults already set, then set those | 916 | * PLL is ON: check if defaults already set, then set those |
915 | * that can be updated in flight. | 917 | * that can be updated in flight. |
916 | */ | 918 | */ |
917 | val = PLLMB_MISC0_DEFAULT_VALUE & (~PLLMB_MISC0_IDDQ); | 919 | val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ); |
918 | mask = PLLMB_MISC0_LOCK_ENABLE | PLLMB_MISC0_LOCK_OVERRIDE; | 920 | mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE; |
919 | _pll_misc_chk_default(clk_base, pllmb->params, 0, val, | 921 | _pll_misc_chk_default(clk_base, pllmb->params, 0, val, |
920 | ~mask & PLLMB_MISC0_WRITE_MASK); | 922 | ~mask & PLLMB_MISC1_WRITE_MASK); |
921 | 923 | ||
922 | /* Enable lock detect */ | 924 | /* Enable lock detect */ |
923 | val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); | 925 | val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); |
924 | val &= ~mask; | 926 | val &= ~mask; |
925 | val |= PLLMB_MISC0_DEFAULT_VALUE & mask; | 927 | val |= PLLMB_MISC1_DEFAULT_VALUE & mask; |
926 | writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); | 928 | writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); |
927 | udelay(1); | 929 | udelay(1); |
928 | 930 | ||
@@ -930,7 +932,7 @@ void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb) | |||
930 | } | 932 | } |
931 | 933 | ||
932 | /* set IDDQ, enable lock detect */ | 934 | /* set IDDQ, enable lock detect */ |
933 | writel_relaxed(PLLMB_MISC0_DEFAULT_VALUE, | 935 | writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE, |
934 | clk_base + pllmb->params->ext_misc_reg[0]); | 936 | clk_base + pllmb->params->ext_misc_reg[0]); |
935 | udelay(1); | 937 | udelay(1); |
936 | } | 938 | } |
@@ -960,7 +962,7 @@ static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled) | |||
960 | ~mask & PLLP_MISC1_WRITE_MASK); | 962 | ~mask & PLLP_MISC1_WRITE_MASK); |
961 | } | 963 | } |
962 | 964 | ||
963 | void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp) | 965 | static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp) |
964 | { | 966 | { |
965 | u32 mask; | 967 | u32 mask; |
966 | u32 val = readl_relaxed(clk_base + pllp->params->base_reg); | 968 | u32 val = readl_relaxed(clk_base + pllp->params->base_reg); |
@@ -1022,7 +1024,7 @@ static void pllu_check_defaults(struct tegra_clk_pll *pll, bool hw_control) | |||
1022 | ~mask & PLLU_MISC1_WRITE_MASK); | 1024 | ~mask & PLLU_MISC1_WRITE_MASK); |
1023 | } | 1025 | } |
1024 | 1026 | ||
1025 | void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu) | 1027 | static void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu) |
1026 | { | 1028 | { |
1027 | u32 val = readl_relaxed(clk_base + pllu->params->base_reg); | 1029 | u32 val = readl_relaxed(clk_base + pllu->params->base_reg); |
1028 | 1030 | ||
@@ -1212,8 +1214,9 @@ static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg) | |||
1212 | cfg->m *= PLL_SDM_COEFF; | 1214 | cfg->m *= PLL_SDM_COEFF; |
1213 | } | 1215 | } |
1214 | 1216 | ||
1215 | unsigned long tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params, | 1217 | static unsigned long |
1216 | unsigned long parent_rate) | 1218 | tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params, |
1219 | unsigned long parent_rate) | ||
1217 | { | 1220 | { |
1218 | unsigned long vco_min = params->vco_min; | 1221 | unsigned long vco_min = params->vco_min; |
1219 | 1222 | ||
@@ -1386,7 +1389,7 @@ static struct tegra_clk_pll_params pll_c_params = { | |||
1386 | .mdiv_default = 3, | 1389 | .mdiv_default = 3, |
1387 | .div_nmp = &pllc_nmp, | 1390 | .div_nmp = &pllc_nmp, |
1388 | .freq_table = pll_cx_freq_table, | 1391 | .freq_table = pll_cx_freq_table, |
1389 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, | 1392 | .flags = TEGRA_PLL_USE_LOCK, |
1390 | .set_defaults = _pllc_set_defaults, | 1393 | .set_defaults = _pllc_set_defaults, |
1391 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | 1394 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
1392 | }; | 1395 | }; |
@@ -1425,7 +1428,7 @@ static struct tegra_clk_pll_params pll_c2_params = { | |||
1425 | .ext_misc_reg[2] = PLLC2_MISC2, | 1428 | .ext_misc_reg[2] = PLLC2_MISC2, |
1426 | .ext_misc_reg[3] = PLLC2_MISC3, | 1429 | .ext_misc_reg[3] = PLLC2_MISC3, |
1427 | .freq_table = pll_cx_freq_table, | 1430 | .freq_table = pll_cx_freq_table, |
1428 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, | 1431 | .flags = TEGRA_PLL_USE_LOCK, |
1429 | .set_defaults = _pllc2_set_defaults, | 1432 | .set_defaults = _pllc2_set_defaults, |
1430 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | 1433 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
1431 | }; | 1434 | }; |
@@ -1455,7 +1458,7 @@ static struct tegra_clk_pll_params pll_c3_params = { | |||
1455 | .ext_misc_reg[2] = PLLC3_MISC2, | 1458 | .ext_misc_reg[2] = PLLC3_MISC2, |
1456 | .ext_misc_reg[3] = PLLC3_MISC3, | 1459 | .ext_misc_reg[3] = PLLC3_MISC3, |
1457 | .freq_table = pll_cx_freq_table, | 1460 | .freq_table = pll_cx_freq_table, |
1458 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, | 1461 | .flags = TEGRA_PLL_USE_LOCK, |
1459 | .set_defaults = _pllc3_set_defaults, | 1462 | .set_defaults = _pllc3_set_defaults, |
1460 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | 1463 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
1461 | }; | 1464 | }; |
@@ -1505,7 +1508,6 @@ static struct tegra_clk_pll_params pll_c4_vco_params = { | |||
1505 | .base_reg = PLLC4_BASE, | 1508 | .base_reg = PLLC4_BASE, |
1506 | .misc_reg = PLLC4_MISC0, | 1509 | .misc_reg = PLLC4_MISC0, |
1507 | .lock_mask = PLL_BASE_LOCK, | 1510 | .lock_mask = PLL_BASE_LOCK, |
1508 | .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, | ||
1509 | .lock_delay = 300, | 1511 | .lock_delay = 300, |
1510 | .max_p = PLL_QLIN_PDIV_MAX, | 1512 | .max_p = PLL_QLIN_PDIV_MAX, |
1511 | .ext_misc_reg[0] = PLLC4_MISC0, | 1513 | .ext_misc_reg[0] = PLLC4_MISC0, |
@@ -1517,8 +1519,7 @@ static struct tegra_clk_pll_params pll_c4_vco_params = { | |||
1517 | .div_nmp = &pllss_nmp, | 1519 | .div_nmp = &pllss_nmp, |
1518 | .freq_table = pll_c4_vco_freq_table, | 1520 | .freq_table = pll_c4_vco_freq_table, |
1519 | .set_defaults = tegra210_pllc4_set_defaults, | 1521 | .set_defaults = tegra210_pllc4_set_defaults, |
1520 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE | | 1522 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, |
1521 | TEGRA_PLL_VCO_OUT, | ||
1522 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | 1523 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
1523 | }; | 1524 | }; |
1524 | 1525 | ||
@@ -1559,15 +1560,15 @@ static struct tegra_clk_pll_params pll_m_params = { | |||
1559 | .vco_min = 800000000, | 1560 | .vco_min = 800000000, |
1560 | .vco_max = 1866000000, | 1561 | .vco_max = 1866000000, |
1561 | .base_reg = PLLM_BASE, | 1562 | .base_reg = PLLM_BASE, |
1562 | .misc_reg = PLLM_MISC1, | 1563 | .misc_reg = PLLM_MISC2, |
1563 | .lock_mask = PLL_BASE_LOCK, | 1564 | .lock_mask = PLL_BASE_LOCK, |
1564 | .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE, | 1565 | .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE, |
1565 | .lock_delay = 300, | 1566 | .lock_delay = 300, |
1566 | .iddq_reg = PLLM_MISC0, | 1567 | .iddq_reg = PLLM_MISC2, |
1567 | .iddq_bit_idx = PLLM_IDDQ_BIT, | 1568 | .iddq_bit_idx = PLLM_IDDQ_BIT, |
1568 | .max_p = PLL_QLIN_PDIV_MAX, | 1569 | .max_p = PLL_QLIN_PDIV_MAX, |
1569 | .ext_misc_reg[0] = PLLM_MISC0, | 1570 | .ext_misc_reg[0] = PLLM_MISC2, |
1570 | .ext_misc_reg[0] = PLLM_MISC1, | 1571 | .ext_misc_reg[1] = PLLM_MISC1, |
1571 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | 1572 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, |
1572 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | 1573 | .pdiv_tohw = pll_qlin_pdiv_to_hw, |
1573 | .div_nmp = &pllm_nmp, | 1574 | .div_nmp = &pllm_nmp, |
@@ -1586,19 +1587,18 @@ static struct tegra_clk_pll_params pll_mb_params = { | |||
1586 | .vco_min = 800000000, | 1587 | .vco_min = 800000000, |
1587 | .vco_max = 1866000000, | 1588 | .vco_max = 1866000000, |
1588 | .base_reg = PLLMB_BASE, | 1589 | .base_reg = PLLMB_BASE, |
1589 | .misc_reg = PLLMB_MISC0, | 1590 | .misc_reg = PLLMB_MISC1, |
1590 | .lock_mask = PLL_BASE_LOCK, | 1591 | .lock_mask = PLL_BASE_LOCK, |
1591 | .lock_enable_bit_idx = PLLMB_MISC_LOCK_ENABLE, | ||
1592 | .lock_delay = 300, | 1592 | .lock_delay = 300, |
1593 | .iddq_reg = PLLMB_MISC0, | 1593 | .iddq_reg = PLLMB_MISC1, |
1594 | .iddq_bit_idx = PLLMB_IDDQ_BIT, | 1594 | .iddq_bit_idx = PLLMB_IDDQ_BIT, |
1595 | .max_p = PLL_QLIN_PDIV_MAX, | 1595 | .max_p = PLL_QLIN_PDIV_MAX, |
1596 | .ext_misc_reg[0] = PLLMB_MISC0, | 1596 | .ext_misc_reg[0] = PLLMB_MISC1, |
1597 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | 1597 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, |
1598 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | 1598 | .pdiv_tohw = pll_qlin_pdiv_to_hw, |
1599 | .div_nmp = &pllm_nmp, | 1599 | .div_nmp = &pllm_nmp, |
1600 | .freq_table = pll_m_freq_table, | 1600 | .freq_table = pll_m_freq_table, |
1601 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, | 1601 | .flags = TEGRA_PLL_USE_LOCK, |
1602 | .set_defaults = tegra210_pllmb_set_defaults, | 1602 | .set_defaults = tegra210_pllmb_set_defaults, |
1603 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | 1603 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
1604 | }; | 1604 | }; |
@@ -1671,7 +1671,6 @@ static struct tegra_clk_pll_params pll_re_vco_params = { | |||
1671 | .base_reg = PLLRE_BASE, | 1671 | .base_reg = PLLRE_BASE, |
1672 | .misc_reg = PLLRE_MISC0, | 1672 | .misc_reg = PLLRE_MISC0, |
1673 | .lock_mask = PLLRE_MISC_LOCK, | 1673 | .lock_mask = PLLRE_MISC_LOCK, |
1674 | .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE, | ||
1675 | .lock_delay = 300, | 1674 | .lock_delay = 300, |
1676 | .max_p = PLL_QLIN_PDIV_MAX, | 1675 | .max_p = PLL_QLIN_PDIV_MAX, |
1677 | .ext_misc_reg[0] = PLLRE_MISC0, | 1676 | .ext_misc_reg[0] = PLLRE_MISC0, |
@@ -1681,8 +1680,7 @@ static struct tegra_clk_pll_params pll_re_vco_params = { | |||
1681 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | 1680 | .pdiv_tohw = pll_qlin_pdiv_to_hw, |
1682 | .div_nmp = &pllre_nmp, | 1681 | .div_nmp = &pllre_nmp, |
1683 | .freq_table = pll_re_vco_freq_table, | 1682 | .freq_table = pll_re_vco_freq_table, |
1684 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | | 1683 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT, |
1685 | TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_VCO_OUT, | ||
1686 | .set_defaults = tegra210_pllre_set_defaults, | 1684 | .set_defaults = tegra210_pllre_set_defaults, |
1687 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | 1685 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
1688 | }; | 1686 | }; |
@@ -1712,7 +1710,6 @@ static struct tegra_clk_pll_params pll_p_params = { | |||
1712 | .base_reg = PLLP_BASE, | 1710 | .base_reg = PLLP_BASE, |
1713 | .misc_reg = PLLP_MISC0, | 1711 | .misc_reg = PLLP_MISC0, |
1714 | .lock_mask = PLL_BASE_LOCK, | 1712 | .lock_mask = PLL_BASE_LOCK, |
1715 | .lock_enable_bit_idx = PLLP_MISC_LOCK_ENABLE, | ||
1716 | .lock_delay = 300, | 1713 | .lock_delay = 300, |
1717 | .iddq_reg = PLLP_MISC0, | 1714 | .iddq_reg = PLLP_MISC0, |
1718 | .iddq_bit_idx = PLLXP_IDDQ_BIT, | 1715 | .iddq_bit_idx = PLLXP_IDDQ_BIT, |
@@ -1721,8 +1718,7 @@ static struct tegra_clk_pll_params pll_p_params = { | |||
1721 | .div_nmp = &pllp_nmp, | 1718 | .div_nmp = &pllp_nmp, |
1722 | .freq_table = pll_p_freq_table, | 1719 | .freq_table = pll_p_freq_table, |
1723 | .fixed_rate = 408000000, | 1720 | .fixed_rate = 408000000, |
1724 | .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | | 1721 | .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, |
1725 | TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_VCO_OUT, | ||
1726 | .set_defaults = tegra210_pllp_set_defaults, | 1722 | .set_defaults = tegra210_pllp_set_defaults, |
1727 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | 1723 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
1728 | }; | 1724 | }; |
@@ -1750,7 +1746,7 @@ static struct tegra_clk_pll_params pll_a1_params = { | |||
1750 | .ext_misc_reg[2] = PLLA1_MISC2, | 1746 | .ext_misc_reg[2] = PLLA1_MISC2, |
1751 | .ext_misc_reg[3] = PLLA1_MISC3, | 1747 | .ext_misc_reg[3] = PLLA1_MISC3, |
1752 | .freq_table = pll_cx_freq_table, | 1748 | .freq_table = pll_cx_freq_table, |
1753 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, | 1749 | .flags = TEGRA_PLL_USE_LOCK, |
1754 | .set_defaults = _plla1_set_defaults, | 1750 | .set_defaults = _plla1_set_defaults, |
1755 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | 1751 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
1756 | }; | 1752 | }; |
@@ -1787,7 +1783,6 @@ static struct tegra_clk_pll_params pll_a_params = { | |||
1787 | .base_reg = PLLA_BASE, | 1783 | .base_reg = PLLA_BASE, |
1788 | .misc_reg = PLLA_MISC0, | 1784 | .misc_reg = PLLA_MISC0, |
1789 | .lock_mask = PLL_BASE_LOCK, | 1785 | .lock_mask = PLL_BASE_LOCK, |
1790 | .lock_enable_bit_idx = PLLA_MISC_LOCK_ENABLE, | ||
1791 | .lock_delay = 300, | 1786 | .lock_delay = 300, |
1792 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | 1787 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, |
1793 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | 1788 | .pdiv_tohw = pll_qlin_pdiv_to_hw, |
@@ -1802,8 +1797,7 @@ static struct tegra_clk_pll_params pll_a_params = { | |||
1802 | .ext_misc_reg[1] = PLLA_MISC1, | 1797 | .ext_misc_reg[1] = PLLA_MISC1, |
1803 | .ext_misc_reg[2] = PLLA_MISC2, | 1798 | .ext_misc_reg[2] = PLLA_MISC2, |
1804 | .freq_table = pll_a_freq_table, | 1799 | .freq_table = pll_a_freq_table, |
1805 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW | | 1800 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW, |
1806 | TEGRA_PLL_HAS_LOCK_ENABLE, | ||
1807 | .set_defaults = tegra210_plla_set_defaults, | 1801 | .set_defaults = tegra210_plla_set_defaults, |
1808 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | 1802 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
1809 | .set_gain = tegra210_clk_pll_set_gain, | 1803 | .set_gain = tegra210_clk_pll_set_gain, |
@@ -1836,7 +1830,6 @@ static struct tegra_clk_pll_params pll_d_params = { | |||
1836 | .base_reg = PLLD_BASE, | 1830 | .base_reg = PLLD_BASE, |
1837 | .misc_reg = PLLD_MISC0, | 1831 | .misc_reg = PLLD_MISC0, |
1838 | .lock_mask = PLL_BASE_LOCK, | 1832 | .lock_mask = PLL_BASE_LOCK, |
1839 | .lock_enable_bit_idx = PLLD_MISC_LOCK_ENABLE, | ||
1840 | .lock_delay = 1000, | 1833 | .lock_delay = 1000, |
1841 | .iddq_reg = PLLD_MISC0, | 1834 | .iddq_reg = PLLD_MISC0, |
1842 | .iddq_bit_idx = PLLD_IDDQ_BIT, | 1835 | .iddq_bit_idx = PLLD_IDDQ_BIT, |
@@ -1850,7 +1843,7 @@ static struct tegra_clk_pll_params pll_d_params = { | |||
1850 | .ext_misc_reg[0] = PLLD_MISC0, | 1843 | .ext_misc_reg[0] = PLLD_MISC0, |
1851 | .ext_misc_reg[1] = PLLD_MISC1, | 1844 | .ext_misc_reg[1] = PLLD_MISC1, |
1852 | .freq_table = pll_d_freq_table, | 1845 | .freq_table = pll_d_freq_table, |
1853 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, | 1846 | .flags = TEGRA_PLL_USE_LOCK, |
1854 | .mdiv_default = 1, | 1847 | .mdiv_default = 1, |
1855 | .set_defaults = tegra210_plld_set_defaults, | 1848 | .set_defaults = tegra210_plld_set_defaults, |
1856 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | 1849 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
@@ -1876,7 +1869,6 @@ static struct tegra_clk_pll_params pll_d2_params = { | |||
1876 | .base_reg = PLLD2_BASE, | 1869 | .base_reg = PLLD2_BASE, |
1877 | .misc_reg = PLLD2_MISC0, | 1870 | .misc_reg = PLLD2_MISC0, |
1878 | .lock_mask = PLL_BASE_LOCK, | 1871 | .lock_mask = PLL_BASE_LOCK, |
1879 | .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, | ||
1880 | .lock_delay = 300, | 1872 | .lock_delay = 300, |
1881 | .iddq_reg = PLLD2_BASE, | 1873 | .iddq_reg = PLLD2_BASE, |
1882 | .iddq_bit_idx = PLLSS_IDDQ_BIT, | 1874 | .iddq_bit_idx = PLLSS_IDDQ_BIT, |
@@ -1897,7 +1889,7 @@ static struct tegra_clk_pll_params pll_d2_params = { | |||
1897 | .mdiv_default = 1, | 1889 | .mdiv_default = 1, |
1898 | .freq_table = tegra210_pll_d2_freq_table, | 1890 | .freq_table = tegra210_pll_d2_freq_table, |
1899 | .set_defaults = tegra210_plld2_set_defaults, | 1891 | .set_defaults = tegra210_plld2_set_defaults, |
1900 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, | 1892 | .flags = TEGRA_PLL_USE_LOCK, |
1901 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | 1893 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
1902 | .set_gain = tegra210_clk_pll_set_gain, | 1894 | .set_gain = tegra210_clk_pll_set_gain, |
1903 | .adjust_vco = tegra210_clk_adjust_vco_min, | 1895 | .adjust_vco = tegra210_clk_adjust_vco_min, |
@@ -1920,7 +1912,6 @@ static struct tegra_clk_pll_params pll_dp_params = { | |||
1920 | .base_reg = PLLDP_BASE, | 1912 | .base_reg = PLLDP_BASE, |
1921 | .misc_reg = PLLDP_MISC, | 1913 | .misc_reg = PLLDP_MISC, |
1922 | .lock_mask = PLL_BASE_LOCK, | 1914 | .lock_mask = PLL_BASE_LOCK, |
1923 | .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, | ||
1924 | .lock_delay = 300, | 1915 | .lock_delay = 300, |
1925 | .iddq_reg = PLLDP_BASE, | 1916 | .iddq_reg = PLLDP_BASE, |
1926 | .iddq_bit_idx = PLLSS_IDDQ_BIT, | 1917 | .iddq_bit_idx = PLLSS_IDDQ_BIT, |
@@ -1941,7 +1932,7 @@ static struct tegra_clk_pll_params pll_dp_params = { | |||
1941 | .mdiv_default = 1, | 1932 | .mdiv_default = 1, |
1942 | .freq_table = pll_dp_freq_table, | 1933 | .freq_table = pll_dp_freq_table, |
1943 | .set_defaults = tegra210_plldp_set_defaults, | 1934 | .set_defaults = tegra210_plldp_set_defaults, |
1944 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, | 1935 | .flags = TEGRA_PLL_USE_LOCK, |
1945 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | 1936 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
1946 | .set_gain = tegra210_clk_pll_set_gain, | 1937 | .set_gain = tegra210_clk_pll_set_gain, |
1947 | .adjust_vco = tegra210_clk_adjust_vco_min, | 1938 | .adjust_vco = tegra210_clk_adjust_vco_min, |
@@ -1973,7 +1964,6 @@ static struct tegra_clk_pll_params pll_u_vco_params = { | |||
1973 | .base_reg = PLLU_BASE, | 1964 | .base_reg = PLLU_BASE, |
1974 | .misc_reg = PLLU_MISC0, | 1965 | .misc_reg = PLLU_MISC0, |
1975 | .lock_mask = PLL_BASE_LOCK, | 1966 | .lock_mask = PLL_BASE_LOCK, |
1976 | .lock_enable_bit_idx = PLLU_MISC_LOCK_ENABLE, | ||
1977 | .lock_delay = 1000, | 1967 | .lock_delay = 1000, |
1978 | .iddq_reg = PLLU_MISC0, | 1968 | .iddq_reg = PLLU_MISC0, |
1979 | .iddq_bit_idx = PLLU_IDDQ_BIT, | 1969 | .iddq_bit_idx = PLLU_IDDQ_BIT, |
@@ -1983,8 +1973,7 @@ static struct tegra_clk_pll_params pll_u_vco_params = { | |||
1983 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | 1973 | .pdiv_tohw = pll_qlin_pdiv_to_hw, |
1984 | .div_nmp = &pllu_nmp, | 1974 | .div_nmp = &pllu_nmp, |
1985 | .freq_table = pll_u_freq_table, | 1975 | .freq_table = pll_u_freq_table, |
1986 | .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE | | 1976 | .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, |
1987 | TEGRA_PLL_VCO_OUT, | ||
1988 | .set_defaults = tegra210_pllu_set_defaults, | 1977 | .set_defaults = tegra210_pllu_set_defaults, |
1989 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | 1978 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
1990 | }; | 1979 | }; |
@@ -2218,6 +2207,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { | |||
2218 | [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true }, | 2207 | [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true }, |
2219 | [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true }, | 2208 | [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true }, |
2220 | [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true }, | 2209 | [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true }, |
2210 | [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true }, | ||
2221 | }; | 2211 | }; |
2222 | 2212 | ||
2223 | static struct tegra_devclk devclks[] __initdata = { | 2213 | static struct tegra_devclk devclks[] __initdata = { |
@@ -2519,7 +2509,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base, | |||
2519 | 2509 | ||
2520 | /* PLLU_VCO */ | 2510 | /* PLLU_VCO */ |
2521 | val = readl(clk_base + pll_u_vco_params.base_reg); | 2511 | val = readl(clk_base + pll_u_vco_params.base_reg); |
2522 | val &= ~BIT(24); /* disable PLLU_OVERRIDE */ | 2512 | val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */ |
2523 | writel(val, clk_base + pll_u_vco_params.base_reg); | 2513 | writel(val, clk_base + pll_u_vco_params.base_reg); |
2524 | 2514 | ||
2525 | clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc, | 2515 | clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc, |
@@ -2738,8 +2728,6 @@ static struct tegra_clk_init_table init_table[] __initdata = { | |||
2738 | { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 }, | 2728 | { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 }, |
2739 | { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 }, | 2729 | { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 }, |
2740 | { TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 }, | 2730 | { TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 }, |
2741 | { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 }, | ||
2742 | { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 }, | ||
2743 | { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 }, | 2731 | { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 }, |
2744 | { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 }, | 2732 | { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 }, |
2745 | { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 }, | 2733 | { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 }, |
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 6f45aea49e4f..0a05b0d36ae7 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h | |||
@@ -126,7 +126,7 @@ | |||
126 | /* 104 */ | 126 | /* 104 */ |
127 | /* 105 */ | 127 | /* 105 */ |
128 | #define TEGRA210_CLK_D_AUDIO 106 | 128 | #define TEGRA210_CLK_D_AUDIO 106 |
129 | /* 107 ( affects abp -> ape) */ | 129 | #define TEGRA210_CLK_APB2APE 107 |
130 | /* 108 */ | 130 | /* 108 */ |
131 | /* 109 */ | 131 | /* 109 */ |
132 | /* 110 */ | 132 | /* 110 */ |