diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-02-28 06:05:13 -0500 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-03-03 19:02:28 -0500 |
| commit | 0e836c3bea7da04cd4e2ed22d8c20654d5a09273 (patch) | |
| tree | 3df4c9edc1e22522291c871d4508ad4c54344e20 | |
| parent | daad4d2a0a60b0b2879e66194100b43c41e96ca9 (diff) | |
spi: sh-msiof: Restrict bits per word to 8/16/24/32 on R-Car Gen2/3
While the MSIOF variants in older SuperH and SH/R-Mobile SoCs support
bits-per-word values in the full range 8..32, the variants present in
R-Car Gen2 and Gen3 SoCs are restricted to 8, 16, 24, or 32.
Obtain the value from family-specific sh_msiof_chipdata to fix this.
Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | drivers/spi/spi-sh-msiof.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index b20e70a2bdd1..e2eb466db10a 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c | |||
| @@ -32,6 +32,7 @@ | |||
| 32 | #include <asm/unaligned.h> | 32 | #include <asm/unaligned.h> |
| 33 | 33 | ||
| 34 | struct sh_msiof_chipdata { | 34 | struct sh_msiof_chipdata { |
| 35 | u32 bits_per_word_mask; | ||
| 35 | u16 tx_fifo_size; | 36 | u16 tx_fifo_size; |
| 36 | u16 rx_fifo_size; | 37 | u16 rx_fifo_size; |
| 37 | u16 ctlr_flags; | 38 | u16 ctlr_flags; |
| @@ -1048,6 +1049,7 @@ static int sh_msiof_transfer_one(struct spi_controller *ctlr, | |||
| 1048 | } | 1049 | } |
| 1049 | 1050 | ||
| 1050 | static const struct sh_msiof_chipdata sh_data = { | 1051 | static const struct sh_msiof_chipdata sh_data = { |
| 1052 | .bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32), | ||
| 1051 | .tx_fifo_size = 64, | 1053 | .tx_fifo_size = 64, |
| 1052 | .rx_fifo_size = 64, | 1054 | .rx_fifo_size = 64, |
| 1053 | .ctlr_flags = 0, | 1055 | .ctlr_flags = 0, |
| @@ -1055,6 +1057,8 @@ static const struct sh_msiof_chipdata sh_data = { | |||
| 1055 | }; | 1057 | }; |
| 1056 | 1058 | ||
| 1057 | static const struct sh_msiof_chipdata rcar_gen2_data = { | 1059 | static const struct sh_msiof_chipdata rcar_gen2_data = { |
| 1060 | .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | | ||
| 1061 | SPI_BPW_MASK(24) | SPI_BPW_MASK(32), | ||
| 1058 | .tx_fifo_size = 64, | 1062 | .tx_fifo_size = 64, |
| 1059 | .rx_fifo_size = 64, | 1063 | .rx_fifo_size = 64, |
| 1060 | .ctlr_flags = SPI_CONTROLLER_MUST_TX, | 1064 | .ctlr_flags = SPI_CONTROLLER_MUST_TX, |
| @@ -1062,6 +1066,8 @@ static const struct sh_msiof_chipdata rcar_gen2_data = { | |||
| 1062 | }; | 1066 | }; |
| 1063 | 1067 | ||
| 1064 | static const struct sh_msiof_chipdata rcar_gen3_data = { | 1068 | static const struct sh_msiof_chipdata rcar_gen3_data = { |
| 1069 | .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | | ||
| 1070 | SPI_BPW_MASK(24) | SPI_BPW_MASK(32), | ||
| 1065 | .tx_fifo_size = 64, | 1071 | .tx_fifo_size = 64, |
| 1066 | .rx_fifo_size = 64, | 1072 | .rx_fifo_size = 64, |
| 1067 | .ctlr_flags = SPI_CONTROLLER_MUST_TX, | 1073 | .ctlr_flags = SPI_CONTROLLER_MUST_TX, |
| @@ -1386,7 +1392,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) | |||
| 1386 | ctlr->setup = sh_msiof_spi_setup; | 1392 | ctlr->setup = sh_msiof_spi_setup; |
| 1387 | ctlr->prepare_message = sh_msiof_prepare_message; | 1393 | ctlr->prepare_message = sh_msiof_prepare_message; |
| 1388 | ctlr->slave_abort = sh_msiof_slave_abort; | 1394 | ctlr->slave_abort = sh_msiof_slave_abort; |
| 1389 | ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); | 1395 | ctlr->bits_per_word_mask = chipdata->bits_per_word_mask; |
| 1390 | ctlr->auto_runtime_pm = true; | 1396 | ctlr->auto_runtime_pm = true; |
| 1391 | ctlr->transfer_one = sh_msiof_transfer_one; | 1397 | ctlr->transfer_one = sh_msiof_transfer_one; |
| 1392 | 1398 | ||
