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authorSteven Eckhoff <steven.eckhoff.opensource@gmail.com>2018-05-31 16:24:07 -0400
committerMark Brown <broonie@kernel.org>2018-06-01 07:05:30 -0400
commit0e725b483bbed3c6178c3928fd9b62dadc2eb240 (patch)
treebdad4748194fc12fe092a0d1e5707fae3abb5414
parent56c3a95385df558a471f7fcedba73c9ed836a906 (diff)
ASoC: TSCS454: Add Support
Currently there is no support for Tempo Semiconductor's TSCS454 CODEC. Add support for it. Signed-off-by: Steven Eckhoff <steven.eckhoff.opensource@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/sound/tscs454.txt23
-rw-r--r--sound/soc/codecs/Kconfig8
-rw-r--r--sound/soc/codecs/Makefile2
-rw-r--r--sound/soc/codecs/tscs454.c3497
-rw-r--r--sound/soc/codecs/tscs454.h2323
5 files changed, 5853 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/sound/tscs454.txt b/Documentation/devicetree/bindings/sound/tscs454.txt
new file mode 100644
index 000000000000..3ba3e2d2c206
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tscs454.txt
@@ -0,0 +1,23 @@
1TSCS454 Audio CODEC
2
3Required Properties:
4
5 - compatible : "tempo,tscs454"
6
7 - reg : <0x69>
8
9 - clock-names: Must one of the following "xtal", "mclk1", "mclk2"
10
11 - clocks: phandle of the clock that provides the codec sysclk
12
13 Note: If clock is not provided then bit clock is assumed
14
15Example:
16
17redwood: codec@69 {
18 #sound-dai-cells = <1>;
19 compatible = "tempo,tscs454";
20 reg = <0x69>;
21 clock-names = "mclk1";
22 clocks = <&audio_mclk>;
23};
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 55a989d15b46..63cf62e9c9aa 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -172,6 +172,7 @@ config SND_SOC_ALL_CODECS
172 select SND_SOC_TPA6130A2 if I2C 172 select SND_SOC_TPA6130A2 if I2C
173 select SND_SOC_TLV320DAC33 if I2C 173 select SND_SOC_TLV320DAC33 if I2C
174 select SND_SOC_TSCS42XX if I2C 174 select SND_SOC_TSCS42XX if I2C
175 select SND_SOC_TSCS454 if I2C
175 select SND_SOC_TS3A227E if I2C 176 select SND_SOC_TS3A227E if I2C
176 select SND_SOC_TWL4030 if TWL4030_CORE 177 select SND_SOC_TWL4030 if TWL4030_CORE
177 select SND_SOC_TWL6040 if TWL6040_CORE 178 select SND_SOC_TWL6040 if TWL6040_CORE
@@ -1031,6 +1032,13 @@ config SND_SOC_TSCS42XX
1031 help 1032 help
1032 Add support for Tempo Semiconductor's TSCS42xx audio CODEC. 1033 Add support for Tempo Semiconductor's TSCS42xx audio CODEC.
1033 1034
1035config SND_SOC_TSCS454
1036 tristate "Tempo Semiconductor TSCS454 CODEC"
1037 depends on I2C
1038 select REGMAP_I2C
1039 help
1040 Add support for Tempo Semiconductor's TSCS454 audio CODEC.
1041
1034config SND_SOC_TWL4030 1042config SND_SOC_TWL4030
1035 select MFD_TWL4030_AUDIO 1043 select MFD_TWL4030_AUDIO
1036 tristate 1044 tristate
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 4c85f3391705..e023fdf85221 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -184,6 +184,7 @@ snd-soc-tlv320aic32x4-spi-objs := tlv320aic32x4-spi.o
184snd-soc-tlv320aic3x-objs := tlv320aic3x.o 184snd-soc-tlv320aic3x-objs := tlv320aic3x.o
185snd-soc-tlv320dac33-objs := tlv320dac33.o 185snd-soc-tlv320dac33-objs := tlv320dac33.o
186snd-soc-tscs42xx-objs := tscs42xx.o 186snd-soc-tscs42xx-objs := tscs42xx.o
187snd-soc-tscs454-objs := tscs454.o
187snd-soc-ts3a227e-objs := ts3a227e.o 188snd-soc-ts3a227e-objs := ts3a227e.o
188snd-soc-twl4030-objs := twl4030.o 189snd-soc-twl4030-objs := twl4030.o
189snd-soc-twl6040-objs := twl6040.o 190snd-soc-twl6040-objs := twl6040.o
@@ -440,6 +441,7 @@ obj-$(CONFIG_SND_SOC_TLV320AIC32X4_SPI) += snd-soc-tlv320aic32x4-spi.o
440obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o 441obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o
441obj-$(CONFIG_SND_SOC_TLV320DAC33) += snd-soc-tlv320dac33.o 442obj-$(CONFIG_SND_SOC_TLV320DAC33) += snd-soc-tlv320dac33.o
442obj-$(CONFIG_SND_SOC_TSCS42XX) += snd-soc-tscs42xx.o 443obj-$(CONFIG_SND_SOC_TSCS42XX) += snd-soc-tscs42xx.o
444obj-$(CONFIG_SND_SOC_TSCS454) += snd-soc-tscs454.o
443obj-$(CONFIG_SND_SOC_TS3A227E) += snd-soc-ts3a227e.o 445obj-$(CONFIG_SND_SOC_TS3A227E) += snd-soc-ts3a227e.o
444obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o 446obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o
445obj-$(CONFIG_SND_SOC_TWL6040) += snd-soc-twl6040.o 447obj-$(CONFIG_SND_SOC_TWL6040) += snd-soc-twl6040.o
diff --git a/sound/soc/codecs/tscs454.c b/sound/soc/codecs/tscs454.c
new file mode 100644
index 000000000000..ff85a0bf6170
--- /dev/null
+++ b/sound/soc/codecs/tscs454.c
@@ -0,0 +1,3497 @@
1// SPDX-License-Identifier: GPL-2.0
2// tscs454.c -- TSCS454 ALSA SoC Audio driver
3// Copyright 2018 Tempo Semiconductor, Inc.
4// Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com>
5
6#include <linux/kernel.h>
7#include <linux/clk.h>
8#include <linux/device.h>
9#include <linux/regmap.h>
10#include <linux/i2c.h>
11#include <linux/err.h>
12#include <linux/string.h>
13#include <linux/module.h>
14#include <linux/delay.h>
15#include <linux/mutex.h>
16
17#include <sound/tlv.h>
18#include <sound/pcm_params.h>
19#include <sound/pcm.h>
20#include <sound/soc.h>
21#include <sound/soc-dapm.h>
22
23#include "tscs454.h"
24
25static const unsigned int PLL_48K_RATE = (48000 * 256);
26static const unsigned int PLL_44_1K_RATE = (44100 * 256);
27
28#define COEFF_SIZE 3
29#define BIQUAD_COEFF_COUNT 5
30#define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT)
31
32#define COEFF_RAM_MAX_ADDR 0xcd
33#define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1)
34#define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT)
35
36enum {
37 TSCS454_DAI1_ID,
38 TSCS454_DAI2_ID,
39 TSCS454_DAI3_ID,
40 TSCS454_DAI_COUNT,
41};
42
43struct pll {
44 int id;
45 unsigned int users;
46 struct mutex lock;
47};
48
49static inline void pll_init(struct pll *pll, int id)
50{
51 pll->id = id;
52 mutex_init(&pll->lock);
53}
54
55struct internal_rate {
56 struct pll *pll;
57};
58
59struct aif {
60 unsigned int id;
61 bool master;
62 struct pll *pll;
63};
64
65static inline void aif_init(struct aif *aif, unsigned int id)
66{
67 aif->id = id;
68}
69
70struct coeff_ram {
71 u8 cache[COEFF_RAM_SIZE];
72 bool synced;
73 struct mutex lock;
74};
75
76static inline void init_coeff_ram_cache(u8 *cache)
77{
78 static const u8 norm_addrs[] = { 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19,
79 0x1f, 0x20, 0x25, 0x2a, 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45,
80 0x4a, 0x4f, 0x54, 0x59, 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74,
81 0x79, 0x7f, 0x80, 0x85, 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3,
82 0xa8, 0xad, 0xaf, 0xb0, 0xb5, 0xba, 0xbf, 0xc4, 0xc9};
83 int i;
84
85 for (i = 0; i < ARRAY_SIZE(norm_addrs); i++)
86 cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40;
87}
88
89static inline void coeff_ram_init(struct coeff_ram *ram)
90{
91 init_coeff_ram_cache(ram->cache);
92 mutex_init(&ram->lock);
93}
94
95struct aifs_status {
96 u8 streams;
97};
98
99static inline void set_aif_status_active(struct aifs_status *status,
100 int aif_id, bool playback)
101{
102 u8 mask = 0x01 << (aif_id * 2 + !playback);
103
104 status->streams |= mask;
105}
106
107static inline void set_aif_status_inactive(struct aifs_status *status,
108 int aif_id, bool playback)
109{
110 u8 mask = ~(0x01 << (aif_id * 2 + !playback));
111
112 status->streams &= mask;
113}
114
115static bool aifs_active(struct aifs_status *status)
116{
117 return status->streams;
118}
119
120static bool aif_active(struct aifs_status *status, int aif_id)
121{
122 return (0x03 << aif_id * 2) & status->streams;
123}
124
125struct tscs454 {
126 struct regmap *regmap;
127 struct aif aifs[TSCS454_DAI_COUNT];
128
129 struct aifs_status aifs_status;
130 struct mutex aifs_status_lock;
131
132 struct pll pll1;
133 struct pll pll2;
134 struct internal_rate internal_rate;
135
136 struct coeff_ram dac_ram;
137 struct coeff_ram spk_ram;
138 struct coeff_ram sub_ram;
139
140 struct clk *sysclk;
141 int sysclk_src_id;
142 unsigned int bclk_freq;
143};
144
145struct coeff_ram_ctl {
146 unsigned int addr;
147 struct soc_bytes_ext bytes_ext;
148};
149
150static const struct reg_sequence tscs454_patch[] = {
151 /* Assign ASRC out of the box so DAI 1 just works */
152 { R_AUDIOMUX1, FV_ASRCIMUX_I2S1 | FV_I2S2MUX_I2S2 },
153 { R_AUDIOMUX2, FV_ASRCOMUX_I2S1 | FV_DACMUX_I2S1 | FV_I2S3MUX_I2S3 },
154 { R_AUDIOMUX3, FV_CLSSDMUX_I2S1 | FV_SUBMUX_I2S1_LR },
155 { R_TDMCTL0, FV_TDMMD_256 },
156 { VIRT_ADDR(0x0A, 0x13), 1 << 3 },
157};
158
159static bool tscs454_volatile(struct device *dev, unsigned int reg)
160{
161 switch (reg) {
162 case R_PLLSTAT:
163
164 case R_SPKCRRDL:
165 case R_SPKCRRDM:
166 case R_SPKCRRDH:
167 case R_SPKCRS:
168
169 case R_DACCRRDL:
170 case R_DACCRRDM:
171 case R_DACCRRDH:
172 case R_DACCRS:
173
174 case R_SUBCRRDL:
175 case R_SUBCRRDM:
176 case R_SUBCRRDH:
177 case R_SUBCRS:
178 return true;
179 default:
180 return false;
181 };
182}
183
184static bool tscs454_writable(struct device *dev, unsigned int reg)
185{
186 switch (reg) {
187 case R_SPKCRRDL:
188 case R_SPKCRRDM:
189 case R_SPKCRRDH:
190
191 case R_DACCRRDL:
192 case R_DACCRRDM:
193 case R_DACCRRDH:
194
195 case R_SUBCRRDL:
196 case R_SUBCRRDM:
197 case R_SUBCRRDH:
198 return false;
199 default:
200 return true;
201 };
202}
203
204static bool tscs454_readable(struct device *dev, unsigned int reg)
205{
206 switch (reg) {
207 case R_SPKCRWDL:
208 case R_SPKCRWDM:
209 case R_SPKCRWDH:
210
211 case R_DACCRWDL:
212 case R_DACCRWDM:
213 case R_DACCRWDH:
214
215 case R_SUBCRWDL:
216 case R_SUBCRWDM:
217 case R_SUBCRWDH:
218 return false;
219 default:
220 return true;
221 };
222}
223
224static bool tscs454_precious(struct device *dev, unsigned int reg)
225{
226 switch (reg) {
227 case R_SPKCRWDL:
228 case R_SPKCRWDM:
229 case R_SPKCRWDH:
230 case R_SPKCRRDL:
231 case R_SPKCRRDM:
232 case R_SPKCRRDH:
233
234 case R_DACCRWDL:
235 case R_DACCRWDM:
236 case R_DACCRWDH:
237 case R_DACCRRDL:
238 case R_DACCRRDM:
239 case R_DACCRRDH:
240
241 case R_SUBCRWDL:
242 case R_SUBCRWDM:
243 case R_SUBCRWDH:
244 case R_SUBCRRDL:
245 case R_SUBCRRDM:
246 case R_SUBCRRDH:
247 return true;
248 default:
249 return false;
250 };
251}
252
253static const struct regmap_range_cfg tscs454_regmap_range_cfg = {
254 .name = "Pages",
255 .range_min = VIRT_BASE,
256 .range_max = VIRT_ADDR(0xFE, 0x02),
257 .selector_reg = R_PAGESEL,
258 .selector_mask = 0xff,
259 .selector_shift = 0,
260 .window_start = 0,
261 .window_len = 0x100,
262};
263
264static struct regmap_config const tscs454_regmap_cfg = {
265 .reg_bits = 8,
266 .val_bits = 8,
267 .writeable_reg = tscs454_writable,
268 .readable_reg = tscs454_readable,
269 .volatile_reg = tscs454_volatile,
270 .precious_reg = tscs454_precious,
271 .ranges = &tscs454_regmap_range_cfg,
272 .num_ranges = 1,
273 .max_register = VIRT_ADDR(0xFE, 0x02),
274 .cache_type = REGCACHE_RBTREE,
275};
276
277static inline int tscs454_data_init(struct tscs454 *tscs454,
278 struct i2c_client *i2c)
279{
280 int i;
281 int ret;
282
283 tscs454->regmap = devm_regmap_init_i2c(i2c, &tscs454_regmap_cfg);
284 if (IS_ERR(tscs454->regmap)) {
285 ret = PTR_ERR(tscs454->regmap);
286 return ret;
287 }
288
289 for (i = 0; i < TSCS454_DAI_COUNT; i++)
290 aif_init(&tscs454->aifs[i], i);
291
292 mutex_init(&tscs454->aifs_status_lock);
293 pll_init(&tscs454->pll1, 1);
294 pll_init(&tscs454->pll2, 2);
295
296 coeff_ram_init(&tscs454->dac_ram);
297 coeff_ram_init(&tscs454->spk_ram);
298 coeff_ram_init(&tscs454->sub_ram);
299
300 return 0;
301}
302
303struct reg_setting {
304 unsigned int addr;
305 unsigned int val;
306};
307
308static int coeff_ram_get(struct snd_kcontrol *kcontrol,
309 struct snd_ctl_elem_value *ucontrol)
310{
311 struct snd_soc_component *component =
312 snd_soc_kcontrol_component(kcontrol);
313 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
314 struct coeff_ram_ctl *ctl =
315 (struct coeff_ram_ctl *)kcontrol->private_value;
316 struct soc_bytes_ext *params = &ctl->bytes_ext;
317 u8 *coeff_ram;
318 struct mutex *coeff_ram_lock;
319
320 if (strstr(kcontrol->id.name, "DAC")) {
321 coeff_ram = tscs454->dac_ram.cache;
322 coeff_ram_lock = &tscs454->dac_ram.lock;
323 } else if (strstr(kcontrol->id.name, "Speaker")) {
324 coeff_ram = tscs454->spk_ram.cache;
325 coeff_ram_lock = &tscs454->spk_ram.lock;
326 } else if (strstr(kcontrol->id.name, "Sub")) {
327 coeff_ram = tscs454->sub_ram.cache;
328 coeff_ram_lock = &tscs454->sub_ram.lock;
329 } else {
330 return -EINVAL;
331 }
332
333 mutex_lock(coeff_ram_lock);
334
335 memcpy(ucontrol->value.bytes.data,
336 &coeff_ram[ctl->addr * COEFF_SIZE], params->max);
337
338 mutex_unlock(coeff_ram_lock);
339
340 return 0;
341}
342
343#define DACCRSTAT_MAX_TRYS 10
344static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram,
345 unsigned int r_stat, unsigned int r_addr, unsigned int r_wr,
346 unsigned int coeff_addr, unsigned int coeff_cnt)
347{
348 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
349 unsigned int val;
350 int cnt;
351 int trys;
352 int ret;
353
354 for (cnt = 0; cnt < coeff_cnt; cnt++, coeff_addr++) {
355
356 for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) {
357 ret = snd_soc_component_read(component, r_stat, &val);
358 if (ret < 0) {
359 dev_err(component->dev,
360 "Failed to read stat (%d)\n", ret);
361 return ret;
362 }
363 if (!val)
364 break;
365 }
366
367 if (trys == DACCRSTAT_MAX_TRYS) {
368 ret = -EIO;
369 dev_err(component->dev,
370 "Coefficient write error (%d)\n", ret);
371 return ret;
372 }
373
374 ret = regmap_write(tscs454->regmap, r_addr, coeff_addr);
375 if (ret < 0) {
376 dev_err(component->dev,
377 "Failed to write dac ram address (%d)\n", ret);
378 return ret;
379 }
380
381 ret = regmap_bulk_write(tscs454->regmap, r_wr,
382 &coeff_ram[coeff_addr * COEFF_SIZE],
383 COEFF_SIZE);
384 if (ret < 0) {
385 dev_err(component->dev,
386 "Failed to write dac ram (%d)\n", ret);
387 return ret;
388 }
389 }
390
391 return 0;
392}
393
394static int coeff_ram_put(struct snd_kcontrol *kcontrol,
395 struct snd_ctl_elem_value *ucontrol)
396{
397 struct snd_soc_component *component =
398 snd_soc_kcontrol_component(kcontrol);
399 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
400 struct coeff_ram_ctl *ctl =
401 (struct coeff_ram_ctl *)kcontrol->private_value;
402 struct soc_bytes_ext *params = &ctl->bytes_ext;
403 unsigned int coeff_cnt = params->max / COEFF_SIZE;
404 u8 *coeff_ram;
405 struct mutex *coeff_ram_lock;
406 bool *coeff_ram_synced;
407 unsigned int r_stat;
408 unsigned int r_addr;
409 unsigned int r_wr;
410 unsigned int val;
411 int ret;
412
413 if (strstr(kcontrol->id.name, "DAC")) {
414 coeff_ram = tscs454->dac_ram.cache;
415 coeff_ram_lock = &tscs454->dac_ram.lock;
416 coeff_ram_synced = &tscs454->dac_ram.synced;
417 r_stat = R_DACCRS;
418 r_addr = R_DACCRADD;
419 r_wr = R_DACCRWDL;
420 } else if (strstr(kcontrol->id.name, "Speaker")) {
421 coeff_ram = tscs454->spk_ram.cache;
422 coeff_ram_lock = &tscs454->spk_ram.lock;
423 coeff_ram_synced = &tscs454->spk_ram.synced;
424 r_stat = R_SPKCRS;
425 r_addr = R_SPKCRADD;
426 r_wr = R_SPKCRWDL;
427 } else if (strstr(kcontrol->id.name, "Sub")) {
428 coeff_ram = tscs454->sub_ram.cache;
429 coeff_ram_lock = &tscs454->sub_ram.lock;
430 coeff_ram_synced = &tscs454->sub_ram.synced;
431 r_stat = R_SUBCRS;
432 r_addr = R_SUBCRADD;
433 r_wr = R_SUBCRWDL;
434 } else {
435 return -EINVAL;
436 }
437
438 mutex_lock(coeff_ram_lock);
439
440 *coeff_ram_synced = false;
441
442 memcpy(&coeff_ram[ctl->addr * COEFF_SIZE],
443 ucontrol->value.bytes.data, params->max);
444
445 mutex_lock(&tscs454->pll1.lock);
446 mutex_lock(&tscs454->pll2.lock);
447
448 ret = snd_soc_component_read(component, R_PLLSTAT, &val);
449 if (ret < 0) {
450 dev_err(component->dev, "Failed to read PLL status (%d)\n",
451 ret);
452 goto exit;
453 }
454 if (val) { /* PLLs locked */
455 ret = write_coeff_ram(component, coeff_ram,
456 r_stat, r_addr, r_wr,
457 ctl->addr, coeff_cnt);
458 if (ret < 0) {
459 dev_err(component->dev,
460 "Failed to flush coeff ram cache (%d)\n", ret);
461 goto exit;
462 }
463 *coeff_ram_synced = true;
464 }
465
466 ret = 0;
467exit:
468 mutex_unlock(&tscs454->pll2.lock);
469 mutex_unlock(&tscs454->pll1.lock);
470 mutex_unlock(coeff_ram_lock);
471
472 return ret;
473}
474
475static inline int coeff_ram_sync(struct snd_soc_component *component,
476 struct tscs454 *tscs454)
477{
478 int ret;
479
480 mutex_lock(&tscs454->dac_ram.lock);
481 if (!tscs454->dac_ram.synced) {
482 ret = write_coeff_ram(component, tscs454->dac_ram.cache,
483 R_DACCRS, R_DACCRADD, R_DACCRWDL,
484 0x00, COEFF_RAM_COEFF_COUNT);
485 if (ret < 0) {
486 mutex_unlock(&tscs454->dac_ram.lock);
487 return ret;
488 }
489 }
490 mutex_unlock(&tscs454->dac_ram.lock);
491
492 mutex_lock(&tscs454->spk_ram.lock);
493 if (!tscs454->spk_ram.synced) {
494 ret = write_coeff_ram(component, tscs454->spk_ram.cache,
495 R_SPKCRS, R_SPKCRADD, R_SPKCRWDL,
496 0x00, COEFF_RAM_COEFF_COUNT);
497 if (ret < 0) {
498 mutex_unlock(&tscs454->spk_ram.lock);
499 return ret;
500 }
501 }
502 mutex_unlock(&tscs454->spk_ram.lock);
503
504 mutex_lock(&tscs454->sub_ram.lock);
505 if (!tscs454->sub_ram.synced) {
506 ret = write_coeff_ram(component, tscs454->sub_ram.cache,
507 R_SUBCRS, R_SUBCRADD, R_SUBCRWDL,
508 0x00, COEFF_RAM_COEFF_COUNT);
509 if (ret < 0) {
510 mutex_unlock(&tscs454->sub_ram.lock);
511 return ret;
512 }
513 }
514 mutex_unlock(&tscs454->sub_ram.lock);
515
516 return 0;
517}
518
519#define PLL_REG_SETTINGS_COUNT 11
520struct pll_ctl {
521 int freq_in;
522 struct reg_setting settings[PLL_REG_SETTINGS_COUNT];
523};
524
525#define PLL_CTL(f, t, c1, r1, o1, f1l, f1h, c2, r2, o2, f2l, f2h) \
526 { \
527 .freq_in = f, \
528 .settings = { \
529 {R_PLL1CTL, c1}, \
530 {R_PLL1RDIV, r1}, \
531 {R_PLL1ODIV, o1}, \
532 {R_PLL1FDIVL, f1l}, \
533 {R_PLL1FDIVH, f1h}, \
534 {R_PLL2CTL, c2}, \
535 {R_PLL2RDIV, r2}, \
536 {R_PLL2ODIV, o2}, \
537 {R_PLL2FDIVL, f2l}, \
538 {R_PLL2FDIVH, f2h}, \
539 {R_TIMEBASE, t}, \
540 }, \
541 }
542
543static const struct pll_ctl pll_ctls[] = {
544 PLL_CTL(1411200, 0x05,
545 0xB9, 0x07, 0x02, 0xC3, 0x04,
546 0x5A, 0x02, 0x03, 0xE0, 0x01),
547 PLL_CTL(1536000, 0x05,
548 0x5A, 0x02, 0x03, 0xE0, 0x01,
549 0x5A, 0x02, 0x03, 0xB9, 0x01),
550 PLL_CTL(2822400, 0x0A,
551 0x63, 0x07, 0x04, 0xC3, 0x04,
552 0x62, 0x07, 0x03, 0x48, 0x03),
553 PLL_CTL(3072000, 0x0B,
554 0x62, 0x07, 0x03, 0x48, 0x03,
555 0x5A, 0x04, 0x03, 0xB9, 0x01),
556 PLL_CTL(5644800, 0x15,
557 0x63, 0x0E, 0x04, 0xC3, 0x04,
558 0x5A, 0x08, 0x03, 0xE0, 0x01),
559 PLL_CTL(6144000, 0x17,
560 0x5A, 0x08, 0x03, 0xE0, 0x01,
561 0x5A, 0x08, 0x03, 0xB9, 0x01),
562 PLL_CTL(12000000, 0x2E,
563 0x5B, 0x19, 0x03, 0x00, 0x03,
564 0x6A, 0x19, 0x05, 0x98, 0x04),
565 PLL_CTL(19200000, 0x4A,
566 0x53, 0x14, 0x03, 0x80, 0x01,
567 0x5A, 0x19, 0x03, 0xB9, 0x01),
568 PLL_CTL(22000000, 0x55,
569 0x6A, 0x37, 0x05, 0x00, 0x06,
570 0x62, 0x26, 0x03, 0x49, 0x02),
571 PLL_CTL(22579200, 0x57,
572 0x62, 0x31, 0x03, 0x20, 0x03,
573 0x53, 0x1D, 0x03, 0xB3, 0x01),
574 PLL_CTL(24000000, 0x5D,
575 0x53, 0x19, 0x03, 0x80, 0x01,
576 0x5B, 0x19, 0x05, 0x4C, 0x02),
577 PLL_CTL(24576000, 0x5F,
578 0x53, 0x1D, 0x03, 0xB3, 0x01,
579 0x62, 0x40, 0x03, 0x72, 0x03),
580 PLL_CTL(27000000, 0x68,
581 0x62, 0x4B, 0x03, 0x00, 0x04,
582 0x6A, 0x7D, 0x03, 0x20, 0x06),
583 PLL_CTL(36000000, 0x8C,
584 0x5B, 0x4B, 0x03, 0x00, 0x03,
585 0x6A, 0x7D, 0x03, 0x98, 0x04),
586 PLL_CTL(11289600, 0x2B,
587 0x6A, 0x31, 0x03, 0x40, 0x06,
588 0x5A, 0x12, 0x03, 0x1C, 0x02),
589 PLL_CTL(26000000, 0x65,
590 0x63, 0x41, 0x05, 0x00, 0x06,
591 0x5A, 0x26, 0x03, 0xEF, 0x01),
592 PLL_CTL(12288000, 0x2F,
593 0x5A, 0x12, 0x03, 0x1C, 0x02,
594 0x62, 0x20, 0x03, 0x72, 0x03),
595 PLL_CTL(40000000, 0x9B,
596 0xA2, 0x7D, 0x03, 0x80, 0x04,
597 0x63, 0x7D, 0x05, 0xE4, 0x06),
598 PLL_CTL(512000, 0x01,
599 0x62, 0x01, 0x03, 0xD0, 0x02,
600 0x5B, 0x01, 0x04, 0x72, 0x03),
601 PLL_CTL(705600, 0x02,
602 0x62, 0x02, 0x03, 0x15, 0x04,
603 0x62, 0x01, 0x04, 0x80, 0x02),
604 PLL_CTL(1024000, 0x03,
605 0x62, 0x02, 0x03, 0xD0, 0x02,
606 0x5B, 0x02, 0x04, 0x72, 0x03),
607 PLL_CTL(2048000, 0x07,
608 0x62, 0x04, 0x03, 0xD0, 0x02,
609 0x5B, 0x04, 0x04, 0x72, 0x03),
610 PLL_CTL(2400000, 0x08,
611 0x62, 0x05, 0x03, 0x00, 0x03,
612 0x63, 0x05, 0x05, 0x98, 0x04),
613};
614
615static inline const struct pll_ctl *get_pll_ctl(unsigned long freq_in)
616{
617 int i;
618 struct pll_ctl const *pll_ctl = NULL;
619
620 for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i)
621 if (pll_ctls[i].freq_in == freq_in) {
622 pll_ctl = &pll_ctls[i];
623 break;
624 }
625
626 return pll_ctl;
627}
628
629enum {
630 PLL_INPUT_XTAL = 0,
631 PLL_INPUT_MCLK1,
632 PLL_INPUT_MCLK2,
633 PLL_INPUT_BCLK,
634};
635
636static int set_sysclk(struct snd_soc_component *component)
637{
638 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
639 struct pll_ctl const *pll_ctl;
640 unsigned long freq;
641 int i;
642 int ret;
643
644 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
645 freq = clk_get_rate(tscs454->sysclk);
646 else
647 freq = tscs454->bclk_freq;
648 pll_ctl = get_pll_ctl(freq);
649 if (!pll_ctl) {
650 ret = -EINVAL;
651 dev_err(component->dev,
652 "Invalid PLL input %lu (%d)\n", freq, ret);
653 return ret;
654 }
655
656 for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) {
657 ret = snd_soc_component_write(component,
658 pll_ctl->settings[i].addr,
659 pll_ctl->settings[i].val);
660 if (ret < 0) {
661 dev_err(component->dev,
662 "Failed to set pll setting (%d)\n",
663 ret);
664 return ret;
665 }
666 }
667
668 return 0;
669}
670
671static inline void reserve_pll(struct pll *pll)
672{
673 mutex_lock(&pll->lock);
674 pll->users++;
675 mutex_unlock(&pll->lock);
676}
677
678static inline void free_pll(struct pll *pll)
679{
680 mutex_lock(&pll->lock);
681 pll->users--;
682 mutex_unlock(&pll->lock);
683}
684
685static int pll_connected(struct snd_soc_dapm_widget *source,
686 struct snd_soc_dapm_widget *sink)
687{
688 struct snd_soc_component *component =
689 snd_soc_dapm_to_component(source->dapm);
690 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
691 int users;
692
693 if (strstr(source->name, "PLL 1")) {
694 mutex_lock(&tscs454->pll1.lock);
695 users = tscs454->pll1.users;
696 mutex_unlock(&tscs454->pll1.lock);
697 dev_dbg(component->dev, "%s(): PLL 1 users = %d\n", __func__,
698 users);
699 } else {
700 mutex_lock(&tscs454->pll2.lock);
701 users = tscs454->pll2.users;
702 mutex_unlock(&tscs454->pll2.lock);
703 dev_dbg(component->dev, "%s(): PLL 2 users = %d\n", __func__,
704 users);
705 }
706
707 return users;
708}
709
710/*
711 * PLL must be enabled after power up and must be disabled before power down
712 * for proper clock switching.
713 */
714static int pll_power_event(struct snd_soc_dapm_widget *w,
715 struct snd_kcontrol *kcontrol, int event)
716{
717 struct snd_soc_component *component =
718 snd_soc_dapm_to_component(w->dapm);
719 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
720 bool enable;
721 bool pll1;
722 unsigned int msk;
723 unsigned int val;
724 int ret;
725
726 if (strstr(w->name, "PLL 1"))
727 pll1 = true;
728 else
729 pll1 = false;
730
731 msk = pll1 ? FM_PLLCTL_PLL1CLKEN : FM_PLLCTL_PLL2CLKEN;
732
733 if (event == SND_SOC_DAPM_POST_PMU)
734 enable = true;
735 else
736 enable = false;
737
738 if (enable)
739 val = pll1 ? FV_PLL1CLKEN_ENABLE : FV_PLL2CLKEN_ENABLE;
740 else
741 val = pll1 ? FV_PLL1CLKEN_DISABLE : FV_PLL2CLKEN_DISABLE;
742
743 ret = snd_soc_component_update_bits(component, R_PLLCTL, msk, val);
744 if (ret < 0) {
745 dev_err(component->dev, "Failed to %s PLL %d (%d)\n",
746 enable ? "enable" : "disable",
747 pll1 ? 1 : 2,
748 ret);
749 return ret;
750 }
751
752 if (enable) {
753 msleep(20); // Wait for lock
754 ret = coeff_ram_sync(component, tscs454);
755 if (ret < 0) {
756 dev_err(component->dev,
757 "Failed to sync coeff ram (%d)\n", ret);
758 return ret;
759 }
760 }
761
762 return 0;
763}
764
765static inline int aif_set_master(struct snd_soc_component *component,
766 unsigned int aif_id, bool master)
767{
768 unsigned int reg;
769 unsigned int mask;
770 unsigned int val;
771 int ret;
772
773 switch (aif_id) {
774 case TSCS454_DAI1_ID:
775 reg = R_I2SP1CTL;
776 break;
777 case TSCS454_DAI2_ID:
778 reg = R_I2SP2CTL;
779 break;
780 case TSCS454_DAI3_ID:
781 reg = R_I2SP3CTL;
782 break;
783 default:
784 ret = -ENODEV;
785 dev_err(component->dev, "Unknown DAI %d (%d)\n", aif_id, ret);
786 return ret;
787 }
788 mask = FM_I2SPCTL_PORTMS;
789 val = master ? FV_PORTMS_MASTER : FV_PORTMS_SLAVE;
790
791 ret = snd_soc_component_update_bits(component, reg, mask, val);
792 if (ret < 0) {
793 dev_err(component->dev, "Failed to set DAI %d to %s (%d)\n",
794 aif_id, master ? "master" : "slave", ret);
795 return ret;
796 }
797
798 return 0;
799}
800
801static inline
802int aif_prepare(struct snd_soc_component *component, struct aif *aif)
803{
804 int ret;
805
806 ret = aif_set_master(component, aif->id, aif->master);
807 if (ret < 0)
808 return ret;
809
810 return 0;
811}
812
813static inline int aif_free(struct snd_soc_component *component,
814 struct aif *aif, bool playback)
815{
816 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
817
818 mutex_lock(&tscs454->aifs_status_lock);
819
820 dev_dbg(component->dev, "%s(): aif %d\n", __func__, aif->id);
821
822 set_aif_status_inactive(&tscs454->aifs_status, aif->id, playback);
823
824 dev_dbg(component->dev, "Set aif %d inactive. Streams status is 0x%x\n",
825 aif->id, tscs454->aifs_status.streams);
826
827 if (!aif_active(&tscs454->aifs_status, aif->id)) {
828 /* Do config in slave mode */
829 aif_set_master(component, aif->id, false);
830 dev_dbg(component->dev, "Freeing pll %d from aif %d\n",
831 aif->pll->id, aif->id);
832 free_pll(aif->pll);
833 }
834
835 if (!aifs_active(&tscs454->aifs_status)) {
836 dev_dbg(component->dev, "Freeing pll %d from ir\n",
837 tscs454->internal_rate.pll->id);
838 free_pll(tscs454->internal_rate.pll);
839 }
840
841 mutex_unlock(&tscs454->aifs_status_lock);
842
843 return 0;
844}
845
846/* R_PLLCTL PG 0 ADDR 0x15 */
847static char const * const bclk_sel_txt[] = {
848 "BCLK 1", "BCLK 2", "BCLK 3"};
849
850static struct soc_enum const bclk_sel_enum =
851 SOC_ENUM_SINGLE(R_PLLCTL, FB_PLLCTL_BCLKSEL,
852 ARRAY_SIZE(bclk_sel_txt), bclk_sel_txt);
853
854/* R_ISRC PG 0 ADDR 0x16 */
855static char const * const isrc_br_txt[] = {
856 "44.1kHz", "48kHz"};
857
858static struct soc_enum const isrc_br_enum =
859 SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBR,
860 ARRAY_SIZE(isrc_br_txt), isrc_br_txt);
861
862static char const * const isrc_bm_txt[] = {
863 "0.25x", "0.5x", "1.0x", "2.0x"};
864
865static struct soc_enum const isrc_bm_enum =
866 SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBM,
867 ARRAY_SIZE(isrc_bm_txt), isrc_bm_txt);
868
869/* R_SCLKCTL PG 0 ADDR 0x18 */
870static char const * const modular_rate_txt[] = {
871 "Reserved", "Half", "Full", "Auto",};
872
873static struct soc_enum const adc_modular_rate_enum =
874 SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_ASDM,
875 ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
876
877static struct soc_enum const dac_modular_rate_enum =
878 SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_DSDM,
879 ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
880
881/* R_I2SIDCTL PG 0 ADDR 0x38 */
882static char const * const data_ctrl_txt[] = {
883 "L/R", "L/L", "R/R", "R/L"};
884
885static struct soc_enum const data_in_ctrl_enums[] = {
886 SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI1DCTL,
887 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
888 SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI2DCTL,
889 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
890 SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI3DCTL,
891 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
892};
893
894/* R_I2SODCTL PG 0 ADDR 0x39 */
895static struct soc_enum const data_out_ctrl_enums[] = {
896 SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO1DCTL,
897 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
898 SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO2DCTL,
899 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
900 SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO3DCTL,
901 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
902};
903
904/* R_AUDIOMUX1 PG 0 ADDR 0x3A */
905static char const * const asrc_mux_txt[] = {
906 "None", "DAI 1", "DAI 2", "DAI 3"};
907
908static struct soc_enum const asrc_in_mux_enum =
909 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_ASRCIMUX,
910 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
911
912static char const * const dai_mux_txt[] = {
913 "CH 0_1", "CH 2_3", "CH 4_5", "ADC/DMic 1",
914 "DMic 2", "ClassD", "DAC", "Sub"};
915
916static struct soc_enum const dai2_mux_enum =
917 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S2MUX,
918 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
919
920static struct snd_kcontrol_new const dai2_mux_dapm_enum =
921 SOC_DAPM_ENUM("DAI 2 Mux", dai2_mux_enum);
922
923static struct soc_enum const dai1_mux_enum =
924 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S1MUX,
925 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
926
927static struct snd_kcontrol_new const dai1_mux_dapm_enum =
928 SOC_DAPM_ENUM("DAI 1 Mux", dai1_mux_enum);
929
930/* R_AUDIOMUX2 PG 0 ADDR 0x3B */
931static struct soc_enum const asrc_out_mux_enum =
932 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_ASRCOMUX,
933 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
934
935static struct soc_enum const dac_mux_enum =
936 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_DACMUX,
937 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
938
939static struct snd_kcontrol_new const dac_mux_dapm_enum =
940 SOC_DAPM_ENUM("DAC Mux", dac_mux_enum);
941
942static struct soc_enum const dai3_mux_enum =
943 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_I2S3MUX,
944 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
945
946static struct snd_kcontrol_new const dai3_mux_dapm_enum =
947 SOC_DAPM_ENUM("DAI 3 Mux", dai3_mux_enum);
948
949/* R_AUDIOMUX3 PG 0 ADDR 0x3C */
950static char const * const sub_mux_txt[] = {
951 "CH 0", "CH 1", "CH 0 + 1",
952 "CH 2", "CH 3", "CH 2 + 3",
953 "CH 4", "CH 5", "CH 4 + 5",
954 "ADC/DMic 1 Left", "ADC/DMic 1 Right",
955 "ADC/DMic 1 Left Plus Right",
956 "DMic 2 Left", "DMic 2 Right", "DMic 2 Left Plus Right",
957 "ClassD Left", "ClassD Right", "ClassD Left Plus Right"};
958
959static struct soc_enum const sub_mux_enum =
960 SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_SUBMUX,
961 ARRAY_SIZE(sub_mux_txt), sub_mux_txt);
962
963static struct snd_kcontrol_new const sub_mux_dapm_enum =
964 SOC_DAPM_ENUM("Sub Mux", sub_mux_enum);
965
966static struct soc_enum const classd_mux_enum =
967 SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_CLSSDMUX,
968 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
969
970static struct snd_kcontrol_new const classd_mux_dapm_enum =
971 SOC_DAPM_ENUM("ClassD Mux", classd_mux_enum);
972
973/* R_HSDCTL1 PG 1 ADDR 0x01 */
974static char const * const jack_type_txt[] = {
975 "3 Terminal", "4 Terminal"};
976
977static struct soc_enum const hp_jack_type_enum =
978 SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HPJKTYPE,
979 ARRAY_SIZE(jack_type_txt), jack_type_txt);
980
981static char const * const hs_det_pol_txt[] = {
982 "Rising", "Falling"};
983
984static struct soc_enum const hs_det_pol_enum =
985 SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HSDETPOL,
986 ARRAY_SIZE(hs_det_pol_txt), hs_det_pol_txt);
987
988/* R_HSDCTL1 PG 1 ADDR 0x02 */
989static char const * const hs_mic_bias_force_txt[] = {
990 "Off", "Ring", "Sleeve"};
991
992static struct soc_enum const hs_mic_bias_force_enum =
993 SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FMICBIAS1,
994 ARRAY_SIZE(hs_mic_bias_force_txt),
995 hs_mic_bias_force_txt);
996
997static char const * const plug_type_txt[] = {
998 "OMTP", "CTIA", "Reserved", "Headphone"};
999
1000static struct soc_enum const plug_type_force_enum =
1001 SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FPLUGTYPE,
1002 ARRAY_SIZE(plug_type_txt), plug_type_txt);
1003
1004
1005/* R_CH0AIC PG 1 ADDR 0x06 */
1006static char const * const in_bst_mux_txt[] = {
1007 "Input 1", "Input 2", "Input 3", "D2S"};
1008
1009static struct soc_enum const in_bst_mux_ch0_enum =
1010 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_INSELL,
1011 ARRAY_SIZE(in_bst_mux_txt),
1012 in_bst_mux_txt);
1013static struct snd_kcontrol_new const in_bst_mux_ch0_dapm_enum =
1014 SOC_DAPM_ENUM("Input Boost Channel 0 Enum",
1015 in_bst_mux_ch0_enum);
1016
1017static DECLARE_TLV_DB_SCALE(in_bst_vol_tlv_arr, 0, 1000, 0);
1018
1019static char const * const adc_mux_txt[] = {
1020 "Input 1 Boost Bypass", "Input 2 Boost Bypass",
1021 "Input 3 Boost Bypass", "Input Boost"};
1022
1023static struct soc_enum const adc_mux_ch0_enum =
1024 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_LADCIN,
1025 ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
1026static struct snd_kcontrol_new const adc_mux_ch0_dapm_enum =
1027 SOC_DAPM_ENUM("ADC Channel 0 Enum", adc_mux_ch0_enum);
1028
1029static char const * const in_proc_mux_txt[] = {
1030 "ADC", "DMic"};
1031
1032static struct soc_enum const in_proc_ch0_enum =
1033 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_IPCH0S,
1034 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
1035static struct snd_kcontrol_new const in_proc_mux_ch0_dapm_enum =
1036 SOC_DAPM_ENUM("Input Processor Channel 0 Enum",
1037 in_proc_ch0_enum);
1038
1039/* R_CH1AIC PG 1 ADDR 0x07 */
1040static struct soc_enum const in_bst_mux_ch1_enum =
1041 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_INSELR,
1042 ARRAY_SIZE(in_bst_mux_txt),
1043 in_bst_mux_txt);
1044static struct snd_kcontrol_new const in_bst_mux_ch1_dapm_enum =
1045 SOC_DAPM_ENUM("Input Boost Channel 1 Enum",
1046 in_bst_mux_ch1_enum);
1047
1048static struct soc_enum const adc_mux_ch1_enum =
1049 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_RADCIN,
1050 ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
1051static struct snd_kcontrol_new const adc_mux_ch1_dapm_enum =
1052 SOC_DAPM_ENUM("ADC Channel 1 Enum", adc_mux_ch1_enum);
1053
1054static struct soc_enum const in_proc_ch1_enum =
1055 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_IPCH1S,
1056 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
1057static struct snd_kcontrol_new const in_proc_mux_ch1_dapm_enum =
1058 SOC_DAPM_ENUM("Input Processor Channel 1 Enum",
1059 in_proc_ch1_enum);
1060
1061/* R_ICTL0 PG 1 ADDR 0x0A */
1062static char const * const pol_txt[] = {
1063 "Normal", "Invert"};
1064
1065static struct soc_enum const in_pol_ch1_enum =
1066 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN0POL,
1067 ARRAY_SIZE(pol_txt), pol_txt);
1068
1069static struct soc_enum const in_pol_ch0_enum =
1070 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN1POL,
1071 ARRAY_SIZE(pol_txt), pol_txt);
1072
1073static char const * const in_proc_ch_sel_txt[] = {
1074 "Normal", "Mono Mix to Channel 0",
1075 "Mono Mix to Channel 1", "Add"};
1076
1077static struct soc_enum const in_proc_ch01_sel_enum =
1078 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_INPCH10SEL,
1079 ARRAY_SIZE(in_proc_ch_sel_txt),
1080 in_proc_ch_sel_txt);
1081
1082/* R_ICTL1 PG 1 ADDR 0x0B */
1083static struct soc_enum const in_pol_ch3_enum =
1084 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN2POL,
1085 ARRAY_SIZE(pol_txt), pol_txt);
1086
1087static struct soc_enum const in_pol_ch2_enum =
1088 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN3POL,
1089 ARRAY_SIZE(pol_txt), pol_txt);
1090
1091static struct soc_enum const in_proc_ch23_sel_enum =
1092 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_INPCH32SEL,
1093 ARRAY_SIZE(in_proc_ch_sel_txt),
1094 in_proc_ch_sel_txt);
1095
1096/* R_MICBIAS PG 1 ADDR 0x0C */
1097static char const * const mic_bias_txt[] = {
1098 "2.5V", "2.1V", "1.8V", "Vdd"};
1099
1100static struct soc_enum const mic_bias_2_enum =
1101 SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV2,
1102 ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
1103
1104static struct soc_enum const mic_bias_1_enum =
1105 SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV1,
1106 ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
1107
1108/* R_PGACTL0 PG 1 ADDR 0x0D */
1109/* R_PGACTL1 PG 1 ADDR 0x0E */
1110/* R_PGACTL2 PG 1 ADDR 0x0F */
1111/* R_PGACTL3 PG 1 ADDR 0x10 */
1112static DECLARE_TLV_DB_SCALE(in_pga_vol_tlv_arr, -1725, 75, 0);
1113
1114/* R_ICH0VOL PG1 ADDR 0x12 */
1115/* R_ICH1VOL PG1 ADDR 0x13 */
1116/* R_ICH2VOL PG1 ADDR 0x14 */
1117/* R_ICH3VOL PG1 ADDR 0x15 */
1118static DECLARE_TLV_DB_MINMAX(in_vol_tlv_arr, -7125, 2400);
1119
1120/* R_ASRCILVOL PG1 ADDR 0x16 */
1121/* R_ASRCIRVOL PG1 ADDR 0x17 */
1122/* R_ASRCOLVOL PG1 ADDR 0x18 */
1123/* R_ASRCORVOL PG1 ADDR 0x19 */
1124static DECLARE_TLV_DB_MINMAX(asrc_vol_tlv_arr, -9562, 600);
1125
1126/* R_ALCCTL0 PG1 ADDR 0x1D */
1127static char const * const alc_mode_txt[] = {
1128 "ALC", "Limiter"};
1129
1130static struct soc_enum const alc_mode_enum =
1131 SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCMODE,
1132 ARRAY_SIZE(alc_mode_txt), alc_mode_txt);
1133
1134static char const * const alc_ref_text[] = {
1135 "Channel 0", "Channel 1", "Channel 2", "Channel 3", "Peak"};
1136
1137static struct soc_enum const alc_ref_enum =
1138 SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCREF,
1139 ARRAY_SIZE(alc_ref_text), alc_ref_text);
1140
1141/* R_ALCCTL1 PG 1 ADDR 0x1E */
1142static DECLARE_TLV_DB_SCALE(alc_max_gain_tlv_arr, -1200, 600, 0);
1143static DECLARE_TLV_DB_SCALE(alc_target_tlv_arr, -2850, 150, 0);
1144
1145/* R_ALCCTL2 PG 1 ADDR 0x1F */
1146static DECLARE_TLV_DB_SCALE(alc_min_gain_tlv_arr, -1725, 600, 0);
1147
1148/* R_NGATE PG 1 ADDR 0x21 */
1149static DECLARE_TLV_DB_SCALE(ngth_tlv_arr, -7650, 150, 0);
1150
1151static char const * const ngate_type_txt[] = {
1152 "PGA Constant", "ADC Mute"};
1153
1154static struct soc_enum const ngate_type_enum =
1155 SOC_ENUM_SINGLE(R_NGATE, FB_NGATE_NGG,
1156 ARRAY_SIZE(ngate_type_txt), ngate_type_txt);
1157
1158/* R_DMICCTL PG 1 ADDR 0x22 */
1159static char const * const dmic_mono_sel_txt[] = {
1160 "Stereo", "Mono"};
1161
1162static struct soc_enum const dmic_mono_sel_enum =
1163 SOC_ENUM_SINGLE(R_DMICCTL, FB_DMICCTL_DMONO,
1164 ARRAY_SIZE(dmic_mono_sel_txt), dmic_mono_sel_txt);
1165
1166/* R_DACCTL PG 2 ADDR 0x01 */
1167static struct soc_enum const dac_pol_r_enum =
1168 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLR,
1169 ARRAY_SIZE(pol_txt), pol_txt);
1170
1171static struct soc_enum const dac_pol_l_enum =
1172 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLL,
1173 ARRAY_SIZE(pol_txt), pol_txt);
1174
1175static char const * const dac_dith_txt[] = {
1176 "Half", "Full", "Disabled", "Static"};
1177
1178static struct soc_enum const dac_dith_enum =
1179 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACDITH,
1180 ARRAY_SIZE(dac_dith_txt), dac_dith_txt);
1181
1182/* R_SPKCTL PG 2 ADDR 0x02 */
1183static struct soc_enum const spk_pol_r_enum =
1184 SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLR,
1185 ARRAY_SIZE(pol_txt), pol_txt);
1186
1187static struct soc_enum const spk_pol_l_enum =
1188 SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLL,
1189 ARRAY_SIZE(pol_txt), pol_txt);
1190
1191/* R_SUBCTL PG 2 ADDR 0x03 */
1192static struct soc_enum const sub_pol_enum =
1193 SOC_ENUM_SINGLE(R_SUBCTL, FB_SUBCTL_SUBPOL,
1194 ARRAY_SIZE(pol_txt), pol_txt);
1195
1196/* R_MVOLL PG 2 ADDR 0x08 */
1197/* R_MVOLR PG 2 ADDR 0x09 */
1198static DECLARE_TLV_DB_MINMAX(mvol_tlv_arr, -9562, 0);
1199
1200/* R_HPVOLL PG 2 ADDR 0x0A */
1201/* R_HPVOLR PG 2 ADDR 0x0B */
1202static DECLARE_TLV_DB_SCALE(hp_vol_tlv_arr, -8850, 75, 0);
1203
1204/* R_SPKVOLL PG 2 ADDR 0x0C */
1205/* R_SPKVOLR PG 2 ADDR 0x0D */
1206static DECLARE_TLV_DB_SCALE(spk_vol_tlv_arr, -7725, 75, 0);
1207
1208/* R_SPKEQFILT PG 3 ADDR 0x01 */
1209static char const * const eq_txt[] = {
1210 "Pre Scale",
1211 "Pre Scale + EQ Band 0",
1212 "Pre Scale + EQ Band 0 - 1",
1213 "Pre Scale + EQ Band 0 - 2",
1214 "Pre Scale + EQ Band 0 - 3",
1215 "Pre Scale + EQ Band 0 - 4",
1216 "Pre Scale + EQ Band 0 - 5",
1217};
1218
1219static struct soc_enum const spk_eq_enums[] = {
1220 SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ2BE,
1221 ARRAY_SIZE(eq_txt), eq_txt),
1222 SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ1BE,
1223 ARRAY_SIZE(eq_txt), eq_txt),
1224};
1225
1226/* R_SPKMBCCTL PG 3 ADDR 0x0B */
1227static char const * const lvl_mode_txt[] = {
1228 "Average", "Peak"};
1229
1230static struct soc_enum const spk_mbc3_lvl_det_mode_enum =
1231 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE3,
1232 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1233
1234static char const * const win_sel_txt[] = {
1235 "512", "64"};
1236
1237static struct soc_enum const spk_mbc3_win_sel_enum =
1238 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL3,
1239 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1240
1241static struct soc_enum const spk_mbc2_lvl_det_mode_enum =
1242 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE2,
1243 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1244
1245static struct soc_enum const spk_mbc2_win_sel_enum =
1246 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL2,
1247 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1248
1249static struct soc_enum const spk_mbc1_lvl_det_mode_enum =
1250 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE1,
1251 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1252
1253static struct soc_enum const spk_mbc1_win_sel_enum =
1254 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL1,
1255 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1256
1257/* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
1258static struct soc_enum const spk_mbc1_phase_pol_enum =
1259 SOC_ENUM_SINGLE(R_SPKMBCMUG1, FB_SPKMBCMUG_PHASE,
1260 ARRAY_SIZE(pol_txt), pol_txt);
1261
1262static DECLARE_TLV_DB_MINMAX(mbc_mug_tlv_arr, -4650, 0);
1263
1264/* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
1265static DECLARE_TLV_DB_MINMAX(thr_tlv_arr, -9562, 0);
1266
1267/* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
1268static char const * const comp_rat_txt[] = {
1269 "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1",
1270 "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1",
1271 "15:1", "16:1", "17:1", "18:1", "19:1", "20:1"};
1272
1273static struct soc_enum const spk_mbc1_comp_rat_enum =
1274 SOC_ENUM_SINGLE(R_SPKMBCRAT1, FB_SPKMBCRAT_RATIO,
1275 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1276
1277/* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
1278static struct soc_enum const spk_mbc2_phase_pol_enum =
1279 SOC_ENUM_SINGLE(R_SPKMBCMUG2, FB_SPKMBCMUG_PHASE,
1280 ARRAY_SIZE(pol_txt), pol_txt);
1281
1282/* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
1283static struct soc_enum const spk_mbc2_comp_rat_enum =
1284 SOC_ENUM_SINGLE(R_SPKMBCRAT2, FB_SPKMBCRAT_RATIO,
1285 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1286
1287/* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
1288static struct soc_enum const spk_mbc3_phase_pol_enum =
1289 SOC_ENUM_SINGLE(R_SPKMBCMUG3, FB_SPKMBCMUG_PHASE,
1290 ARRAY_SIZE(pol_txt), pol_txt);
1291
1292/* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
1293static struct soc_enum const spk_mbc3_comp_rat_enum =
1294 SOC_ENUM_SINGLE(R_SPKMBCRAT3, FB_SPKMBCRAT_RATIO,
1295 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1296
1297/* R_SPKCLECTL PG 3 ADDR 0x21 */
1298static struct soc_enum const spk_cle_lvl_mode_enum =
1299 SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_LVLMODE,
1300 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1301
1302static struct soc_enum const spk_cle_win_sel_enum =
1303 SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_WINSEL,
1304 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1305
1306/* R_SPKCLEMUG PG 3 ADDR 0x22 */
1307static DECLARE_TLV_DB_MINMAX(cle_mug_tlv_arr, 0, 4650);
1308
1309/* R_SPKCOMPRAT PG 3 ADDR 0x24 */
1310static struct soc_enum const spk_comp_rat_enum =
1311 SOC_ENUM_SINGLE(R_SPKCOMPRAT, FB_SPKCOMPRAT_RATIO,
1312 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1313
1314/* R_SPKEXPTHR PG 3 ADDR 0x2F */
1315static char const * const exp_rat_txt[] = {
1316 "Reserved", "Reserved", "1:2", "1:3",
1317 "1:4", "1:5", "1:6", "1:7"};
1318
1319static struct soc_enum const spk_exp_rat_enum =
1320 SOC_ENUM_SINGLE(R_SPKEXPRAT, FB_SPKEXPRAT_RATIO,
1321 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1322
1323/* R_DACEQFILT PG 4 ADDR 0x01 */
1324static struct soc_enum const dac_eq_enums[] = {
1325 SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ2BE,
1326 ARRAY_SIZE(eq_txt), eq_txt),
1327 SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ1BE,
1328 ARRAY_SIZE(eq_txt), eq_txt),
1329};
1330
1331/* R_DACMBCCTL PG 4 ADDR 0x0B */
1332static struct soc_enum const dac_mbc3_lvl_det_mode_enum =
1333 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3,
1334 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1335
1336static struct soc_enum const dac_mbc3_win_sel_enum =
1337 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3,
1338 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1339
1340static struct soc_enum const dac_mbc2_lvl_det_mode_enum =
1341 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2,
1342 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1343
1344static struct soc_enum const dac_mbc2_win_sel_enum =
1345 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2,
1346 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1347
1348static struct soc_enum const dac_mbc1_lvl_det_mode_enum =
1349 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1,
1350 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1351
1352static struct soc_enum const dac_mbc1_win_sel_enum =
1353 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1,
1354 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1355
1356/* R_DACMBCMUG1 PG 4 ADDR 0x0C */
1357static struct soc_enum const dac_mbc1_phase_pol_enum =
1358 SOC_ENUM_SINGLE(R_DACMBCMUG1, FB_DACMBCMUG_PHASE,
1359 ARRAY_SIZE(pol_txt), pol_txt);
1360
1361/* R_DACMBCRAT1 PG 4 ADDR 0x0E */
1362static struct soc_enum const dac_mbc1_comp_rat_enum =
1363 SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT_RATIO,
1364 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1365
1366/* R_DACMBCMUG2 PG 4 ADDR 0x13 */
1367static struct soc_enum const dac_mbc2_phase_pol_enum =
1368 SOC_ENUM_SINGLE(R_DACMBCMUG2, FB_DACMBCMUG_PHASE,
1369 ARRAY_SIZE(pol_txt), pol_txt);
1370
1371/* R_DACMBCRAT2 PG 4 ADDR 0x15 */
1372static struct soc_enum const dac_mbc2_comp_rat_enum =
1373 SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT_RATIO,
1374 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1375
1376/* R_DACMBCMUG3 PG 4 ADDR 0x1A */
1377static struct soc_enum const dac_mbc3_phase_pol_enum =
1378 SOC_ENUM_SINGLE(R_DACMBCMUG3, FB_DACMBCMUG_PHASE,
1379 ARRAY_SIZE(pol_txt), pol_txt);
1380
1381/* R_DACMBCRAT3 PG 4 ADDR 0x1C */
1382static struct soc_enum const dac_mbc3_comp_rat_enum =
1383 SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT_RATIO,
1384 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1385
1386/* R_DACCLECTL PG 4 ADDR 0x21 */
1387static struct soc_enum const dac_cle_lvl_mode_enum =
1388 SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_LVLMODE,
1389 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1390
1391static struct soc_enum const dac_cle_win_sel_enum =
1392 SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_WINSEL,
1393 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1394
1395/* R_DACCOMPRAT PG 4 ADDR 0x24 */
1396static struct soc_enum const dac_comp_rat_enum =
1397 SOC_ENUM_SINGLE(R_DACCOMPRAT, FB_DACCOMPRAT_RATIO,
1398 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1399
1400/* R_DACEXPRAT PG 4 ADDR 0x30 */
1401static struct soc_enum const dac_exp_rat_enum =
1402 SOC_ENUM_SINGLE(R_DACEXPRAT, FB_DACEXPRAT_RATIO,
1403 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1404
1405/* R_SUBEQFILT PG 5 ADDR 0x01 */
1406static struct soc_enum const sub_eq_enums[] = {
1407 SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ2BE,
1408 ARRAY_SIZE(eq_txt), eq_txt),
1409 SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ1BE,
1410 ARRAY_SIZE(eq_txt), eq_txt),
1411};
1412
1413/* R_SUBMBCCTL PG 5 ADDR 0x0B */
1414static struct soc_enum const sub_mbc3_lvl_det_mode_enum =
1415 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE3,
1416 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1417
1418static struct soc_enum const sub_mbc3_win_sel_enum =
1419 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL3,
1420 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1421
1422static struct soc_enum const sub_mbc2_lvl_det_mode_enum =
1423 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE2,
1424 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1425
1426static struct soc_enum const sub_mbc2_win_sel_enum =
1427 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL2,
1428 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1429
1430static struct soc_enum const sub_mbc1_lvl_det_mode_enum =
1431 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE1,
1432 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1433
1434static struct soc_enum const sub_mbc1_win_sel_enum =
1435 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL1,
1436 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1437
1438/* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
1439static struct soc_enum const sub_mbc1_phase_pol_enum =
1440 SOC_ENUM_SINGLE(R_SUBMBCMUG1, FB_SUBMBCMUG_PHASE,
1441 ARRAY_SIZE(pol_txt), pol_txt);
1442
1443/* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
1444static struct soc_enum const sub_mbc1_comp_rat_enum =
1445 SOC_ENUM_SINGLE(R_SUBMBCRAT1, FB_SUBMBCRAT_RATIO,
1446 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1447
1448/* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
1449static struct soc_enum const sub_mbc2_phase_pol_enum =
1450 SOC_ENUM_SINGLE(R_SUBMBCMUG2, FB_SUBMBCMUG_PHASE,
1451 ARRAY_SIZE(pol_txt), pol_txt);
1452
1453/* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
1454static struct soc_enum const sub_mbc2_comp_rat_enum =
1455 SOC_ENUM_SINGLE(R_SUBMBCRAT2, FB_SUBMBCRAT_RATIO,
1456 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1457
1458/* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
1459static struct soc_enum const sub_mbc3_phase_pol_enum =
1460 SOC_ENUM_SINGLE(R_SUBMBCMUG3, FB_SUBMBCMUG_PHASE,
1461 ARRAY_SIZE(pol_txt), pol_txt);
1462
1463/* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
1464static struct soc_enum const sub_mbc3_comp_rat_enum =
1465 SOC_ENUM_SINGLE(R_SUBMBCRAT3, FB_SUBMBCRAT_RATIO,
1466 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1467
1468/* R_SUBCLECTL PG 5 ADDR 0x21 */
1469static struct soc_enum const sub_cle_lvl_mode_enum =
1470 SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_LVLMODE,
1471 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1472static struct soc_enum const sub_cle_win_sel_enum =
1473 SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_WINSEL,
1474 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1475
1476/* R_SUBCOMPRAT PG 5 ADDR 0x24 */
1477static struct soc_enum const sub_comp_rat_enum =
1478 SOC_ENUM_SINGLE(R_SUBCOMPRAT, FB_SUBCOMPRAT_RATIO,
1479 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1480
1481/* R_SUBEXPRAT PG 5 ADDR 0x30 */
1482static struct soc_enum const sub_exp_rat_enum =
1483 SOC_ENUM_SINGLE(R_SUBEXPRAT, FB_SUBEXPRAT_RATIO,
1484 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1485
1486static int bytes_info_ext(struct snd_kcontrol *kcontrol,
1487 struct snd_ctl_elem_info *ucontrol)
1488{
1489 struct coeff_ram_ctl *ctl =
1490 (struct coeff_ram_ctl *)kcontrol->private_value;
1491 struct soc_bytes_ext *params = &ctl->bytes_ext;
1492
1493 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1494 ucontrol->count = params->max;
1495
1496 return 0;
1497}
1498
1499/* CH 0_1 Input Mux */
1500static char const * const ch_0_1_mux_txt[] = {"DAI 1", "TDM 0_1"};
1501
1502static struct soc_enum const ch_0_1_mux_enum =
1503 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1504 ARRAY_SIZE(ch_0_1_mux_txt), ch_0_1_mux_txt);
1505
1506static struct snd_kcontrol_new const ch_0_1_mux_dapm_enum =
1507 SOC_DAPM_ENUM("CH 0_1 Input Mux", ch_0_1_mux_enum);
1508
1509/* CH 2_3 Input Mux */
1510static char const * const ch_2_3_mux_txt[] = {"DAI 2", "TDM 2_3"};
1511
1512static struct soc_enum const ch_2_3_mux_enum =
1513 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1514 ARRAY_SIZE(ch_2_3_mux_txt), ch_2_3_mux_txt);
1515
1516static struct snd_kcontrol_new const ch_2_3_mux_dapm_enum =
1517 SOC_DAPM_ENUM("CH 2_3 Input Mux", ch_2_3_mux_enum);
1518
1519/* CH 4_5 Input Mux */
1520static char const * const ch_4_5_mux_txt[] = {"DAI 3", "TDM 4_5"};
1521
1522static struct soc_enum const ch_4_5_mux_enum =
1523 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1524 ARRAY_SIZE(ch_4_5_mux_txt), ch_4_5_mux_txt);
1525
1526static struct snd_kcontrol_new const ch_4_5_mux_dapm_enum =
1527 SOC_DAPM_ENUM("CH 4_5 Input Mux", ch_4_5_mux_enum);
1528
1529#define COEFF_RAM_CTL(xname, xcount, xaddr) \
1530{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1531 .info = bytes_info_ext, \
1532 .get = coeff_ram_get, .put = coeff_ram_put, \
1533 .private_value = (unsigned long)&(struct coeff_ram_ctl) { \
1534 .addr = xaddr, \
1535 .bytes_ext = {.max = xcount, }, \
1536 } \
1537}
1538
1539static struct snd_kcontrol_new const tscs454_snd_controls[] = {
1540 /* R_PLLCTL PG 0 ADDR 0x15 */
1541 SOC_ENUM("PLL BCLK Input", bclk_sel_enum),
1542 /* R_ISRC PG 0 ADDR 0x16 */
1543 SOC_ENUM("Internal Rate", isrc_br_enum),
1544 SOC_ENUM("Internal Rate Multiple", isrc_bm_enum),
1545 /* R_SCLKCTL PG 0 ADDR 0x18 */
1546 SOC_ENUM("ADC Modular Rate", adc_modular_rate_enum),
1547 SOC_ENUM("DAC Modular Rate", dac_modular_rate_enum),
1548 /* R_ASRC PG 0 ADDR 0x28 */
1549 SOC_SINGLE("ASRC Out High Bandwidth Switch",
1550 R_ASRC, FB_ASRC_ASRCOBW, 1, 0),
1551 SOC_SINGLE("ASRC In High Bandwidth Switch",
1552 R_ASRC, FB_ASRC_ASRCIBW, 1, 0),
1553 /* R_I2SIDCTL PG 0 ADDR 0x38 */
1554 SOC_ENUM("I2S 1 Data In Control", data_in_ctrl_enums[0]),
1555 SOC_ENUM("I2S 2 Data In Control", data_in_ctrl_enums[1]),
1556 SOC_ENUM("I2S 3 Data In Control", data_in_ctrl_enums[2]),
1557 /* R_I2SODCTL PG 0 ADDR 0x39 */
1558 SOC_ENUM("I2S 1 Data Out Control", data_out_ctrl_enums[0]),
1559 SOC_ENUM("I2S 2 Data Out Control", data_out_ctrl_enums[1]),
1560 SOC_ENUM("I2S 3 Data Out Control", data_out_ctrl_enums[2]),
1561 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
1562 SOC_ENUM("ASRC In", asrc_in_mux_enum),
1563 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
1564 SOC_ENUM("ASRC Out", asrc_out_mux_enum),
1565 /* R_HSDCTL1 PG 1 ADDR 0x01 */
1566 SOC_ENUM("Headphone Jack Type", hp_jack_type_enum),
1567 SOC_ENUM("Headset Detection Polarity", hs_det_pol_enum),
1568 SOC_SINGLE("Headphone Detection Switch",
1569 R_HSDCTL1, FB_HSDCTL1_HPID_EN, 1, 0),
1570 SOC_SINGLE("Headset OMTP/CTIA Switch",
1571 R_HSDCTL1, FB_HSDCTL1_GBLHS_EN, 1, 0),
1572 /* R_HSDCTL1 PG 1 ADDR 0x02 */
1573 SOC_ENUM("Headset Mic Bias Force", hs_mic_bias_force_enum),
1574 SOC_SINGLE("Manual Mic Bias Switch",
1575 R_HSDCTL2, FB_HSDCTL2_MB1MODE, 1, 0),
1576 SOC_SINGLE("Ring/Sleeve Auto Switch",
1577 R_HSDCTL2, FB_HSDCTL2_SWMODE, 1, 0),
1578 SOC_ENUM("Manual Mode Plug Type", plug_type_force_enum),
1579 /* R_CH0AIC PG 1 ADDR 0x06 */
1580 SOC_SINGLE_TLV("Input Boost Channel 0 Volume", R_CH0AIC,
1581 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1582 /* R_CH1AIC PG 1 ADDR 0x07 */
1583 SOC_SINGLE_TLV("Input Boost Channel 1 Volume", R_CH1AIC,
1584 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1585 /* R_CH2AIC PG 1 ADDR 0x08 */
1586 SOC_SINGLE_TLV("Input Boost Channel 2 Volume", R_CH2AIC,
1587 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1588 /* R_CH3AIC PG 1 ADDR 0x09 */
1589 SOC_SINGLE_TLV("Input Boost Channel 3 Volume", R_CH3AIC,
1590 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1591 /* R_ICTL0 PG 1 ADDR 0x0A */
1592 SOC_ENUM("Input Channel 1 Polarity", in_pol_ch1_enum),
1593 SOC_ENUM("Input Channel 0 Polarity", in_pol_ch0_enum),
1594 SOC_ENUM("Input Processor Channel 0/1 Operation",
1595 in_proc_ch01_sel_enum),
1596 SOC_SINGLE("Input Channel 1 Mute Switch",
1597 R_ICTL0, FB_ICTL0_IN1MUTE, 1, 0),
1598 SOC_SINGLE("Input Channel 0 Mute Switch",
1599 R_ICTL0, FB_ICTL0_IN0MUTE, 1, 0),
1600 SOC_SINGLE("Input Channel 1 HPF Disable Switch",
1601 R_ICTL0, FB_ICTL0_IN1HP, 1, 0),
1602 SOC_SINGLE("Input Channel 0 HPF Disable Switch",
1603 R_ICTL0, FB_ICTL0_IN0HP, 1, 0),
1604 /* R_ICTL1 PG 1 ADDR 0x0B */
1605 SOC_ENUM("Input Channel 3 Polarity", in_pol_ch3_enum),
1606 SOC_ENUM("Input Channel 2 Polarity", in_pol_ch2_enum),
1607 SOC_ENUM("Input Processor Channel 2/3 Operation",
1608 in_proc_ch23_sel_enum),
1609 SOC_SINGLE("Input Channel 3 Mute Switch",
1610 R_ICTL1, FB_ICTL1_IN3MUTE, 1, 0),
1611 SOC_SINGLE("Input Channel 2 Mute Switch",
1612 R_ICTL1, FB_ICTL1_IN2MUTE, 1, 0),
1613 SOC_SINGLE("Input Channel 3 HPF Disable Switch",
1614 R_ICTL1, FB_ICTL1_IN3HP, 1, 0),
1615 SOC_SINGLE("Input Channel 2 HPF Disable Switch",
1616 R_ICTL1, FB_ICTL1_IN2HP, 1, 0),
1617 /* R_MICBIAS PG 1 ADDR 0x0C */
1618 SOC_ENUM("Mic Bias 2 Voltage", mic_bias_2_enum),
1619 SOC_ENUM("Mic Bias 1 Voltage", mic_bias_1_enum),
1620 /* R_PGACTL0 PG 1 ADDR 0x0D */
1621 SOC_SINGLE("Input Channel 0 PGA Mute Switch",
1622 R_PGACTL0, FB_PGACTL_PGAMUTE, 1, 0),
1623 SOC_SINGLE_TLV("Input Channel 0 PGA Volume", R_PGACTL0,
1624 FB_PGACTL_PGAVOL,
1625 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1626 /* R_PGACTL1 PG 1 ADDR 0x0E */
1627 SOC_SINGLE("Input Channel 1 PGA Mute Switch",
1628 R_PGACTL1, FB_PGACTL_PGAMUTE, 1, 0),
1629 SOC_SINGLE_TLV("Input Channel 1 PGA Volume", R_PGACTL1,
1630 FB_PGACTL_PGAVOL,
1631 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1632 /* R_PGACTL2 PG 1 ADDR 0x0F */
1633 SOC_SINGLE("Input Channel 2 PGA Mute Switch",
1634 R_PGACTL2, FB_PGACTL_PGAMUTE, 1, 0),
1635 SOC_SINGLE_TLV("Input Channel 2 PGA Volume", R_PGACTL2,
1636 FB_PGACTL_PGAVOL,
1637 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1638 /* R_PGACTL3 PG 1 ADDR 0x10 */
1639 SOC_SINGLE("Input Channel 3 PGA Mute Switch",
1640 R_PGACTL3, FB_PGACTL_PGAMUTE, 1, 0),
1641 SOC_SINGLE_TLV("Input Channel 3 PGA Volume", R_PGACTL3,
1642 FB_PGACTL_PGAVOL,
1643 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1644 /* R_ICH0VOL PG 1 ADDR 0x12 */
1645 SOC_SINGLE_TLV("Input Channel 0 Volume", R_ICH0VOL,
1646 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1647 /* R_ICH1VOL PG 1 ADDR 0x13 */
1648 SOC_SINGLE_TLV("Input Channel 1 Volume", R_ICH1VOL,
1649 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1650 /* R_ICH2VOL PG 1 ADDR 0x14 */
1651 SOC_SINGLE_TLV("Input Channel 2 Volume", R_ICH2VOL,
1652 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1653 /* R_ICH3VOL PG 1 ADDR 0x15 */
1654 SOC_SINGLE_TLV("Input Channel 3 Volume", R_ICH3VOL,
1655 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1656 /* R_ASRCILVOL PG 1 ADDR 0x16 */
1657 SOC_SINGLE_TLV("ASRC Input Left Volume", R_ASRCILVOL,
1658 FB_ASRCILVOL_ASRCILVOL, FM_ASRCILVOL_ASRCILVOL,
1659 0, asrc_vol_tlv_arr),
1660 /* R_ASRCIRVOL PG 1 ADDR 0x17 */
1661 SOC_SINGLE_TLV("ASRC Input Right Volume", R_ASRCIRVOL,
1662 FB_ASRCIRVOL_ASRCIRVOL, FM_ASRCIRVOL_ASRCIRVOL,
1663 0, asrc_vol_tlv_arr),
1664 /* R_ASRCOLVOL PG 1 ADDR 0x18 */
1665 SOC_SINGLE_TLV("ASRC Output Left Volume", R_ASRCOLVOL,
1666 FB_ASRCOLVOL_ASRCOLVOL, FM_ASRCOLVOL_ASRCOLVOL,
1667 0, asrc_vol_tlv_arr),
1668 /* R_ASRCORVOL PG 1 ADDR 0x19 */
1669 SOC_SINGLE_TLV("ASRC Output Right Volume", R_ASRCORVOL,
1670 FB_ASRCORVOL_ASRCOLVOL, FM_ASRCORVOL_ASRCOLVOL,
1671 0, asrc_vol_tlv_arr),
1672 /* R_IVOLCTLU PG 1 ADDR 0x1C */
1673 /* R_ALCCTL0 PG 1 ADDR 0x1D */
1674 SOC_ENUM("ALC Mode", alc_mode_enum),
1675 SOC_ENUM("ALC Reference", alc_ref_enum),
1676 SOC_SINGLE("Input Channel 3 ALC Switch",
1677 R_ALCCTL0, FB_ALCCTL0_ALCEN3, 1, 0),
1678 SOC_SINGLE("Input Channel 2 ALC Switch",
1679 R_ALCCTL0, FB_ALCCTL0_ALCEN2, 1, 0),
1680 SOC_SINGLE("Input Channel 1 ALC Switch",
1681 R_ALCCTL0, FB_ALCCTL0_ALCEN1, 1, 0),
1682 SOC_SINGLE("Input Channel 0 ALC Switch",
1683 R_ALCCTL0, FB_ALCCTL0_ALCEN0, 1, 0),
1684 /* R_ALCCTL1 PG 1 ADDR 0x1E */
1685 SOC_SINGLE_TLV("ALC Max Gain Volume", R_ALCCTL1,
1686 FB_ALCCTL1_MAXGAIN, FM_ALCCTL1_MAXGAIN,
1687 0, alc_max_gain_tlv_arr),
1688 SOC_SINGLE_TLV("ALC Target Volume", R_ALCCTL1,
1689 FB_ALCCTL1_ALCL, FM_ALCCTL1_ALCL,
1690 0, alc_target_tlv_arr),
1691 /* R_ALCCTL2 PG 1 ADDR 0x1F */
1692 SOC_SINGLE("ALC Zero Cross Switch",
1693 R_ALCCTL2, FB_ALCCTL2_ALCZC, 1, 0),
1694 SOC_SINGLE_TLV("ALC Min Gain Volume", R_ALCCTL2,
1695 FB_ALCCTL2_MINGAIN, FM_ALCCTL2_MINGAIN,
1696 0, alc_min_gain_tlv_arr),
1697 SOC_SINGLE_RANGE("ALC Hold", R_ALCCTL2,
1698 FB_ALCCTL2_HLD, 0, FM_ALCCTL2_HLD, 0),
1699 /* R_ALCCTL3 PG 1 ADDR 0x20 */
1700 SOC_SINGLE_RANGE("ALC Decay", R_ALCCTL3,
1701 FB_ALCCTL3_DCY, 0, FM_ALCCTL3_DCY, 0),
1702 SOC_SINGLE_RANGE("ALC Attack", R_ALCCTL3,
1703 FB_ALCCTL3_ATK, 0, FM_ALCCTL3_ATK, 0),
1704 /* R_NGATE PG 1 ADDR 0x21 */
1705 SOC_SINGLE_TLV("Noise Gate Threshold Volume", R_NGATE,
1706 FB_NGATE_NGTH, FM_NGATE_NGTH, 0, ngth_tlv_arr),
1707 SOC_ENUM("Noise Gate Type", ngate_type_enum),
1708 SOC_SINGLE("Noise Gate Switch", R_NGATE, FB_NGATE_NGAT, 1, 0),
1709 /* R_DMICCTL PG 1 ADDR 0x22 */
1710 SOC_SINGLE("Digital Mic 2 Switch", R_DMICCTL, FB_DMICCTL_DMIC2EN, 1, 0),
1711 SOC_SINGLE("Digital Mic 1 Switch", R_DMICCTL, FB_DMICCTL_DMIC1EN, 1, 0),
1712 SOC_ENUM("Digital Mic Mono Select", dmic_mono_sel_enum),
1713 /* R_DACCTL PG 2 ADDR 0x01 */
1714 SOC_ENUM("DAC Polarity Left", dac_pol_r_enum),
1715 SOC_ENUM("DAC Polarity Right", dac_pol_l_enum),
1716 SOC_ENUM("DAC Dither", dac_dith_enum),
1717 SOC_SINGLE("DAC Mute Switch", R_DACCTL, FB_DACCTL_DACMUTE, 1, 0),
1718 SOC_SINGLE("DAC De-Emphasis Switch", R_DACCTL, FB_DACCTL_DACDEM, 1, 0),
1719 /* R_SPKCTL PG 2 ADDR 0x02 */
1720 SOC_ENUM("Speaker Polarity Right", spk_pol_r_enum),
1721 SOC_ENUM("Speaker Polarity Left", spk_pol_l_enum),
1722 SOC_SINGLE("Speaker Mute Switch", R_SPKCTL, FB_SPKCTL_SPKMUTE, 1, 0),
1723 SOC_SINGLE("Speaker De-Emphasis Switch",
1724 R_SPKCTL, FB_SPKCTL_SPKDEM, 1, 0),
1725 /* R_SUBCTL PG 2 ADDR 0x03 */
1726 SOC_ENUM("Sub Polarity", sub_pol_enum),
1727 SOC_SINGLE("SUB Mute Switch", R_SUBCTL, FB_SUBCTL_SUBMUTE, 1, 0),
1728 SOC_SINGLE("Sub De-Emphasis Switch", R_SUBCTL, FB_SUBCTL_SUBDEM, 1, 0),
1729 /* R_DCCTL PG 2 ADDR 0x04 */
1730 SOC_SINGLE("Sub DC Removal Switch", R_DCCTL, FB_DCCTL_SUBDCBYP, 1, 1),
1731 SOC_SINGLE("DAC DC Removal Switch", R_DCCTL, FB_DCCTL_DACDCBYP, 1, 1),
1732 SOC_SINGLE("Speaker DC Removal Switch",
1733 R_DCCTL, FB_DCCTL_SPKDCBYP, 1, 1),
1734 SOC_SINGLE("DC Removal Coefficient Switch", R_DCCTL, FB_DCCTL_DCCOEFSEL,
1735 FM_DCCTL_DCCOEFSEL, 0),
1736 /* R_OVOLCTLU PG 2 ADDR 0x06 */
1737 SOC_SINGLE("Output Fade Switch", R_OVOLCTLU, FB_OVOLCTLU_OFADE, 1, 0),
1738 /* R_MVOLL PG 2 ADDR 0x08 */
1739 /* R_MVOLR PG 2 ADDR 0x09 */
1740 SOC_DOUBLE_R_TLV("Master Volume", R_MVOLL, R_MVOLR,
1741 FB_MVOLL_MVOL_L, FM_MVOLL_MVOL_L, 0, mvol_tlv_arr),
1742 /* R_HPVOLL PG 2 ADDR 0x0A */
1743 /* R_HPVOLR PG 2 ADDR 0x0B */
1744 SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR,
1745 FB_HPVOLL_HPVOL_L, FM_HPVOLL_HPVOL_L, 0,
1746 hp_vol_tlv_arr),
1747 /* R_SPKVOLL PG 2 ADDR 0x0C */
1748 /* R_SPKVOLR PG 2 ADDR 0x0D */
1749 SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR,
1750 FB_SPKVOLL_SPKVOL_L, FM_SPKVOLL_SPKVOL_L, 0,
1751 spk_vol_tlv_arr),
1752 /* R_SUBVOL PG 2 ADDR 0x10 */
1753 SOC_SINGLE_TLV("Sub Volume", R_SUBVOL,
1754 FB_SUBVOL_SUBVOL, FM_SUBVOL_SUBVOL, 0, spk_vol_tlv_arr),
1755 /* R_SPKEQFILT PG 3 ADDR 0x01 */
1756 SOC_SINGLE("Speaker EQ 2 Switch",
1757 R_SPKEQFILT, FB_SPKEQFILT_EQ2EN, 1, 0),
1758 SOC_ENUM("Speaker EQ 2 Band", spk_eq_enums[0]),
1759 SOC_SINGLE("Speaker EQ 1 Switch",
1760 R_SPKEQFILT, FB_SPKEQFILT_EQ1EN, 1, 0),
1761 SOC_ENUM("Speaker EQ 1 Band", spk_eq_enums[1]),
1762 /* R_SPKMBCEN PG 3 ADDR 0x0A */
1763 SOC_SINGLE("Speaker MBC 3 Switch",
1764 R_SPKMBCEN, FB_SPKMBCEN_MBCEN3, 1, 0),
1765 SOC_SINGLE("Speaker MBC 2 Switch",
1766 R_SPKMBCEN, FB_SPKMBCEN_MBCEN2, 1, 0),
1767 SOC_SINGLE("Speaker MBC 1 Switch",
1768 R_SPKMBCEN, FB_SPKMBCEN_MBCEN1, 1, 0),
1769 /* R_SPKMBCCTL PG 3 ADDR 0x0B */
1770 SOC_ENUM("Speaker MBC 3 Mode", spk_mbc3_lvl_det_mode_enum),
1771 SOC_ENUM("Speaker MBC 3 Window", spk_mbc3_win_sel_enum),
1772 SOC_ENUM("Speaker MBC 2 Mode", spk_mbc2_lvl_det_mode_enum),
1773 SOC_ENUM("Speaker MBC 2 Window", spk_mbc2_win_sel_enum),
1774 SOC_ENUM("Speaker MBC 1 Mode", spk_mbc1_lvl_det_mode_enum),
1775 SOC_ENUM("Speaker MBC 1 Window", spk_mbc1_win_sel_enum),
1776 /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
1777 SOC_ENUM("Speaker MBC 1 Phase Polarity", spk_mbc1_phase_pol_enum),
1778 SOC_SINGLE_TLV("Speaker MBC1 Make-Up Gain Volume", R_SPKMBCMUG1,
1779 FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1780 0, mbc_mug_tlv_arr),
1781 /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
1782 SOC_SINGLE_TLV("Speaker MBC 1 Compressor Threshold Volume",
1783 R_SPKMBCTHR1, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1784 0, thr_tlv_arr),
1785 /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
1786 SOC_ENUM("Speaker MBC 1 Compressor Ratio", spk_mbc1_comp_rat_enum),
1787 /* R_SPKMBCATK1L PG 3 ADDR 0x0F */
1788 /* R_SPKMBCATK1H PG 3 ADDR 0x10 */
1789 SND_SOC_BYTES("Speaker MBC 1 Attack", R_SPKMBCATK1L, 2),
1790 /* R_SPKMBCREL1L PG 3 ADDR 0x11 */
1791 /* R_SPKMBCREL1H PG 3 ADDR 0x12 */
1792 SND_SOC_BYTES("Speaker MBC 1 Release", R_SPKMBCREL1L, 2),
1793 /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
1794 SOC_ENUM("Speaker MBC 2 Phase Polarity", spk_mbc2_phase_pol_enum),
1795 SOC_SINGLE_TLV("Speaker MBC2 Make-Up Gain Volume", R_SPKMBCMUG2,
1796 FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1797 0, mbc_mug_tlv_arr),
1798 /* R_SPKMBCTHR2 PG 3 ADDR 0x14 */
1799 SOC_SINGLE_TLV("Speaker MBC 2 Compressor Threshold Volume",
1800 R_SPKMBCTHR2, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1801 0, thr_tlv_arr),
1802 /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
1803 SOC_ENUM("Speaker MBC 2 Compressor Ratio", spk_mbc2_comp_rat_enum),
1804 /* R_SPKMBCATK2L PG 3 ADDR 0x16 */
1805 /* R_SPKMBCATK2H PG 3 ADDR 0x17 */
1806 SND_SOC_BYTES("Speaker MBC 2 Attack", R_SPKMBCATK2L, 2),
1807 /* R_SPKMBCREL2L PG 3 ADDR 0x18 */
1808 /* R_SPKMBCREL2H PG 3 ADDR 0x19 */
1809 SND_SOC_BYTES("Speaker MBC 2 Release", R_SPKMBCREL2L, 2),
1810 /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
1811 SOC_ENUM("Speaker MBC 3 Phase Polarity", spk_mbc3_phase_pol_enum),
1812 SOC_SINGLE_TLV("Speaker MBC 3 Make-Up Gain Volume", R_SPKMBCMUG3,
1813 FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1814 0, mbc_mug_tlv_arr),
1815 /* R_SPKMBCTHR3 PG 3 ADDR 0x1B */
1816 SOC_SINGLE_TLV("Speaker MBC 3 Threshold Volume", R_SPKMBCTHR3,
1817 FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1818 0, thr_tlv_arr),
1819 /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
1820 SOC_ENUM("Speaker MBC 3 Compressor Ratio", spk_mbc3_comp_rat_enum),
1821 /* R_SPKMBCATK3L PG 3 ADDR 0x1D */
1822 /* R_SPKMBCATK3H PG 3 ADDR 0x1E */
1823 SND_SOC_BYTES("Speaker MBC 3 Attack", R_SPKMBCATK3L, 3),
1824 /* R_SPKMBCREL3L PG 3 ADDR 0x1F */
1825 /* R_SPKMBCREL3H PG 3 ADDR 0x20 */
1826 SND_SOC_BYTES("Speaker MBC 3 Release", R_SPKMBCREL3L, 3),
1827 /* R_SPKCLECTL PG 3 ADDR 0x21 */
1828 SOC_ENUM("Speaker CLE Level Mode", spk_cle_lvl_mode_enum),
1829 SOC_ENUM("Speaker CLE Window", spk_cle_win_sel_enum),
1830 SOC_SINGLE("Speaker CLE Expander Switch",
1831 R_SPKCLECTL, FB_SPKCLECTL_EXPEN, 1, 0),
1832 SOC_SINGLE("Speaker CLE Limiter Switch",
1833 R_SPKCLECTL, FB_SPKCLECTL_LIMEN, 1, 0),
1834 SOC_SINGLE("Speaker CLE Compressor Switch",
1835 R_SPKCLECTL, FB_SPKCLECTL_COMPEN, 1, 0),
1836 /* R_SPKCLEMUG PG 3 ADDR 0x22 */
1837 SOC_SINGLE_TLV("Speaker CLE Make-Up Gain Volume", R_SPKCLEMUG,
1838 FB_SPKCLEMUG_MUGAIN, FM_SPKCLEMUG_MUGAIN,
1839 0, cle_mug_tlv_arr),
1840 /* R_SPKCOMPTHR PG 3 ADDR 0x23 */
1841 SOC_SINGLE_TLV("Speaker Compressor Threshold Volume", R_SPKCOMPTHR,
1842 FB_SPKCOMPTHR_THRESH, FM_SPKCOMPTHR_THRESH,
1843 0, thr_tlv_arr),
1844 /* R_SPKCOMPRAT PG 3 ADDR 0x24 */
1845 SOC_ENUM("Speaker Compressor Ratio", spk_comp_rat_enum),
1846 /* R_SPKCOMPATKL PG 3 ADDR 0x25 */
1847 /* R_SPKCOMPATKH PG 3 ADDR 0x26 */
1848 SND_SOC_BYTES("Speaker Compressor Attack", R_SPKCOMPATKL, 2),
1849 /* R_SPKCOMPRELL PG 3 ADDR 0x27 */
1850 /* R_SPKCOMPRELH PG 3 ADDR 0x28 */
1851 SND_SOC_BYTES("Speaker Compressor Release", R_SPKCOMPRELL, 2),
1852 /* R_SPKLIMTHR PG 3 ADDR 0x29 */
1853 SOC_SINGLE_TLV("Speaker Limiter Threshold Volume", R_SPKLIMTHR,
1854 FB_SPKLIMTHR_THRESH, FM_SPKLIMTHR_THRESH,
1855 0, thr_tlv_arr),
1856 /* R_SPKLIMTGT PG 3 ADDR 0x2A */
1857 SOC_SINGLE_TLV("Speaker Limiter Target Volume", R_SPKLIMTGT,
1858 FB_SPKLIMTGT_TARGET, FM_SPKLIMTGT_TARGET,
1859 0, thr_tlv_arr),
1860 /* R_SPKLIMATKL PG 3 ADDR 0x2B */
1861 /* R_SPKLIMATKH PG 3 ADDR 0x2C */
1862 SND_SOC_BYTES("Speaker Limiter Attack", R_SPKLIMATKL, 2),
1863 /* R_SPKLIMRELL PG 3 ADDR 0x2D */
1864 /* R_SPKLIMRELR PG 3 ADDR 0x2E */
1865 SND_SOC_BYTES("Speaker Limiter Release", R_SPKLIMRELL, 2),
1866 /* R_SPKEXPTHR PG 3 ADDR 0x2F */
1867 SOC_SINGLE_TLV("Speaker Expander Threshold Volume", R_SPKEXPTHR,
1868 FB_SPKEXPTHR_THRESH, FM_SPKEXPTHR_THRESH,
1869 0, thr_tlv_arr),
1870 /* R_SPKEXPRAT PG 3 ADDR 0x30 */
1871 SOC_ENUM("Speaker Expander Ratio", spk_exp_rat_enum),
1872 /* R_SPKEXPATKL PG 3 ADDR 0x31 */
1873 /* R_SPKEXPATKR PG 3 ADDR 0x32 */
1874 SND_SOC_BYTES("Speaker Expander Attack", R_SPKEXPATKL, 2),
1875 /* R_SPKEXPRELL PG 3 ADDR 0x33 */
1876 /* R_SPKEXPRELR PG 3 ADDR 0x34 */
1877 SND_SOC_BYTES("Speaker Expander Release", R_SPKEXPRELL, 2),
1878 /* R_SPKFXCTL PG 3 ADDR 0x35 */
1879 SOC_SINGLE("Speaker 3D Switch", R_SPKFXCTL, FB_SPKFXCTL_3DEN, 1, 0),
1880 SOC_SINGLE("Speaker Treble Enhancement Switch",
1881 R_SPKFXCTL, FB_SPKFXCTL_TEEN, 1, 0),
1882 SOC_SINGLE("Speaker Treble NLF Switch",
1883 R_SPKFXCTL, FB_SPKFXCTL_TNLFBYP, 1, 1),
1884 SOC_SINGLE("Speaker Bass Enhancement Switch",
1885 R_SPKFXCTL, FB_SPKFXCTL_BEEN, 1, 0),
1886 SOC_SINGLE("Speaker Bass NLF Switch",
1887 R_SPKFXCTL, FB_SPKFXCTL_BNLFBYP, 1, 1),
1888 /* R_DACEQFILT PG 4 ADDR 0x01 */
1889 SOC_SINGLE("DAC EQ 2 Switch",
1890 R_DACEQFILT, FB_DACEQFILT_EQ2EN, 1, 0),
1891 SOC_ENUM("DAC EQ 2 Band", dac_eq_enums[0]),
1892 SOC_SINGLE("DAC EQ 1 Switch", R_DACEQFILT, FB_DACEQFILT_EQ1EN, 1, 0),
1893 SOC_ENUM("DAC EQ 1 Band", dac_eq_enums[1]),
1894 /* R_DACMBCEN PG 4 ADDR 0x0A */
1895 SOC_SINGLE("DAC MBC 3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0),
1896 SOC_SINGLE("DAC MBC 2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0),
1897 SOC_SINGLE("DAC MBC 1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0),
1898 /* R_DACMBCCTL PG 4 ADDR 0x0B */
1899 SOC_ENUM("DAC MBC 3 Mode", dac_mbc3_lvl_det_mode_enum),
1900 SOC_ENUM("DAC MBC 3 Window", dac_mbc3_win_sel_enum),
1901 SOC_ENUM("DAC MBC 2 Mode", dac_mbc2_lvl_det_mode_enum),
1902 SOC_ENUM("DAC MBC 2 Window", dac_mbc2_win_sel_enum),
1903 SOC_ENUM("DAC MBC 1 Mode", dac_mbc1_lvl_det_mode_enum),
1904 SOC_ENUM("DAC MBC 1 Window", dac_mbc1_win_sel_enum),
1905 /* R_DACMBCMUG1 PG 4 ADDR 0x0C */
1906 SOC_ENUM("DAC MBC 1 Phase Polarity", dac_mbc1_phase_pol_enum),
1907 SOC_SINGLE_TLV("DAC MBC 1 Make-Up Gain Volume", R_DACMBCMUG1,
1908 FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1909 0, mbc_mug_tlv_arr),
1910 /* R_DACMBCTHR1 PG 4 ADDR 0x0D */
1911 SOC_SINGLE_TLV("DAC MBC 1 Compressor Threshold Volume", R_DACMBCTHR1,
1912 FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1913 0, thr_tlv_arr),
1914 /* R_DACMBCRAT1 PG 4 ADDR 0x0E */
1915 SOC_ENUM("DAC MBC 1 Compressor Ratio", dac_mbc1_comp_rat_enum),
1916 /* R_DACMBCATK1L PG 4 ADDR 0x0F */
1917 /* R_DACMBCATK1H PG 4 ADDR 0x10 */
1918 SND_SOC_BYTES("DAC MBC 1 Attack", R_DACMBCATK1L, 2),
1919 /* R_DACMBCREL1L PG 4 ADDR 0x11 */
1920 /* R_DACMBCREL1H PG 4 ADDR 0x12 */
1921 SND_SOC_BYTES("DAC MBC 1 Release", R_DACMBCREL1L, 2),
1922 /* R_DACMBCMUG2 PG 4 ADDR 0x13 */
1923 SOC_ENUM("DAC MBC 2 Phase Polarity", dac_mbc2_phase_pol_enum),
1924 SOC_SINGLE_TLV("DAC MBC 2 Make-Up Gain Volume", R_DACMBCMUG2,
1925 FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1926 0, mbc_mug_tlv_arr),
1927 /* R_DACMBCTHR2 PG 4 ADDR 0x14 */
1928 SOC_SINGLE_TLV("DAC MBC 2 Compressor Threshold Volume", R_DACMBCTHR2,
1929 FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1930 0, thr_tlv_arr),
1931 /* R_DACMBCRAT2 PG 4 ADDR 0x15 */
1932 SOC_ENUM("DAC MBC 2 Compressor Ratio", dac_mbc2_comp_rat_enum),
1933 /* R_DACMBCATK2L PG 4 ADDR 0x16 */
1934 /* R_DACMBCATK2H PG 4 ADDR 0x17 */
1935 SND_SOC_BYTES("DAC MBC 2 Attack", R_DACMBCATK2L, 2),
1936 /* R_DACMBCREL2L PG 4 ADDR 0x18 */
1937 /* R_DACMBCREL2H PG 4 ADDR 0x19 */
1938 SND_SOC_BYTES("DAC MBC 2 Release", R_DACMBCREL2L, 2),
1939 /* R_DACMBCMUG3 PG 4 ADDR 0x1A */
1940 SOC_ENUM("DAC MBC 3 Phase Polarity", dac_mbc3_phase_pol_enum),
1941 SOC_SINGLE_TLV("DAC MBC 3 Make-Up Gain Volume", R_DACMBCMUG3,
1942 FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1943 0, mbc_mug_tlv_arr),
1944 /* R_DACMBCTHR3 PG 4 ADDR 0x1B */
1945 SOC_SINGLE_TLV("DAC MBC 3 Threshold Volume", R_DACMBCTHR3,
1946 FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1947 0, thr_tlv_arr),
1948 /* R_DACMBCRAT3 PG 4 ADDR 0x1C */
1949 SOC_ENUM("DAC MBC 3 Compressor Ratio", dac_mbc3_comp_rat_enum),
1950 /* R_DACMBCATK3L PG 4 ADDR 0x1D */
1951 /* R_DACMBCATK3H PG 4 ADDR 0x1E */
1952 SND_SOC_BYTES("DAC MBC 3 Attack", R_DACMBCATK3L, 3),
1953 /* R_DACMBCREL3L PG 4 ADDR 0x1F */
1954 /* R_DACMBCREL3H PG 4 ADDR 0x20 */
1955 SND_SOC_BYTES("DAC MBC 3 Release", R_DACMBCREL3L, 3),
1956 /* R_DACCLECTL PG 4 ADDR 0x21 */
1957 SOC_ENUM("DAC CLE Level Mode", dac_cle_lvl_mode_enum),
1958 SOC_ENUM("DAC CLE Window", dac_cle_win_sel_enum),
1959 SOC_SINGLE("DAC CLE Expander Switch",
1960 R_DACCLECTL, FB_DACCLECTL_EXPEN, 1, 0),
1961 SOC_SINGLE("DAC CLE Limiter Switch",
1962 R_DACCLECTL, FB_DACCLECTL_LIMEN, 1, 0),
1963 SOC_SINGLE("DAC CLE Compressor Switch",
1964 R_DACCLECTL, FB_DACCLECTL_COMPEN, 1, 0),
1965 /* R_DACCLEMUG PG 4 ADDR 0x22 */
1966 SOC_SINGLE_TLV("DAC CLE Make-Up Gain Volume", R_DACCLEMUG,
1967 FB_DACCLEMUG_MUGAIN, FM_DACCLEMUG_MUGAIN,
1968 0, cle_mug_tlv_arr),
1969 /* R_DACCOMPTHR PG 4 ADDR 0x23 */
1970 SOC_SINGLE_TLV("DAC Compressor Threshold Volume", R_DACCOMPTHR,
1971 FB_DACCOMPTHR_THRESH, FM_DACCOMPTHR_THRESH,
1972 0, thr_tlv_arr),
1973 /* R_DACCOMPRAT PG 4 ADDR 0x24 */
1974 SOC_ENUM("DAC Compressor Ratio", dac_comp_rat_enum),
1975 /* R_DACCOMPATKL PG 4 ADDR 0x25 */
1976 /* R_DACCOMPATKH PG 4 ADDR 0x26 */
1977 SND_SOC_BYTES("DAC Compressor Attack", R_DACCOMPATKL, 2),
1978 /* R_DACCOMPRELL PG 4 ADDR 0x27 */
1979 /* R_DACCOMPRELH PG 4 ADDR 0x28 */
1980 SND_SOC_BYTES("DAC Compressor Release", R_DACCOMPRELL, 2),
1981 /* R_DACLIMTHR PG 4 ADDR 0x29 */
1982 SOC_SINGLE_TLV("DAC Limiter Threshold Volume", R_DACLIMTHR,
1983 FB_DACLIMTHR_THRESH, FM_DACLIMTHR_THRESH,
1984 0, thr_tlv_arr),
1985 /* R_DACLIMTGT PG 4 ADDR 0x2A */
1986 SOC_SINGLE_TLV("DAC Limiter Target Volume", R_DACLIMTGT,
1987 FB_DACLIMTGT_TARGET, FM_DACLIMTGT_TARGET,
1988 0, thr_tlv_arr),
1989 /* R_DACLIMATKL PG 4 ADDR 0x2B */
1990 /* R_DACLIMATKH PG 4 ADDR 0x2C */
1991 SND_SOC_BYTES("DAC Limiter Attack", R_DACLIMATKL, 2),
1992 /* R_DACLIMRELL PG 4 ADDR 0x2D */
1993 /* R_DACLIMRELR PG 4 ADDR 0x2E */
1994 SND_SOC_BYTES("DAC Limiter Release", R_DACLIMRELL, 2),
1995 /* R_DACEXPTHR PG 4 ADDR 0x2F */
1996 SOC_SINGLE_TLV("DAC Expander Threshold Volume", R_DACEXPTHR,
1997 FB_DACEXPTHR_THRESH, FM_DACEXPTHR_THRESH,
1998 0, thr_tlv_arr),
1999 /* R_DACEXPRAT PG 4 ADDR 0x30 */
2000 SOC_ENUM("DAC Expander Ratio", dac_exp_rat_enum),
2001 /* R_DACEXPATKL PG 4 ADDR 0x31 */
2002 /* R_DACEXPATKR PG 4 ADDR 0x32 */
2003 SND_SOC_BYTES("DAC Expander Attack", R_DACEXPATKL, 2),
2004 /* R_DACEXPRELL PG 4 ADDR 0x33 */
2005 /* R_DACEXPRELR PG 4 ADDR 0x34 */
2006 SND_SOC_BYTES("DAC Expander Release", R_DACEXPRELL, 2),
2007 /* R_DACFXCTL PG 4 ADDR 0x35 */
2008 SOC_SINGLE("DAC 3D Switch", R_DACFXCTL, FB_DACFXCTL_3DEN, 1, 0),
2009 SOC_SINGLE("DAC Treble Enhancement Switch",
2010 R_DACFXCTL, FB_DACFXCTL_TEEN, 1, 0),
2011 SOC_SINGLE("DAC Treble NLF Switch",
2012 R_DACFXCTL, FB_DACFXCTL_TNLFBYP, 1, 1),
2013 SOC_SINGLE("DAC Bass Enhancement Switch",
2014 R_DACFXCTL, FB_DACFXCTL_BEEN, 1, 0),
2015 SOC_SINGLE("DAC Bass NLF Switch",
2016 R_DACFXCTL, FB_DACFXCTL_BNLFBYP, 1, 1),
2017 /* R_SUBEQFILT PG 5 ADDR 0x01 */
2018 SOC_SINGLE("Sub EQ 2 Switch",
2019 R_SUBEQFILT, FB_SUBEQFILT_EQ2EN, 1, 0),
2020 SOC_ENUM("Sub EQ 2 Band", sub_eq_enums[0]),
2021 SOC_SINGLE("Sub EQ 1 Switch", R_SUBEQFILT, FB_SUBEQFILT_EQ1EN, 1, 0),
2022 SOC_ENUM("Sub EQ 1 Band", sub_eq_enums[1]),
2023 /* R_SUBMBCEN PG 5 ADDR 0x0A */
2024 SOC_SINGLE("Sub MBC 3 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN3, 1, 0),
2025 SOC_SINGLE("Sub MBC 2 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN2, 1, 0),
2026 SOC_SINGLE("Sub MBC 1 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN1, 1, 0),
2027 /* R_SUBMBCCTL PG 5 ADDR 0x0B */
2028 SOC_ENUM("Sub MBC 3 Mode", sub_mbc3_lvl_det_mode_enum),
2029 SOC_ENUM("Sub MBC 3 Window", sub_mbc3_win_sel_enum),
2030 SOC_ENUM("Sub MBC 2 Mode", sub_mbc2_lvl_det_mode_enum),
2031 SOC_ENUM("Sub MBC 2 Window", sub_mbc2_win_sel_enum),
2032 SOC_ENUM("Sub MBC 1 Mode", sub_mbc1_lvl_det_mode_enum),
2033 SOC_ENUM("Sub MBC 1 Window", sub_mbc1_win_sel_enum),
2034 /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
2035 SOC_ENUM("Sub MBC 1 Phase Polarity", sub_mbc1_phase_pol_enum),
2036 SOC_SINGLE_TLV("Sub MBC 1 Make-Up Gain Volume", R_SUBMBCMUG1,
2037 FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2038 0, mbc_mug_tlv_arr),
2039 /* R_SUBMBCTHR1 PG 5 ADDR 0x0D */
2040 SOC_SINGLE_TLV("Sub MBC 1 Compressor Threshold Volume", R_SUBMBCTHR1,
2041 FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2042 0, thr_tlv_arr),
2043 /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
2044 SOC_ENUM("Sub MBC 1 Compressor Ratio", sub_mbc1_comp_rat_enum),
2045 /* R_SUBMBCATK1L PG 5 ADDR 0x0F */
2046 /* R_SUBMBCATK1H PG 5 ADDR 0x10 */
2047 SND_SOC_BYTES("Sub MBC 1 Attack", R_SUBMBCATK1L, 2),
2048 /* R_SUBMBCREL1L PG 5 ADDR 0x11 */
2049 /* R_SUBMBCREL1H PG 5 ADDR 0x12 */
2050 SND_SOC_BYTES("Sub MBC 1 Release", R_SUBMBCREL1L, 2),
2051 /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
2052 SOC_ENUM("Sub MBC 2 Phase Polarity", sub_mbc2_phase_pol_enum),
2053 SOC_SINGLE_TLV("Sub MBC 2 Make-Up Gain Volume", R_SUBMBCMUG2,
2054 FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2055 0, mbc_mug_tlv_arr),
2056 /* R_SUBMBCTHR2 PG 5 ADDR 0x14 */
2057 SOC_SINGLE_TLV("Sub MBC 2 Compressor Threshold Volume", R_SUBMBCTHR2,
2058 FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2059 0, thr_tlv_arr),
2060 /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
2061 SOC_ENUM("Sub MBC 2 Compressor Ratio", sub_mbc2_comp_rat_enum),
2062 /* R_SUBMBCATK2L PG 5 ADDR 0x16 */
2063 /* R_SUBMBCATK2H PG 5 ADDR 0x17 */
2064 SND_SOC_BYTES("Sub MBC 2 Attack", R_SUBMBCATK2L, 2),
2065 /* R_SUBMBCREL2L PG 5 ADDR 0x18 */
2066 /* R_SUBMBCREL2H PG 5 ADDR 0x19 */
2067 SND_SOC_BYTES("Sub MBC 2 Release", R_SUBMBCREL2L, 2),
2068 /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
2069 SOC_ENUM("Sub MBC 3 Phase Polarity", sub_mbc3_phase_pol_enum),
2070 SOC_SINGLE_TLV("Sub MBC 3 Make-Up Gain Volume", R_SUBMBCMUG3,
2071 FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2072 0, mbc_mug_tlv_arr),
2073 /* R_SUBMBCTHR3 PG 5 ADDR 0x1B */
2074 SOC_SINGLE_TLV("Sub MBC 3 Threshold Volume", R_SUBMBCTHR3,
2075 FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2076 0, thr_tlv_arr),
2077 /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
2078 SOC_ENUM("Sub MBC 3 Compressor Ratio", sub_mbc3_comp_rat_enum),
2079 /* R_SUBMBCATK3L PG 5 ADDR 0x1D */
2080 /* R_SUBMBCATK3H PG 5 ADDR 0x1E */
2081 SND_SOC_BYTES("Sub MBC 3 Attack", R_SUBMBCATK3L, 3),
2082 /* R_SUBMBCREL3L PG 5 ADDR 0x1F */
2083 /* R_SUBMBCREL3H PG 5 ADDR 0x20 */
2084 SND_SOC_BYTES("Sub MBC 3 Release", R_SUBMBCREL3L, 3),
2085 /* R_SUBCLECTL PG 5 ADDR 0x21 */
2086 SOC_ENUM("Sub CLE Level Mode", sub_cle_lvl_mode_enum),
2087 SOC_ENUM("Sub CLE Window", sub_cle_win_sel_enum),
2088 SOC_SINGLE("Sub CLE Expander Switch",
2089 R_SUBCLECTL, FB_SUBCLECTL_EXPEN, 1, 0),
2090 SOC_SINGLE("Sub CLE Limiter Switch",
2091 R_SUBCLECTL, FB_SUBCLECTL_LIMEN, 1, 0),
2092 SOC_SINGLE("Sub CLE Compressor Switch",
2093 R_SUBCLECTL, FB_SUBCLECTL_COMPEN, 1, 0),
2094 /* R_SUBCLEMUG PG 5 ADDR 0x22 */
2095 SOC_SINGLE_TLV("Sub CLE Make-Up Gain Volume", R_SUBCLEMUG,
2096 FB_SUBCLEMUG_MUGAIN, FM_SUBCLEMUG_MUGAIN,
2097 0, cle_mug_tlv_arr),
2098 /* R_SUBCOMPTHR PG 5 ADDR 0x23 */
2099 SOC_SINGLE_TLV("Sub Compressor Threshold Volume", R_SUBCOMPTHR,
2100 FB_SUBCOMPTHR_THRESH, FM_SUBCOMPTHR_THRESH,
2101 0, thr_tlv_arr),
2102 /* R_SUBCOMPRAT PG 5 ADDR 0x24 */
2103 SOC_ENUM("Sub Compressor Ratio", sub_comp_rat_enum),
2104 /* R_SUBCOMPATKL PG 5 ADDR 0x25 */
2105 /* R_SUBCOMPATKH PG 5 ADDR 0x26 */
2106 SND_SOC_BYTES("Sub Compressor Attack", R_SUBCOMPATKL, 2),
2107 /* R_SUBCOMPRELL PG 5 ADDR 0x27 */
2108 /* R_SUBCOMPRELH PG 5 ADDR 0x28 */
2109 SND_SOC_BYTES("Sub Compressor Release", R_SUBCOMPRELL, 2),
2110 /* R_SUBLIMTHR PG 5 ADDR 0x29 */
2111 SOC_SINGLE_TLV("Sub Limiter Threshold Volume", R_SUBLIMTHR,
2112 FB_SUBLIMTHR_THRESH, FM_SUBLIMTHR_THRESH,
2113 0, thr_tlv_arr),
2114 /* R_SUBLIMTGT PG 5 ADDR 0x2A */
2115 SOC_SINGLE_TLV("Sub Limiter Target Volume", R_SUBLIMTGT,
2116 FB_SUBLIMTGT_TARGET, FM_SUBLIMTGT_TARGET,
2117 0, thr_tlv_arr),
2118 /* R_SUBLIMATKL PG 5 ADDR 0x2B */
2119 /* R_SUBLIMATKH PG 5 ADDR 0x2C */
2120 SND_SOC_BYTES("Sub Limiter Attack", R_SUBLIMATKL, 2),
2121 /* R_SUBLIMRELL PG 5 ADDR 0x2D */
2122 /* R_SUBLIMRELR PG 5 ADDR 0x2E */
2123 SND_SOC_BYTES("Sub Limiter Release", R_SUBLIMRELL, 2),
2124 /* R_SUBEXPTHR PG 5 ADDR 0x2F */
2125 SOC_SINGLE_TLV("Sub Expander Threshold Volume", R_SUBEXPTHR,
2126 FB_SUBEXPTHR_THRESH, FM_SUBEXPTHR_THRESH,
2127 0, thr_tlv_arr),
2128 /* R_SUBEXPRAT PG 5 ADDR 0x30 */
2129 SOC_ENUM("Sub Expander Ratio", sub_exp_rat_enum),
2130 /* R_SUBEXPATKL PG 5 ADDR 0x31 */
2131 /* R_SUBEXPATKR PG 5 ADDR 0x32 */
2132 SND_SOC_BYTES("Sub Expander Attack", R_SUBEXPATKL, 2),
2133 /* R_SUBEXPRELL PG 5 ADDR 0x33 */
2134 /* R_SUBEXPRELR PG 5 ADDR 0x34 */
2135 SND_SOC_BYTES("Sub Expander Release", R_SUBEXPRELL, 2),
2136 /* R_SUBFXCTL PG 5 ADDR 0x35 */
2137 SOC_SINGLE("Sub Treble Enhancement Switch",
2138 R_SUBFXCTL, FB_SUBFXCTL_TEEN, 1, 0),
2139 SOC_SINGLE("Sub Treble NLF Switch",
2140 R_SUBFXCTL, FB_SUBFXCTL_TNLFBYP, 1, 1),
2141 SOC_SINGLE("Sub Bass Enhancement Switch",
2142 R_SUBFXCTL, FB_SUBFXCTL_BEEN, 1, 0),
2143 SOC_SINGLE("Sub Bass NLF Switch",
2144 R_SUBFXCTL, FB_SUBFXCTL_BNLFBYP, 1, 1),
2145 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2146 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2147 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2148 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2149 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2150 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2151
2152 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2153 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2154 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2155 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2156 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2157 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2158
2159 COEFF_RAM_CTL("DAC Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2160 COEFF_RAM_CTL("DAC Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2161
2162 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2163 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2164 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2165 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2166 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2167 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2168
2169 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2170 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2171 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2172 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2173 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2174 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2175
2176 COEFF_RAM_CTL("DAC Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2177 COEFF_RAM_CTL("DAC Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2178
2179 COEFF_RAM_CTL("DAC Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2180 COEFF_RAM_CTL("DAC Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2181
2182 COEFF_RAM_CTL("DAC Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2183 COEFF_RAM_CTL("DAC Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2184
2185 COEFF_RAM_CTL("DAC Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2186
2187 COEFF_RAM_CTL("DAC Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2188
2189 COEFF_RAM_CTL("DAC Bass Mix", COEFF_SIZE, 0x96),
2190
2191 COEFF_RAM_CTL("DAC Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2192 COEFF_RAM_CTL("DAC Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2193
2194 COEFF_RAM_CTL("DAC Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2195 COEFF_RAM_CTL("DAC Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2196
2197 COEFF_RAM_CTL("DAC Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2198
2199 COEFF_RAM_CTL("DAC Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2200
2201 COEFF_RAM_CTL("DAC Treb Mix", COEFF_SIZE, 0xad),
2202
2203 COEFF_RAM_CTL("DAC 3D", COEFF_SIZE, 0xae),
2204
2205 COEFF_RAM_CTL("DAC 3D Mix", COEFF_SIZE, 0xaf),
2206
2207 COEFF_RAM_CTL("DAC MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2208 COEFF_RAM_CTL("DAC MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2209
2210 COEFF_RAM_CTL("DAC MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2211 COEFF_RAM_CTL("DAC MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2212
2213 COEFF_RAM_CTL("DAC MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2214 COEFF_RAM_CTL("DAC MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2215
2216 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2217 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2218 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2219 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2220 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2221 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2222
2223 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2224 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2225 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2226 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2227 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2228 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2229
2230 COEFF_RAM_CTL("Speaker Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2231 COEFF_RAM_CTL("Speaker Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2232
2233 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2234 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2235 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2236 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2237 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2238 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2239
2240 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2241 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2242 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2243 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2244 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2245 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2246
2247 COEFF_RAM_CTL("Speaker Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2248 COEFF_RAM_CTL("Speaker Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2249
2250 COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2251 COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2252
2253 COEFF_RAM_CTL("Speaker Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2254 COEFF_RAM_CTL("Speaker Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2255
2256 COEFF_RAM_CTL("Speaker Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2257
2258 COEFF_RAM_CTL("Speaker Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2259
2260 COEFF_RAM_CTL("Speaker Bass Mix", COEFF_SIZE, 0x96),
2261
2262 COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2263 COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2264
2265 COEFF_RAM_CTL("Speaker Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2266 COEFF_RAM_CTL("Speaker Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2267
2268 COEFF_RAM_CTL("Speaker Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2269
2270 COEFF_RAM_CTL("Speaker Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2271
2272 COEFF_RAM_CTL("Speaker Treb Mix", COEFF_SIZE, 0xad),
2273
2274 COEFF_RAM_CTL("Speaker 3D", COEFF_SIZE, 0xae),
2275
2276 COEFF_RAM_CTL("Speaker 3D Mix", COEFF_SIZE, 0xaf),
2277
2278 COEFF_RAM_CTL("Speaker MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2279 COEFF_RAM_CTL("Speaker MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2280
2281 COEFF_RAM_CTL("Speaker MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2282 COEFF_RAM_CTL("Speaker MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2283
2284 COEFF_RAM_CTL("Speaker MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2285 COEFF_RAM_CTL("Speaker MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2286
2287 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2288 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2289 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2290 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2291 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2292 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2293
2294 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2295 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2296 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2297 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2298 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2299 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2300
2301 COEFF_RAM_CTL("Sub Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2302 COEFF_RAM_CTL("Sub Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2303
2304 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2305 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2306 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2307 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2308 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2309 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2310
2311 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2312 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2313 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2314 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2315 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2316 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2317
2318 COEFF_RAM_CTL("Sub Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2319 COEFF_RAM_CTL("Sub Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2320
2321 COEFF_RAM_CTL("Sub Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2322 COEFF_RAM_CTL("Sub Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2323
2324 COEFF_RAM_CTL("Sub Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2325 COEFF_RAM_CTL("Sub Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2326
2327 COEFF_RAM_CTL("Sub Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2328
2329 COEFF_RAM_CTL("Sub Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2330
2331 COEFF_RAM_CTL("Sub Bass Mix", COEFF_SIZE, 0x96),
2332
2333 COEFF_RAM_CTL("Sub Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2334 COEFF_RAM_CTL("Sub Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2335
2336 COEFF_RAM_CTL("Sub Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2337 COEFF_RAM_CTL("Sub Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2338
2339 COEFF_RAM_CTL("Sub Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2340
2341 COEFF_RAM_CTL("Sub Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2342
2343 COEFF_RAM_CTL("Sub Treb Mix", COEFF_SIZE, 0xad),
2344
2345 COEFF_RAM_CTL("Sub 3D", COEFF_SIZE, 0xae),
2346
2347 COEFF_RAM_CTL("Sub 3D Mix", COEFF_SIZE, 0xaf),
2348
2349 COEFF_RAM_CTL("Sub MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2350 COEFF_RAM_CTL("Sub MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2351
2352 COEFF_RAM_CTL("Sub MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2353 COEFF_RAM_CTL("Sub MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2354
2355 COEFF_RAM_CTL("Sub MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2356 COEFF_RAM_CTL("Sub MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2357};
2358
2359static struct snd_soc_dapm_widget const tscs454_dapm_widgets[] = {
2360 /* R_PLLCTL PG 0 ADDR 0x15 */
2361 SND_SOC_DAPM_SUPPLY("PLL 1 Power", R_PLLCTL, FB_PLLCTL_PU_PLL1, 0,
2362 pll_power_event,
2363 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
2364 SND_SOC_DAPM_SUPPLY("PLL 2 Power", R_PLLCTL, FB_PLLCTL_PU_PLL2, 0,
2365 pll_power_event,
2366 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
2367 /* R_I2SPINC0 PG 0 ADDR 0x22 */
2368 SND_SOC_DAPM_AIF_OUT("DAI 3 Out", "DAI 3 Capture", 0,
2369 R_I2SPINC0, FB_I2SPINC0_SDO3TRI, 1),
2370 SND_SOC_DAPM_AIF_OUT("DAI 2 Out", "DAI 2 Capture", 0,
2371 R_I2SPINC0, FB_I2SPINC0_SDO2TRI, 1),
2372 SND_SOC_DAPM_AIF_OUT("DAI 1 Out", "DAI 1 Capture", 0,
2373 R_I2SPINC0, FB_I2SPINC0_SDO1TRI, 1),
2374 /* R_PWRM0 PG 0 ADDR 0x33 */
2375 SND_SOC_DAPM_ADC("Input Processor Channel 3", NULL,
2376 R_PWRM0, FB_PWRM0_INPROC3PU, 0),
2377 SND_SOC_DAPM_ADC("Input Processor Channel 2", NULL,
2378 R_PWRM0, FB_PWRM0_INPROC2PU, 0),
2379 SND_SOC_DAPM_ADC("Input Processor Channel 1", NULL,
2380 R_PWRM0, FB_PWRM0_INPROC1PU, 0),
2381 SND_SOC_DAPM_ADC("Input Processor Channel 0", NULL,
2382 R_PWRM0, FB_PWRM0_INPROC0PU, 0),
2383 SND_SOC_DAPM_SUPPLY("Mic Bias 2",
2384 R_PWRM0, FB_PWRM0_MICB2PU, 0, NULL, 0),
2385 SND_SOC_DAPM_SUPPLY("Mic Bias 1", R_PWRM0,
2386 FB_PWRM0_MICB1PU, 0, NULL, 0),
2387 /* R_PWRM1 PG 0 ADDR 0x34 */
2388 SND_SOC_DAPM_SUPPLY("Sub Power", R_PWRM1, FB_PWRM1_SUBPU, 0, NULL, 0),
2389 SND_SOC_DAPM_SUPPLY("Headphone Left Power",
2390 R_PWRM1, FB_PWRM1_HPLPU, 0, NULL, 0),
2391 SND_SOC_DAPM_SUPPLY("Headphone Right Power",
2392 R_PWRM1, FB_PWRM1_HPRPU, 0, NULL, 0),
2393 SND_SOC_DAPM_SUPPLY("Speaker Left Power",
2394 R_PWRM1, FB_PWRM1_SPKLPU, 0, NULL, 0),
2395 SND_SOC_DAPM_SUPPLY("Speaker Right Power",
2396 R_PWRM1, FB_PWRM1_SPKRPU, 0, NULL, 0),
2397 SND_SOC_DAPM_SUPPLY("Differential Input 2 Power",
2398 R_PWRM1, FB_PWRM1_D2S2PU, 0, NULL, 0),
2399 SND_SOC_DAPM_SUPPLY("Differential Input 1 Power",
2400 R_PWRM1, FB_PWRM1_D2S1PU, 0, NULL, 0),
2401 /* R_PWRM2 PG 0 ADDR 0x35 */
2402 SND_SOC_DAPM_SUPPLY("DAI 3 Out Power",
2403 R_PWRM2, FB_PWRM2_I2S3OPU, 0, NULL, 0),
2404 SND_SOC_DAPM_SUPPLY("DAI 2 Out Power",
2405 R_PWRM2, FB_PWRM2_I2S2OPU, 0, NULL, 0),
2406 SND_SOC_DAPM_SUPPLY("DAI 1 Out Power",
2407 R_PWRM2, FB_PWRM2_I2S1OPU, 0, NULL, 0),
2408 SND_SOC_DAPM_SUPPLY("DAI 3 In Power",
2409 R_PWRM2, FB_PWRM2_I2S3IPU, 0, NULL, 0),
2410 SND_SOC_DAPM_SUPPLY("DAI 2 In Power",
2411 R_PWRM2, FB_PWRM2_I2S2IPU, 0, NULL, 0),
2412 SND_SOC_DAPM_SUPPLY("DAI 1 In Power",
2413 R_PWRM2, FB_PWRM2_I2S1IPU, 0, NULL, 0),
2414 /* R_PWRM3 PG 0 ADDR 0x36 */
2415 SND_SOC_DAPM_SUPPLY("Line Out Left Power",
2416 R_PWRM3, FB_PWRM3_LLINEPU, 0, NULL, 0),
2417 SND_SOC_DAPM_SUPPLY("Line Out Right Power",
2418 R_PWRM3, FB_PWRM3_RLINEPU, 0, NULL, 0),
2419 /* R_PWRM4 PG 0 ADDR 0x37 */
2420 SND_SOC_DAPM_DAC("Sub", NULL, R_PWRM4, FB_PWRM4_OPSUBPU, 0),
2421 SND_SOC_DAPM_DAC("DAC Left", NULL, R_PWRM4, FB_PWRM4_OPDACLPU, 0),
2422 SND_SOC_DAPM_DAC("DAC Right", NULL, R_PWRM4, FB_PWRM4_OPDACRPU, 0),
2423 SND_SOC_DAPM_DAC("ClassD Left", NULL, R_PWRM4, FB_PWRM4_OPSPKLPU, 0),
2424 SND_SOC_DAPM_DAC("ClassD Right", NULL, R_PWRM4, FB_PWRM4_OPSPKRPU, 0),
2425 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
2426 SND_SOC_DAPM_MUX("DAI 2 Out Mux", SND_SOC_NOPM, 0, 0,
2427 &dai2_mux_dapm_enum),
2428 SND_SOC_DAPM_MUX("DAI 1 Out Mux", SND_SOC_NOPM, 0, 0,
2429 &dai1_mux_dapm_enum),
2430 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
2431 SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0,
2432 &dac_mux_dapm_enum),
2433 SND_SOC_DAPM_MUX("DAI 3 Out Mux", SND_SOC_NOPM, 0, 0,
2434 &dai3_mux_dapm_enum),
2435 /* R_AUDIOMUX3 PG 0 ADDR 0x3C */
2436 SND_SOC_DAPM_MUX("Sub Mux", SND_SOC_NOPM, 0, 0,
2437 &sub_mux_dapm_enum),
2438 SND_SOC_DAPM_MUX("Speaker Mux", SND_SOC_NOPM, 0, 0,
2439 &classd_mux_dapm_enum),
2440 /* R_HSDCTL1 PG 1 ADDR 0x01 */
2441 SND_SOC_DAPM_SUPPLY("GHS Detect Power", R_HSDCTL1,
2442 FB_HSDCTL1_CON_DET_PWD, 1, NULL, 0),
2443 /* R_CH0AIC PG 1 ADDR 0x06 */
2444 SND_SOC_DAPM_MUX("Input Boost Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2445 &in_bst_mux_ch0_dapm_enum),
2446 SND_SOC_DAPM_MUX("ADC Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2447 &adc_mux_ch0_dapm_enum),
2448 SND_SOC_DAPM_MUX("Input Processor Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2449 &in_proc_mux_ch0_dapm_enum),
2450 /* R_CH1AIC PG 1 ADDR 0x07 */
2451 SND_SOC_DAPM_MUX("Input Boost Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2452 &in_bst_mux_ch1_dapm_enum),
2453 SND_SOC_DAPM_MUX("ADC Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2454 &adc_mux_ch1_dapm_enum),
2455 SND_SOC_DAPM_MUX("Input Processor Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2456 &in_proc_mux_ch1_dapm_enum),
2457 /* Virtual */
2458 SND_SOC_DAPM_AIF_IN("DAI 3 In", "DAI 3 Playback", 0,
2459 SND_SOC_NOPM, 0, 0),
2460 SND_SOC_DAPM_AIF_IN("DAI 2 In", "DAI 2 Playback", 0,
2461 SND_SOC_NOPM, 0, 0),
2462 SND_SOC_DAPM_AIF_IN("DAI 1 In", "DAI 1 Playback", 0,
2463 SND_SOC_NOPM, 0, 0),
2464 SND_SOC_DAPM_SUPPLY("PLLs", SND_SOC_NOPM, 0, 0, NULL, 0),
2465 SND_SOC_DAPM_OUTPUT("Sub Out"),
2466 SND_SOC_DAPM_OUTPUT("Headphone Left"),
2467 SND_SOC_DAPM_OUTPUT("Headphone Right"),
2468 SND_SOC_DAPM_OUTPUT("Speaker Left"),
2469 SND_SOC_DAPM_OUTPUT("Speaker Right"),
2470 SND_SOC_DAPM_OUTPUT("Line Out Left"),
2471 SND_SOC_DAPM_OUTPUT("Line Out Right"),
2472 SND_SOC_DAPM_INPUT("D2S 2"),
2473 SND_SOC_DAPM_INPUT("D2S 1"),
2474 SND_SOC_DAPM_INPUT("Line In 1 Left"),
2475 SND_SOC_DAPM_INPUT("Line In 1 Right"),
2476 SND_SOC_DAPM_INPUT("Line In 2 Left"),
2477 SND_SOC_DAPM_INPUT("Line In 2 Right"),
2478 SND_SOC_DAPM_INPUT("Line In 3 Left"),
2479 SND_SOC_DAPM_INPUT("Line In 3 Right"),
2480 SND_SOC_DAPM_INPUT("DMic 1"),
2481 SND_SOC_DAPM_INPUT("DMic 2"),
2482
2483 SND_SOC_DAPM_MUX("CH 0_1 Mux", SND_SOC_NOPM, 0, 0,
2484 &ch_0_1_mux_dapm_enum),
2485 SND_SOC_DAPM_MUX("CH 2_3 Mux", SND_SOC_NOPM, 0, 0,
2486 &ch_2_3_mux_dapm_enum),
2487 SND_SOC_DAPM_MUX("CH 4_5 Mux", SND_SOC_NOPM, 0, 0,
2488 &ch_4_5_mux_dapm_enum),
2489};
2490
2491static struct snd_soc_dapm_route const tscs454_intercon[] = {
2492 /* PLLs */
2493 {"PLLs", NULL, "PLL 1 Power", pll_connected},
2494 {"PLLs", NULL, "PLL 2 Power", pll_connected},
2495 /* Inputs */
2496 {"DAI 3 In", NULL, "DAI 3 In Power"},
2497 {"DAI 2 In", NULL, "DAI 2 In Power"},
2498 {"DAI 1 In", NULL, "DAI 1 In Power"},
2499 /* Outputs */
2500 {"DAI 3 Out", NULL, "DAI 3 Out Power"},
2501 {"DAI 2 Out", NULL, "DAI 2 Out Power"},
2502 {"DAI 1 Out", NULL, "DAI 1 Out Power"},
2503 /* Ch Muxing */
2504 {"CH 0_1 Mux", "DAI 1", "DAI 1 In"},
2505 {"CH 0_1 Mux", "TDM 0_1", "DAI 1 In"},
2506 {"CH 2_3 Mux", "DAI 2", "DAI 2 In"},
2507 {"CH 2_3 Mux", "TDM 2_3", "DAI 1 In"},
2508 {"CH 4_5 Mux", "DAI 3", "DAI 2 In"},
2509 {"CH 4_5 Mux", "TDM 4_5", "DAI 1 In"},
2510 /* In/Out Muxing */
2511 {"DAI 1 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2512 {"DAI 1 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2513 {"DAI 1 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2514 {"DAI 2 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2515 {"DAI 2 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2516 {"DAI 2 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2517 {"DAI 3 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2518 {"DAI 3 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2519 {"DAI 3 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2520 /******************
2521 * Playback Paths *
2522 ******************/
2523 /* DAC Path */
2524 {"DAC Mux", "CH 4_5", "CH 4_5 Mux"},
2525 {"DAC Mux", "CH 2_3", "CH 2_3 Mux"},
2526 {"DAC Mux", "CH 0_1", "CH 0_1 Mux"},
2527 {"DAC Left", NULL, "DAC Mux"},
2528 {"DAC Right", NULL, "DAC Mux"},
2529 {"DAC Left", NULL, "PLLs"},
2530 {"DAC Right", NULL, "PLLs"},
2531 {"Headphone Left", NULL, "Headphone Left Power"},
2532 {"Headphone Right", NULL, "Headphone Right Power"},
2533 {"Headphone Left", NULL, "DAC Left"},
2534 {"Headphone Right", NULL, "DAC Right"},
2535 /* Line Out */
2536 {"Line Out Left", NULL, "Line Out Left Power"},
2537 {"Line Out Right", NULL, "Line Out Right Power"},
2538 {"Line Out Left", NULL, "DAC Left"},
2539 {"Line Out Right", NULL, "DAC Right"},
2540 /* ClassD Path */
2541 {"Speaker Mux", "CH 4_5", "CH 4_5 Mux"},
2542 {"Speaker Mux", "CH 2_3", "CH 2_3 Mux"},
2543 {"Speaker Mux", "CH 0_1", "CH 0_1 Mux"},
2544 {"ClassD Left", NULL, "Speaker Mux"},
2545 {"ClassD Right", NULL, "Speaker Mux"},
2546 {"ClassD Left", NULL, "PLLs"},
2547 {"ClassD Right", NULL, "PLLs"},
2548 {"Speaker Left", NULL, "Speaker Left Power"},
2549 {"Speaker Right", NULL, "Speaker Right Power"},
2550 {"Speaker Left", NULL, "ClassD Left"},
2551 {"Speaker Right", NULL, "ClassD Right"},
2552 /* Sub Path */
2553 {"Sub Mux", "CH 4", "CH 4_5 Mux"},
2554 {"Sub Mux", "CH 5", "CH 4_5 Mux"},
2555 {"Sub Mux", "CH 4 + 5", "CH 4_5 Mux"},
2556 {"Sub Mux", "CH 2", "CH 2_3 Mux"},
2557 {"Sub Mux", "CH 3", "CH 2_3 Mux"},
2558 {"Sub Mux", "CH 2 + 3", "CH 2_3 Mux"},
2559 {"Sub Mux", "CH 0", "CH 0_1 Mux"},
2560 {"Sub Mux", "CH 1", "CH 0_1 Mux"},
2561 {"Sub Mux", "CH 0 + 1", "CH 0_1 Mux"},
2562 {"Sub Mux", "ADC/DMic 1 Left", "Input Processor Channel 0"},
2563 {"Sub Mux", "ADC/DMic 1 Right", "Input Processor Channel 1"},
2564 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 0"},
2565 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 1"},
2566 {"Sub Mux", "DMic 2 Left", "DMic 2"},
2567 {"Sub Mux", "DMic 2 Right", "DMic 2"},
2568 {"Sub Mux", "DMic 2 Left Plus Right", "DMic 2"},
2569 {"Sub Mux", "ClassD Left", "ClassD Left"},
2570 {"Sub Mux", "ClassD Right", "ClassD Right"},
2571 {"Sub Mux", "ClassD Left Plus Right", "ClassD Left"},
2572 {"Sub Mux", "ClassD Left Plus Right", "ClassD Right"},
2573 {"Sub", NULL, "Sub Mux"},
2574 {"Sub", NULL, "PLLs"},
2575 {"Sub Out", NULL, "Sub Power"},
2576 {"Sub Out", NULL, "Sub"},
2577 /*****************
2578 * Capture Paths *
2579 *****************/
2580 {"Input Boost Channel 0 Mux", "Input 3", "Line In 3 Left"},
2581 {"Input Boost Channel 0 Mux", "Input 2", "Line In 2 Left"},
2582 {"Input Boost Channel 0 Mux", "Input 1", "Line In 1 Left"},
2583 {"Input Boost Channel 0 Mux", "D2S", "D2S 1"},
2584
2585 {"Input Boost Channel 1 Mux", "Input 3", "Line In 3 Right"},
2586 {"Input Boost Channel 1 Mux", "Input 2", "Line In 2 Right"},
2587 {"Input Boost Channel 1 Mux", "Input 1", "Line In 1 Right"},
2588 {"Input Boost Channel 1 Mux", "D2S", "D2S 2"},
2589
2590 {"ADC Channel 0 Mux", "Input 3 Boost Bypass", "Line In 3 Left"},
2591 {"ADC Channel 0 Mux", "Input 2 Boost Bypass", "Line In 2 Left"},
2592 {"ADC Channel 0 Mux", "Input 1 Boost Bypass", "Line In 1 Left"},
2593 {"ADC Channel 0 Mux", "Input Boost", "Input Boost Channel 0 Mux"},
2594
2595 {"ADC Channel 1 Mux", "Input 3 Boost Bypass", "Line In 3 Right"},
2596 {"ADC Channel 1 Mux", "Input 2 Boost Bypass", "Line In 2 Right"},
2597 {"ADC Channel 1 Mux", "Input 1 Boost Bypass", "Line In 1 Right"},
2598 {"ADC Channel 1 Mux", "Input Boost", "Input Boost Channel 1 Mux"},
2599
2600 {"Input Processor Channel 0 Mux", "ADC", "ADC Channel 0 Mux"},
2601 {"Input Processor Channel 0 Mux", "DMic", "DMic 1"},
2602
2603 {"Input Processor Channel 0", NULL, "PLLs"},
2604 {"Input Processor Channel 0", NULL, "Input Processor Channel 0 Mux"},
2605
2606 {"Input Processor Channel 1 Mux", "ADC", "ADC Channel 1 Mux"},
2607 {"Input Processor Channel 1 Mux", "DMic", "DMic 1"},
2608
2609 {"Input Processor Channel 1", NULL, "PLLs"},
2610 {"Input Processor Channel 1", NULL, "Input Processor Channel 1 Mux"},
2611
2612 {"Input Processor Channel 2", NULL, "PLLs"},
2613 {"Input Processor Channel 2", NULL, "DMic 2"},
2614
2615 {"Input Processor Channel 3", NULL, "PLLs"},
2616 {"Input Processor Channel 3", NULL, "DMic 2"},
2617
2618 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2619 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2620 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 2"},
2621 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 3"},
2622
2623 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2624 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2625 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 2"},
2626 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 3"},
2627
2628 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2629 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2630 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 2"},
2631 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 3"},
2632
2633 {"DAI 1 Out", NULL, "DAI 1 Out Mux"},
2634 {"DAI 2 Out", NULL, "DAI 2 Out Mux"},
2635 {"DAI 3 Out", NULL, "DAI 3 Out Mux"},
2636};
2637
2638/* This is used when BCLK is sourcing the PLLs */
2639static int tscs454_set_sysclk(struct snd_soc_dai *dai,
2640 int clk_id, unsigned int freq, int dir)
2641{
2642 struct snd_soc_component *component = dai->component;
2643 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
2644 unsigned int val;
2645 int bclk_dai;
2646 int ret;
2647
2648 dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq);
2649
2650 ret = snd_soc_component_read(component, R_PLLCTL, &val);
2651 if (ret < 0)
2652 return ret;
2653
2654 bclk_dai = (val & FM_PLLCTL_BCLKSEL) >> FB_PLLCTL_BCLKSEL;
2655 if (bclk_dai != dai->id)
2656 return 0;
2657
2658 tscs454->bclk_freq = freq;
2659 return set_sysclk(component);
2660}
2661
2662static int tscs454_set_bclk_ratio(struct snd_soc_dai *dai,
2663 unsigned int ratio)
2664{
2665 unsigned int mask;
2666 int ret;
2667 struct snd_soc_component *component = dai->component;
2668 unsigned int val;
2669 int shift;
2670
2671 dev_dbg(component->dev, "set_bclk_ratio() id = %d ratio = %u\n",
2672 dai->id, ratio);
2673
2674 switch (dai->id) {
2675 case TSCS454_DAI1_ID:
2676 mask = FM_I2SCMC_BCMP1;
2677 shift = FB_I2SCMC_BCMP1;
2678 break;
2679 case TSCS454_DAI2_ID:
2680 mask = FM_I2SCMC_BCMP2;
2681 shift = FB_I2SCMC_BCMP2;
2682 break;
2683 case TSCS454_DAI3_ID:
2684 mask = FM_I2SCMC_BCMP3;
2685 shift = FB_I2SCMC_BCMP3;
2686 break;
2687 default:
2688 ret = -EINVAL;
2689 dev_err(component->dev, "Unknown audio interface (%d)\n", ret);
2690 return ret;
2691 }
2692
2693 switch (ratio) {
2694 case 32:
2695 val = I2SCMC_BCMP_32X;
2696 break;
2697 case 40:
2698 val = I2SCMC_BCMP_40X;
2699 break;
2700 case 64:
2701 val = I2SCMC_BCMP_64X;
2702 break;
2703 default:
2704 ret = -EINVAL;
2705 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret);
2706 return ret;
2707 }
2708
2709 ret = snd_soc_component_update_bits(component,
2710 R_I2SCMC, mask, val << shift);
2711 if (ret < 0) {
2712 dev_err(component->dev,
2713 "Failed to set DAI BCLK ratio (%d)\n", ret);
2714 return ret;
2715 }
2716
2717 return 0;
2718}
2719
2720static inline int set_aif_master_from_fmt(struct snd_soc_component *component,
2721 struct aif *aif, unsigned int fmt)
2722{
2723 int ret;
2724
2725 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2726 case SND_SOC_DAIFMT_CBM_CFM:
2727 aif->master = true;
2728 break;
2729 case SND_SOC_DAIFMT_CBS_CFS:
2730 aif->master = false;
2731 break;
2732 default:
2733 ret = -EINVAL;
2734 dev_err(component->dev, "Unsupported format (%d)\n", ret);
2735 return ret;
2736 }
2737
2738 return 0;
2739}
2740
2741static inline int set_aif_tdm_delay(struct snd_soc_component *component,
2742 unsigned int dai_id, bool delay)
2743{
2744 unsigned int reg;
2745 int ret;
2746
2747 switch (dai_id) {
2748 case TSCS454_DAI1_ID:
2749 reg = R_TDMCTL0;
2750 break;
2751 case TSCS454_DAI2_ID:
2752 reg = R_PCMP2CTL0;
2753 break;
2754 case TSCS454_DAI3_ID:
2755 reg = R_PCMP3CTL0;
2756 break;
2757 default:
2758 ret = -EINVAL;
2759 dev_err(component->dev,
2760 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2761 return ret;
2762 }
2763 ret = snd_soc_component_update_bits(component,
2764 reg, FM_TDMCTL0_BDELAY, delay);
2765 if (ret < 0) {
2766 dev_err(component->dev, "Failed to setup tdm format (%d)\n",
2767 ret);
2768 return ret;
2769 }
2770
2771 return 0;
2772}
2773
2774static inline int set_aif_format_from_fmt(struct snd_soc_component *component,
2775 unsigned int dai_id, unsigned int fmt)
2776{
2777 unsigned int reg;
2778 unsigned int val;
2779 int ret;
2780
2781 switch (dai_id) {
2782 case TSCS454_DAI1_ID:
2783 reg = R_I2SP1CTL;
2784 break;
2785 case TSCS454_DAI2_ID:
2786 reg = R_I2SP2CTL;
2787 break;
2788 case TSCS454_DAI3_ID:
2789 reg = R_I2SP3CTL;
2790 break;
2791 default:
2792 ret = -EINVAL;
2793 dev_err(component->dev,
2794 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2795 return ret;
2796 }
2797
2798 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2799 case SND_SOC_DAIFMT_RIGHT_J:
2800 val = FV_FORMAT_RIGHT;
2801 break;
2802 case SND_SOC_DAIFMT_LEFT_J:
2803 val = FV_FORMAT_LEFT;
2804 break;
2805 case SND_SOC_DAIFMT_I2S:
2806 val = FV_FORMAT_I2S;
2807 break;
2808 case SND_SOC_DAIFMT_DSP_A:
2809 ret = set_aif_tdm_delay(component, dai_id, true);
2810 if (ret < 0)
2811 return ret;
2812 val = FV_FORMAT_TDM;
2813 break;
2814 case SND_SOC_DAIFMT_DSP_B:
2815 ret = set_aif_tdm_delay(component, dai_id, false);
2816 if (ret < 0)
2817 return ret;
2818 val = FV_FORMAT_TDM;
2819 break;
2820 default:
2821 ret = -EINVAL;
2822 dev_err(component->dev, "Format unsupported (%d)\n", ret);
2823 return ret;
2824 }
2825
2826 ret = snd_soc_component_update_bits(component,
2827 reg, FM_I2SPCTL_FORMAT, val);
2828 if (ret < 0) {
2829 dev_err(component->dev, "Failed to set DAI %d format (%d)\n",
2830 dai_id + 1, ret);
2831 return ret;
2832 }
2833
2834 return 0;
2835}
2836
2837static inline int
2838set_aif_clock_format_from_fmt(struct snd_soc_component *component,
2839 unsigned int dai_id, unsigned int fmt)
2840{
2841 unsigned int reg;
2842 unsigned int val;
2843 int ret;
2844
2845 switch (dai_id) {
2846 case TSCS454_DAI1_ID:
2847 reg = R_I2SP1CTL;
2848 break;
2849 case TSCS454_DAI2_ID:
2850 reg = R_I2SP2CTL;
2851 break;
2852 case TSCS454_DAI3_ID:
2853 reg = R_I2SP3CTL;
2854 break;
2855 default:
2856 ret = -EINVAL;
2857 dev_err(component->dev,
2858 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2859 return ret;
2860 }
2861
2862 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2863 case SND_SOC_DAIFMT_NB_NF:
2864 val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_NOT_INVERTED;
2865 break;
2866 case SND_SOC_DAIFMT_NB_IF:
2867 val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_INVERTED;
2868 break;
2869 case SND_SOC_DAIFMT_IB_NF:
2870 val = FV_BCLKP_INVERTED | FV_LRCLKP_NOT_INVERTED;
2871 break;
2872 case SND_SOC_DAIFMT_IB_IF:
2873 val = FV_BCLKP_INVERTED | FV_LRCLKP_INVERTED;
2874 break;
2875 default:
2876 ret = -EINVAL;
2877 dev_err(component->dev, "Format unknown (%d)\n", ret);
2878 return ret;
2879 }
2880
2881 ret = snd_soc_component_update_bits(component, reg,
2882 FM_I2SPCTL_BCLKP | FM_I2SPCTL_LRCLKP, val);
2883 if (ret < 0) {
2884 dev_err(component->dev,
2885 "Failed to set clock polarity for DAI%d (%d)\n",
2886 dai_id + 1, ret);
2887 return ret;
2888 }
2889
2890 return 0;
2891}
2892
2893static int tscs454_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2894{
2895 struct snd_soc_component *component = dai->component;
2896 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
2897 struct aif *aif = &tscs454->aifs[dai->id];
2898 int ret;
2899
2900 ret = set_aif_master_from_fmt(component, aif, fmt);
2901 if (ret < 0)
2902 return ret;
2903
2904 ret = set_aif_format_from_fmt(component, dai->id, fmt);
2905 if (ret < 0)
2906 return ret;
2907
2908 ret = set_aif_clock_format_from_fmt(component, dai->id, fmt);
2909 if (ret < 0)
2910 return ret;
2911
2912 return 0;
2913}
2914
2915static int tscs454_dai1_set_tdm_slot(struct snd_soc_dai *dai,
2916 unsigned int tx_mask, unsigned int rx_mask, int slots,
2917 int slot_width)
2918{
2919 struct snd_soc_component *component = dai->component;
2920 unsigned int val;
2921 int ret;
2922
2923 if (!slots)
2924 return 0;
2925
2926 if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
2927 ret = -EINVAL;
2928 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
2929 return ret;
2930 }
2931
2932 switch (slots) {
2933 case 2:
2934 val = FV_TDMSO_2 | FV_TDMSI_2;
2935 break;
2936 case 4:
2937 val = FV_TDMSO_4 | FV_TDMSI_4;
2938 break;
2939 case 6:
2940 val = FV_TDMSO_6 | FV_TDMSI_6;
2941 break;
2942 default:
2943 ret = -EINVAL;
2944 dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
2945 return ret;
2946 }
2947
2948 switch (slot_width) {
2949 case 16:
2950 val = val | FV_TDMDSS_16;
2951 break;
2952 case 24:
2953 val = val | FV_TDMDSS_24;
2954 break;
2955 case 32:
2956 val = val | FV_TDMDSS_32;
2957 break;
2958 default:
2959 ret = -EINVAL;
2960 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
2961 return ret;
2962 }
2963 ret = snd_soc_component_write(component, R_TDMCTL1, val);
2964 if (ret < 0) {
2965 dev_err(component->dev, "Failed to set slots (%d)\n", ret);
2966 return ret;
2967 }
2968
2969 return 0;
2970}
2971
2972static int tscs454_dai23_set_tdm_slot(struct snd_soc_dai *dai,
2973 unsigned int tx_mask, unsigned int rx_mask, int slots,
2974 int slot_width)
2975{
2976 struct snd_soc_component *component = dai->component;
2977 unsigned int reg;
2978 unsigned int val;
2979 int ret;
2980
2981 if (!slots)
2982 return 0;
2983
2984 if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
2985 ret = -EINVAL;
2986 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
2987 return ret;
2988 }
2989
2990 switch (dai->id) {
2991 case TSCS454_DAI2_ID:
2992 reg = R_PCMP2CTL1;
2993 break;
2994 case TSCS454_DAI3_ID:
2995 reg = R_PCMP3CTL1;
2996 break;
2997 default:
2998 ret = -EINVAL;
2999 dev_err(component->dev, "Unrecognized interface %d (%d)\n",
3000 dai->id, ret);
3001 return ret;
3002 }
3003
3004 switch (slots) {
3005 case 1:
3006 val = FV_PCMSOP_1 | FV_PCMSIP_1;
3007 break;
3008 case 2:
3009 val = FV_PCMSOP_2 | FV_PCMSIP_2;
3010 break;
3011 default:
3012 ret = -EINVAL;
3013 dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
3014 return ret;
3015 }
3016
3017 switch (slot_width) {
3018 case 16:
3019 val = val | FV_PCMDSSP_16;
3020 break;
3021 case 24:
3022 val = val | FV_PCMDSSP_24;
3023 break;
3024 case 32:
3025 val = val | FV_PCMDSSP_32;
3026 break;
3027 default:
3028 ret = -EINVAL;
3029 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
3030 return ret;
3031 }
3032 ret = snd_soc_component_write(component, reg, val);
3033 if (ret < 0) {
3034 dev_err(component->dev, "Failed to set slots (%d)\n", ret);
3035 return ret;
3036 }
3037
3038 return 0;
3039}
3040
3041static int set_aif_fs(struct snd_soc_component *component,
3042 unsigned int id,
3043 unsigned int rate)
3044{
3045 unsigned int reg;
3046 unsigned int br;
3047 unsigned int bm;
3048 int ret;
3049
3050 switch (rate) {
3051 case 8000:
3052 br = FV_I2SMBR_32;
3053 bm = FV_I2SMBM_0PT25;
3054 break;
3055 case 16000:
3056 br = FV_I2SMBR_32;
3057 bm = FV_I2SMBM_0PT5;
3058 break;
3059 case 24000:
3060 br = FV_I2SMBR_48;
3061 bm = FV_I2SMBM_0PT5;
3062 break;
3063 case 32000:
3064 br = FV_I2SMBR_32;
3065 bm = FV_I2SMBM_1;
3066 break;
3067 case 48000:
3068 br = FV_I2SMBR_48;
3069 bm = FV_I2SMBM_1;
3070 break;
3071 case 96000:
3072 br = FV_I2SMBR_48;
3073 bm = FV_I2SMBM_2;
3074 break;
3075 case 11025:
3076 br = FV_I2SMBR_44PT1;
3077 bm = FV_I2SMBM_0PT25;
3078 break;
3079 case 22050:
3080 br = FV_I2SMBR_44PT1;
3081 bm = FV_I2SMBM_0PT5;
3082 break;
3083 case 44100:
3084 br = FV_I2SMBR_44PT1;
3085 bm = FV_I2SMBM_1;
3086 break;
3087 case 88200:
3088 br = FV_I2SMBR_44PT1;
3089 bm = FV_I2SMBM_2;
3090 break;
3091 default:
3092 ret = -EINVAL;
3093 dev_err(component->dev, "Unsupported sample rate (%d)\n", ret);
3094 return ret;
3095 }
3096
3097 switch (id) {
3098 case TSCS454_DAI1_ID:
3099 reg = R_I2S1MRATE;
3100 break;
3101 case TSCS454_DAI2_ID:
3102 reg = R_I2S2MRATE;
3103 break;
3104 case TSCS454_DAI3_ID:
3105 reg = R_I2S3MRATE;
3106 break;
3107 default:
3108 ret = -EINVAL;
3109 dev_err(component->dev, "DAI ID not recognized (%d)\n", ret);
3110 return ret;
3111 }
3112
3113 ret = snd_soc_component_update_bits(component, reg,
3114 FM_I2SMRATE_I2SMBR | FM_I2SMRATE_I2SMBM, br|bm);
3115 if (ret < 0) {
3116 dev_err(component->dev,
3117 "Failed to update register (%d)\n", ret);
3118 return ret;
3119 }
3120
3121 return 0;
3122}
3123
3124static int set_aif_sample_format(struct snd_soc_component *component,
3125 snd_pcm_format_t format,
3126 int aif_id)
3127{
3128 unsigned int reg;
3129 unsigned int width;
3130 int ret;
3131
3132 switch (format) {
3133 case SNDRV_PCM_FORMAT_S16_LE:
3134 width = FV_WL_16;
3135 break;
3136 case SNDRV_PCM_FORMAT_S20_3LE:
3137 width = FV_WL_20;
3138 break;
3139 case SNDRV_PCM_FORMAT_S24_3LE:
3140 width = FV_WL_24;
3141 break;
3142 case SNDRV_PCM_FORMAT_S24_LE:
3143 case SNDRV_PCM_FORMAT_S32_LE:
3144 width = FV_WL_32;
3145 break;
3146 default:
3147 ret = -EINVAL;
3148 dev_err(component->dev, "Unsupported format width (%d)\n", ret);
3149 return ret;
3150 }
3151
3152 switch (aif_id) {
3153 case TSCS454_DAI1_ID:
3154 reg = R_I2SP1CTL;
3155 break;
3156 case TSCS454_DAI2_ID:
3157 reg = R_I2SP2CTL;
3158 break;
3159 case TSCS454_DAI3_ID:
3160 reg = R_I2SP3CTL;
3161 break;
3162 default:
3163 ret = -EINVAL;
3164 dev_err(component->dev, "AIF ID not recognized (%d)\n", ret);
3165 return ret;
3166 }
3167
3168 ret = snd_soc_component_update_bits(component,
3169 reg, FM_I2SPCTL_WL, width);
3170 if (ret < 0) {
3171 dev_err(component->dev,
3172 "Failed to set sample width (%d)\n", ret);
3173 return ret;
3174 }
3175
3176 return 0;
3177}
3178
3179static int tscs454_hw_params(struct snd_pcm_substream *substream,
3180 struct snd_pcm_hw_params *params,
3181 struct snd_soc_dai *dai)
3182{
3183 struct snd_soc_component *component = dai->component;
3184 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3185 unsigned int fs = params_rate(params);
3186 struct aif *aif = &tscs454->aifs[dai->id];
3187 unsigned int val;
3188 int ret;
3189
3190 mutex_lock(&tscs454->aifs_status_lock);
3191
3192 dev_dbg(component->dev, "%s(): aif %d fs = %u\n", __func__,
3193 aif->id, fs);
3194
3195 if (!aif_active(&tscs454->aifs_status, aif->id)) {
3196 if (PLL_44_1K_RATE % fs)
3197 aif->pll = &tscs454->pll1;
3198 else
3199 aif->pll = &tscs454->pll2;
3200
3201 dev_dbg(component->dev, "Reserving pll %d for aif %d\n",
3202 aif->pll->id, aif->id);
3203
3204 reserve_pll(aif->pll);
3205 }
3206
3207 if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */
3208 ret = snd_soc_component_read(component, R_ISRC, &val);
3209 if (ret < 0)
3210 goto exit;
3211
3212 if ((val & FM_ISRC_IBR) == FV_IBR_48)
3213 tscs454->internal_rate.pll = &tscs454->pll1;
3214 else
3215 tscs454->internal_rate.pll = &tscs454->pll2;
3216
3217 dev_dbg(component->dev, "Reserving pll %d for ir\n",
3218 tscs454->internal_rate.pll->id);
3219
3220 reserve_pll(tscs454->internal_rate.pll);
3221 }
3222
3223 ret = set_aif_fs(component, aif->id, fs);
3224 if (ret < 0) {
3225 dev_err(component->dev, "Failed to set aif fs (%d)\n", ret);
3226 goto exit;
3227 }
3228
3229 ret = set_aif_sample_format(component, params_format(params), aif->id);
3230 if (ret < 0) {
3231 dev_err(component->dev,
3232 "Failed to set aif sample format (%d)\n", ret);
3233 goto exit;
3234 }
3235
3236 set_aif_status_active(&tscs454->aifs_status, aif->id,
3237 substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
3238
3239 dev_dbg(component->dev, "Set aif %d active. Streams status is 0x%x\n",
3240 aif->id, tscs454->aifs_status.streams);
3241
3242 ret = 0;
3243exit:
3244 mutex_unlock(&tscs454->aifs_status_lock);
3245
3246 return ret;
3247}
3248
3249static int tscs454_hw_free(struct snd_pcm_substream *substream,
3250 struct snd_soc_dai *dai)
3251{
3252 struct snd_soc_component *component = dai->component;
3253 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3254 struct aif *aif = &tscs454->aifs[dai->id];
3255
3256 return aif_free(component, aif,
3257 substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
3258}
3259
3260static int tscs454_prepare(struct snd_pcm_substream *substream,
3261 struct snd_soc_dai *dai)
3262{
3263 int ret;
3264 struct snd_soc_component *component = dai->component;
3265 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3266 struct aif *aif = &tscs454->aifs[dai->id];
3267
3268 ret = aif_prepare(component, aif);
3269 if (ret < 0)
3270 return ret;
3271
3272 return 0;
3273}
3274
3275static struct snd_soc_dai_ops const tscs454_dai1_ops = {
3276 .set_sysclk = tscs454_set_sysclk,
3277 .set_bclk_ratio = tscs454_set_bclk_ratio,
3278 .set_fmt = tscs454_set_dai_fmt,
3279 .set_tdm_slot = tscs454_dai1_set_tdm_slot,
3280 .hw_params = tscs454_hw_params,
3281 .hw_free = tscs454_hw_free,
3282 .prepare = tscs454_prepare,
3283};
3284
3285static struct snd_soc_dai_ops const tscs454_dai23_ops = {
3286 .set_sysclk = tscs454_set_sysclk,
3287 .set_bclk_ratio = tscs454_set_bclk_ratio,
3288 .set_fmt = tscs454_set_dai_fmt,
3289 .set_tdm_slot = tscs454_dai23_set_tdm_slot,
3290 .hw_params = tscs454_hw_params,
3291 .hw_free = tscs454_hw_free,
3292 .prepare = tscs454_prepare,
3293};
3294
3295static int tscs454_probe(struct snd_soc_component *component)
3296{
3297 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3298 unsigned int val;
3299 int ret = 0;
3300
3301 switch (tscs454->sysclk_src_id) {
3302 case PLL_INPUT_XTAL:
3303 val = FV_PLLISEL_XTAL;
3304 break;
3305 case PLL_INPUT_MCLK1:
3306 val = FV_PLLISEL_MCLK1;
3307 break;
3308 case PLL_INPUT_MCLK2:
3309 val = FV_PLLISEL_MCLK2;
3310 break;
3311 case PLL_INPUT_BCLK:
3312 val = FV_PLLISEL_BCLK;
3313 break;
3314 default:
3315 ret = -EINVAL;
3316 dev_err(component->dev, "Invalid sysclk src id (%d)\n", ret);
3317 return ret;
3318 }
3319
3320 ret = snd_soc_component_update_bits(component, R_PLLCTL,
3321 FM_PLLCTL_PLLISEL, val);
3322 if (ret < 0) {
3323 dev_err(component->dev, "Failed to set PLL input (%d)\n", ret);
3324 return ret;
3325 }
3326
3327 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
3328 ret = set_sysclk(component);
3329
3330 return ret;
3331}
3332
3333static const struct snd_soc_component_driver soc_component_dev_tscs454 = {
3334 .probe = tscs454_probe,
3335 .dapm_widgets = tscs454_dapm_widgets,
3336 .num_dapm_widgets = ARRAY_SIZE(tscs454_dapm_widgets),
3337 .dapm_routes = tscs454_intercon,
3338 .num_dapm_routes = ARRAY_SIZE(tscs454_intercon),
3339 .controls = tscs454_snd_controls,
3340 .num_controls = ARRAY_SIZE(tscs454_snd_controls),
3341};
3342
3343#define TSCS454_RATES SNDRV_PCM_RATE_8000_96000
3344
3345#define TSCS454_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
3346 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \
3347 | SNDRV_PCM_FMTBIT_S32_LE)
3348
3349static struct snd_soc_dai_driver tscs454_dais[] = {
3350 {
3351 .name = "tscs454-dai1",
3352 .id = TSCS454_DAI1_ID,
3353 .playback = {
3354 .stream_name = "DAI 1 Playback",
3355 .channels_min = 1,
3356 .channels_max = 6,
3357 .rates = TSCS454_RATES,
3358 .formats = TSCS454_FORMATS,},
3359 .capture = {
3360 .stream_name = "DAI 1 Capture",
3361 .channels_min = 1,
3362 .channels_max = 6,
3363 .rates = TSCS454_RATES,
3364 .formats = TSCS454_FORMATS,},
3365 .ops = &tscs454_dai1_ops,
3366 .symmetric_rates = 1,
3367 .symmetric_channels = 1,
3368 .symmetric_samplebits = 1,
3369 },
3370 {
3371 .name = "tscs454-dai2",
3372 .id = TSCS454_DAI2_ID,
3373 .playback = {
3374 .stream_name = "DAI 2 Playback",
3375 .channels_min = 1,
3376 .channels_max = 2,
3377 .rates = TSCS454_RATES,
3378 .formats = TSCS454_FORMATS,},
3379 .capture = {
3380 .stream_name = "DAI 2 Capture",
3381 .channels_min = 1,
3382 .channels_max = 2,
3383 .rates = TSCS454_RATES,
3384 .formats = TSCS454_FORMATS,},
3385 .ops = &tscs454_dai23_ops,
3386 .symmetric_rates = 1,
3387 .symmetric_channels = 1,
3388 .symmetric_samplebits = 1,
3389 },
3390 {
3391 .name = "tscs454-dai3",
3392 .id = TSCS454_DAI3_ID,
3393 .playback = {
3394 .stream_name = "DAI 3 Playback",
3395 .channels_min = 1,
3396 .channels_max = 2,
3397 .rates = TSCS454_RATES,
3398 .formats = TSCS454_FORMATS,},
3399 .capture = {
3400 .stream_name = "DAI 3 Capture",
3401 .channels_min = 1,
3402 .channels_max = 2,
3403 .rates = TSCS454_RATES,
3404 .formats = TSCS454_FORMATS,},
3405 .ops = &tscs454_dai23_ops,
3406 .symmetric_rates = 1,
3407 .symmetric_channels = 1,
3408 .symmetric_samplebits = 1,
3409 },
3410};
3411
3412static char const * const src_names[] = {
3413 "xtal", "mclk1", "mclk2", "bclk"};
3414
3415static int tscs454_i2c_probe(struct i2c_client *i2c,
3416 const struct i2c_device_id *id)
3417{
3418 struct tscs454 *tscs454;
3419 int src;
3420 int ret;
3421
3422 tscs454 = devm_kzalloc(&i2c->dev, sizeof(*tscs454), GFP_KERNEL);
3423 if (!tscs454)
3424 return -ENOMEM;
3425
3426 ret = tscs454_data_init(tscs454, i2c);
3427 if (ret < 0)
3428 return ret;
3429
3430 i2c_set_clientdata(i2c, tscs454);
3431
3432 for (src = PLL_INPUT_XTAL; src < PLL_INPUT_BCLK; src++) {
3433 tscs454->sysclk = devm_clk_get(&i2c->dev, src_names[src]);
3434 if (!IS_ERR(tscs454->sysclk)) {
3435 break;
3436 } else if (PTR_ERR(tscs454->sysclk) != -ENOENT) {
3437 ret = PTR_ERR(tscs454->sysclk);
3438 dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret);
3439 return ret;
3440 }
3441 }
3442 dev_dbg(&i2c->dev, "PLL input is %s\n", src_names[src]);
3443 tscs454->sysclk_src_id = src;
3444
3445 ret = regmap_write(tscs454->regmap,
3446 R_RESET, FV_RESET_PWR_ON_DEFAULTS);
3447 if (ret < 0) {
3448 dev_err(&i2c->dev, "Failed to reset the component (%d)\n", ret);
3449 return ret;
3450 }
3451 regcache_mark_dirty(tscs454->regmap);
3452
3453 ret = regmap_register_patch(tscs454->regmap, tscs454_patch,
3454 ARRAY_SIZE(tscs454_patch));
3455 if (ret < 0) {
3456 dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret);
3457 return ret;
3458 }
3459 /* Sync pg sel reg with cache */
3460 regmap_write(tscs454->regmap, R_PAGESEL, 0x00);
3461
3462 ret = snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454,
3463 tscs454_dais, ARRAY_SIZE(tscs454_dais));
3464 if (ret) {
3465 dev_err(&i2c->dev, "Failed to register component (%d)\n", ret);
3466 return ret;
3467 }
3468
3469 return 0;
3470}
3471
3472static const struct i2c_device_id tscs454_i2c_id[] = {
3473 { "tscs454", 0 },
3474 { }
3475};
3476MODULE_DEVICE_TABLE(i2c, tscs454_i2c_id);
3477
3478static const struct of_device_id tscs454_of_match[] = {
3479 { .compatible = "tempo,tscs454", },
3480 { }
3481};
3482MODULE_DEVICE_TABLE(of, tscs454_of_match);
3483
3484static struct i2c_driver tscs454_i2c_driver = {
3485 .driver = {
3486 .name = "tscs454",
3487 .of_match_table = tscs454_of_match,
3488 },
3489 .probe = tscs454_i2c_probe,
3490 .id_table = tscs454_i2c_id,
3491};
3492
3493module_i2c_driver(tscs454_i2c_driver);
3494
3495MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com");
3496MODULE_DESCRIPTION("ASoC TSCS454 driver");
3497MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/tscs454.h b/sound/soc/codecs/tscs454.h
new file mode 100644
index 000000000000..1142d73d3168
--- /dev/null
+++ b/sound/soc/codecs/tscs454.h
@@ -0,0 +1,2323 @@
1// SPDX-License-Identifier: GPL-2.0
2// tscs454.h -- TSCS454 ALSA SoC Audio driver
3// Copyright 2018 Tempo Semiconductor, Inc.
4// Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com>
5
6#ifndef __REDWOODPUBLIC_H__
7#define __REDWOODPUBLIC_H__
8
9#define VIRT_BASE 0x00
10#define PAGE_LEN 0x100
11#define VIRT_PAGE_BASE(page) (VIRT_BASE + (PAGE_LEN * page))
12#define VIRT_ADDR(page, address) (VIRT_PAGE_BASE(page) + address)
13#define ADDR(page, virt_address) (virt_address - VIRT_PAGE_BASE(page))
14
15#define R_PAGESEL 0x0
16#define R_RESET VIRT_ADDR(0x0, 0x1)
17#define R_IRQEN VIRT_ADDR(0x0, 0x2)
18#define R_IRQMASK VIRT_ADDR(0x0, 0x3)
19#define R_IRQSTAT VIRT_ADDR(0x0, 0x4)
20#define R_DEVADD0 VIRT_ADDR(0x0, 0x6)
21#define R_DEVID VIRT_ADDR(0x0, 0x8)
22#define R_DEVREV VIRT_ADDR(0x0, 0x9)
23#define R_PLLSTAT VIRT_ADDR(0x0, 0x0A)
24#define R_PLL1CTL VIRT_ADDR(0x0, 0x0B)
25#define R_PLL1RDIV VIRT_ADDR(0x0, 0x0C)
26#define R_PLL1ODIV VIRT_ADDR(0x0, 0x0D)
27#define R_PLL1FDIVL VIRT_ADDR(0x0, 0x0E)
28#define R_PLL1FDIVH VIRT_ADDR(0x0, 0x0F)
29#define R_PLL2CTL VIRT_ADDR(0x0, 0x10)
30#define R_PLL2RDIV VIRT_ADDR(0x0, 0x11)
31#define R_PLL2ODIV VIRT_ADDR(0x0, 0x12)
32#define R_PLL2FDIVL VIRT_ADDR(0x0, 0x13)
33#define R_PLL2FDIVH VIRT_ADDR(0x0, 0x14)
34#define R_PLLCTL VIRT_ADDR(0x0, 0x15)
35#define R_ISRC VIRT_ADDR(0x0, 0x16)
36#define R_SCLKCTL VIRT_ADDR(0x0, 0x18)
37#define R_TIMEBASE VIRT_ADDR(0x0, 0x19)
38#define R_I2SP1CTL VIRT_ADDR(0x0, 0x1A)
39#define R_I2SP2CTL VIRT_ADDR(0x0, 0x1B)
40#define R_I2SP3CTL VIRT_ADDR(0x0, 0x1C)
41#define R_I2S1MRATE VIRT_ADDR(0x0, 0x1D)
42#define R_I2S2MRATE VIRT_ADDR(0x0, 0x1E)
43#define R_I2S3MRATE VIRT_ADDR(0x0, 0x1F)
44#define R_I2SCMC VIRT_ADDR(0x0, 0x20)
45#define R_MCLK2PINC VIRT_ADDR(0x0, 0x21)
46#define R_I2SPINC0 VIRT_ADDR(0x0, 0x22)
47#define R_I2SPINC1 VIRT_ADDR(0x0, 0x23)
48#define R_I2SPINC2 VIRT_ADDR(0x0, 0x24)
49#define R_GPIOCTL0 VIRT_ADDR(0x0, 0x25)
50#define R_GPIOCTL1 VIRT_ADDR(0x0, 0x26)
51#define R_ASRC VIRT_ADDR(0x0, 0x28)
52#define R_TDMCTL0 VIRT_ADDR(0x0, 0x2D)
53#define R_TDMCTL1 VIRT_ADDR(0x0, 0x2E)
54#define R_PCMP2CTL0 VIRT_ADDR(0x0, 0x2F)
55#define R_PCMP2CTL1 VIRT_ADDR(0x0, 0x30)
56#define R_PCMP3CTL0 VIRT_ADDR(0x0, 0x31)
57#define R_PCMP3CTL1 VIRT_ADDR(0x0, 0x32)
58#define R_PWRM0 VIRT_ADDR(0x0, 0x33)
59#define R_PWRM1 VIRT_ADDR(0x0, 0x34)
60#define R_PWRM2 VIRT_ADDR(0x0, 0x35)
61#define R_PWRM3 VIRT_ADDR(0x0, 0x36)
62#define R_PWRM4 VIRT_ADDR(0x0, 0x37)
63#define R_I2SIDCTL VIRT_ADDR(0x0, 0x38)
64#define R_I2SODCTL VIRT_ADDR(0x0, 0x39)
65#define R_AUDIOMUX1 VIRT_ADDR(0x0, 0x3A)
66#define R_AUDIOMUX2 VIRT_ADDR(0x0, 0x3B)
67#define R_AUDIOMUX3 VIRT_ADDR(0x0, 0x3C)
68#define R_HSDCTL1 VIRT_ADDR(0x1, 0x1)
69#define R_HSDCTL2 VIRT_ADDR(0x1, 0x2)
70#define R_HSDSTAT VIRT_ADDR(0x1, 0x3)
71#define R_HSDDELAY VIRT_ADDR(0x1, 0x4)
72#define R_BUTCTL VIRT_ADDR(0x1, 0x5)
73#define R_CH0AIC VIRT_ADDR(0x1, 0x6)
74#define R_CH1AIC VIRT_ADDR(0x1, 0x7)
75#define R_CH2AIC VIRT_ADDR(0x1, 0x8)
76#define R_CH3AIC VIRT_ADDR(0x1, 0x9)
77#define R_ICTL0 VIRT_ADDR(0x1, 0x0A)
78#define R_ICTL1 VIRT_ADDR(0x1, 0x0B)
79#define R_MICBIAS VIRT_ADDR(0x1, 0x0C)
80#define R_PGACTL0 VIRT_ADDR(0x1, 0x0D)
81#define R_PGACTL1 VIRT_ADDR(0x1, 0x0E)
82#define R_PGACTL2 VIRT_ADDR(0x1, 0x0F)
83#define R_PGACTL3 VIRT_ADDR(0x1, 0x10)
84#define R_PGAZ VIRT_ADDR(0x1, 0x11)
85#define R_ICH0VOL VIRT_ADDR(0x1, 0x12)
86#define R_ICH1VOL VIRT_ADDR(0x1, 0x13)
87#define R_ICH2VOL VIRT_ADDR(0x1, 0x14)
88#define R_ICH3VOL VIRT_ADDR(0x1, 0x15)
89#define R_ASRCILVOL VIRT_ADDR(0x1, 0x16)
90#define R_ASRCIRVOL VIRT_ADDR(0x1, 0x17)
91#define R_ASRCOLVOL VIRT_ADDR(0x1, 0x18)
92#define R_ASRCORVOL VIRT_ADDR(0x1, 0x19)
93#define R_IVOLCTLU VIRT_ADDR(0x1, 0x1C)
94#define R_ALCCTL0 VIRT_ADDR(0x1, 0x1D)
95#define R_ALCCTL1 VIRT_ADDR(0x1, 0x1E)
96#define R_ALCCTL2 VIRT_ADDR(0x1, 0x1F)
97#define R_ALCCTL3 VIRT_ADDR(0x1, 0x20)
98#define R_NGATE VIRT_ADDR(0x1, 0x21)
99#define R_DMICCTL VIRT_ADDR(0x1, 0x22)
100#define R_DACCTL VIRT_ADDR(0x2, 0x1)
101#define R_SPKCTL VIRT_ADDR(0x2, 0x2)
102#define R_SUBCTL VIRT_ADDR(0x2, 0x3)
103#define R_DCCTL VIRT_ADDR(0x2, 0x4)
104#define R_OVOLCTLU VIRT_ADDR(0x2, 0x6)
105#define R_MUTEC VIRT_ADDR(0x2, 0x7)
106#define R_MVOLL VIRT_ADDR(0x2, 0x8)
107#define R_MVOLR VIRT_ADDR(0x2, 0x9)
108#define R_HPVOLL VIRT_ADDR(0x2, 0x0A)
109#define R_HPVOLR VIRT_ADDR(0x2, 0x0B)
110#define R_SPKVOLL VIRT_ADDR(0x2, 0x0C)
111#define R_SPKVOLR VIRT_ADDR(0x2, 0x0D)
112#define R_SUBVOL VIRT_ADDR(0x2, 0x10)
113#define R_COP0 VIRT_ADDR(0x2, 0x11)
114#define R_COP1 VIRT_ADDR(0x2, 0x12)
115#define R_COPSTAT VIRT_ADDR(0x2, 0x13)
116#define R_PWM0 VIRT_ADDR(0x2, 0x14)
117#define R_PWM1 VIRT_ADDR(0x2, 0x15)
118#define R_PWM2 VIRT_ADDR(0x2, 0x16)
119#define R_PWM3 VIRT_ADDR(0x2, 0x17)
120#define R_HPSW VIRT_ADDR(0x2, 0x18)
121#define R_THERMTS VIRT_ADDR(0x2, 0x19)
122#define R_THERMSPK1 VIRT_ADDR(0x2, 0x1A)
123#define R_THERMSTAT VIRT_ADDR(0x2, 0x1B)
124#define R_SCSTAT VIRT_ADDR(0x2, 0x1C)
125#define R_SDMON VIRT_ADDR(0x2, 0x1D)
126#define R_SPKEQFILT VIRT_ADDR(0x3, 0x1)
127#define R_SPKCRWDL VIRT_ADDR(0x3, 0x2)
128#define R_SPKCRWDM VIRT_ADDR(0x3, 0x3)
129#define R_SPKCRWDH VIRT_ADDR(0x3, 0x4)
130#define R_SPKCRRDL VIRT_ADDR(0x3, 0x5)
131#define R_SPKCRRDM VIRT_ADDR(0x3, 0x6)
132#define R_SPKCRRDH VIRT_ADDR(0x3, 0x7)
133#define R_SPKCRADD VIRT_ADDR(0x3, 0x8)
134#define R_SPKCRS VIRT_ADDR(0x3, 0x9)
135#define R_SPKMBCEN VIRT_ADDR(0x3, 0x0A)
136#define R_SPKMBCCTL VIRT_ADDR(0x3, 0x0B)
137#define R_SPKMBCMUG1 VIRT_ADDR(0x3, 0x0C)
138#define R_SPKMBCTHR1 VIRT_ADDR(0x3, 0x0D)
139#define R_SPKMBCRAT1 VIRT_ADDR(0x3, 0x0E)
140#define R_SPKMBCATK1L VIRT_ADDR(0x3, 0x0F)
141#define R_SPKMBCATK1H VIRT_ADDR(0x3, 0x10)
142#define R_SPKMBCREL1L VIRT_ADDR(0x3, 0x11)
143#define R_SPKMBCREL1H VIRT_ADDR(0x3, 0x12)
144#define R_SPKMBCMUG2 VIRT_ADDR(0x3, 0x13)
145#define R_SPKMBCTHR2 VIRT_ADDR(0x3, 0x14)
146#define R_SPKMBCRAT2 VIRT_ADDR(0x3, 0x15)
147#define R_SPKMBCATK2L VIRT_ADDR(0x3, 0x16)
148#define R_SPKMBCATK2H VIRT_ADDR(0x3, 0x17)
149#define R_SPKMBCREL2L VIRT_ADDR(0x3, 0x18)
150#define R_SPKMBCREL2H VIRT_ADDR(0x3, 0x19)
151#define R_SPKMBCMUG3 VIRT_ADDR(0x3, 0x1A)
152#define R_SPKMBCTHR3 VIRT_ADDR(0x3, 0x1B)
153#define R_SPKMBCRAT3 VIRT_ADDR(0x3, 0x1C)
154#define R_SPKMBCATK3L VIRT_ADDR(0x3, 0x1D)
155#define R_SPKMBCATK3H VIRT_ADDR(0x3, 0x1E)
156#define R_SPKMBCREL3L VIRT_ADDR(0x3, 0x1F)
157#define R_SPKMBCREL3H VIRT_ADDR(0x3, 0x20)
158#define R_SPKCLECTL VIRT_ADDR(0x3, 0x21)
159#define R_SPKCLEMUG VIRT_ADDR(0x3, 0x22)
160#define R_SPKCOMPTHR VIRT_ADDR(0x3, 0x23)
161#define R_SPKCOMPRAT VIRT_ADDR(0x3, 0x24)
162#define R_SPKCOMPATKL VIRT_ADDR(0x3, 0x25)
163#define R_SPKCOMPATKH VIRT_ADDR(0x3, 0x26)
164#define R_SPKCOMPRELL VIRT_ADDR(0x3, 0x27)
165#define R_SPKCOMPRELH VIRT_ADDR(0x3, 0x28)
166#define R_SPKLIMTHR VIRT_ADDR(0x3, 0x29)
167#define R_SPKLIMTGT VIRT_ADDR(0x3, 0x2A)
168#define R_SPKLIMATKL VIRT_ADDR(0x3, 0x2B)
169#define R_SPKLIMATKH VIRT_ADDR(0x3, 0x2C)
170#define R_SPKLIMRELL VIRT_ADDR(0x3, 0x2D)
171#define R_SPKLIMRELH VIRT_ADDR(0x3, 0x2E)
172#define R_SPKEXPTHR VIRT_ADDR(0x3, 0x2F)
173#define R_SPKEXPRAT VIRT_ADDR(0x3, 0x30)
174#define R_SPKEXPATKL VIRT_ADDR(0x3, 0x31)
175#define R_SPKEXPATKH VIRT_ADDR(0x3, 0x32)
176#define R_SPKEXPRELL VIRT_ADDR(0x3, 0x33)
177#define R_SPKEXPRELH VIRT_ADDR(0x3, 0x34)
178#define R_SPKFXCTL VIRT_ADDR(0x3, 0x35)
179#define R_DACEQFILT VIRT_ADDR(0x4, 0x1)
180#define R_DACCRWDL VIRT_ADDR(0x4, 0x2)
181#define R_DACCRWDM VIRT_ADDR(0x4, 0x3)
182#define R_DACCRWDH VIRT_ADDR(0x4, 0x4)
183#define R_DACCRRDL VIRT_ADDR(0x4, 0x5)
184#define R_DACCRRDM VIRT_ADDR(0x4, 0x6)
185#define R_DACCRRDH VIRT_ADDR(0x4, 0x7)
186#define R_DACCRADD VIRT_ADDR(0x4, 0x8)
187#define R_DACCRS VIRT_ADDR(0x4, 0x9)
188#define R_DACMBCEN VIRT_ADDR(0x4, 0x0A)
189#define R_DACMBCCTL VIRT_ADDR(0x4, 0x0B)
190#define R_DACMBCMUG1 VIRT_ADDR(0x4, 0x0C)
191#define R_DACMBCTHR1 VIRT_ADDR(0x4, 0x0D)
192#define R_DACMBCRAT1 VIRT_ADDR(0x4, 0x0E)
193#define R_DACMBCATK1L VIRT_ADDR(0x4, 0x0F)
194#define R_DACMBCATK1H VIRT_ADDR(0x4, 0x10)
195#define R_DACMBCREL1L VIRT_ADDR(0x4, 0x11)
196#define R_DACMBCREL1H VIRT_ADDR(0x4, 0x12)
197#define R_DACMBCMUG2 VIRT_ADDR(0x4, 0x13)
198#define R_DACMBCTHR2 VIRT_ADDR(0x4, 0x14)
199#define R_DACMBCRAT2 VIRT_ADDR(0x4, 0x15)
200#define R_DACMBCATK2L VIRT_ADDR(0x4, 0x16)
201#define R_DACMBCATK2H VIRT_ADDR(0x4, 0x17)
202#define R_DACMBCREL2L VIRT_ADDR(0x4, 0x18)
203#define R_DACMBCREL2H VIRT_ADDR(0x4, 0x19)
204#define R_DACMBCMUG3 VIRT_ADDR(0x4, 0x1A)
205#define R_DACMBCTHR3 VIRT_ADDR(0x4, 0x1B)
206#define R_DACMBCRAT3 VIRT_ADDR(0x4, 0x1C)
207#define R_DACMBCATK3L VIRT_ADDR(0x4, 0x1D)
208#define R_DACMBCATK3H VIRT_ADDR(0x4, 0x1E)
209#define R_DACMBCREL3L VIRT_ADDR(0x4, 0x1F)
210#define R_DACMBCREL3H VIRT_ADDR(0x4, 0x20)
211#define R_DACCLECTL VIRT_ADDR(0x4, 0x21)
212#define R_DACCLEMUG VIRT_ADDR(0x4, 0x22)
213#define R_DACCOMPTHR VIRT_ADDR(0x4, 0x23)
214#define R_DACCOMPRAT VIRT_ADDR(0x4, 0x24)
215#define R_DACCOMPATKL VIRT_ADDR(0x4, 0x25)
216#define R_DACCOMPATKH VIRT_ADDR(0x4, 0x26)
217#define R_DACCOMPRELL VIRT_ADDR(0x4, 0x27)
218#define R_DACCOMPRELH VIRT_ADDR(0x4, 0x28)
219#define R_DACLIMTHR VIRT_ADDR(0x4, 0x29)
220#define R_DACLIMTGT VIRT_ADDR(0x4, 0x2A)
221#define R_DACLIMATKL VIRT_ADDR(0x4, 0x2B)
222#define R_DACLIMATKH VIRT_ADDR(0x4, 0x2C)
223#define R_DACLIMRELL VIRT_ADDR(0x4, 0x2D)
224#define R_DACLIMRELH VIRT_ADDR(0x4, 0x2E)
225#define R_DACEXPTHR VIRT_ADDR(0x4, 0x2F)
226#define R_DACEXPRAT VIRT_ADDR(0x4, 0x30)
227#define R_DACEXPATKL VIRT_ADDR(0x4, 0x31)
228#define R_DACEXPATKH VIRT_ADDR(0x4, 0x32)
229#define R_DACEXPRELL VIRT_ADDR(0x4, 0x33)
230#define R_DACEXPRELH VIRT_ADDR(0x4, 0x34)
231#define R_DACFXCTL VIRT_ADDR(0x4, 0x35)
232#define R_SUBEQFILT VIRT_ADDR(0x5, 0x1)
233#define R_SUBCRWDL VIRT_ADDR(0x5, 0x2)
234#define R_SUBCRWDM VIRT_ADDR(0x5, 0x3)
235#define R_SUBCRWDH VIRT_ADDR(0x5, 0x4)
236#define R_SUBCRRDL VIRT_ADDR(0x5, 0x5)
237#define R_SUBCRRDM VIRT_ADDR(0x5, 0x6)
238#define R_SUBCRRDH VIRT_ADDR(0x5, 0x7)
239#define R_SUBCRADD VIRT_ADDR(0x5, 0x8)
240#define R_SUBCRS VIRT_ADDR(0x5, 0x9)
241#define R_SUBMBCEN VIRT_ADDR(0x5, 0x0A)
242#define R_SUBMBCCTL VIRT_ADDR(0x5, 0x0B)
243#define R_SUBMBCMUG1 VIRT_ADDR(0x5, 0x0C)
244#define R_SUBMBCTHR1 VIRT_ADDR(0x5, 0x0D)
245#define R_SUBMBCRAT1 VIRT_ADDR(0x5, 0x0E)
246#define R_SUBMBCATK1L VIRT_ADDR(0x5, 0x0F)
247#define R_SUBMBCATK1H VIRT_ADDR(0x5, 0x10)
248#define R_SUBMBCREL1L VIRT_ADDR(0x5, 0x11)
249#define R_SUBMBCREL1H VIRT_ADDR(0x5, 0x12)
250#define R_SUBMBCMUG2 VIRT_ADDR(0x5, 0x13)
251#define R_SUBMBCTHR2 VIRT_ADDR(0x5, 0x14)
252#define R_SUBMBCRAT2 VIRT_ADDR(0x5, 0x15)
253#define R_SUBMBCATK2L VIRT_ADDR(0x5, 0x16)
254#define R_SUBMBCATK2H VIRT_ADDR(0x5, 0x17)
255#define R_SUBMBCREL2L VIRT_ADDR(0x5, 0x18)
256#define R_SUBMBCREL2H VIRT_ADDR(0x5, 0x19)
257#define R_SUBMBCMUG3 VIRT_ADDR(0x5, 0x1A)
258#define R_SUBMBCTHR3 VIRT_ADDR(0x5, 0x1B)
259#define R_SUBMBCRAT3 VIRT_ADDR(0x5, 0x1C)
260#define R_SUBMBCATK3L VIRT_ADDR(0x5, 0x1D)
261#define R_SUBMBCATK3H VIRT_ADDR(0x5, 0x1E)
262#define R_SUBMBCREL3L VIRT_ADDR(0x5, 0x1F)
263#define R_SUBMBCREL3H VIRT_ADDR(0x5, 0x20)
264#define R_SUBCLECTL VIRT_ADDR(0x5, 0x21)
265#define R_SUBCLEMUG VIRT_ADDR(0x5, 0x22)
266#define R_SUBCOMPTHR VIRT_ADDR(0x5, 0x23)
267#define R_SUBCOMPRAT VIRT_ADDR(0x5, 0x24)
268#define R_SUBCOMPATKL VIRT_ADDR(0x5, 0x25)
269#define R_SUBCOMPATKH VIRT_ADDR(0x5, 0x26)
270#define R_SUBCOMPRELL VIRT_ADDR(0x5, 0x27)
271#define R_SUBCOMPRELH VIRT_ADDR(0x5, 0x28)
272#define R_SUBLIMTHR VIRT_ADDR(0x5, 0x29)
273#define R_SUBLIMTGT VIRT_ADDR(0x5, 0x2A)
274#define R_SUBLIMATKL VIRT_ADDR(0x5, 0x2B)
275#define R_SUBLIMATKH VIRT_ADDR(0x5, 0x2C)
276#define R_SUBLIMRELL VIRT_ADDR(0x5, 0x2D)
277#define R_SUBLIMRELH VIRT_ADDR(0x5, 0x2E)
278#define R_SUBEXPTHR VIRT_ADDR(0x5, 0x2F)
279#define R_SUBEXPRAT VIRT_ADDR(0x5, 0x30)
280#define R_SUBEXPATKL VIRT_ADDR(0x5, 0x31)
281#define R_SUBEXPATKH VIRT_ADDR(0x5, 0x32)
282#define R_SUBEXPRELL VIRT_ADDR(0x5, 0x33)
283#define R_SUBEXPRELH VIRT_ADDR(0x5, 0x34)
284#define R_SUBFXCTL VIRT_ADDR(0x5, 0x35)
285
286// *** PLLCTL ***
287#define FB_PLLCTL_VCCI_PLL 6
288#define FM_PLLCTL_VCCI_PLL 0xC0
289
290#define FB_PLLCTL_RZ_PLL 3
291#define FM_PLLCTL_RZ_PLL 0x38
292
293#define FB_PLLCTL_CP_PLL 0
294#define FM_PLLCTL_CP_PLL 0x7
295
296// *** PLLRDIV ***
297#define FB_PLLRDIV_REFDIV_PLL 0
298#define FM_PLLRDIV_REFDIV_PLL 0xFF
299
300// *** PLLODIV ***
301#define FB_PLLODIV_OUTDIV_PLL 0
302#define FM_PLLODIV_OUTDIV_PLL 0xFF
303
304// *** PLLFDIVL ***
305#define FB_PLLFDIVL_FBDIVL_PLL 0
306#define FM_PLLFDIVL_FBDIVL_PLL 0xFF
307
308// *** PLLFDIVH ***
309#define FB_PLLFDIVH_FBDIVH_PLL 0
310#define FM_PLLFDIVH_FBDIVH_PLL 0xF
311
312// *** I2SPCTL ***
313#define FB_I2SPCTL_BCLKSTAT 7
314#define FM_I2SPCTL_BCLKSTAT 0x80
315#define FV_BCLKSTAT_LOST 0x80
316#define FV_BCLKSTAT_NOT_LOST 0x0
317
318#define FB_I2SPCTL_BCLKP 6
319#define FM_I2SPCTL_BCLKP 0x40
320#define FV_BCLKP_NOT_INVERTED 0x0
321#define FV_BCLKP_INVERTED 0x40
322
323#define FB_I2SPCTL_PORTMS 5
324#define FM_I2SPCTL_PORTMS 0x20
325#define FV_PORTMS_SLAVE 0x0
326#define FV_PORTMS_MASTER 0x20
327
328#define FB_I2SPCTL_LRCLKP 4
329#define FM_I2SPCTL_LRCLKP 0x10
330#define FV_LRCLKP_NOT_INVERTED 0x0
331#define FV_LRCLKP_INVERTED 0x10
332
333#define FB_I2SPCTL_WL 2
334#define FM_I2SPCTL_WL 0xC
335#define FV_WL_16 0x0
336#define FV_WL_20 0x4
337#define FV_WL_24 0x8
338#define FV_WL_32 0xC
339
340#define FB_I2SPCTL_FORMAT 0
341#define FM_I2SPCTL_FORMAT 0x3
342#define FV_FORMAT_RIGHT 0x0
343#define FV_FORMAT_LEFT 0x1
344#define FV_FORMAT_I2S 0x2
345#define FV_FORMAT_TDM 0x3
346
347// *** I2SMRATE ***
348#define FB_I2SMRATE_I2SMCLKHALF 7
349#define FM_I2SMRATE_I2SMCLKHALF 0x80
350#define FV_I2SMCLKHALF_I2S1MCLKDIV_DIV_2 0x0
351#define FV_I2SMCLKHALF_I2S1MCLKDIV_ONLY 0x80
352
353#define FB_I2SMRATE_I2SMCLKDIV 5
354#define FM_I2SMRATE_I2SMCLKDIV 0x60
355#define FV_I2SMCLKDIV_125 0x0
356#define FV_I2SMCLKDIV_128 0x20
357#define FV_I2SMCLKDIV_136 0x40
358#define FV_I2SMCLKDIV_192 0x60
359
360#define FB_I2SMRATE_I2SMBR 3
361#define FM_I2SMRATE_I2SMBR 0x18
362#define FV_I2SMBR_32 0x0
363#define FV_I2SMBR_44PT1 0x8
364#define FV_I2SMBR_48 0x10
365#define FV_I2SMBR_MCLK_MODE 0x18
366
367#define FB_I2SMRATE_I2SMBM 0
368#define FM_I2SMRATE_I2SMBM 0x3
369#define FV_I2SMBM_0PT25 0x0
370#define FV_I2SMBM_0PT5 0x1
371#define FV_I2SMBM_1 0x2
372#define FV_I2SMBM_2 0x3
373
374// *** PCMPCTL0 ***
375#define FB_PCMPCTL0_PCMFLENP 2
376#define FM_PCMPCTL0_PCMFLENP 0x4
377#define FV_PCMFLENP_128 0x0
378#define FV_PCMFLENP_256 0x4
379
380#define FB_PCMPCTL0_SLSYNCP 1
381#define FM_PCMPCTL0_SLSYNCP 0x2
382#define FV_SLSYNCP_SHORT 0x0
383#define FV_SLSYNCP_LONG 0x2
384
385#define FB_PCMPCTL0_BDELAYP 0
386#define FM_PCMPCTL0_BDELAYP 0x1
387#define FV_BDELAYP_NO_DELAY 0x0
388#define FV_BDELAYP_1BCLK_DELAY 0x1
389
390// *** PCMPCTL1 ***
391#define FB_PCMPCTL1_PCMMOMP 6
392#define FM_PCMPCTL1_PCMMOMP 0x40
393
394#define FB_PCMPCTL1_PCMSOP 5
395#define FM_PCMPCTL1_PCMSOP 0x20
396#define FV_PCMSOP_1 0x0
397#define FV_PCMSOP_2 0x20
398
399#define FB_PCMPCTL1_PCMDSSP 3
400#define FM_PCMPCTL1_PCMDSSP 0x18
401#define FV_PCMDSSP_16 0x0
402#define FV_PCMDSSP_24 0x8
403#define FV_PCMDSSP_32 0x10
404
405#define FB_PCMPCTL1_PCMMIMP 1
406#define FM_PCMPCTL1_PCMMIMP 0x2
407
408#define FB_PCMPCTL1_PCMSIP 0
409#define FM_PCMPCTL1_PCMSIP 0x1
410#define FV_PCMSIP_1 0x0
411#define FV_PCMSIP_2 0x1
412
413// *** CHAIC ***
414#define FB_CHAIC_MICBST 4
415#define FM_CHAIC_MICBST 0x30
416
417// *** PGACTL ***
418#define FB_PGACTL_PGAMUTE 7
419#define FM_PGACTL_PGAMUTE 0x80
420
421#define FB_PGACTL_PGAVOL 0
422#define FM_PGACTL_PGAVOL 0x3F
423
424// *** ICHVOL ***
425#define FB_ICHVOL_ICHVOL 0
426#define FM_ICHVOL_ICHVOL 0xFF
427
428// *** SPKMBCMUG ***
429#define FB_SPKMBCMUG_PHASE 5
430#define FM_SPKMBCMUG_PHASE 0x20
431
432#define FB_SPKMBCMUG_MUGAIN 0
433#define FM_SPKMBCMUG_MUGAIN 0x1F
434
435// *** SPKMBCTHR ***
436#define FB_SPKMBCTHR_THRESH 0
437#define FM_SPKMBCTHR_THRESH 0xFF
438
439// *** SPKMBCRAT ***
440#define FB_SPKMBCRAT_RATIO 0
441#define FM_SPKMBCRAT_RATIO 0x1F
442
443// *** SPKMBCATKL ***
444#define FB_SPKMBCATKL_TCATKL 0
445#define FM_SPKMBCATKL_TCATKL 0xFF
446
447// *** SPKMBCATKH ***
448#define FB_SPKMBCATKH_TCATKH 0
449#define FM_SPKMBCATKH_TCATKH 0xFF
450
451// *** SPKMBCRELL ***
452#define FB_SPKMBCRELL_TCRELL 0
453#define FM_SPKMBCRELL_TCRELL 0xFF
454
455// *** SPKMBCRELH ***
456#define FB_SPKMBCRELH_TCRELH 0
457#define FM_SPKMBCRELH_TCRELH 0xFF
458
459// *** DACMBCMUG ***
460#define FB_DACMBCMUG_PHASE 5
461#define FM_DACMBCMUG_PHASE 0x20
462
463#define FB_DACMBCMUG_MUGAIN 0
464#define FM_DACMBCMUG_MUGAIN 0x1F
465
466// *** DACMBCTHR ***
467#define FB_DACMBCTHR_THRESH 0
468#define FM_DACMBCTHR_THRESH 0xFF
469
470// *** DACMBCRAT ***
471#define FB_DACMBCRAT_RATIO 0
472#define FM_DACMBCRAT_RATIO 0x1F
473
474// *** DACMBCATKL ***
475#define FB_DACMBCATKL_TCATKL 0
476#define FM_DACMBCATKL_TCATKL 0xFF
477
478// *** DACMBCATKH ***
479#define FB_DACMBCATKH_TCATKH 0
480#define FM_DACMBCATKH_TCATKH 0xFF
481
482// *** DACMBCRELL ***
483#define FB_DACMBCRELL_TCRELL 0
484#define FM_DACMBCRELL_TCRELL 0xFF
485
486// *** DACMBCRELH ***
487#define FB_DACMBCRELH_TCRELH 0
488#define FM_DACMBCRELH_TCRELH 0xFF
489
490// *** SUBMBCMUG ***
491#define FB_SUBMBCMUG_PHASE 5
492#define FM_SUBMBCMUG_PHASE 0x20
493
494#define FB_SUBMBCMUG_MUGAIN 0
495#define FM_SUBMBCMUG_MUGAIN 0x1F
496
497// *** SUBMBCTHR ***
498#define FB_SUBMBCTHR_THRESH 0
499#define FM_SUBMBCTHR_THRESH 0xFF
500
501// *** SUBMBCRAT ***
502#define FB_SUBMBCRAT_RATIO 0
503#define FM_SUBMBCRAT_RATIO 0x1F
504
505// *** SUBMBCATKL ***
506#define FB_SUBMBCATKL_TCATKL 0
507#define FM_SUBMBCATKL_TCATKL 0xFF
508
509// *** SUBMBCATKH ***
510#define FB_SUBMBCATKH_TCATKH 0
511#define FM_SUBMBCATKH_TCATKH 0xFF
512
513// *** SUBMBCRELL ***
514#define FB_SUBMBCRELL_TCRELL 0
515#define FM_SUBMBCRELL_TCRELL 0xFF
516
517// *** SUBMBCRELH ***
518#define FB_SUBMBCRELH_TCRELH 0
519#define FM_SUBMBCRELH_TCRELH 0xFF
520
521// *** PAGESEL ***
522#define FB_PAGESEL_PAGESEL 0
523#define FM_PAGESEL_PAGESEL 0xFF
524
525// *** RESET ***
526#define FB_RESET_RESET 0
527#define FM_RESET_RESET 0xFF
528#define FV_RESET_PWR_ON_DEFAULTS 0x85
529
530// *** IRQEN ***
531#define FB_IRQEN_THRMINTEN 6
532#define FM_IRQEN_THRMINTEN 0x40
533#define FV_THRMINTEN_ENABLED 0x40
534#define FV_THRMINTEN_DISABLED 0x0
535
536#define FB_IRQEN_HBPINTEN 5
537#define FM_IRQEN_HBPINTEN 0x20
538#define FV_HBPINTEN_ENABLED 0x20
539#define FV_HBPINTEN_DISABLED 0x0
540
541#define FB_IRQEN_HSDINTEN 4
542#define FM_IRQEN_HSDINTEN 0x10
543#define FV_HSDINTEN_ENABLED 0x10
544#define FV_HSDINTEN_DISABLED 0x0
545
546#define FB_IRQEN_HPDINTEN 3
547#define FM_IRQEN_HPDINTEN 0x8
548#define FV_HPDINTEN_ENABLED 0x8
549#define FV_HPDINTEN_DISABLED 0x0
550
551#define FB_IRQEN_GPIO3INTEN 1
552#define FM_IRQEN_GPIO3INTEN 0x2
553#define FV_GPIO3INTEN_ENABLED 0x2
554#define FV_GPIO3INTEN_DISABLED 0x0
555
556#define FB_IRQEN_GPIO2INTEN 0
557#define FM_IRQEN_GPIO2INTEN 0x1
558#define FV_GPIO2INTEN_ENABLED 0x1
559#define FV_GPIO2INTEN_DISABLED 0x0
560
561#define IRQEN_GPIOINTEN_ENABLED 0x1
562#define IRQEN_GPIOINTEN_DISABLED 0x0
563
564// *** IRQMASK ***
565#define FB_IRQMASK_THRMIM 6
566#define FM_IRQMASK_THRMIM 0x40
567#define FV_THRMIM_MASKED 0x0
568#define FV_THRMIM_NOT_MASKED 0x40
569
570#define FB_IRQMASK_HBPIM 5
571#define FM_IRQMASK_HBPIM 0x20
572#define FV_HBPIM_MASKED 0x0
573#define FV_HBPIM_NOT_MASKED 0x20
574
575#define FB_IRQMASK_HSDIM 4
576#define FM_IRQMASK_HSDIM 0x10
577#define FV_HSDIM_MASKED 0x0
578#define FV_HSDIM_NOT_MASKED 0x10
579
580#define FB_IRQMASK_HPDIM 3
581#define FM_IRQMASK_HPDIM 0x8
582#define FV_HPDIM_MASKED 0x0
583#define FV_HPDIM_NOT_MASKED 0x8
584
585#define FB_IRQMASK_GPIO3M 1
586#define FM_IRQMASK_GPIO3M 0x2
587#define FV_GPIO3M_MASKED 0x0
588#define FV_GPIO3M_NOT_MASKED 0x2
589
590#define FB_IRQMASK_GPIO2M 0
591#define FM_IRQMASK_GPIO2M 0x1
592#define FV_GPIO2M_MASKED 0x0
593#define FV_GPIO2M_NOT_MASKED 0x1
594
595#define IRQMASK_GPIOM_MASKED 0x0
596#define IRQMASK_GPIOM_NOT_MASKED 0x1
597
598// *** IRQSTAT ***
599#define FB_IRQSTAT_THRMINT 6
600#define FM_IRQSTAT_THRMINT 0x40
601#define FV_THRMINT_INTERRUPTED 0x40
602#define FV_THRMINT_NOT_INTERRUPTED 0x0
603
604#define FB_IRQSTAT_HBPINT 5
605#define FM_IRQSTAT_HBPINT 0x20
606#define FV_HBPINT_INTERRUPTED 0x20
607#define FV_HBPINT_NOT_INTERRUPTED 0x0
608
609#define FB_IRQSTAT_HSDINT 4
610#define FM_IRQSTAT_HSDINT 0x10
611#define FV_HSDINT_INTERRUPTED 0x10
612#define FV_HSDINT_NOT_INTERRUPTED 0x0
613
614#define FB_IRQSTAT_HPDINT 3
615#define FM_IRQSTAT_HPDINT 0x8
616#define FV_HPDINT_INTERRUPTED 0x8
617#define FV_HPDINT_NOT_INTERRUPTED 0x0
618
619#define FB_IRQSTAT_GPIO3INT 1
620#define FM_IRQSTAT_GPIO3INT 0x2
621#define FV_GPIO3INT_INTERRUPTED 0x2
622#define FV_GPIO3INT_NOT_INTERRUPTED 0x0
623
624#define FB_IRQSTAT_GPIO2INT 0
625#define FM_IRQSTAT_GPIO2INT 0x1
626#define FV_GPIO2INT_INTERRUPTED 0x1
627#define FV_GPIO2INT_NOT_INTERRUPTED 0x0
628
629#define IRQSTAT_GPIOINT_INTERRUPTED 0x1
630#define IRQSTAT_GPIOINT_NOT_INTERRUPTED 0x0
631
632// *** DEVADD0 ***
633#define FB_DEVADD0_DEVADD0 1
634#define FM_DEVADD0_DEVADD0 0xFE
635
636#define FB_DEVADD0_I2C_ADDRLK 0
637#define FM_DEVADD0_I2C_ADDRLK 0x1
638#define FV_I2C_ADDRLK_LOCK 0x1
639
640// *** DEVID ***
641#define FB_DEVID_DEV_ID 0
642#define FM_DEVID_DEV_ID 0xFF
643
644// *** DEVREV ***
645#define FB_DEVREV_MAJ_REV 4
646#define FM_DEVREV_MAJ_REV 0xF0
647
648#define FB_DEVREV_MIN_REV 0
649#define FM_DEVREV_MIN_REV 0xF
650
651// *** PLLSTAT ***
652#define FB_PLLSTAT_PLL2LK 1
653#define FM_PLLSTAT_PLL2LK 0x2
654#define FV_PLL2LK_LOCKED 0x2
655#define FV_PLL2LK_UNLOCKED 0x0
656
657#define FB_PLLSTAT_PLL1LK 0
658#define FM_PLLSTAT_PLL1LK 0x1
659#define FV_PLL1LK_LOCKED 0x1
660#define FV_PLL1LK_UNLOCKED 0x0
661
662#define PLLSTAT_PLLLK_LOCKED 0x1
663#define PLLSTAT_PLLLK_UNLOCKED 0x0
664
665// *** PLLCTL ***
666#define FB_PLLCTL_PU_PLL2 7
667#define FM_PLLCTL_PU_PLL2 0x80
668#define FV_PU_PLL2_PWR_UP 0x80
669#define FV_PU_PLL2_PWR_DWN 0x0
670
671#define FB_PLLCTL_PU_PLL1 6
672#define FM_PLLCTL_PU_PLL1 0x40
673#define FV_PU_PLL1_PWR_UP 0x40
674#define FV_PU_PLL1_PWR_DWN 0x0
675
676#define FB_PLLCTL_PLL2CLKEN 5
677#define FM_PLLCTL_PLL2CLKEN 0x20
678#define FV_PLL2CLKEN_ENABLE 0x20
679#define FV_PLL2CLKEN_DISABLE 0x0
680
681#define FB_PLLCTL_PLL1CLKEN 4
682#define FM_PLLCTL_PLL1CLKEN 0x10
683#define FV_PLL1CLKEN_ENABLE 0x10
684#define FV_PLL1CLKEN_DISABLE 0x0
685
686#define FB_PLLCTL_BCLKSEL 2
687#define FM_PLLCTL_BCLKSEL 0xC
688#define FV_BCLKSEL_BCLK1 0x0
689#define FV_BCLKSEL_BCLK2 0x4
690#define FV_BCLKSEL_BCLK3 0x8
691
692#define FB_PLLCTL_PLLISEL 0
693#define FM_PLLCTL_PLLISEL 0x3
694#define FV_PLLISEL_XTAL 0x0
695#define FV_PLLISEL_MCLK1 0x1
696#define FV_PLLISEL_MCLK2 0x2
697#define FV_PLLISEL_BCLK 0x3
698
699#define PLLCTL_PU_PLL_PWR_UP 0x1
700#define PLLCTL_PU_PLL_PWR_DWN 0x0
701#define PLLCTL_PLLCLKEN_ENABLE 0x1
702#define PLLCTL_PLLCLKEN_DISABLE 0x0
703
704// *** ISRC ***
705#define FB_ISRC_IBR 2
706#define FM_ISRC_IBR 0x4
707#define FV_IBR_44PT1 0x0
708#define FV_IBR_48 0x4
709
710#define FB_ISRC_IBM 0
711#define FM_ISRC_IBM 0x3
712#define FV_IBM_0PT25 0x0
713#define FV_IBM_0PT5 0x1
714#define FV_IBM_1 0x2
715#define FV_IBM_2 0x3
716
717// *** SCLKCTL ***
718#define FB_SCLKCTL_ASDM 6
719#define FM_SCLKCTL_ASDM 0xC0
720#define FV_ASDM_HALF 0x40
721#define FV_ASDM_FULL 0x80
722#define FV_ASDM_AUTO 0xC0
723
724#define FB_SCLKCTL_DSDM 4
725#define FM_SCLKCTL_DSDM 0x30
726#define FV_DSDM_HALF 0x10
727#define FV_DSDM_FULL 0x20
728#define FV_DSDM_AUTO 0x30
729
730// *** TIMEBASE ***
731#define FB_TIMEBASE_TIMEBASE 0
732#define FM_TIMEBASE_TIMEBASE 0xFF
733
734// *** I2SCMC ***
735#define FB_I2SCMC_BCMP3 4
736#define FM_I2SCMC_BCMP3 0x30
737#define FV_BCMP3_AUTO 0x0
738#define FV_BCMP3_32X 0x10
739#define FV_BCMP3_40X 0x20
740#define FV_BCMP3_64X 0x30
741
742#define FB_I2SCMC_BCMP2 2
743#define FM_I2SCMC_BCMP2 0xC
744#define FV_BCMP2_AUTO 0x0
745#define FV_BCMP2_32X 0x4
746#define FV_BCMP2_40X 0x8
747#define FV_BCMP2_64X 0xC
748
749#define FB_I2SCMC_BCMP1 0
750#define FM_I2SCMC_BCMP1 0x3
751#define FV_BCMP1_AUTO 0x0
752#define FV_BCMP1_32X 0x1
753#define FV_BCMP1_40X 0x2
754#define FV_BCMP1_64X 0x3
755
756#define I2SCMC_BCMP_AUTO 0x0
757#define I2SCMC_BCMP_32X 0x1
758#define I2SCMC_BCMP_40X 0x2
759#define I2SCMC_BCMP_64X 0x3
760
761// *** MCLK2PINC ***
762#define FB_MCLK2PINC_SLEWOUT 4
763#define FM_MCLK2PINC_SLEWOUT 0xF0
764
765#define FB_MCLK2PINC_MCLK2IO 2
766#define FM_MCLK2PINC_MCLK2IO 0x4
767#define FV_MCLK2IO_INPUT 0x0
768#define FV_MCLK2IO_OUTPUT 0x4
769
770#define FB_MCLK2PINC_MCLK2OS 0
771#define FM_MCLK2PINC_MCLK2OS 0x3
772#define FV_MCLK2OS_24PT576 0x0
773#define FV_MCLK2OS_22PT5792 0x1
774#define FV_MCLK2OS_PLL2 0x2
775
776// *** I2SPINC0 ***
777#define FB_I2SPINC0_SDO3TRI 7
778#define FM_I2SPINC0_SDO3TRI 0x80
779
780#define FB_I2SPINC0_SDO2TRI 6
781#define FM_I2SPINC0_SDO2TRI 0x40
782
783#define FB_I2SPINC0_SDO1TRI 5
784#define FM_I2SPINC0_SDO1TRI 0x20
785
786#define FB_I2SPINC0_PCM3TRI 2
787#define FM_I2SPINC0_PCM3TRI 0x4
788
789#define FB_I2SPINC0_PCM2TRI 1
790#define FM_I2SPINC0_PCM2TRI 0x2
791
792#define FB_I2SPINC0_PCM1TRI 0
793#define FM_I2SPINC0_PCM1TRI 0x1
794
795// *** I2SPINC1 ***
796#define FB_I2SPINC1_SDO3PDD 2
797#define FM_I2SPINC1_SDO3PDD 0x4
798
799#define FB_I2SPINC1_SDO2PDD 1
800#define FM_I2SPINC1_SDO2PDD 0x2
801
802#define FB_I2SPINC1_SDO1PDD 0
803#define FM_I2SPINC1_SDO1PDD 0x1
804
805// *** I2SPINC2 ***
806#define FB_I2SPINC2_LR3PDD 5
807#define FM_I2SPINC2_LR3PDD 0x20
808
809#define FB_I2SPINC2_BC3PDD 4
810#define FM_I2SPINC2_BC3PDD 0x10
811
812#define FB_I2SPINC2_LR2PDD 3
813#define FM_I2SPINC2_LR2PDD 0x8
814
815#define FB_I2SPINC2_BC2PDD 2
816#define FM_I2SPINC2_BC2PDD 0x4
817
818#define FB_I2SPINC2_LR1PDD 1
819#define FM_I2SPINC2_LR1PDD 0x2
820
821#define FB_I2SPINC2_BC1PDD 0
822#define FM_I2SPINC2_BC1PDD 0x1
823
824// *** GPIOCTL0 ***
825#define FB_GPIOCTL0_GPIO3INTP 7
826#define FM_GPIOCTL0_GPIO3INTP 0x80
827
828#define FB_GPIOCTL0_GPIO2INTP 6
829#define FM_GPIOCTL0_GPIO2INTP 0x40
830
831#define FB_GPIOCTL0_GPIO3CFG 5
832#define FM_GPIOCTL0_GPIO3CFG 0x20
833
834#define FB_GPIOCTL0_GPIO2CFG 4
835#define FM_GPIOCTL0_GPIO2CFG 0x10
836
837#define FB_GPIOCTL0_GPIO3IO 3
838#define FM_GPIOCTL0_GPIO3IO 0x8
839
840#define FB_GPIOCTL0_GPIO2IO 2
841#define FM_GPIOCTL0_GPIO2IO 0x4
842
843#define FB_GPIOCTL0_GPIO1IO 1
844#define FM_GPIOCTL0_GPIO1IO 0x2
845
846#define FB_GPIOCTL0_GPIO0IO 0
847#define FM_GPIOCTL0_GPIO0IO 0x1
848
849// *** GPIOCTL1 ***
850#define FB_GPIOCTL1_GPIO3 7
851#define FM_GPIOCTL1_GPIO3 0x80
852
853#define FB_GPIOCTL1_GPIO2 6
854#define FM_GPIOCTL1_GPIO2 0x40
855
856#define FB_GPIOCTL1_GPIO1 5
857#define FM_GPIOCTL1_GPIO1 0x20
858
859#define FB_GPIOCTL1_GPIO0 4
860#define FM_GPIOCTL1_GPIO0 0x10
861
862#define FB_GPIOCTL1_GPIO3RD 3
863#define FM_GPIOCTL1_GPIO3RD 0x8
864
865#define FB_GPIOCTL1_GPIO2RD 2
866#define FM_GPIOCTL1_GPIO2RD 0x4
867
868#define FB_GPIOCTL1_GPIO1RD 1
869#define FM_GPIOCTL1_GPIO1RD 0x2
870
871#define FB_GPIOCTL1_GPIO0RD 0
872#define FM_GPIOCTL1_GPIO0RD 0x1
873
874// *** ASRC ***
875#define FB_ASRC_ASRCOBW 7
876#define FM_ASRC_ASRCOBW 0x80
877
878#define FB_ASRC_ASRCIBW 6
879#define FM_ASRC_ASRCIBW 0x40
880
881#define FB_ASRC_ASRCOB 5
882#define FM_ASRC_ASRCOB 0x20
883#define FV_ASRCOB_ACTIVE 0x0
884#define FV_ASRCOB_BYPASSED 0x20
885
886#define FB_ASRC_ASRCIB 4
887#define FM_ASRC_ASRCIB 0x10
888#define FV_ASRCIB_ACTIVE 0x0
889#define FV_ASRCIB_BYPASSED 0x10
890
891#define FB_ASRC_ASRCOL 3
892#define FM_ASRC_ASRCOL 0x8
893
894#define FB_ASRC_ASRCIL 2
895#define FM_ASRC_ASRCIL 0x4
896
897// *** TDMCTL0 ***
898#define FB_TDMCTL0_TDMMD 2
899#define FM_TDMCTL0_TDMMD 0x4
900#define FV_TDMMD_200 0x0
901#define FV_TDMMD_256 0x4
902
903#define FB_TDMCTL0_SLSYNC 1
904#define FM_TDMCTL0_SLSYNC 0x2
905#define FV_SLSYNC_SHORT 0x0
906#define FV_SLSYNC_LONG 0x2
907
908#define FB_TDMCTL0_BDELAY 0
909#define FM_TDMCTL0_BDELAY 0x1
910#define FV_BDELAY_NO_DELAY 0x0
911#define FV_BDELAY_1BCLK_DELAY 0x1
912
913// *** TDMCTL1 ***
914#define FB_TDMCTL1_TDMSO 5
915#define FM_TDMCTL1_TDMSO 0x60
916#define FV_TDMSO_2 0x0
917#define FV_TDMSO_4 0x20
918#define FV_TDMSO_6 0x40
919
920#define FB_TDMCTL1_TDMDSS 3
921#define FM_TDMCTL1_TDMDSS 0x18
922#define FV_TDMDSS_16 0x0
923#define FV_TDMDSS_24 0x10
924#define FV_TDMDSS_32 0x18
925
926#define FB_TDMCTL1_TDMSI 0
927#define FM_TDMCTL1_TDMSI 0x3
928#define FV_TDMSI_2 0x0
929#define FV_TDMSI_4 0x1
930#define FV_TDMSI_6 0x2
931
932// *** PWRM0 ***
933#define FB_PWRM0_INPROC3PU 6
934#define FM_PWRM0_INPROC3PU 0x40
935
936#define FB_PWRM0_INPROC2PU 5
937#define FM_PWRM0_INPROC2PU 0x20
938
939#define FB_PWRM0_INPROC1PU 4
940#define FM_PWRM0_INPROC1PU 0x10
941
942#define FB_PWRM0_INPROC0PU 3
943#define FM_PWRM0_INPROC0PU 0x8
944
945#define FB_PWRM0_MICB2PU 2
946#define FM_PWRM0_MICB2PU 0x4
947
948#define FB_PWRM0_MICB1PU 1
949#define FM_PWRM0_MICB1PU 0x2
950
951#define FB_PWRM0_MCLKPEN 0
952#define FM_PWRM0_MCLKPEN 0x1
953
954// *** PWRM1 ***
955#define FB_PWRM1_SUBPU 7
956#define FM_PWRM1_SUBPU 0x80
957
958#define FB_PWRM1_HPLPU 6
959#define FM_PWRM1_HPLPU 0x40
960
961#define FB_PWRM1_HPRPU 5
962#define FM_PWRM1_HPRPU 0x20
963
964#define FB_PWRM1_SPKLPU 4
965#define FM_PWRM1_SPKLPU 0x10
966
967#define FB_PWRM1_SPKRPU 3
968#define FM_PWRM1_SPKRPU 0x8
969
970#define FB_PWRM1_D2S2PU 2
971#define FM_PWRM1_D2S2PU 0x4
972
973#define FB_PWRM1_D2S1PU 1
974#define FM_PWRM1_D2S1PU 0x2
975
976#define FB_PWRM1_VREFPU 0
977#define FM_PWRM1_VREFPU 0x1
978
979// *** PWRM2 ***
980#define FB_PWRM2_I2S3OPU 5
981#define FM_PWRM2_I2S3OPU 0x20
982#define FV_I2S3OPU_PWR_DOWN 0x0
983#define FV_I2S3OPU_PWR_UP 0x20
984
985#define FB_PWRM2_I2S2OPU 4
986#define FM_PWRM2_I2S2OPU 0x10
987#define FV_I2S2OPU_PWR_DOWN 0x0
988#define FV_I2S2OPU_PWR_UP 0x10
989
990#define FB_PWRM2_I2S1OPU 3
991#define FM_PWRM2_I2S1OPU 0x8
992#define FV_I2S1OPU_PWR_DOWN 0x0
993#define FV_I2S1OPU_PWR_UP 0x8
994
995#define FB_PWRM2_I2S3IPU 2
996#define FM_PWRM2_I2S3IPU 0x4
997#define FV_I2S3IPU_PWR_DOWN 0x0
998#define FV_I2S3IPU_PWR_UP 0x4
999
1000#define FB_PWRM2_I2S2IPU 1
1001#define FM_PWRM2_I2S2IPU 0x2
1002#define FV_I2S2IPU_PWR_DOWN 0x0
1003#define FV_I2S2IPU_PWR_UP 0x2
1004
1005#define FB_PWRM2_I2S1IPU 0
1006#define FM_PWRM2_I2S1IPU 0x1
1007#define FV_I2S1IPU_PWR_DOWN 0x0
1008#define FV_I2S1IPU_PWR_UP 0x1
1009
1010#define PWRM2_I2SOPU_PWR_DOWN 0x0
1011#define PWRM2_I2SOPU_PWR_UP 0x1
1012#define PWRM2_I2SIPU_PWR_DOWN 0x0
1013#define PWRM2_I2SIPU_PWR_UP 0x1
1014
1015// *** PWRM3 ***
1016#define FB_PWRM3_BGSBUP 6
1017#define FM_PWRM3_BGSBUP 0x40
1018#define FV_BGSBUP_ON 0x0
1019#define FV_BGSBUP_OFF 0x40
1020
1021#define FB_PWRM3_VGBAPU 5
1022#define FM_PWRM3_VGBAPU 0x20
1023#define FV_VGBAPU_ON 0x0
1024#define FV_VGBAPU_OFF 0x20
1025
1026#define FB_PWRM3_LLINEPU 4
1027#define FM_PWRM3_LLINEPU 0x10
1028
1029#define FB_PWRM3_RLINEPU 3
1030#define FM_PWRM3_RLINEPU 0x8
1031
1032// *** PWRM4 ***
1033#define FB_PWRM4_OPSUBPU 4
1034#define FM_PWRM4_OPSUBPU 0x10
1035
1036#define FB_PWRM4_OPDACLPU 3
1037#define FM_PWRM4_OPDACLPU 0x8
1038
1039#define FB_PWRM4_OPDACRPU 2
1040#define FM_PWRM4_OPDACRPU 0x4
1041
1042#define FB_PWRM4_OPSPKLPU 1
1043#define FM_PWRM4_OPSPKLPU 0x2
1044
1045#define FB_PWRM4_OPSPKRPU 0
1046#define FM_PWRM4_OPSPKRPU 0x1
1047
1048// *** I2SIDCTL ***
1049#define FB_I2SIDCTL_I2SI3DCTL 4
1050#define FM_I2SIDCTL_I2SI3DCTL 0x30
1051
1052#define FB_I2SIDCTL_I2SI2DCTL 2
1053#define FM_I2SIDCTL_I2SI2DCTL 0xC
1054
1055#define FB_I2SIDCTL_I2SI1DCTL 0
1056#define FM_I2SIDCTL_I2SI1DCTL 0x3
1057
1058// *** I2SODCTL ***
1059#define FB_I2SODCTL_I2SO3DCTL 4
1060#define FM_I2SODCTL_I2SO3DCTL 0x30
1061
1062#define FB_I2SODCTL_I2SO2DCTL 2
1063#define FM_I2SODCTL_I2SO2DCTL 0xC
1064
1065#define FB_I2SODCTL_I2SO1DCTL 0
1066#define FM_I2SODCTL_I2SO1DCTL 0x3
1067
1068// *** AUDIOMUX1 ***
1069#define FB_AUDIOMUX1_ASRCIMUX 6
1070#define FM_AUDIOMUX1_ASRCIMUX 0xC0
1071#define FV_ASRCIMUX_NONE 0x0
1072#define FV_ASRCIMUX_I2S1 0x40
1073#define FV_ASRCIMUX_I2S2 0x80
1074#define FV_ASRCIMUX_I2S3 0xC0
1075
1076#define FB_AUDIOMUX1_I2S2MUX 3
1077#define FM_AUDIOMUX1_I2S2MUX 0x38
1078#define FV_I2S2MUX_I2S1 0x0
1079#define FV_I2S2MUX_I2S2 0x8
1080#define FV_I2S2MUX_I2S3 0x10
1081#define FV_I2S2MUX_ADC_DMIC 0x18
1082#define FV_I2S2MUX_DMIC2 0x20
1083#define FV_I2S2MUX_CLASSD_DSP 0x28
1084#define FV_I2S2MUX_DAC_DSP 0x30
1085#define FV_I2S2MUX_SUB_DSP 0x38
1086
1087#define FB_AUDIOMUX1_I2S1MUX 0
1088#define FM_AUDIOMUX1_I2S1MUX 0x7
1089#define FV_I2S1MUX_I2S1 0x0
1090#define FV_I2S1MUX_I2S2 0x1
1091#define FV_I2S1MUX_I2S3 0x2
1092#define FV_I2S1MUX_ADC_DMIC 0x3
1093#define FV_I2S1MUX_DMIC2 0x4
1094#define FV_I2S1MUX_CLASSD_DSP 0x5
1095#define FV_I2S1MUX_DAC_DSP 0x6
1096#define FV_I2S1MUX_SUB_DSP 0x7
1097
1098#define AUDIOMUX1_I2SMUX_I2S1 0x0
1099#define AUDIOMUX1_I2SMUX_I2S2 0x1
1100#define AUDIOMUX1_I2SMUX_I2S3 0x2
1101#define AUDIOMUX1_I2SMUX_ADC_DMIC 0x3
1102#define AUDIOMUX1_I2SMUX_DMIC2 0x4
1103#define AUDIOMUX1_I2SMUX_CLASSD_DSP 0x5
1104#define AUDIOMUX1_I2SMUX_DAC_DSP 0x6
1105#define AUDIOMUX1_I2SMUX_SUB_DSP 0x7
1106
1107// *** AUDIOMUX2 ***
1108#define FB_AUDIOMUX2_ASRCOMUX 6
1109#define FM_AUDIOMUX2_ASRCOMUX 0xC0
1110#define FV_ASRCOMUX_NONE 0x0
1111#define FV_ASRCOMUX_I2S1 0x40
1112#define FV_ASRCOMUX_I2S2 0x80
1113#define FV_ASRCOMUX_I2S3 0xC0
1114
1115#define FB_AUDIOMUX2_DACMUX 3
1116#define FM_AUDIOMUX2_DACMUX 0x38
1117#define FV_DACMUX_I2S1 0x0
1118#define FV_DACMUX_I2S2 0x8
1119#define FV_DACMUX_I2S3 0x10
1120#define FV_DACMUX_ADC_DMIC 0x18
1121#define FV_DACMUX_DMIC2 0x20
1122#define FV_DACMUX_CLASSD_DSP 0x28
1123#define FV_DACMUX_DAC_DSP 0x30
1124#define FV_DACMUX_SUB_DSP 0x38
1125
1126#define FB_AUDIOMUX2_I2S3MUX 0
1127#define FM_AUDIOMUX2_I2S3MUX 0x7
1128#define FV_I2S3MUX_I2S1 0x0
1129#define FV_I2S3MUX_I2S2 0x1
1130#define FV_I2S3MUX_I2S3 0x2
1131#define FV_I2S3MUX_ADC_DMIC 0x3
1132#define FV_I2S3MUX_DMIC2 0x4
1133#define FV_I2S3MUX_CLASSD_DSP 0x5
1134#define FV_I2S3MUX_DAC_DSP 0x6
1135#define FV_I2S3MUX_SUB_DSP 0x7
1136
1137// *** AUDIOMUX3 ***
1138#define FB_AUDIOMUX3_SUBMUX 3
1139#define FM_AUDIOMUX3_SUBMUX 0xF8
1140#define FV_SUBMUX_I2S1_L 0x0
1141#define FV_SUBMUX_I2S1_R 0x8
1142#define FV_SUBMUX_I2S1_LR 0x10
1143#define FV_SUBMUX_I2S2_L 0x18
1144#define FV_SUBMUX_I2S2_R 0x20
1145#define FV_SUBMUX_I2S2_LR 0x28
1146#define FV_SUBMUX_I2S3_L 0x30
1147#define FV_SUBMUX_I2S3_R 0x38
1148#define FV_SUBMUX_I2S3_LR 0x40
1149#define FV_SUBMUX_ADC_DMIC_L 0x48
1150#define FV_SUBMUX_ADC_DMIC_R 0x50
1151#define FV_SUBMUX_ADC_DMIC_LR 0x58
1152#define FV_SUBMUX_DMIC_L 0x60
1153#define FV_SUBMUX_DMIC_R 0x68
1154#define FV_SUBMUX_DMIC_LR 0x70
1155#define FV_SUBMUX_CLASSD_DSP_L 0x78
1156#define FV_SUBMUX_CLASSD_DSP_R 0x80
1157#define FV_SUBMUX_CLASSD_DSP_LR 0x88
1158
1159#define FB_AUDIOMUX3_CLSSDMUX 0
1160#define FM_AUDIOMUX3_CLSSDMUX 0x7
1161#define FV_CLSSDMUX_I2S1 0x0
1162#define FV_CLSSDMUX_I2S2 0x1
1163#define FV_CLSSDMUX_I2S3 0x2
1164#define FV_CLSSDMUX_ADC_DMIC 0x3
1165#define FV_CLSSDMUX_DMIC2 0x4
1166#define FV_CLSSDMUX_CLASSD_DSP 0x5
1167#define FV_CLSSDMUX_DAC_DSP 0x6
1168#define FV_CLSSDMUX_SUB_DSP 0x7
1169
1170// *** HSDCTL1 ***
1171#define FB_HSDCTL1_HPJKTYPE 7
1172#define FM_HSDCTL1_HPJKTYPE 0x80
1173
1174#define FB_HSDCTL1_CON_DET_PWD 6
1175#define FM_HSDCTL1_CON_DET_PWD 0x40
1176
1177#define FB_HSDCTL1_DETCYC 4
1178#define FM_HSDCTL1_DETCYC 0x30
1179
1180#define FB_HSDCTL1_HPDLYBYP 3
1181#define FM_HSDCTL1_HPDLYBYP 0x8
1182
1183#define FB_HSDCTL1_HSDETPOL 2
1184#define FM_HSDCTL1_HSDETPOL 0x4
1185
1186#define FB_HSDCTL1_HPID_EN 1
1187#define FM_HSDCTL1_HPID_EN 0x2
1188
1189#define FB_HSDCTL1_GBLHS_EN 0
1190#define FM_HSDCTL1_GBLHS_EN 0x1
1191
1192// *** HSDCTL2 ***
1193#define FB_HSDCTL2_FMICBIAS1 6
1194#define FM_HSDCTL2_FMICBIAS1 0xC0
1195
1196#define FB_HSDCTL2_MB1MODE 5
1197#define FM_HSDCTL2_MB1MODE 0x20
1198#define FV_MB1MODE_AUTO 0x0
1199#define FV_MB1MODE_MANUAL 0x20
1200
1201#define FB_HSDCTL2_FORCETRG 4
1202#define FM_HSDCTL2_FORCETRG 0x10
1203
1204#define FB_HSDCTL2_SWMODE 3
1205#define FM_HSDCTL2_SWMODE 0x8
1206
1207#define FB_HSDCTL2_GHSHIZ 2
1208#define FM_HSDCTL2_GHSHIZ 0x4
1209
1210#define FB_HSDCTL2_FPLUGTYPE 0
1211#define FM_HSDCTL2_FPLUGTYPE 0x3
1212
1213// *** HSDSTAT ***
1214#define FB_HSDSTAT_MBIAS1DRV 5
1215#define FM_HSDSTAT_MBIAS1DRV 0x60
1216
1217#define FB_HSDSTAT_HSDETSTAT 3
1218#define FM_HSDSTAT_HSDETSTAT 0x8
1219
1220#define FB_HSDSTAT_PLUGTYPE 1
1221#define FM_HSDSTAT_PLUGTYPE 0x6
1222
1223#define FB_HSDSTAT_HSDETDONE 0
1224#define FM_HSDSTAT_HSDETDONE 0x1
1225
1226// *** HSDDELAY ***
1227#define FB_HSDDELAY_T_STABLE 0
1228#define FM_HSDDELAY_T_STABLE 0x7
1229
1230// *** BUTCTL ***
1231#define FB_BUTCTL_BPUSHSTAT 7
1232#define FM_BUTCTL_BPUSHSTAT 0x80
1233
1234#define FB_BUTCTL_BPUSHDET 6
1235#define FM_BUTCTL_BPUSHDET 0x40
1236
1237#define FB_BUTCTL_BPUSHEN 5
1238#define FM_BUTCTL_BPUSHEN 0x20
1239
1240#define FB_BUTCTL_BSTABLE_L 3
1241#define FM_BUTCTL_BSTABLE_L 0x18
1242
1243#define FB_BUTCTL_BSTABLE_S 0
1244#define FM_BUTCTL_BSTABLE_S 0x7
1245
1246// *** CH0AIC ***
1247#define FB_CH0AIC_INSELL 6
1248#define FM_CH0AIC_INSELL 0xC0
1249
1250#define FB_CH0AIC_MICBST0 4
1251#define FM_CH0AIC_MICBST0 0x30
1252
1253#define FB_CH0AIC_LADCIN 2
1254#define FM_CH0AIC_LADCIN 0xC
1255
1256#define FB_CH0AIC_IN_BYPS_L_SEL 1
1257#define FM_CH0AIC_IN_BYPS_L_SEL 0x2
1258
1259#define FB_CH0AIC_IPCH0S 0
1260#define FM_CH0AIC_IPCH0S 0x1
1261
1262// *** CH1AIC ***
1263#define FB_CH1AIC_INSELR 6
1264#define FM_CH1AIC_INSELR 0xC0
1265
1266#define FB_CH1AIC_MICBST1 4
1267#define FM_CH1AIC_MICBST1 0x30
1268
1269#define FB_CH1AIC_RADCIN 2
1270#define FM_CH1AIC_RADCIN 0xC
1271
1272#define FB_CH1AIC_IN_BYPS_R_SEL 1
1273#define FM_CH1AIC_IN_BYPS_R_SEL 0x2
1274
1275#define FB_CH1AIC_IPCH1S 0
1276#define FM_CH1AIC_IPCH1S 0x1
1277
1278// *** ICTL0 ***
1279#define FB_ICTL0_IN1POL 7
1280#define FM_ICTL0_IN1POL 0x80
1281
1282#define FB_ICTL0_IN0POL 6
1283#define FM_ICTL0_IN0POL 0x40
1284
1285#define FB_ICTL0_INPCH10SEL 4
1286#define FM_ICTL0_INPCH10SEL 0x30
1287
1288#define FB_ICTL0_IN1MUTE 3
1289#define FM_ICTL0_IN1MUTE 0x8
1290
1291#define FB_ICTL0_IN0MUTE 2
1292#define FM_ICTL0_IN0MUTE 0x4
1293
1294#define FB_ICTL0_IN1HP 1
1295#define FM_ICTL0_IN1HP 0x2
1296
1297#define FB_ICTL0_IN0HP 0
1298#define FM_ICTL0_IN0HP 0x1
1299
1300// *** ICTL1 ***
1301#define FB_ICTL1_IN3POL 7
1302#define FM_ICTL1_IN3POL 0x80
1303
1304#define FB_ICTL1_IN2POL 6
1305#define FM_ICTL1_IN2POL 0x40
1306
1307#define FB_ICTL1_INPCH32SEL 4
1308#define FM_ICTL1_INPCH32SEL 0x30
1309
1310#define FB_ICTL1_IN3MUTE 3
1311#define FM_ICTL1_IN3MUTE 0x8
1312
1313#define FB_ICTL1_IN2MUTE 2
1314#define FM_ICTL1_IN2MUTE 0x4
1315
1316#define FB_ICTL1_IN3HP 1
1317#define FM_ICTL1_IN3HP 0x2
1318
1319#define FB_ICTL1_IN2HP 0
1320#define FM_ICTL1_IN2HP 0x1
1321
1322// *** MICBIAS ***
1323#define FB_MICBIAS_MICBOV2 4
1324#define FM_MICBIAS_MICBOV2 0x30
1325
1326#define FB_MICBIAS_MICBOV1 6
1327#define FM_MICBIAS_MICBOV1 0xC0
1328
1329#define FB_MICBIAS_SPARE1 2
1330#define FM_MICBIAS_SPARE1 0xC
1331
1332#define FB_MICBIAS_SPARE2 0
1333#define FM_MICBIAS_SPARE2 0x3
1334
1335// *** PGAZ ***
1336#define FB_PGAZ_INHPOR 1
1337#define FM_PGAZ_INHPOR 0x2
1338
1339#define FB_PGAZ_TOEN 0
1340#define FM_PGAZ_TOEN 0x1
1341
1342// *** ASRCILVOL ***
1343#define FB_ASRCILVOL_ASRCILVOL 0
1344#define FM_ASRCILVOL_ASRCILVOL 0xFF
1345
1346// *** ASRCIRVOL ***
1347#define FB_ASRCIRVOL_ASRCIRVOL 0
1348#define FM_ASRCIRVOL_ASRCIRVOL 0xFF
1349
1350// *** ASRCOLVOL ***
1351#define FB_ASRCOLVOL_ASRCOLVOL 0
1352#define FM_ASRCOLVOL_ASRCOLVOL 0xFF
1353
1354// *** ASRCORVOL ***
1355#define FB_ASRCORVOL_ASRCOLVOL 0
1356#define FM_ASRCORVOL_ASRCOLVOL 0xFF
1357
1358// *** IVOLCTLU ***
1359#define FB_IVOLCTLU_IFADE 3
1360#define FM_IVOLCTLU_IFADE 0x8
1361
1362#define FB_IVOLCTLU_INPVOLU 2
1363#define FM_IVOLCTLU_INPVOLU 0x4
1364
1365#define FB_IVOLCTLU_PGAVOLU 1
1366#define FM_IVOLCTLU_PGAVOLU 0x2
1367
1368#define FB_IVOLCTLU_ASRCVOLU 0
1369#define FM_IVOLCTLU_ASRCVOLU 0x1
1370
1371// *** ALCCTL0 ***
1372#define FB_ALCCTL0_ALCMODE 7
1373#define FM_ALCCTL0_ALCMODE 0x80
1374
1375#define FB_ALCCTL0_ALCREF 4
1376#define FM_ALCCTL0_ALCREF 0x70
1377
1378#define FB_ALCCTL0_ALCEN3 3
1379#define FM_ALCCTL0_ALCEN3 0x8
1380
1381#define FB_ALCCTL0_ALCEN2 2
1382#define FM_ALCCTL0_ALCEN2 0x4
1383
1384#define FB_ALCCTL0_ALCEN1 1
1385#define FM_ALCCTL0_ALCEN1 0x2
1386
1387#define FB_ALCCTL0_ALCEN0 0
1388#define FM_ALCCTL0_ALCEN0 0x1
1389
1390// *** ALCCTL1 ***
1391#define FB_ALCCTL1_MAXGAIN 4
1392#define FM_ALCCTL1_MAXGAIN 0x70
1393
1394#define FB_ALCCTL1_ALCL 0
1395#define FM_ALCCTL1_ALCL 0xF
1396
1397// *** ALCCTL2 ***
1398#define FB_ALCCTL2_ALCZC 7
1399#define FM_ALCCTL2_ALCZC 0x80
1400
1401#define FB_ALCCTL2_MINGAIN 4
1402#define FM_ALCCTL2_MINGAIN 0x70
1403
1404#define FB_ALCCTL2_HLD 0
1405#define FM_ALCCTL2_HLD 0xF
1406
1407// *** ALCCTL3 ***
1408#define FB_ALCCTL3_DCY 4
1409#define FM_ALCCTL3_DCY 0xF0
1410
1411#define FB_ALCCTL3_ATK 0
1412#define FM_ALCCTL3_ATK 0xF
1413
1414// *** NGATE ***
1415#define FB_NGATE_NGTH 3
1416#define FM_NGATE_NGTH 0xF8
1417
1418#define FB_NGATE_NGG 1
1419#define FM_NGATE_NGG 0x6
1420
1421#define FB_NGATE_NGAT 0
1422#define FM_NGATE_NGAT 0x1
1423
1424// *** DMICCTL ***
1425#define FB_DMICCTL_DMIC2EN 7
1426#define FM_DMICCTL_DMIC2EN 0x80
1427
1428#define FB_DMICCTL_DMIC1EN 6
1429#define FM_DMICCTL_DMIC1EN 0x40
1430
1431#define FB_DMICCTL_DMONO 4
1432#define FM_DMICCTL_DMONO 0x10
1433
1434#define FB_DMICCTL_DMDCLK 2
1435#define FM_DMICCTL_DMDCLK 0xC
1436
1437#define FB_DMICCTL_DMRATE 0
1438#define FM_DMICCTL_DMRATE 0x3
1439
1440// *** DACCTL ***
1441#define FB_DACCTL_DACPOLR 7
1442#define FM_DACCTL_DACPOLR 0x80
1443#define FV_DACPOLR_NORMAL 0x0
1444#define FV_DACPOLR_INVERTED 0x80
1445
1446#define FB_DACCTL_DACPOLL 6
1447#define FM_DACCTL_DACPOLL 0x40
1448#define FV_DACPOLL_NORMAL 0x0
1449#define FV_DACPOLL_INVERTED 0x40
1450
1451#define FB_DACCTL_DACDITH 4
1452#define FM_DACCTL_DACDITH 0x30
1453#define FV_DACDITH_DYNAMIC_HALF 0x0
1454#define FV_DACDITH_DYNAMIC_FULL 0x10
1455#define FV_DACDITH_DISABLED 0x20
1456#define FV_DACDITH_STATIC 0x30
1457
1458#define FB_DACCTL_DACMUTE 3
1459#define FM_DACCTL_DACMUTE 0x8
1460#define FV_DACMUTE_ENABLE 0x8
1461#define FV_DACMUTE_DISABLE 0x0
1462
1463#define FB_DACCTL_DACDEM 2
1464#define FM_DACCTL_DACDEM 0x4
1465#define FV_DACDEM_ENABLE 0x4
1466#define FV_DACDEM_DISABLE 0x0
1467
1468#define FB_DACCTL_ABYPASS 0
1469#define FM_DACCTL_ABYPASS 0x1
1470
1471// *** SPKCTL ***
1472#define FB_SPKCTL_SPKPOLR 7
1473#define FM_SPKCTL_SPKPOLR 0x80
1474#define FV_SPKPOLR_NORMAL 0x0
1475#define FV_SPKPOLR_INVERTED 0x80
1476
1477#define FB_SPKCTL_SPKPOLL 6
1478#define FM_SPKCTL_SPKPOLL 0x40
1479#define FV_SPKPOLL_NORMAL 0x0
1480#define FV_SPKPOLL_INVERTED 0x40
1481
1482#define FB_SPKCTL_SPKMUTE 3
1483#define FM_SPKCTL_SPKMUTE 0x8
1484#define FV_SPKMUTE_ENABLE 0x8
1485#define FV_SPKMUTE_DISABLE 0x0
1486
1487#define FB_SPKCTL_SPKDEM 2
1488#define FM_SPKCTL_SPKDEM 0x4
1489#define FV_SPKDEM_ENABLE 0x4
1490#define FV_SPKDEM_DISABLE 0x0
1491
1492// *** SUBCTL ***
1493#define FB_SUBCTL_SUBPOL 7
1494#define FM_SUBCTL_SUBPOL 0x80
1495
1496#define FB_SUBCTL_SUBMUTE 3
1497#define FM_SUBCTL_SUBMUTE 0x8
1498
1499#define FB_SUBCTL_SUBDEM 2
1500#define FM_SUBCTL_SUBDEM 0x4
1501
1502#define FB_SUBCTL_SUBMUX 1
1503#define FM_SUBCTL_SUBMUX 0x2
1504
1505#define FB_SUBCTL_SUBILMDIS 0
1506#define FM_SUBCTL_SUBILMDIS 0x1
1507
1508// *** DCCTL ***
1509#define FB_DCCTL_SUBDCBYP 7
1510#define FM_DCCTL_SUBDCBYP 0x80
1511
1512#define FB_DCCTL_DACDCBYP 6
1513#define FM_DCCTL_DACDCBYP 0x40
1514
1515#define FB_DCCTL_SPKDCBYP 5
1516#define FM_DCCTL_SPKDCBYP 0x20
1517
1518#define FB_DCCTL_DCCOEFSEL 0
1519#define FM_DCCTL_DCCOEFSEL 0x7
1520
1521// *** OVOLCTLU ***
1522#define FB_OVOLCTLU_OFADE 4
1523#define FM_OVOLCTLU_OFADE 0x10
1524
1525#define FB_OVOLCTLU_SUBVOLU 3
1526#define FM_OVOLCTLU_SUBVOLU 0x8
1527
1528#define FB_OVOLCTLU_MVOLU 2
1529#define FM_OVOLCTLU_MVOLU 0x4
1530
1531#define FB_OVOLCTLU_SPKVOLU 1
1532#define FM_OVOLCTLU_SPKVOLU 0x2
1533
1534#define FB_OVOLCTLU_HPVOLU 0
1535#define FM_OVOLCTLU_HPVOLU 0x1
1536
1537// *** MUTEC ***
1538#define FB_MUTEC_ZDSTAT 7
1539#define FM_MUTEC_ZDSTAT 0x80
1540
1541#define FB_MUTEC_ZDLEN 4
1542#define FM_MUTEC_ZDLEN 0x30
1543
1544#define FB_MUTEC_APWD 3
1545#define FM_MUTEC_APWD 0x8
1546
1547#define FB_MUTEC_AMUTE 2
1548#define FM_MUTEC_AMUTE 0x4
1549
1550// *** MVOLL ***
1551#define FB_MVOLL_MVOL_L 0
1552#define FM_MVOLL_MVOL_L 0xFF
1553
1554// *** MVOLR ***
1555#define FB_MVOLR_MVOL_R 0
1556#define FM_MVOLR_MVOL_R 0xFF
1557
1558// *** HPVOLL ***
1559#define FB_HPVOLL_HPVOL_L 0
1560#define FM_HPVOLL_HPVOL_L 0x7F
1561
1562// *** HPVOLR ***
1563#define FB_HPVOLR_HPVOL_R 0
1564#define FM_HPVOLR_HPVOL_R 0x7F
1565
1566// *** SPKVOLL ***
1567#define FB_SPKVOLL_SPKVOL_L 0
1568#define FM_SPKVOLL_SPKVOL_L 0x7F
1569
1570// *** SPKVOLR ***
1571#define FB_SPKVOLR_SPKVOL_R 0
1572#define FM_SPKVOLR_SPKVOL_R 0x7F
1573
1574// *** SUBVOL ***
1575#define FB_SUBVOL_SUBVOL 0
1576#define FM_SUBVOL_SUBVOL 0x7F
1577
1578// *** COP0 ***
1579#define FB_COP0_COPATTEN 7
1580#define FM_COP0_COPATTEN 0x80
1581
1582#define FB_COP0_COPGAIN 6
1583#define FM_COP0_COPGAIN 0x40
1584
1585#define FB_COP0_HDELTAEN 5
1586#define FM_COP0_HDELTAEN 0x20
1587
1588#define FB_COP0_COPTARGET 0
1589#define FM_COP0_COPTARGET 0x1F
1590
1591// *** COP1 ***
1592#define FB_COP1_HDCOMPMODE 6
1593#define FM_COP1_HDCOMPMODE 0x40
1594
1595#define FB_COP1_AVGLENGTH 2
1596#define FM_COP1_AVGLENGTH 0x3C
1597
1598#define FB_COP1_MONRATE 0
1599#define FM_COP1_MONRATE 0x3
1600
1601// *** COPSTAT ***
1602#define FB_COPSTAT_HDELTADET 7
1603#define FM_COPSTAT_HDELTADET 0x80
1604
1605#define FB_COPSTAT_UV 6
1606#define FM_COPSTAT_UV 0x40
1607
1608#define FB_COPSTAT_COPADJ 0
1609#define FM_COPSTAT_COPADJ 0x3F
1610
1611// *** PWM0 ***
1612#define FB_PWM0_SCTO 6
1613#define FM_PWM0_SCTO 0xC0
1614
1615#define FB_PWM0_UVLO 5
1616#define FM_PWM0_UVLO 0x20
1617
1618#define FB_PWM0_BFDIS 3
1619#define FM_PWM0_BFDIS 0x8
1620
1621#define FB_PWM0_PWMMODE 2
1622#define FM_PWM0_PWMMODE 0x4
1623
1624#define FB_PWM0_NOOFFSET 0
1625#define FM_PWM0_NOOFFSET 0x1
1626
1627// *** PWM1 ***
1628#define FB_PWM1_DITHPOS 4
1629#define FM_PWM1_DITHPOS 0x70
1630
1631#define FB_PWM1_DYNDITH 1
1632#define FM_PWM1_DYNDITH 0x2
1633
1634#define FB_PWM1_DITHDIS 0
1635#define FM_PWM1_DITHDIS 0x1
1636
1637// *** PWM2 ***
1638// *** PWM3 ***
1639#define FB_PWM3_PWMMUX 6
1640#define FM_PWM3_PWMMUX 0xC0
1641
1642#define FB_PWM3_CVALUE 0
1643#define FM_PWM3_CVALUE 0x7
1644
1645// *** HPSW ***
1646#define FB_HPSW_HPDETSTATE 4
1647#define FM_HPSW_HPDETSTATE 0x10
1648
1649#define FB_HPSW_HPSWEN 2
1650#define FM_HPSW_HPSWEN 0xC
1651
1652#define FB_HPSW_HPSWPOL 1
1653#define FM_HPSW_HPSWPOL 0x2
1654
1655#define FB_HPSW_TSDEN 0
1656#define FM_HPSW_TSDEN 0x1
1657
1658// *** THERMTS ***
1659#define FB_THERMTS_TRIPHS 7
1660#define FM_THERMTS_TRIPHS 0x80
1661
1662#define FB_THERMTS_TRIPLS 6
1663#define FM_THERMTS_TRIPLS 0x40
1664
1665#define FB_THERMTS_TRIPSPLIT 4
1666#define FM_THERMTS_TRIPSPLIT 0x30
1667
1668#define FB_THERMTS_TRIPSHIFT 2
1669#define FM_THERMTS_TRIPSHIFT 0xC
1670
1671#define FB_THERMTS_TSPOLL 0
1672#define FM_THERMTS_TSPOLL 0x3
1673
1674// *** THERMSPK1 ***
1675#define FB_THERMSPK1_FORCEPWD 7
1676#define FM_THERMSPK1_FORCEPWD 0x80
1677
1678#define FB_THERMSPK1_INSTCUTMODE 6
1679#define FM_THERMSPK1_INSTCUTMODE 0x40
1680
1681#define FB_THERMSPK1_INCRATIO 4
1682#define FM_THERMSPK1_INCRATIO 0x30
1683
1684#define FB_THERMSPK1_INCSTEP 2
1685#define FM_THERMSPK1_INCSTEP 0xC
1686
1687#define FB_THERMSPK1_DECSTEP 0
1688#define FM_THERMSPK1_DECSTEP 0x3
1689
1690// *** THERMSTAT ***
1691#define FB_THERMSTAT_FPWDS 7
1692#define FM_THERMSTAT_FPWDS 0x80
1693
1694#define FB_THERMSTAT_VOLSTAT 0
1695#define FM_THERMSTAT_VOLSTAT 0x7F
1696
1697// *** SCSTAT ***
1698#define FB_SCSTAT_ESDF 3
1699#define FM_SCSTAT_ESDF 0x18
1700
1701#define FB_SCSTAT_CPF 2
1702#define FM_SCSTAT_CPF 0x4
1703
1704#define FB_SCSTAT_CLSDF 0
1705#define FM_SCSTAT_CLSDF 0x3
1706
1707// *** SDMON ***
1708#define FB_SDMON_SDFORCE 7
1709#define FM_SDMON_SDFORCE 0x80
1710
1711#define FB_SDMON_SDVALUE 0
1712#define FM_SDMON_SDVALUE 0x1F
1713
1714// *** SPKEQFILT ***
1715#define FB_SPKEQFILT_EQ2EN 7
1716#define FM_SPKEQFILT_EQ2EN 0x80
1717#define FV_EQ2EN_ENABLE 0x80
1718#define FV_EQ2EN_DISABLE 0x0
1719
1720#define FB_SPKEQFILT_EQ2BE 4
1721#define FM_SPKEQFILT_EQ2BE 0x70
1722
1723#define FB_SPKEQFILT_EQ1EN 3
1724#define FM_SPKEQFILT_EQ1EN 0x8
1725#define FV_EQ1EN_ENABLE 0x8
1726#define FV_EQ1EN_DISABLE 0x0
1727
1728#define FB_SPKEQFILT_EQ1BE 0
1729#define FM_SPKEQFILT_EQ1BE 0x7
1730
1731#define SPKEQFILT_EQEN_ENABLE 0x1
1732#define SPKEQFILT_EQEN_DISABLE 0x0
1733
1734// *** SPKCRWDL ***
1735#define FB_SPKCRWDL_WDATA_L 0
1736#define FM_SPKCRWDL_WDATA_L 0xFF
1737
1738// *** SPKCRWDM ***
1739#define FB_SPKCRWDM_WDATA_M 0
1740#define FM_SPKCRWDM_WDATA_M 0xFF
1741
1742// *** SPKCRWDH ***
1743#define FB_SPKCRWDH_WDATA_H 0
1744#define FM_SPKCRWDH_WDATA_H 0xFF
1745
1746// *** SPKCRRDL ***
1747#define FB_SPKCRRDL_RDATA_L 0
1748#define FM_SPKCRRDL_RDATA_L 0xFF
1749
1750// *** SPKCRRDM ***
1751#define FB_SPKCRRDM_RDATA_M 0
1752#define FM_SPKCRRDM_RDATA_M 0xFF
1753
1754// *** SPKCRRDH ***
1755#define FB_SPKCRRDH_RDATA_H 0
1756#define FM_SPKCRRDH_RDATA_H 0xFF
1757
1758// *** SPKCRADD ***
1759#define FB_SPKCRADD_ADDRESS 0
1760#define FM_SPKCRADD_ADDRESS 0xFF
1761
1762// *** SPKCRS ***
1763#define FB_SPKCRS_ACCSTAT 7
1764#define FM_SPKCRS_ACCSTAT 0x80
1765
1766// *** SPKMBCEN ***
1767#define FB_SPKMBCEN_MBCEN3 2
1768#define FM_SPKMBCEN_MBCEN3 0x4
1769#define FV_MBCEN3_ENABLE 0x4
1770#define FV_MBCEN3_DISABLE 0x0
1771
1772#define FB_SPKMBCEN_MBCEN2 1
1773#define FM_SPKMBCEN_MBCEN2 0x2
1774#define FV_MBCEN2_ENABLE 0x2
1775#define FV_MBCEN2_DISABLE 0x0
1776
1777#define FB_SPKMBCEN_MBCEN1 0
1778#define FM_SPKMBCEN_MBCEN1 0x1
1779#define FV_MBCEN1_ENABLE 0x1
1780#define FV_MBCEN1_DISABLE 0x0
1781
1782#define SPKMBCEN_MBCEN_ENABLE 0x1
1783#define SPKMBCEN_MBCEN_DISABLE 0x0
1784
1785// *** SPKMBCCTL ***
1786#define FB_SPKMBCCTL_LVLMODE3 5
1787#define FM_SPKMBCCTL_LVLMODE3 0x20
1788
1789#define FB_SPKMBCCTL_WINSEL3 4
1790#define FM_SPKMBCCTL_WINSEL3 0x10
1791
1792#define FB_SPKMBCCTL_LVLMODE2 3
1793#define FM_SPKMBCCTL_LVLMODE2 0x8
1794
1795#define FB_SPKMBCCTL_WINSEL2 2
1796#define FM_SPKMBCCTL_WINSEL2 0x4
1797
1798#define FB_SPKMBCCTL_LVLMODE1 1
1799#define FM_SPKMBCCTL_LVLMODE1 0x2
1800
1801#define FB_SPKMBCCTL_WINSEL1 0
1802#define FM_SPKMBCCTL_WINSEL1 0x1
1803
1804// *** SPKCLECTL ***
1805#define FB_SPKCLECTL_LVLMODE 4
1806#define FM_SPKCLECTL_LVLMODE 0x10
1807
1808#define FB_SPKCLECTL_WINSEL 3
1809#define FM_SPKCLECTL_WINSEL 0x8
1810
1811#define FB_SPKCLECTL_EXPEN 2
1812#define FM_SPKCLECTL_EXPEN 0x4
1813#define FV_EXPEN_ENABLE 0x4
1814#define FV_EXPEN_DISABLE 0x0
1815
1816#define FB_SPKCLECTL_LIMEN 1
1817#define FM_SPKCLECTL_LIMEN 0x2
1818#define FV_LIMEN_ENABLE 0x2
1819#define FV_LIMEN_DISABLE 0x0
1820
1821#define FB_SPKCLECTL_COMPEN 0
1822#define FM_SPKCLECTL_COMPEN 0x1
1823#define FV_COMPEN_ENABLE 0x1
1824#define FV_COMPEN_DISABLE 0x0
1825
1826// *** SPKCLEMUG ***
1827#define FB_SPKCLEMUG_MUGAIN 0
1828#define FM_SPKCLEMUG_MUGAIN 0x1F
1829
1830// *** SPKCOMPTHR ***
1831#define FB_SPKCOMPTHR_THRESH 0
1832#define FM_SPKCOMPTHR_THRESH 0xFF
1833
1834// *** SPKCOMPRAT ***
1835#define FB_SPKCOMPRAT_RATIO 0
1836#define FM_SPKCOMPRAT_RATIO 0x1F
1837
1838// *** SPKCOMPATKL ***
1839#define FB_SPKCOMPATKL_TCATKL 0
1840#define FM_SPKCOMPATKL_TCATKL 0xFF
1841
1842// *** SPKCOMPATKH ***
1843#define FB_SPKCOMPATKH_TCATKH 0
1844#define FM_SPKCOMPATKH_TCATKH 0xFF
1845
1846// *** SPKCOMPRELL ***
1847#define FB_SPKCOMPRELL_TCRELL 0
1848#define FM_SPKCOMPRELL_TCRELL 0xFF
1849
1850// *** SPKCOMPRELH ***
1851#define FB_SPKCOMPRELH_TCRELH 0
1852#define FM_SPKCOMPRELH_TCRELH 0xFF
1853
1854// *** SPKLIMTHR ***
1855#define FB_SPKLIMTHR_THRESH 0
1856#define FM_SPKLIMTHR_THRESH 0xFF
1857
1858// *** SPKLIMTGT ***
1859#define FB_SPKLIMTGT_TARGET 0
1860#define FM_SPKLIMTGT_TARGET 0xFF
1861
1862// *** SPKLIMATKL ***
1863#define FB_SPKLIMATKL_TCATKL 0
1864#define FM_SPKLIMATKL_TCATKL 0xFF
1865
1866// *** SPKLIMATKH ***
1867#define FB_SPKLIMATKH_TCATKH 0
1868#define FM_SPKLIMATKH_TCATKH 0xFF
1869
1870// *** SPKLIMRELL ***
1871#define FB_SPKLIMRELL_TCRELL 0
1872#define FM_SPKLIMRELL_TCRELL 0xFF
1873
1874// *** SPKLIMRELH ***
1875#define FB_SPKLIMRELH_TCRELH 0
1876#define FM_SPKLIMRELH_TCRELH 0xFF
1877
1878// *** SPKEXPTHR ***
1879#define FB_SPKEXPTHR_THRESH 0
1880#define FM_SPKEXPTHR_THRESH 0xFF
1881
1882// *** SPKEXPRAT ***
1883#define FB_SPKEXPRAT_RATIO 0
1884#define FM_SPKEXPRAT_RATIO 0x7
1885
1886// *** SPKEXPATKL ***
1887#define FB_SPKEXPATKL_TCATKL 0
1888#define FM_SPKEXPATKL_TCATKL 0xFF
1889
1890// *** SPKEXPATKH ***
1891#define FB_SPKEXPATKH_TCATKH 0
1892#define FM_SPKEXPATKH_TCATKH 0xFF
1893
1894// *** SPKEXPRELL ***
1895#define FB_SPKEXPRELL_TCRELL 0
1896#define FM_SPKEXPRELL_TCRELL 0xFF
1897
1898// *** SPKEXPRELH ***
1899#define FB_SPKEXPRELH_TCRELH 0
1900#define FM_SPKEXPRELH_TCRELH 0xFF
1901
1902// *** SPKFXCTL ***
1903#define FB_SPKFXCTL_3DEN 4
1904#define FM_SPKFXCTL_3DEN 0x10
1905
1906#define FB_SPKFXCTL_TEEN 3
1907#define FM_SPKFXCTL_TEEN 0x8
1908
1909#define FB_SPKFXCTL_TNLFBYP 2
1910#define FM_SPKFXCTL_TNLFBYP 0x4
1911
1912#define FB_SPKFXCTL_BEEN 1
1913#define FM_SPKFXCTL_BEEN 0x2
1914
1915#define FB_SPKFXCTL_BNLFBYP 0
1916#define FM_SPKFXCTL_BNLFBYP 0x1
1917
1918// *** DACEQFILT ***
1919#define FB_DACEQFILT_EQ2EN 7
1920#define FM_DACEQFILT_EQ2EN 0x80
1921#define FV_EQ2EN_ENABLE 0x80
1922#define FV_EQ2EN_DISABLE 0x0
1923
1924#define FB_DACEQFILT_EQ2BE 4
1925#define FM_DACEQFILT_EQ2BE 0x70
1926
1927#define FB_DACEQFILT_EQ1EN 3
1928#define FM_DACEQFILT_EQ1EN 0x8
1929#define FV_EQ1EN_ENABLE 0x8
1930#define FV_EQ1EN_DISABLE 0x0
1931
1932#define FB_DACEQFILT_EQ1BE 0
1933#define FM_DACEQFILT_EQ1BE 0x7
1934
1935#define DACEQFILT_EQEN_ENABLE 0x1
1936#define DACEQFILT_EQEN_DISABLE 0x0
1937
1938// *** DACCRWDL ***
1939#define FB_DACCRWDL_WDATA_L 0
1940#define FM_DACCRWDL_WDATA_L 0xFF
1941
1942// *** DACCRWDM ***
1943#define FB_DACCRWDM_WDATA_M 0
1944#define FM_DACCRWDM_WDATA_M 0xFF
1945
1946// *** DACCRWDH ***
1947#define FB_DACCRWDH_WDATA_H 0
1948#define FM_DACCRWDH_WDATA_H 0xFF
1949
1950// *** DACCRRDL ***
1951#define FB_DACCRRDL_RDATA_L 0
1952#define FM_DACCRRDL_RDATA_L 0xFF
1953
1954// *** DACCRRDM ***
1955#define FB_DACCRRDM_RDATA_M 0
1956#define FM_DACCRRDM_RDATA_M 0xFF
1957
1958// *** DACCRRDH ***
1959#define FB_DACCRRDH_RDATA_H 0
1960#define FM_DACCRRDH_RDATA_H 0xFF
1961
1962// *** DACCRADD ***
1963#define FB_DACCRADD_ADDRESS 0
1964#define FM_DACCRADD_ADDRESS 0xFF
1965
1966// *** DACCRS ***
1967#define FB_DACCRS_ACCSTAT 7
1968#define FM_DACCRS_ACCSTAT 0x80
1969
1970// *** DACMBCEN ***
1971#define FB_DACMBCEN_MBCEN3 2
1972#define FM_DACMBCEN_MBCEN3 0x4
1973#define FV_MBCEN3_ENABLE 0x4
1974#define FV_MBCEN3_DISABLE 0x0
1975
1976#define FB_DACMBCEN_MBCEN2 1
1977#define FM_DACMBCEN_MBCEN2 0x2
1978#define FV_MBCEN2_ENABLE 0x2
1979#define FV_MBCEN2_DISABLE 0x0
1980
1981#define FB_DACMBCEN_MBCEN1 0
1982#define FM_DACMBCEN_MBCEN1 0x1
1983#define FV_MBCEN1_ENABLE 0x1
1984#define FV_MBCEN1_DISABLE 0x0
1985
1986#define DACMBCEN_MBCEN_ENABLE 0x1
1987#define DACMBCEN_MBCEN_DISABLE 0x0
1988
1989// *** DACMBCCTL ***
1990#define FB_DACMBCCTL_LVLMODE3 5
1991#define FM_DACMBCCTL_LVLMODE3 0x20
1992
1993#define FB_DACMBCCTL_WINSEL3 4
1994#define FM_DACMBCCTL_WINSEL3 0x10
1995
1996#define FB_DACMBCCTL_LVLMODE2 3
1997#define FM_DACMBCCTL_LVLMODE2 0x8
1998
1999#define FB_DACMBCCTL_WINSEL2 2
2000#define FM_DACMBCCTL_WINSEL2 0x4
2001
2002#define FB_DACMBCCTL_LVLMODE1 1
2003#define FM_DACMBCCTL_LVLMODE1 0x2
2004
2005#define FB_DACMBCCTL_WINSEL1 0
2006#define FM_DACMBCCTL_WINSEL1 0x1
2007
2008// *** DACCLECTL ***
2009#define FB_DACCLECTL_LVLMODE 4
2010#define FM_DACCLECTL_LVLMODE 0x10
2011
2012#define FB_DACCLECTL_WINSEL 3
2013#define FM_DACCLECTL_WINSEL 0x8
2014
2015#define FB_DACCLECTL_EXPEN 2
2016#define FM_DACCLECTL_EXPEN 0x4
2017#define FV_EXPEN_ENABLE 0x4
2018#define FV_EXPEN_DISABLE 0x0
2019
2020#define FB_DACCLECTL_LIMEN 1
2021#define FM_DACCLECTL_LIMEN 0x2
2022#define FV_LIMEN_ENABLE 0x2
2023#define FV_LIMEN_DISABLE 0x0
2024
2025#define FB_DACCLECTL_COMPEN 0
2026#define FM_DACCLECTL_COMPEN 0x1
2027#define FV_COMPEN_ENABLE 0x1
2028#define FV_COMPEN_DISABLE 0x0
2029
2030// *** DACCLEMUG ***
2031#define FB_DACCLEMUG_MUGAIN 0
2032#define FM_DACCLEMUG_MUGAIN 0x1F
2033
2034// *** DACCOMPTHR ***
2035#define FB_DACCOMPTHR_THRESH 0
2036#define FM_DACCOMPTHR_THRESH 0xFF
2037
2038// *** DACCOMPRAT ***
2039#define FB_DACCOMPRAT_RATIO 0
2040#define FM_DACCOMPRAT_RATIO 0x1F
2041
2042// *** DACCOMPATKL ***
2043#define FB_DACCOMPATKL_TCATKL 0
2044#define FM_DACCOMPATKL_TCATKL 0xFF
2045
2046// *** DACCOMPATKH ***
2047#define FB_DACCOMPATKH_TCATKH 0
2048#define FM_DACCOMPATKH_TCATKH 0xFF
2049
2050// *** DACCOMPRELL ***
2051#define FB_DACCOMPRELL_TCRELL 0
2052#define FM_DACCOMPRELL_TCRELL 0xFF
2053
2054// *** DACCOMPRELH ***
2055#define FB_DACCOMPRELH_TCRELH 0
2056#define FM_DACCOMPRELH_TCRELH 0xFF
2057
2058// *** DACLIMTHR ***
2059#define FB_DACLIMTHR_THRESH 0
2060#define FM_DACLIMTHR_THRESH 0xFF
2061
2062// *** DACLIMTGT ***
2063#define FB_DACLIMTGT_TARGET 0
2064#define FM_DACLIMTGT_TARGET 0xFF
2065
2066// *** DACLIMATKL ***
2067#define FB_DACLIMATKL_TCATKL 0
2068#define FM_DACLIMATKL_TCATKL 0xFF
2069
2070// *** DACLIMATKH ***
2071#define FB_DACLIMATKH_TCATKH 0
2072#define FM_DACLIMATKH_TCATKH 0xFF
2073
2074// *** DACLIMRELL ***
2075#define FB_DACLIMRELL_TCRELL 0
2076#define FM_DACLIMRELL_TCRELL 0xFF
2077
2078// *** DACLIMRELH ***
2079#define FB_DACLIMRELH_TCRELH 0
2080#define FM_DACLIMRELH_TCRELH 0xFF
2081
2082// *** DACEXPTHR ***
2083#define FB_DACEXPTHR_THRESH 0
2084#define FM_DACEXPTHR_THRESH 0xFF
2085
2086// *** DACEXPRAT ***
2087#define FB_DACEXPRAT_RATIO 0
2088#define FM_DACEXPRAT_RATIO 0x7
2089
2090// *** DACEXPATKL ***
2091#define FB_DACEXPATKL_TCATKL 0
2092#define FM_DACEXPATKL_TCATKL 0xFF
2093
2094// *** DACEXPATKH ***
2095#define FB_DACEXPATKH_TCATKH 0
2096#define FM_DACEXPATKH_TCATKH 0xFF
2097
2098// *** DACEXPRELL ***
2099#define FB_DACEXPRELL_TCRELL 0
2100#define FM_DACEXPRELL_TCRELL 0xFF
2101
2102// *** DACEXPRELH ***
2103#define FB_DACEXPRELH_TCRELH 0
2104#define FM_DACEXPRELH_TCRELH 0xFF
2105
2106// *** DACFXCTL ***
2107#define FB_DACFXCTL_3DEN 4
2108#define FM_DACFXCTL_3DEN 0x10
2109
2110#define FB_DACFXCTL_TEEN 3
2111#define FM_DACFXCTL_TEEN 0x8
2112
2113#define FB_DACFXCTL_TNLFBYP 2
2114#define FM_DACFXCTL_TNLFBYP 0x4
2115
2116#define FB_DACFXCTL_BEEN 1
2117#define FM_DACFXCTL_BEEN 0x2
2118
2119#define FB_DACFXCTL_BNLFBYP 0
2120#define FM_DACFXCTL_BNLFBYP 0x1
2121
2122// *** SUBEQFILT ***
2123#define FB_SUBEQFILT_EQ2EN 7
2124#define FM_SUBEQFILT_EQ2EN 0x80
2125#define FV_EQ2EN_ENABLE 0x80
2126#define FV_EQ2EN_DISABLE 0x0
2127
2128#define FB_SUBEQFILT_EQ2BE 4
2129#define FM_SUBEQFILT_EQ2BE 0x70
2130
2131#define FB_SUBEQFILT_EQ1EN 3
2132#define FM_SUBEQFILT_EQ1EN 0x8
2133#define FV_EQ1EN_ENABLE 0x8
2134#define FV_EQ1EN_DISABLE 0x0
2135
2136#define FB_SUBEQFILT_EQ1BE 0
2137#define FM_SUBEQFILT_EQ1BE 0x7
2138
2139#define SUBEQFILT_EQEN_ENABLE 0x1
2140#define SUBEQFILT_EQEN_DISABLE 0x0
2141
2142// *** SUBCRWDL ***
2143#define FB_SUBCRWDL_WDATA_L 0
2144#define FM_SUBCRWDL_WDATA_L 0xFF
2145
2146// *** SUBCRWDM ***
2147#define FB_SUBCRWDM_WDATA_M 0
2148#define FM_SUBCRWDM_WDATA_M 0xFF
2149
2150// *** SUBCRWDH ***
2151#define FB_SUBCRWDH_WDATA_H 0
2152#define FM_SUBCRWDH_WDATA_H 0xFF
2153
2154// *** SUBCRRDL ***
2155#define FB_SUBCRRDL_RDATA_L 0
2156#define FM_SUBCRRDL_RDATA_L 0xFF
2157
2158// *** SUBCRRDM ***
2159#define FB_SUBCRRDM_RDATA_M 0
2160#define FM_SUBCRRDM_RDATA_M 0xFF
2161
2162// *** SUBCRRDH ***
2163#define FB_SUBCRRDH_RDATA_H 0
2164#define FM_SUBCRRDH_RDATA_H 0xFF
2165
2166// *** SUBCRADD ***
2167#define FB_SUBCRADD_ADDRESS 0
2168#define FM_SUBCRADD_ADDRESS 0xFF
2169
2170// *** SUBCRS ***
2171#define FB_SUBCRS_ACCSTAT 7
2172#define FM_SUBCRS_ACCSTAT 0x80
2173
2174// *** SUBMBCEN ***
2175#define FB_SUBMBCEN_MBCEN3 2
2176#define FM_SUBMBCEN_MBCEN3 0x4
2177#define FV_MBCEN3_ENABLE 0x4
2178#define FV_MBCEN3_DISABLE 0x0
2179
2180#define FB_SUBMBCEN_MBCEN2 1
2181#define FM_SUBMBCEN_MBCEN2 0x2
2182#define FV_MBCEN2_ENABLE 0x2
2183#define FV_MBCEN2_DISABLE 0x0
2184
2185#define FB_SUBMBCEN_MBCEN1 0
2186#define FM_SUBMBCEN_MBCEN1 0x1
2187#define FV_MBCEN1_ENABLE 0x1
2188#define FV_MBCEN1_DISABLE 0x0
2189
2190#define SUBMBCEN_MBCEN_ENABLE 0x1
2191#define SUBMBCEN_MBCEN_DISABLE 0x0
2192
2193// *** SUBMBCCTL ***
2194#define FB_SUBMBCCTL_LVLMODE3 5
2195#define FM_SUBMBCCTL_LVLMODE3 0x20
2196
2197#define FB_SUBMBCCTL_WINSEL3 4
2198#define FM_SUBMBCCTL_WINSEL3 0x10
2199
2200#define FB_SUBMBCCTL_LVLMODE2 3
2201#define FM_SUBMBCCTL_LVLMODE2 0x8
2202
2203#define FB_SUBMBCCTL_WINSEL2 2
2204#define FM_SUBMBCCTL_WINSEL2 0x4
2205
2206#define FB_SUBMBCCTL_LVLMODE1 1
2207#define FM_SUBMBCCTL_LVLMODE1 0x2
2208
2209#define FB_SUBMBCCTL_WINSEL1 0
2210#define FM_SUBMBCCTL_WINSEL1 0x1
2211
2212// *** SUBCLECTL ***
2213#define FB_SUBCLECTL_LVLMODE 4
2214#define FM_SUBCLECTL_LVLMODE 0x10
2215
2216#define FB_SUBCLECTL_WINSEL 3
2217#define FM_SUBCLECTL_WINSEL 0x8
2218
2219#define FB_SUBCLECTL_EXPEN 2
2220#define FM_SUBCLECTL_EXPEN 0x4
2221#define FV_EXPEN_ENABLE 0x4
2222#define FV_EXPEN_DISABLE 0x0
2223
2224#define FB_SUBCLECTL_LIMEN 1
2225#define FM_SUBCLECTL_LIMEN 0x2
2226#define FV_LIMEN_ENABLE 0x2
2227#define FV_LIMEN_DISABLE 0x0
2228
2229#define FB_SUBCLECTL_COMPEN 0
2230#define FM_SUBCLECTL_COMPEN 0x1
2231#define FV_COMPEN_ENABLE 0x1
2232#define FV_COMPEN_DISABLE 0x0
2233
2234// *** SUBCLEMUG ***
2235#define FB_SUBCLEMUG_MUGAIN 0
2236#define FM_SUBCLEMUG_MUGAIN 0x1F
2237
2238// *** SUBCOMPTHR ***
2239#define FB_SUBCOMPTHR_THRESH 0
2240#define FM_SUBCOMPTHR_THRESH 0xFF
2241
2242// *** SUBCOMPRAT ***
2243#define FB_SUBCOMPRAT_RATIO 0
2244#define FM_SUBCOMPRAT_RATIO 0x1F
2245
2246// *** SUBCOMPATKL ***
2247#define FB_SUBCOMPATKL_TCATKL 0
2248#define FM_SUBCOMPATKL_TCATKL 0xFF
2249
2250// *** SUBCOMPATKH ***
2251#define FB_SUBCOMPATKH_TCATKH 0
2252#define FM_SUBCOMPATKH_TCATKH 0xFF
2253
2254// *** SUBCOMPRELL ***
2255#define FB_SUBCOMPRELL_TCRELL 0
2256#define FM_SUBCOMPRELL_TCRELL 0xFF
2257
2258// *** SUBCOMPRELH ***
2259#define FB_SUBCOMPRELH_TCRELH 0
2260#define FM_SUBCOMPRELH_TCRELH 0xFF
2261
2262// *** SUBLIMTHR ***
2263#define FB_SUBLIMTHR_THRESH 0
2264#define FM_SUBLIMTHR_THRESH 0xFF
2265
2266// *** SUBLIMTGT ***
2267#define FB_SUBLIMTGT_TARGET 0
2268#define FM_SUBLIMTGT_TARGET 0xFF
2269
2270// *** SUBLIMATKL ***
2271#define FB_SUBLIMATKL_TCATKL 0
2272#define FM_SUBLIMATKL_TCATKL 0xFF
2273
2274// *** SUBLIMATKH ***
2275#define FB_SUBLIMATKH_TCATKH 0
2276#define FM_SUBLIMATKH_TCATKH 0xFF
2277
2278// *** SUBLIMRELL ***
2279#define FB_SUBLIMRELL_TCRELL 0
2280#define FM_SUBLIMRELL_TCRELL 0xFF
2281
2282// *** SUBLIMRELH ***
2283#define FB_SUBLIMRELH_TCRELH 0
2284#define FM_SUBLIMRELH_TCRELH 0xFF
2285
2286// *** SUBEXPTHR ***
2287#define FB_SUBEXPTHR_THRESH 0
2288#define FM_SUBEXPTHR_THRESH 0xFF
2289
2290// *** SUBEXPRAT ***
2291#define FB_SUBEXPRAT_RATIO 0
2292#define FM_SUBEXPRAT_RATIO 0x7
2293
2294// *** SUBEXPATKL ***
2295#define FB_SUBEXPATKL_TCATKL 0
2296#define FM_SUBEXPATKL_TCATKL 0xFF
2297
2298// *** SUBEXPATKH ***
2299#define FB_SUBEXPATKH_TCATKH 0
2300#define FM_SUBEXPATKH_TCATKH 0xFF
2301
2302// *** SUBEXPRELL ***
2303#define FB_SUBEXPRELL_TCRELL 0
2304#define FM_SUBEXPRELL_TCRELL 0xFF
2305
2306// *** SUBEXPRELH ***
2307#define FB_SUBEXPRELH_TCRELH 0
2308#define FM_SUBEXPRELH_TCRELH 0xFF
2309
2310// *** SUBFXCTL ***
2311#define FB_SUBFXCTL_TEEN 3
2312#define FM_SUBFXCTL_TEEN 0x8
2313
2314#define FB_SUBFXCTL_TNLFBYP 2
2315#define FM_SUBFXCTL_TNLFBYP 0x4
2316
2317#define FB_SUBFXCTL_BEEN 1
2318#define FM_SUBFXCTL_BEEN 0x2
2319
2320#define FB_SUBFXCTL_BNLFBYP 0
2321#define FM_SUBFXCTL_BNLFBYP 0x1
2322
2323#endif /* __REDWOODPUBLIC_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 16:40:32 -0400