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authorRex Zhu <Rex.Zhu@amd.com>2017-04-28 01:49:50 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-05-05 18:12:08 -0400
commit0dca7047512cb31e7a08a677a69fa7d47959dbf8 (patch)
treebc3fffa9bc299a5c0e13d2d48e5c6682a9d5539d
parentb7a1f0e3cca40044952901e659939133e7cd1efe (diff)
drm/amd/powerplay: correct LoadLineResistance value in pptable.
this value is used by avfs to adjust inversion voltage. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c4
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
index 692f752fbb27..3f72268e99bb 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
@@ -48,8 +48,8 @@ void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
48 table->Tliquid1Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid1); 48 table->Tliquid1Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid1);
49 table->Tliquid2Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid2); 49 table->Tliquid2Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid2);
50 table->TplxLimit = cpu_to_le16(tdp_table->usTemperatureLimitPlx); 50 table->TplxLimit = cpu_to_le16(tdp_table->usTemperatureLimitPlx);
51 table->LoadLineResistance = cpu_to_le16( 51 table->LoadLineResistance =
52 hwmgr->platform_descriptor.LoadLineSlope); 52 hwmgr->platform_descriptor.LoadLineSlope * 256;
53 table->FitLimit = 0; /* Not used for Vega10 */ 53 table->FitLimit = 0; /* Not used for Vega10 */
54 54
55 table->Liquid1_I2C_address = tdp_table->ucLiquid1_I2C_address; 55 table->Liquid1_I2C_address = tdp_table->ucLiquid1_I2C_address;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
index 8b55ae01132d..00e95511e19a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
@@ -407,7 +407,7 @@ static int get_tdp_table(
407 tdp_table->ucPlx_I2C_address = power_tune_table->ucPlx_I2C_address; 407 tdp_table->ucPlx_I2C_address = power_tune_table->ucPlx_I2C_address;
408 tdp_table->ucPlx_I2C_Line = power_tune_table->ucPlx_I2C_LineSCL; 408 tdp_table->ucPlx_I2C_Line = power_tune_table->ucPlx_I2C_LineSCL;
409 tdp_table->ucPlx_I2C_LineSDA = power_tune_table->ucPlx_I2C_LineSDA; 409 tdp_table->ucPlx_I2C_LineSDA = power_tune_table->ucPlx_I2C_LineSDA;
410 hwmgr->platform_descriptor.LoadLineSlope = power_tune_table->usLoadLineResistance; 410 hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(power_tune_table->usLoadLineResistance);
411 } else { 411 } else {
412 power_tune_table_v2 = (ATOM_Vega10_PowerTune_Table_V2 *)table; 412 power_tune_table_v2 = (ATOM_Vega10_PowerTune_Table_V2 *)table;
413 tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table_v2->usSocketPowerLimit); 413 tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table_v2->usSocketPowerLimit);
@@ -453,7 +453,7 @@ static int get_tdp_table(
453 tdp_table->ucPlx_I2C_LineSDA = sda; 453 tdp_table->ucPlx_I2C_LineSDA = sda;
454 454
455 hwmgr->platform_descriptor.LoadLineSlope = 455 hwmgr->platform_descriptor.LoadLineSlope =
456 power_tune_table_v2->usLoadLineResistance; 456 le16_to_cpu(power_tune_table_v2->usLoadLineResistance);
457 } 457 }
458 458
459 *info_tdp_table = tdp_table; 459 *info_tdp_table = tdp_table;