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authorTomeu Vizoso <tomeu.vizoso@collabora.com>2016-08-24 10:54:41 -0400
committerArchit Taneja <architt@codeaurora.org>2016-09-24 02:26:34 -0400
commit0d97ad03f4220ca84f700c5fea988859ea0c3b98 (patch)
treed33cf767ec33fc67853d828bd9fb0d1bbe781d38
parentf67ed574946a7385c8034652c9e79abf00beadeb (diff)
drm/bridge: analogix_dp: Remove duplicated code
Remove code for reading the EDID and DPCD fields and use the helpers instead. Besides the obvious code reduction, other helpers are being added to the core that could be used in this driver and will be good to be able to use them instead of duplicating them. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Cc: Javier Martinez Canillas <javier@osg.samsung.com> Cc: Mika Kahola <mika.kahola@intel.com> Cc: Yakir Yang <ykk@rock-chips.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Archit Taneja <architt@codeaurora.org>
Diffstat
-rw-r--r--drivers/gpu/drm/bridge/analogix/analogix_dp_core.c274
-rw-r--r--drivers/gpu/drm/bridge/analogix/analogix_dp_core.h40
-rw-r--r--drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c451
3 files changed, 210 insertions, 555 deletions
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index efac8aba6776..774cc7963e10 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -31,6 +31,7 @@
31#include <drm/bridge/analogix_dp.h> 31#include <drm/bridge/analogix_dp.h>
32 32
33#include "analogix_dp_core.h" 33#include "analogix_dp_core.h"
34#include "analogix_dp_reg.h"
34 35
35#define to_dp(nm) container_of(nm, struct analogix_dp_device, nm) 36#define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
36 37
@@ -147,7 +148,7 @@ static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
147{ 148{
148 unsigned char psr_version; 149 unsigned char psr_version;
149 150
150 analogix_dp_read_byte_from_dpcd(dp, DP_PSR_SUPPORT, &psr_version); 151 drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
151 dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version); 152 dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
152 153
153 return (psr_version & DP_PSR_IS_SUPPORTED) ? true : false; 154 return (psr_version & DP_PSR_IS_SUPPORTED) ? true : false;
@@ -158,166 +159,37 @@ static void analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
158 unsigned char psr_en; 159 unsigned char psr_en;
159 160
160 /* Disable psr function */ 161 /* Disable psr function */
161 analogix_dp_read_byte_from_dpcd(dp, DP_PSR_EN_CFG, &psr_en); 162 drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
162 psr_en &= ~DP_PSR_ENABLE; 163 psr_en &= ~DP_PSR_ENABLE;
163 analogix_dp_write_byte_to_dpcd(dp, DP_PSR_EN_CFG, psr_en); 164 drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
164 165
165 /* Main-Link transmitter remains active during PSR active states */ 166 /* Main-Link transmitter remains active during PSR active states */
166 psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION; 167 psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION;
167 analogix_dp_write_byte_to_dpcd(dp, DP_PSR_EN_CFG, psr_en); 168 drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
168 169
169 /* Enable psr function */ 170 /* Enable psr function */
170 psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE | 171 psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE |
171 DP_PSR_CRC_VERIFICATION; 172 DP_PSR_CRC_VERIFICATION;
172 analogix_dp_write_byte_to_dpcd(dp, DP_PSR_EN_CFG, psr_en); 173 drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
173 174
174 analogix_dp_enable_psr_crc(dp); 175 analogix_dp_enable_psr_crc(dp);
175} 176}
176 177
177static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
178{
179 int i;
180 unsigned char sum = 0;
181
182 for (i = 0; i < EDID_BLOCK_LENGTH; i++)
183 sum = sum + edid_data[i];
184
185 return sum;
186}
187
188static int analogix_dp_read_edid(struct analogix_dp_device *dp)
189{
190 unsigned char *edid = dp->edid;
191 unsigned int extend_block = 0;
192 unsigned char sum;
193 unsigned char test_vector;
194 int retval;
195
196 /*
197 * EDID device address is 0x50.
198 * However, if necessary, you must have set upper address
199 * into E-EDID in I2C device, 0x30.
200 */
201
202 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
203 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
204 EDID_EXTENSION_FLAG,
205 &extend_block);
206 if (retval)
207 return retval;
208
209 if (extend_block > 0) {
210 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
211
212 /* Read EDID data */
213 retval = analogix_dp_read_bytes_from_i2c(dp,
214 I2C_EDID_DEVICE_ADDR,
215 EDID_HEADER_PATTERN,
216 EDID_BLOCK_LENGTH,
217 &edid[EDID_HEADER_PATTERN]);
218 if (retval != 0) {
219 dev_err(dp->dev, "EDID Read failed!\n");
220 return -EIO;
221 }
222 sum = analogix_dp_calc_edid_check_sum(edid);
223 if (sum != 0) {
224 dev_err(dp->dev, "EDID bad checksum!\n");
225 return -EIO;
226 }
227
228 /* Read additional EDID data */
229 retval = analogix_dp_read_bytes_from_i2c(dp,
230 I2C_EDID_DEVICE_ADDR,
231 EDID_BLOCK_LENGTH,
232 EDID_BLOCK_LENGTH,
233 &edid[EDID_BLOCK_LENGTH]);
234 if (retval != 0) {
235 dev_err(dp->dev, "EDID Read failed!\n");
236 return -EIO;
237 }
238 sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
239 if (sum != 0) {
240 dev_err(dp->dev, "EDID bad checksum!\n");
241 return -EIO;
242 }
243
244 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
245 &test_vector);
246 if (test_vector & DP_TEST_LINK_EDID_READ) {
247 analogix_dp_write_byte_to_dpcd(dp,
248 DP_TEST_EDID_CHECKSUM,
249 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
250 analogix_dp_write_byte_to_dpcd(dp,
251 DP_TEST_RESPONSE,
252 DP_TEST_EDID_CHECKSUM_WRITE);
253 }
254 } else {
255 dev_info(dp->dev, "EDID data does not include any extensions.\n");
256
257 /* Read EDID data */
258 retval = analogix_dp_read_bytes_from_i2c(dp,
259 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
260 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
261 if (retval != 0) {
262 dev_err(dp->dev, "EDID Read failed!\n");
263 return -EIO;
264 }
265 sum = analogix_dp_calc_edid_check_sum(edid);
266 if (sum != 0) {
267 dev_err(dp->dev, "EDID bad checksum!\n");
268 return -EIO;
269 }
270
271 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
272 &test_vector);
273 if (test_vector & DP_TEST_LINK_EDID_READ) {
274 analogix_dp_write_byte_to_dpcd(dp,
275 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
276 analogix_dp_write_byte_to_dpcd(dp,
277 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE);
278 }
279 }
280
281 dev_dbg(dp->dev, "EDID Read success!\n");
282 return 0;
283}
284
285static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
286{
287 u8 buf[12];
288 int i;
289 int retval;
290
291 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
292 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
293 if (retval)
294 return retval;
295
296 /* Read EDID */
297 for (i = 0; i < 3; i++) {
298 retval = analogix_dp_read_edid(dp);
299 if (!retval)
300 break;
301 }
302
303 return retval;
304}
305
306static void 178static void
307analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 179analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
308 bool enable) 180 bool enable)
309{ 181{
310 u8 data; 182 u8 data;
311 183
312 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); 184 drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
313 185
314 if (enable) 186 if (enable)
315 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 187 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
316 DP_LANE_COUNT_ENHANCED_FRAME_EN | 188 DP_LANE_COUNT_ENHANCED_FRAME_EN |
317 DPCD_LANE_COUNT_SET(data)); 189 DPCD_LANE_COUNT_SET(data));
318 else 190 else
319 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 191 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
320 DPCD_LANE_COUNT_SET(data)); 192 DPCD_LANE_COUNT_SET(data));
321} 193}
322 194
323static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 195static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
@@ -325,7 +197,7 @@ static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
325 u8 data; 197 u8 data;
326 int retval; 198 int retval;
327 199
328 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 200 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
329 retval = DPCD_ENHANCED_FRAME_CAP(data); 201 retval = DPCD_ENHANCED_FRAME_CAP(data);
330 202
331 return retval; 203 return retval;
@@ -344,8 +216,8 @@ static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
344{ 216{
345 analogix_dp_set_training_pattern(dp, DP_NONE); 217 analogix_dp_set_training_pattern(dp, DP_NONE);
346 218
347 analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, 219 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
348 DP_TRAINING_PATTERN_DISABLE); 220 DP_TRAINING_PATTERN_DISABLE);
349} 221}
350 222
351static void 223static void
@@ -390,8 +262,8 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
390 /* Setup RX configuration */ 262 /* Setup RX configuration */
391 buf[0] = dp->link_train.link_rate; 263 buf[0] = dp->link_train.link_rate;
392 buf[1] = dp->link_train.lane_count; 264 buf[1] = dp->link_train.lane_count;
393 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); 265 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
394 if (retval) 266 if (retval < 0)
395 return retval; 267 return retval;
396 268
397 /* Set TX pre-emphasis to minimum */ 269 /* Set TX pre-emphasis to minimum */
@@ -415,20 +287,22 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
415 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 287 analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
416 288
417 /* Set RX training pattern */ 289 /* Set RX training pattern */
418 retval = analogix_dp_write_byte_to_dpcd(dp, 290 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
419 DP_TRAINING_PATTERN_SET, 291 DP_LINK_SCRAMBLING_DISABLE |
420 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 292 DP_TRAINING_PATTERN_1);
421 if (retval) 293 if (retval < 0)
422 return retval; 294 return retval;
423 295
424 for (lane = 0; lane < lane_count; lane++) 296 for (lane = 0; lane < lane_count; lane++)
425 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 297 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
426 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 298 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
427 299
428 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 300 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
429 lane_count, buf); 301 lane_count);
302 if (retval < 0)
303 return retval;
430 304
431 return retval; 305 return 0;
432} 306}
433 307
434static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 308static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
@@ -580,25 +454,23 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
580 454
581 lane_count = dp->link_train.lane_count; 455 lane_count = dp->link_train.lane_count;
582 456
583 retval = analogix_dp_read_bytes_from_dpcd(dp, 457 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
584 DP_LANE0_1_STATUS, 2, link_status); 458 if (retval < 0)
585 if (retval)
586 return retval; 459 return retval;
587 460
588 retval = analogix_dp_read_bytes_from_dpcd(dp, 461 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
589 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 462 adjust_request, 2);
590 if (retval) 463 if (retval < 0)
591 return retval; 464 return retval;
592 465
593 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 466 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
594 /* set training pattern 2 for EQ */ 467 /* set training pattern 2 for EQ */
595 analogix_dp_set_training_pattern(dp, TRAINING_PTN2); 468 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
596 469
597 retval = analogix_dp_write_byte_to_dpcd(dp, 470 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
598 DP_TRAINING_PATTERN_SET, 471 DP_LINK_SCRAMBLING_DISABLE |
599 DP_LINK_SCRAMBLING_DISABLE | 472 DP_TRAINING_PATTERN_2);
600 DP_TRAINING_PATTERN_2); 473 if (retval < 0)
601 if (retval)
602 return retval; 474 return retval;
603 475
604 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 476 dev_info(dp->dev, "Link Training Clock Recovery success\n");
@@ -636,13 +508,12 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
636 analogix_dp_set_lane_link_training(dp, 508 analogix_dp_set_lane_link_training(dp,
637 dp->link_train.training_lane[lane], lane); 509 dp->link_train.training_lane[lane], lane);
638 510
639 retval = analogix_dp_write_bytes_to_dpcd(dp, 511 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
640 DP_TRAINING_LANE0_SET, lane_count, 512 dp->link_train.training_lane, lane_count);
641 dp->link_train.training_lane); 513 if (retval < 0)
642 if (retval)
643 return retval; 514 return retval;
644 515
645 return retval; 516 return 0;
646} 517}
647 518
648static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 519static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
@@ -655,9 +526,8 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
655 526
656 lane_count = dp->link_train.lane_count; 527 lane_count = dp->link_train.lane_count;
657 528
658 retval = analogix_dp_read_bytes_from_dpcd(dp, 529 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
659 DP_LANE0_1_STATUS, 2, link_status); 530 if (retval < 0)
660 if (retval)
661 return retval; 531 return retval;
662 532
663 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 533 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
@@ -665,14 +535,14 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
665 return -EIO; 535 return -EIO;
666 } 536 }
667 537
668 retval = analogix_dp_read_bytes_from_dpcd(dp, 538 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
669 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 539 adjust_request, 2);
670 if (retval) 540 if (retval < 0)
671 return retval; 541 return retval;
672 542
673 retval = analogix_dp_read_byte_from_dpcd(dp, 543 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
674 DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 544 &link_align);
675 if (retval) 545 if (retval < 0)
676 return retval; 546 return retval;
677 547
678 analogix_dp_get_adjust_training_lane(dp, adjust_request); 548 analogix_dp_get_adjust_training_lane(dp, adjust_request);
@@ -713,10 +583,12 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
713 analogix_dp_set_lane_link_training(dp, 583 analogix_dp_set_lane_link_training(dp,
714 dp->link_train.training_lane[lane], lane); 584 dp->link_train.training_lane[lane], lane);
715 585
716 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 586 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
717 lane_count, dp->link_train.training_lane); 587 dp->link_train.training_lane, lane_count);
588 if (retval < 0)
589 return retval;
718 590
719 return retval; 591 return 0;
720} 592}
721 593
722static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 594static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
@@ -730,7 +602,7 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
730 * For DP rev.1.2, Maximum link rate of Main Link lanes 602 * For DP rev.1.2, Maximum link rate of Main Link lanes
731 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 603 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
732 */ 604 */
733 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); 605 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
734 *bandwidth = data; 606 *bandwidth = data;
735} 607}
736 608
@@ -743,7 +615,7 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
743 * For DP rev.1.1, Maximum number of Main Link lanes 615 * For DP rev.1.1, Maximum number of Main Link lanes
744 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 616 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
745 */ 617 */
746 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 618 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
747 *lane_count = DPCD_MAX_LANE_COUNT(data); 619 *lane_count = DPCD_MAX_LANE_COUNT(data);
748} 620}
749 621
@@ -912,19 +784,15 @@ static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
912 if (enable) { 784 if (enable) {
913 analogix_dp_enable_scrambling(dp); 785 analogix_dp_enable_scrambling(dp);
914 786
915 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 787 drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data);
916 &data); 788 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
917 analogix_dp_write_byte_to_dpcd(dp, 789 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
918 DP_TRAINING_PATTERN_SET,
919 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
920 } else { 790 } else {
921 analogix_dp_disable_scrambling(dp); 791 analogix_dp_disable_scrambling(dp);
922 792
923 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 793 drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data);
924 &data); 794 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
925 analogix_dp_write_byte_to_dpcd(dp, 795 (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
926 DP_TRAINING_PATTERN_SET,
927 (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
928 } 796 }
929} 797}
930 798
@@ -1053,7 +921,7 @@ out:
1053int analogix_dp_get_modes(struct drm_connector *connector) 921int analogix_dp_get_modes(struct drm_connector *connector)
1054{ 922{
1055 struct analogix_dp_device *dp = to_dp(connector); 923 struct analogix_dp_device *dp = to_dp(connector);
1056 struct edid *edid = (struct edid *)dp->edid; 924 struct edid *edid;
1057 int ret, num_modes = 0; 925 int ret, num_modes = 0;
1058 926
1059 ret = analogix_dp_prepare_panel(dp, true, false); 927 ret = analogix_dp_prepare_panel(dp, true, false);
@@ -1062,9 +930,11 @@ int analogix_dp_get_modes(struct drm_connector *connector)
1062 return 0; 930 return 0;
1063 } 931 }
1064 932
1065 if (analogix_dp_handle_edid(dp) == 0) { 933 edid = drm_get_edid(connector, &dp->aux.ddc);
934 if (edid) {
1066 drm_mode_connector_update_edid_property(&dp->connector, edid); 935 drm_mode_connector_update_edid_property(&dp->connector, edid);
1067 num_modes += drm_add_edid_modes(&dp->connector, edid); 936 num_modes += drm_add_edid_modes(&dp->connector, edid);
937 kfree(edid);
1068 } 938 }
1069 939
1070 if (dp->plat_data->panel) 940 if (dp->plat_data->panel)
@@ -1395,6 +1265,14 @@ static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1395 return 0; 1265 return 0;
1396} 1266}
1397 1267
1268static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux,
1269 struct drm_dp_aux_msg *msg)
1270{
1271 struct analogix_dp_device *dp = to_dp(aux);
1272
1273 return analogix_dp_transfer(dp, msg);
1274}
1275
1398int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev, 1276int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
1399 struct analogix_dp_plat_data *plat_data) 1277 struct analogix_dp_plat_data *plat_data)
1400{ 1278{
@@ -1515,6 +1393,14 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
1515 dp->drm_dev = drm_dev; 1393 dp->drm_dev = drm_dev;
1516 dp->encoder = dp->plat_data->encoder; 1394 dp->encoder = dp->plat_data->encoder;
1517 1395
1396 dp->aux.name = "DP-AUX";
1397 dp->aux.transfer = analogix_dpaux_transfer;
1398 dp->aux.dev = &pdev->dev;
1399
1400 ret = drm_dp_aux_register(&dp->aux);
1401 if (ret)
1402 goto err_disable_pm_runtime;
1403
1518 ret = analogix_dp_create_bridge(drm_dev, dp); 1404 ret = analogix_dp_create_bridge(drm_dev, dp);
1519 if (ret) { 1405 if (ret) {
1520 DRM_ERROR("failed to create bridge (%d)\n", ret); 1406 DRM_ERROR("failed to create bridge (%d)\n", ret);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 473b9802b2d6..5c6a28806129 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,15 +20,6 @@
20#define MAX_CR_LOOP 5 20#define MAX_CR_LOOP 5
21#define MAX_EQ_LOOP 5 21#define MAX_EQ_LOOP 5
22 22
23/* I2C EDID Chip ID, Slave Address */
24#define I2C_EDID_DEVICE_ADDR 0x50
25#define I2C_E_EDID_DEVICE_ADDR 0x30
26
27#define EDID_BLOCK_LENGTH 0x80
28#define EDID_HEADER_PATTERN 0x00
29#define EDID_EXTENSION_FLAG 0x7e
30#define EDID_CHECKSUM 0x7f
31
32/* DP_MAX_LANE_COUNT */ 23/* DP_MAX_LANE_COUNT */
33#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) 24#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
34#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) 25#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
@@ -166,6 +157,7 @@ struct analogix_dp_device {
166 struct drm_device *drm_dev; 157 struct drm_device *drm_dev;
167 struct drm_connector connector; 158 struct drm_connector connector;
168 struct drm_bridge *bridge; 159 struct drm_bridge *bridge;
160 struct drm_dp_aux aux;
169 struct clk *clock; 161 struct clk *clock;
170 unsigned int irq; 162 unsigned int irq;
171 void __iomem *reg_base; 163 void __iomem *reg_base;
@@ -176,7 +168,6 @@ struct analogix_dp_device {
176 int dpms_mode; 168 int dpms_mode;
177 int hpd_gpio; 169 int hpd_gpio;
178 bool force_hpd; 170 bool force_hpd;
179 unsigned char edid[EDID_BLOCK_LENGTH * 2];
180 bool psr_support; 171 bool psr_support;
181 172
182 struct mutex panel_lock; 173 struct mutex panel_lock;
@@ -210,33 +201,6 @@ void analogix_dp_reset_aux(struct analogix_dp_device *dp);
210void analogix_dp_init_aux(struct analogix_dp_device *dp); 201void analogix_dp_init_aux(struct analogix_dp_device *dp);
211int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp); 202int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
212void analogix_dp_enable_sw_function(struct analogix_dp_device *dp); 203void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
213int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
214int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
215 unsigned int reg_addr,
216 unsigned char data);
217int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
218 unsigned int reg_addr,
219 unsigned char *data);
220int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
221 unsigned int reg_addr,
222 unsigned int count,
223 unsigned char data[]);
224int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
225 unsigned int reg_addr,
226 unsigned int count,
227 unsigned char data[]);
228int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
229 unsigned int device_addr,
230 unsigned int reg_addr);
231int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
232 unsigned int device_addr,
233 unsigned int reg_addr,
234 unsigned int *data);
235int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
236 unsigned int device_addr,
237 unsigned int reg_addr,
238 unsigned int count,
239 unsigned char edid[]);
240void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype); 204void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
241void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype); 205void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
242void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count); 206void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
@@ -285,5 +249,7 @@ void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
285void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp); 249void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp);
286void analogix_dp_send_psr_spd(struct analogix_dp_device *dp, 250void analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
287 struct edp_vsc_psr *vsc); 251 struct edp_vsc_psr *vsc);
252ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
253 struct drm_dp_aux_msg *msg);
288 254
289#endif /* _ANALOGIX_DP_CORE_H */ 255#endif /* _ANALOGIX_DP_CORE_H */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index fae0293d509a..cd37ac058675 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -585,330 +585,6 @@ int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
585 return retval; 585 return retval;
586} 586}
587 587
588int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
589 unsigned int reg_addr,
590 unsigned char *data)
591{
592 u32 reg;
593 int i;
594 int retval;
595
596 for (i = 0; i < 3; i++) {
597 /* Clear AUX CH data buffer */
598 reg = BUF_CLR;
599 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
600
601 /* Select DPCD device address */
602 reg = AUX_ADDR_7_0(reg_addr);
603 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
604 reg = AUX_ADDR_15_8(reg_addr);
605 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
606 reg = AUX_ADDR_19_16(reg_addr);
607 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
608
609 /*
610 * Set DisplayPort transaction and read 1 byte
611 * If bit 3 is 1, DisplayPort transaction.
612 * If Bit 3 is 0, I2C transaction.
613 */
614 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
615 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
616
617 /* Start AUX transaction */
618 retval = analogix_dp_start_aux_transaction(dp);
619 if (retval == 0)
620 break;
621
622 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
623 }
624
625 /* Read data buffer */
626 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
627 *data = (unsigned char)(reg & 0xff);
628
629 return retval;
630}
631
632int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
633 unsigned int reg_addr,
634 unsigned int count,
635 unsigned char data[])
636{
637 u32 reg;
638 unsigned int start_offset;
639 unsigned int cur_data_count;
640 unsigned int cur_data_idx;
641 int i;
642 int retval = 0;
643
644 /* Clear AUX CH data buffer */
645 reg = BUF_CLR;
646 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
647
648 start_offset = 0;
649 while (start_offset < count) {
650 /* Buffer size of AUX CH is 16 * 4bytes */
651 if ((count - start_offset) > 16)
652 cur_data_count = 16;
653 else
654 cur_data_count = count - start_offset;
655
656 for (i = 0; i < 3; i++) {
657 /* Select DPCD device address */
658 reg = AUX_ADDR_7_0(reg_addr + start_offset);
659 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
660 reg = AUX_ADDR_15_8(reg_addr + start_offset);
661 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
662 reg = AUX_ADDR_19_16(reg_addr + start_offset);
663 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
664
665 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
666 cur_data_idx++) {
667 reg = data[start_offset + cur_data_idx];
668 writel(reg, dp->reg_base +
669 ANALOGIX_DP_BUF_DATA_0 +
670 4 * cur_data_idx);
671 }
672
673 /*
674 * Set DisplayPort transaction and write
675 * If bit 3 is 1, DisplayPort transaction.
676 * If Bit 3 is 0, I2C transaction.
677 */
678 reg = AUX_LENGTH(cur_data_count) |
679 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
680 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
681
682 /* Start AUX transaction */
683 retval = analogix_dp_start_aux_transaction(dp);
684 if (retval == 0)
685 break;
686
687 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
688 __func__);
689 }
690
691 start_offset += cur_data_count;
692 }
693
694 return retval;
695}
696
697int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
698 unsigned int reg_addr,
699 unsigned int count,
700 unsigned char data[])
701{
702 u32 reg;
703 unsigned int start_offset;
704 unsigned int cur_data_count;
705 unsigned int cur_data_idx;
706 int i;
707 int retval = 0;
708
709 /* Clear AUX CH data buffer */
710 reg = BUF_CLR;
711 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
712
713 start_offset = 0;
714 while (start_offset < count) {
715 /* Buffer size of AUX CH is 16 * 4bytes */
716 if ((count - start_offset) > 16)
717 cur_data_count = 16;
718 else
719 cur_data_count = count - start_offset;
720
721 /* AUX CH Request Transaction process */
722 for (i = 0; i < 3; i++) {
723 /* Select DPCD device address */
724 reg = AUX_ADDR_7_0(reg_addr + start_offset);
725 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
726 reg = AUX_ADDR_15_8(reg_addr + start_offset);
727 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
728 reg = AUX_ADDR_19_16(reg_addr + start_offset);
729 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
730
731 /*
732 * Set DisplayPort transaction and read
733 * If bit 3 is 1, DisplayPort transaction.
734 * If Bit 3 is 0, I2C transaction.
735 */
736 reg = AUX_LENGTH(cur_data_count) |
737 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
738 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
739
740 /* Start AUX transaction */
741 retval = analogix_dp_start_aux_transaction(dp);
742 if (retval == 0)
743 break;
744
745 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
746 __func__);
747 }
748
749 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
750 cur_data_idx++) {
751 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
752 + 4 * cur_data_idx);
753 data[start_offset + cur_data_idx] =
754 (unsigned char)reg;
755 }
756
757 start_offset += cur_data_count;
758 }
759
760 return retval;
761}
762
763int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
764 unsigned int device_addr,
765 unsigned int reg_addr)
766{
767 u32 reg;
768 int retval;
769
770 /* Set EDID device address */
771 reg = device_addr;
772 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
773 writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
774 writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
775
776 /* Set offset from base address of EDID device */
777 writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
778
779 /*
780 * Set I2C transaction and write address
781 * If bit 3 is 1, DisplayPort transaction.
782 * If Bit 3 is 0, I2C transaction.
783 */
784 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
785 AUX_TX_COMM_WRITE;
786 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
787
788 /* Start AUX transaction */
789 retval = analogix_dp_start_aux_transaction(dp);
790 if (retval != 0)
791 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
792
793 return retval;
794}
795
796int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
797 unsigned int device_addr,
798 unsigned int reg_addr,
799 unsigned int *data)
800{
801 u32 reg;
802 int i;
803 int retval;
804
805 for (i = 0; i < 3; i++) {
806 /* Clear AUX CH data buffer */
807 reg = BUF_CLR;
808 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
809
810 /* Select EDID device */
811 retval = analogix_dp_select_i2c_device(dp, device_addr,
812 reg_addr);
813 if (retval != 0)
814 continue;
815
816 /*
817 * Set I2C transaction and read data
818 * If bit 3 is 1, DisplayPort transaction.
819 * If Bit 3 is 0, I2C transaction.
820 */
821 reg = AUX_TX_COMM_I2C_TRANSACTION |
822 AUX_TX_COMM_READ;
823 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
824
825 /* Start AUX transaction */
826 retval = analogix_dp_start_aux_transaction(dp);
827 if (retval == 0)
828 break;
829
830 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
831 }
832
833 /* Read data */
834 if (retval == 0)
835 *data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
836
837 return retval;
838}
839
840int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
841 unsigned int device_addr,
842 unsigned int reg_addr,
843 unsigned int count,
844 unsigned char edid[])
845{
846 u32 reg;
847 unsigned int i, j;
848 unsigned int cur_data_idx;
849 unsigned int defer = 0;
850 int retval = 0;
851
852 for (i = 0; i < count; i += 16) {
853 for (j = 0; j < 3; j++) {
854 /* Clear AUX CH data buffer */
855 reg = BUF_CLR;
856 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
857
858 /* Set normal AUX CH command */
859 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
860 reg &= ~ADDR_ONLY;
861 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
862
863 /*
864 * If Rx sends defer, Tx sends only reads
865 * request without sending address
866 */
867 if (!defer)
868 retval = analogix_dp_select_i2c_device(dp,
869 device_addr, reg_addr + i);
870 else
871 defer = 0;
872
873 if (retval == 0) {
874 /*
875 * Set I2C transaction and write data
876 * If bit 3 is 1, DisplayPort transaction.
877 * If Bit 3 is 0, I2C transaction.
878 */
879 reg = AUX_LENGTH(16) |
880 AUX_TX_COMM_I2C_TRANSACTION |
881 AUX_TX_COMM_READ;
882 writel(reg, dp->reg_base +
883 ANALOGIX_DP_AUX_CH_CTL_1);
884
885 /* Start AUX transaction */
886 retval = analogix_dp_start_aux_transaction(dp);
887 if (retval == 0)
888 break;
889
890 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
891 __func__);
892 }
893 /* Check if Rx sends defer */
894 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
895 if (reg == AUX_RX_COMM_AUX_DEFER ||
896 reg == AUX_RX_COMM_I2C_DEFER) {
897 dev_err(dp->dev, "Defer: %d\n\n", reg);
898 defer = 1;
899 }
900 }
901
902 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
903 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
904 + 4 * cur_data_idx);
905 edid[i + cur_data_idx] = (unsigned char)reg;
906 }
907 }
908
909 return retval;
910}
911
912void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) 588void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
913{ 589{
914 u32 reg; 590 u32 reg;
@@ -1361,3 +1037,130 @@ void analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
1361 val |= IF_EN; 1037 val |= IF_EN;
1362 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 1038 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1363} 1039}
1040
1041ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
1042 struct drm_dp_aux_msg *msg)
1043{
1044 u32 reg;
1045 u8 *buffer = msg->buffer;
1046 int timeout_loop = 0;
1047 unsigned int i;
1048 int num_transferred = 0;
1049
1050 /* Buffer size of AUX CH is 16 bytes */
1051 if (WARN_ON(msg->size > 16))
1052 return -E2BIG;
1053
1054 /* Clear AUX CH data buffer */
1055 reg = BUF_CLR;
1056 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
1057
1058 switch (msg->request & ~DP_AUX_I2C_MOT) {
1059 case DP_AUX_I2C_WRITE:
1060 reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_I2C_TRANSACTION;
1061 if (msg->request & DP_AUX_I2C_MOT)
1062 reg |= AUX_TX_COMM_MOT;
1063 break;
1064
1065 case DP_AUX_I2C_READ:
1066 reg = AUX_TX_COMM_READ | AUX_TX_COMM_I2C_TRANSACTION;
1067 if (msg->request & DP_AUX_I2C_MOT)
1068 reg |= AUX_TX_COMM_MOT;
1069 break;
1070
1071 case DP_AUX_NATIVE_WRITE:
1072 reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_DP_TRANSACTION;
1073 break;
1074
1075 case DP_AUX_NATIVE_READ:
1076 reg = AUX_TX_COMM_READ | AUX_TX_COMM_DP_TRANSACTION;
1077 break;
1078
1079 default:
1080 return -EINVAL;
1081 }
1082
1083 reg |= AUX_LENGTH(msg->size);
1084 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
1085
1086 /* Select DPCD device address */
1087 reg = AUX_ADDR_7_0(msg->address);
1088 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
1089 reg = AUX_ADDR_15_8(msg->address);
1090 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
1091 reg = AUX_ADDR_19_16(msg->address);
1092 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
1093
1094 if (!(msg->request & DP_AUX_I2C_READ)) {
1095 for (i = 0; i < msg->size; i++) {
1096 reg = buffer[i];
1097 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0 +
1098 4 * i);
1099 num_transferred++;
1100 }
1101 }
1102
1103 /* Enable AUX CH operation */
1104 reg = AUX_EN;
1105
1106 /* Zero-sized messages specify address-only transactions. */
1107 if (msg->size < 1)
1108 reg |= ADDR_ONLY;
1109
1110 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
1111
1112 /* Is AUX CH command reply received? */
1113 /* TODO: Wait for an interrupt instead of looping? */
1114 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
1115 while (!(reg & RPLY_RECEIV)) {
1116 timeout_loop++;
1117 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
1118 dev_err(dp->dev, "AUX CH command reply failed!\n");
1119 return -ETIMEDOUT;
1120 }
1121 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
1122 usleep_range(10, 11);
1123 }
1124
1125 /* Clear interrupt source for AUX CH command reply */
1126 writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
1127
1128 /* Clear interrupt source for AUX CH access error */
1129 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
1130 if (reg & AUX_ERR) {
1131 writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
1132 return -EREMOTEIO;
1133 }
1134
1135 /* Check AUX CH error access status */
1136 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
1137 if ((reg & AUX_STATUS_MASK)) {
1138 dev_err(dp->dev, "AUX CH error happened: %d\n\n",
1139 reg & AUX_STATUS_MASK);
1140 return -EREMOTEIO;
1141 }
1142
1143 if (msg->request & DP_AUX_I2C_READ) {
1144 for (i = 0; i < msg->size; i++) {
1145 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 +
1146 4 * i);
1147 buffer[i] = (unsigned char)reg;
1148 num_transferred++;
1149 }
1150 }
1151
1152 /* Check if Rx sends defer */
1153 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
1154 if (reg == AUX_RX_COMM_AUX_DEFER)
1155 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
1156 else if (reg == AUX_RX_COMM_I2C_DEFER)
1157 msg->reply = DP_AUX_I2C_REPLY_DEFER;
1158 else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE ||
1159 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_READ)
1160 msg->reply = DP_AUX_I2C_REPLY_ACK;
1161 else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE ||
1162 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ)
1163 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1164
1165 return num_transferred;
1166}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 14:36:44 -0400