mtd: spi-nor: add driver for STM32 quad spi flash controller

The quadspi is a specialized communication interface targeting single,
dual or quad SPI Flash memories.

It can operate in any of the following modes:
-indirect mode: all the operations are performed using the quadspi
 registers
-read memory-mapped mode: the external Flash memory is mapped to the
 microcontroller address space and is seen by the system as if it was
 an internal memory

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>

3 files changed, 701 insertions, 0 deletions

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 7252087ef407..bfdfb1e72b38 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -106,4 +106,11 @@ config SPI_INTEL_SPI_PLATFORM
           To compile this driver as a module, choose M here: the module
           will be called intel-spi-platform.
 
+config SPI_STM32_QUADSPI
+        tristate "STM32 Quad SPI controller"
+        depends on ARCH_STM32
+        help
+          This enables support for the STM32 Quad SPI controller.
+          We only connect the NOR to this controller.
+
 endif # MTD_SPI_NOR
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index 72238a793198..285aab86c7ca 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_MTD_MT81xx_NOR)    += mtk-quadspi.o
 obj-$(CONFIG_SPI_NXP_SPIFI)     += nxp-spifi.o
 obj-$(CONFIG_SPI_INTEL_SPI)     += intel-spi.o
 obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM)    += intel-spi-platform.o
+obj-$(CONFIG_SPI_STM32_QUADSPI) += stm32-quadspi.o
\ No newline at end of file
diff --git a/drivers/mtd/spi-nor/stm32-quadspi.c b/drivers/mtd/spi-nor/stm32-quadspi.c
new file mode 100644
index 000000000000..ae45f81b8cd3
--- /dev/null
+++ b/drivers/mtd/spi-nor/stm32-quadspi.c
@@ -0,0 +1,693 @@
+/*
+ * stm32_quadspi.c
+ *
+ * Copyright (C) 2017, Ludovic Barre
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+#include <linux/clk.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/spi-nor.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#define QUADSPI_CR              0x00
+#define CR_EN                   BIT(0)
+#define CR_ABORT                BIT(1)
+#define CR_DMAEN                BIT(2)
+#define CR_TCEN                 BIT(3)
+#define CR_SSHIFT               BIT(4)
+#define CR_DFM                  BIT(6)
+#define CR_FSEL                 BIT(7)
+#define CR_FTHRES_SHIFT         8
+#define CR_FTHRES_MASK          GENMASK(12, 8)
+#define CR_FTHRES(n)            (((n) << CR_FTHRES_SHIFT) & CR_FTHRES_MASK)
+#define CR_TEIE                 BIT(16)
+#define CR_TCIE                 BIT(17)
+#define CR_FTIE                 BIT(18)
+#define CR_SMIE                 BIT(19)
+#define CR_TOIE                 BIT(20)
+#define CR_PRESC_SHIFT          24
+#define CR_PRESC_MASK           GENMASK(31, 24)
+#define CR_PRESC(n)             (((n) << CR_PRESC_SHIFT) & CR_PRESC_MASK)
+
+#define QUADSPI_DCR             0x04
+#define DCR_CSHT_SHIFT          8
+#define DCR_CSHT_MASK           GENMASK(10, 8)
+#define DCR_CSHT(n)             (((n) << DCR_CSHT_SHIFT) & DCR_CSHT_MASK)
+#define DCR_FSIZE_SHIFT         16
+#define DCR_FSIZE_MASK          GENMASK(20, 16)
+#define DCR_FSIZE(n)            (((n) << DCR_FSIZE_SHIFT) & DCR_FSIZE_MASK)
+
+#define QUADSPI_SR              0x08
+#define SR_TEF                  BIT(0)
+#define SR_TCF                  BIT(1)
+#define SR_FTF                  BIT(2)
+#define SR_SMF                  BIT(3)
+#define SR_TOF                  BIT(4)
+#define SR_BUSY                 BIT(5)
+#define SR_FLEVEL_SHIFT         8
+#define SR_FLEVEL_MASK          GENMASK(13, 8)
+
+#define QUADSPI_FCR             0x0c
+#define FCR_CTCF                BIT(1)
+
+#define QUADSPI_DLR             0x10
+
+#define QUADSPI_CCR             0x14
+#define CCR_INST_SHIFT          0
+#define CCR_INST_MASK           GENMASK(7, 0)
+#define CCR_INST(n)             (((n) << CCR_INST_SHIFT) & CCR_INST_MASK)
+#define CCR_IMODE_NONE          (0U << 8)
+#define CCR_IMODE_1             (1U << 8)
+#define CCR_IMODE_2             (2U << 8)
+#define CCR_IMODE_4             (3U << 8)
+#define CCR_ADMODE_NONE         (0U << 10)
+#define CCR_ADMODE_1            (1U << 10)
+#define CCR_ADMODE_2            (2U << 10)
+#define CCR_ADMODE_4            (3U << 10)
+#define CCR_ADSIZE_SHIFT        12
+#define CCR_ADSIZE_MASK         GENMASK(13, 12)
+#define CCR_ADSIZE(n)           (((n) << CCR_ADSIZE_SHIFT) & CCR_ADSIZE_MASK)
+#define CCR_ABMODE_NONE         (0U << 14)
+#define CCR_ABMODE_1            (1U << 14)
+#define CCR_ABMODE_2            (2U << 14)
+#define CCR_ABMODE_4            (3U << 14)
+#define CCR_ABSIZE_8            (0U << 16)
+#define CCR_ABSIZE_16           (1U << 16)
+#define CCR_ABSIZE_24           (2U << 16)
+#define CCR_ABSIZE_32           (3U << 16)
+#define CCR_DCYC_SHIFT          18
+#define CCR_DCYC_MASK           GENMASK(22, 18)
+#define CCR_DCYC(n)             (((n) << CCR_DCYC_SHIFT) & CCR_DCYC_MASK)
+#define CCR_DMODE_NONE          (0U << 24)
+#define CCR_DMODE_1             (1U << 24)
+#define CCR_DMODE_2             (2U << 24)
+#define CCR_DMODE_4             (3U << 24)
+#define CCR_FMODE_INDW          (0U << 26)
+#define CCR_FMODE_INDR          (1U << 26)
+#define CCR_FMODE_APM           (2U << 26)
+#define CCR_FMODE_MM            (3U << 26)
+
+#define QUADSPI_AR              0x18
+#define QUADSPI_ABR             0x1c
+#define QUADSPI_DR              0x20
+#define QUADSPI_PSMKR           0x24
+#define QUADSPI_PSMAR           0x28
+#define QUADSPI_PIR             0x2c
+#define QUADSPI_LPTR            0x30
+#define LPTR_DFT_TIMEOUT        0x10
+
+#define FSIZE_VAL(size)         (__fls(size) - 1)
+
+#define STM32_MAX_MMAP_SZ       SZ_256M
+#define STM32_MAX_NORCHIP       2
+
+#define STM32_QSPI_FIFO_TIMEOUT_US 30000
+#define STM32_QSPI_BUSY_TIMEOUT_US 100000
+
+struct stm32_qspi_flash {
+        struct spi_nor nor;
+        struct stm32_qspi *qspi;
+        u32 cs;
+        u32 fsize;
+        u32 presc;
+        u32 read_mode;
+        bool registered;
+};
+
+struct stm32_qspi {
+        struct device *dev;
+        void __iomem *io_base;
+        void __iomem *mm_base;
+        resource_size_t mm_size;
+        u32 nor_num;
+        struct clk *clk;
+        u32 clk_rate;
+        struct stm32_qspi_flash flash[STM32_MAX_NORCHIP];
+        struct completion cmd_completion;
+
+        /*
+         * to protect device configuration, could be different between
+         * 2 flash access (bk1, bk2)
+         */
+        struct mutex lock;
+};
+
+struct stm32_qspi_cmd {
+        u8 addr_width;
+        u8 dummy;
+        bool tx_data;
+        u8 opcode;
+        u32 framemode;
+        u32 qspimode;
+        u32 addr;
+        size_t len;
+        void *buf;
+};
+
+static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi)
+{
+        u32 cr;
+        int err = 0;
+
+        if (readl_relaxed(qspi->io_base + QUADSPI_SR) & SR_TCF)
+                return 0;
+
+        reinit_completion(&qspi->cmd_completion);
+        cr = readl_relaxed(qspi->io_base + QUADSPI_CR);
+        writel_relaxed(cr | CR_TCIE, qspi->io_base + QUADSPI_CR);
+
+        if (!wait_for_completion_interruptible_timeout(&qspi->cmd_completion,
+                                                       msecs_to_jiffies(1000)))
+                err = -ETIMEDOUT;
+
+        writel_relaxed(cr, qspi->io_base + QUADSPI_CR);
+        return err;
+}
+