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authorAkinobu Mita <akinobu.mita@gmail.com>2017-07-20 11:24:17 -0400
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2017-08-20 10:41:12 -0400
commit0d106b74c558e3000aa0e058b4725cacb70ce77a (patch)
treeb391bf08be7e17aca932ffbdc8244551d701bcf5
parent8cfa26a77cfcad888f44c0ed902fe6c7c73783fe (diff)
iio: adc: ti-ads1015: fix incorrect data rate setting update
The ti-ads1015 driver has eight iio voltage channels and each iio channel can hold own sampling frequency information. The ADS1015 device only have a single config register which contains an input multiplexer selection, PGA and data rate settings. So the driver should load the correct settings when the input multiplexer selection is changed. However, regardless of which channlel is currently selected, changing any iio channel's sampling frequency information immediately overwrites the current data rate setting in the config register. It breaks the current data rate setting if the different channel's sampling frequency information is changed because the data rate setting is not reloaded when the input multiplexer is switched. This removes the unexpected config register update and correctly load the data rate setting before getting adc result. Cc: Daniel Baluta <daniel.baluta@gmail.com> Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
-rw-r--r--drivers/iio/adc/ti-ads1015.c27
1 files changed, 10 insertions, 17 deletions
diff --git a/drivers/iio/adc/ti-ads1015.c b/drivers/iio/adc/ti-ads1015.c
index 7972845b3823..897bc2f04ab6 100644
--- a/drivers/iio/adc/ti-ads1015.c
+++ b/drivers/iio/adc/ti-ads1015.c
@@ -252,9 +252,11 @@ int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
252 252
253 ret = regmap_update_bits_check(data->regmap, ADS1015_CFG_REG, 253 ret = regmap_update_bits_check(data->regmap, ADS1015_CFG_REG,
254 ADS1015_CFG_MUX_MASK | 254 ADS1015_CFG_MUX_MASK |
255 ADS1015_CFG_PGA_MASK, 255 ADS1015_CFG_PGA_MASK |
256 ADS1015_CFG_DR_MASK,
256 chan << ADS1015_CFG_MUX_SHIFT | 257 chan << ADS1015_CFG_MUX_SHIFT |
257 pga << ADS1015_CFG_PGA_SHIFT, 258 pga << ADS1015_CFG_PGA_SHIFT |
259 dr << ADS1015_CFG_DR_SHIFT,
258 &change); 260 &change);
259 if (ret < 0) 261 if (ret < 0)
260 return ret; 262 return ret;
@@ -325,25 +327,16 @@ static int ads1015_set_scale(struct ads1015_data *data, int chan,
325 327
326static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate) 328static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
327{ 329{
328 int i, ret, rindex = -1; 330 int i;
329 331
330 for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) 332 for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) {
331 if (data->data_rate[i] == rate) { 333 if (data->data_rate[i] == rate) {
332 rindex = i; 334 data->channel_data[chan].data_rate = i;
333 break; 335 return 0;
334 } 336 }
335 if (rindex < 0) 337 }
336 return -EINVAL;
337
338 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
339 ADS1015_CFG_DR_MASK,
340 rindex << ADS1015_CFG_DR_SHIFT);
341 if (ret < 0)
342 return ret;
343
344 data->channel_data[chan].data_rate = rindex;
345 338
346 return 0; 339 return -EINVAL;
347} 340}
348 341
349static int ads1015_read_raw(struct iio_dev *indio_dev, 342static int ads1015_read_raw(struct iio_dev *indio_dev,