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authorMaxime Ripard <maxime.ripard@free-electrons.com>2015-05-07 11:38:10 -0400
committerVinod Koul <vinod.koul@intel.com>2015-05-18 01:29:35 -0400
commit0d0ee751f7f7cd7d44eeb596f3b430ed0b178e07 (patch)
treec41357b2ee6a55490b52cf2b3b81fb8b3f595868
parentf0816a36887b5b6acb387d8a554c5f5ed4069d33 (diff)
dmaengine: xdmac: Rework the chaining logic
So far, we were setting the NDE bit in our descriptors through some logic to try to see if we were the last descriptor in the chain. However, that was turning out to be rather complex to get right, while this information is also available when we actually chain a new descriptor after an already existing one. Simplify this by never setting NDE unless when we actually chain a descriptor. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r--drivers/dma/at_xdmac.c41
1 files changed, 20 insertions, 21 deletions
diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index cbeadeeed9c0..0144a935b8f2 100644
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -471,6 +471,20 @@ static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan)
471 return desc; 471 return desc;
472} 472}
473 473
474static void at_xdmac_queue_desc(struct dma_chan *chan,
475 struct at_xdmac_desc *prev,
476 struct at_xdmac_desc *desc)
477{
478 if (!prev || !desc)
479 return;
480
481 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
482 prev->lld.mbr_ubc |= AT_XDMAC_MBR_UBC_NDE;
483
484 dev_dbg(chan2dev(chan), "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
485 __func__, prev, &prev->lld.mbr_nda);
486}
487
474static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec, 488static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec,
475 struct of_dma *of_dma) 489 struct of_dma *of_dma)
476{ 490{
@@ -627,19 +641,14 @@ at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
627 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */ 641 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */
628 | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */ 642 | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */
629 | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */ 643 | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */
630 | (i == sg_len - 1 ? 0 : AT_XDMAC_MBR_UBC_NDE) /* descriptor fetch */
631 | (len >> fixed_dwidth); /* microblock length */ 644 | (len >> fixed_dwidth); /* microblock length */
632 dev_dbg(chan2dev(chan), 645 dev_dbg(chan2dev(chan),
633 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", 646 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
634 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc); 647 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
635 648
636 /* Chain lld. */ 649 /* Chain lld. */
637 if (prev) { 650 if (prev)
638 prev->lld.mbr_nda = desc->tx_dma_desc.phys; 651 at_xdmac_queue_desc(chan, prev, desc);
639 dev_dbg(chan2dev(chan),
640 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
641 __func__, prev, &prev->lld.mbr_nda);
642 }
643 652
644 prev = desc; 653 prev = desc;
645 if (!first) 654 if (!first)
@@ -714,7 +723,6 @@ at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
714 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1 723 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1
715 | AT_XDMAC_MBR_UBC_NDEN 724 | AT_XDMAC_MBR_UBC_NDEN
716 | AT_XDMAC_MBR_UBC_NSEN 725 | AT_XDMAC_MBR_UBC_NSEN
717 | AT_XDMAC_MBR_UBC_NDE
718 | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg); 726 | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg);
719 727
720 dev_dbg(chan2dev(chan), 728 dev_dbg(chan2dev(chan),
@@ -722,12 +730,8 @@ at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
722 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc); 730 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
723 731
724 /* Chain lld. */ 732 /* Chain lld. */
725 if (prev) { 733 if (prev)
726 prev->lld.mbr_nda = desc->tx_dma_desc.phys; 734 at_xdmac_queue_desc(chan, prev, desc);
727 dev_dbg(chan2dev(chan),
728 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
729 __func__, prev, &prev->lld.mbr_nda);
730 }
731 735
732 prev = desc; 736 prev = desc;
733 if (!first) 737 if (!first)
@@ -850,7 +854,6 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
850 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 854 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2
851 | AT_XDMAC_MBR_UBC_NDEN 855 | AT_XDMAC_MBR_UBC_NDEN
852 | AT_XDMAC_MBR_UBC_NSEN 856 | AT_XDMAC_MBR_UBC_NSEN
853 | (remaining_size ? AT_XDMAC_MBR_UBC_NDE : 0)
854 | ublen; 857 | ublen;
855 desc->lld.mbr_cfg = chan_cc; 858 desc->lld.mbr_cfg = chan_cc;
856 859
@@ -859,12 +862,8 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
859 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg); 862 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);
860 863
861 /* Chain lld. */ 864 /* Chain lld. */
862 if (prev) { 865 if (prev)
863 prev->lld.mbr_nda = desc->tx_dma_desc.phys; 866 at_xdmac_queue_desc(chan, prev, desc);
864 dev_dbg(chan2dev(chan),
865 "%s: chain lld: prev=0x%p, mbr_nda=0x%08x\n",
866 __func__, prev, prev->lld.mbr_nda);
867 }
868 867
869 prev = desc; 868 prev = desc;
870 if (!first) 869 if (!first)