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authorDave Airlie <airlied@redhat.com>2016-07-19 03:51:19 -0400
committerDave Airlie <airlied@redhat.com>2016-07-19 03:51:19 -0400
commit0cf09031540cc6d8a6b41fcb1a32a704d5e55af7 (patch)
treef4fa3fa1b31c487be6d2f206fe3b43aaa5f6025b
parentd315495d21bf44fd5e422807e8324ff82bfaabab (diff)
parent1d926114d8f4e9f138617b95c6cd377667c36369 (diff)
Merge branch 'drm_bridge_for_4.8' of https://github.com/boddob/linux into drm-next
This is an update to the previous drm bridge pull request. The ADV7511 driver's conversion from slave encoder to bridge meant that its users (the rcar-du kms driver) should use the bridge interface too. This pull request now also contains a commit that updates the rcar-du's hdmi encoder interface from slave encoder to bridge. The other updates are as before: - Converts the ADV7511 i2c slave encoder driver to a bridge driver. Adds support for the ADV7533 bridge chip. - Add bridge driver for TC358767 (DSI/DPI to eDP) encoder chips. * 'drm_bridge_for_4.8' of https://github.com/boddob/linux: drm: rcar-du: Remove i2c slave encoder interface for hdmi encoder drm/bridge: tc358767: Add DPI to eDP bridge driver dt-bindings: tc358767: add DT documentation dt-bindings: drm/bridge: Update bindings for ADV7533 drm/bridge: adv7533: Change number of DSI lanes dynamically drm/bridge: adv7533: Use internal timing generator drm/bridge: adv7533: Create a MIPI DSI device drm/bridge: adv7533: Initial support for ADV7533 drm/bridge: adv7511: Fix mutex deadlock when interrupts are disabled drm/i2c: adv7511: Move to bridge folder drm/i2c: adv7511: Convert to drm_bridge
Diffstat
-rw-r--r--Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt26
-rw-r--r--Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.txt53
-rw-r--r--drivers/gpu/drm/bridge/Kconfig11
-rw-r--r--drivers/gpu/drm/bridge/Makefile2
-rw-r--r--drivers/gpu/drm/bridge/adv7511/Kconfig15
-rw-r--r--drivers/gpu/drm/bridge/adv7511/Makefile3
-rw-r--r--drivers/gpu/drm/bridge/adv7511/adv7511.h (renamed from drivers/gpu/drm/i2c/adv7511.h)103
-rw-r--r--drivers/gpu/drm/bridge/adv7511/adv7511_drv.c (renamed from drivers/gpu/drm/i2c/adv7511.c)324
-rw-r--r--drivers/gpu/drm/bridge/adv7511/adv7533.c265
-rw-r--r--drivers/gpu/drm/bridge/tc358767.c1413
-rw-r--r--drivers/gpu/drm/i2c/Kconfig6
-rw-r--r--drivers/gpu/drm/i2c/Makefile2
-rw-r--r--drivers/gpu/drm/rcar-du/Makefile4
-rw-r--r--drivers/gpu/drm/rcar-du/rcar_du_encoder.c3
-rw-r--r--drivers/gpu/drm/rcar-du/rcar_du_encoder.h7
-rw-r--r--drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c116
-rw-r--r--drivers/gpu/drm/rcar-du/rcar_du_hdmicon.h31
-rw-r--r--drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c68
18 files changed, 2120 insertions, 332 deletions
diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
index 96c25ee01501..6532a59c9b43 100644
--- a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
+++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
@@ -1,13 +1,19 @@
1Analog Device ADV7511(W)/13 HDMI Encoders 1Analog Device ADV7511(W)/13/33 HDMI Encoders
2----------------------------------------- 2-----------------------------------------
3 3
4The ADV7511, ADV7511W and ADV7513 are HDMI audio and video transmitters 4The ADV7511, ADV7511W, ADV7513 and ADV7533 are HDMI audio and video transmitters
5compatible with HDMI 1.4 and DVI 1.0. They support color space conversion, 5compatible with HDMI 1.4 and DVI 1.0. They support color space conversion,
6S/PDIF, CEC and HDCP. 6S/PDIF, CEC and HDCP. ADV7533 supports the DSI interface for input pixels, while
7the others support RGB interface.
7 8
8Required properties: 9Required properties:
9 10
10- compatible: Should be one of "adi,adv7511", "adi,adv7511w" or "adi,adv7513" 11- compatible: Should be one of:
12 "adi,adv7511"
13 "adi,adv7511w"
14 "adi,adv7513"
15 "adi,adv7533"
16
11- reg: I2C slave address 17- reg: I2C slave address
12 18
13The ADV7511 supports a large number of input data formats that differ by their 19The ADV7511 supports a large number of input data formats that differ by their
@@ -32,6 +38,11 @@ The following input format properties are required except in "rgb 1x" and
32- adi,input-justification: The input bit justification ("left", "evenly", 38- adi,input-justification: The input bit justification ("left", "evenly",
33 "right"). 39 "right").
34 40
41The following properties are required for ADV7533:
42
43- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should
44 be one of 1, 2, 3 or 4.
45
35Optional properties: 46Optional properties:
36 47
37- interrupts: Specifier for the ADV7511 interrupt 48- interrupts: Specifier for the ADV7511 interrupt
@@ -42,13 +53,18 @@ Optional properties:
42- adi,embedded-sync: The input uses synchronization signals embedded in the 53- adi,embedded-sync: The input uses synchronization signals embedded in the
43 data stream (similar to BT.656). Defaults to separate H/V synchronization 54 data stream (similar to BT.656). Defaults to separate H/V synchronization
44 signals. 55 signals.
56- adi,disable-timing-generator: Only for ADV7533. Disables the internal timing
57 generator. The chip will rely on the sync signals in the DSI data lanes,
58 rather than generate its own timings for HDMI output.
45 59
46Required nodes: 60Required nodes:
47 61
48The ADV7511 has two video ports. Their connections are modelled using the OF 62The ADV7511 has two video ports. Their connections are modelled using the OF
49graph bindings specified in Documentation/devicetree/bindings/graph.txt. 63graph bindings specified in Documentation/devicetree/bindings/graph.txt.
50 64
51- Video port 0 for the RGB or YUV input 65- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533, the
66 remote endpoint phandle should be a reference to a valid mipi_dsi_host device
67 node.
52- Video port 1 for the HDMI output 68- Video port 1 for the HDMI output
53 69
54 70
diff --git a/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.txt b/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.txt
new file mode 100644
index 000000000000..e3f6aa6a214d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.txt
@@ -0,0 +1,53 @@
1Toshiba TC358767 eDP bridge bindings
2
3Required properties:
4 - compatible: "toshiba,tc358767"
5 - reg: i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins
6 - clock-names: should be "ref"
7 - clocks: OF device-tree clock specification for refclk input. The reference
8 clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
9
10Optional properties:
11 - shutdown-gpios: OF device-tree gpio specification for SD pin
12 (active high shutdown input)
13 - reset-gpios: OF device-tree gpio specification for RSTX pin
14 (active low system reset)
15 - ports: the ports node can contain video interface port nodes to connect
16 to a DPI/DSI source and to an eDP/DP sink according to [1][2]:
17 - port@0: DSI input port
18 - port@1: DPI input port
19 - port@2: eDP/DP output port
20
21[1]: Documentation/devicetree/bindings/graph.txt
22[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
23
24Example:
25 edp-bridge@68 {
26 compatible = "toshiba,tc358767";
27 reg = <0x68>;
28 shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
29 reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
30 clock-names = "ref";
31 clocks = <&edp_refclk>;
32
33 ports {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 port@1 {
38 reg = <1>;
39
40 bridge_in: endpoint {
41 remote-endpoint = <&dpi_out>;
42 };
43 };
44
45 port@2 {
46 reg = <2>;
47
48 bridge_out: endpoint {
49 remote-endpoint = <&panel_in>;
50 };
51 };
52 };
53 };
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index a141921445f4..b590e678052d 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -58,6 +58,17 @@ config DRM_SII902X
58 ---help--- 58 ---help---
59 Silicon Image sii902x bridge chip driver. 59 Silicon Image sii902x bridge chip driver.
60 60
61config DRM_TOSHIBA_TC358767
62 tristate "Toshiba TC358767 eDP bridge"
63 depends on OF
64 select DRM_KMS_HELPER
65 select REGMAP_I2C
66 select DRM_PANEL
67 ---help---
68 Toshiba TC358767 eDP bridge chip driver.
69
61source "drivers/gpu/drm/bridge/analogix/Kconfig" 70source "drivers/gpu/drm/bridge/analogix/Kconfig"
62 71
72source "drivers/gpu/drm/bridge/adv7511/Kconfig"
73
63endmenu 74endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index bfec9f8cb9d2..efdb07e878f5 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -6,4 +6,6 @@ obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
6obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o 6obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
7obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o 7obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
8obj-$(CONFIG_DRM_SII902X) += sii902x.o 8obj-$(CONFIG_DRM_SII902X) += sii902x.o
9obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
9obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ 10obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
11obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
diff --git a/drivers/gpu/drm/bridge/adv7511/Kconfig b/drivers/gpu/drm/bridge/adv7511/Kconfig
new file mode 100644
index 000000000000..d2b0499ab7d7
--- /dev/null
+++ b/drivers/gpu/drm/bridge/adv7511/Kconfig
@@ -0,0 +1,15 @@
1config DRM_I2C_ADV7511
2 tristate "AV7511 encoder"
3 depends on OF
4 select DRM_KMS_HELPER
5 select REGMAP_I2C
6 help
7 Support for the Analog Device ADV7511(W) and ADV7513 HDMI encoders.
8
9config DRM_I2C_ADV7533
10 bool "ADV7533 encoder"
11 depends on DRM_I2C_ADV7511
12 select DRM_MIPI_DSI
13 default y
14 help
15 Support for the Analog Devices ADV7533 DSI to HDMI encoder.
diff --git a/drivers/gpu/drm/bridge/adv7511/Makefile b/drivers/gpu/drm/bridge/adv7511/Makefile
new file mode 100644
index 000000000000..9019327fff4c
--- /dev/null
+++ b/drivers/gpu/drm/bridge/adv7511/Makefile
@@ -0,0 +1,3 @@
1adv7511-y := adv7511_drv.o
2adv7511-$(CONFIG_DRM_I2C_ADV7533) += adv7533.o
3obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511.o
diff --git a/drivers/gpu/drm/i2c/adv7511.h b/drivers/gpu/drm/bridge/adv7511/adv7511.h
index 38515b30cedf..161c923d6162 100644
--- a/drivers/gpu/drm/i2c/adv7511.h
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h
@@ -10,6 +10,11 @@
10#define __DRM_I2C_ADV7511_H__ 10#define __DRM_I2C_ADV7511_H__
11 11
12#include <linux/hdmi.h> 12#include <linux/hdmi.h>
13#include <linux/i2c.h>
14#include <linux/regmap.h>
15
16#include <drm/drm_crtc_helper.h>
17#include <drm/drm_mipi_dsi.h>
13 18
14#define ADV7511_REG_CHIP_REVISION 0x00 19#define ADV7511_REG_CHIP_REVISION 0x00
15#define ADV7511_REG_N0 0x01 20#define ADV7511_REG_N0 0x01
@@ -286,4 +291,102 @@ struct adv7511_video_config {
286 struct hdmi_avi_infoframe avi_infoframe; 291 struct hdmi_avi_infoframe avi_infoframe;
287}; 292};
288 293
294enum adv7511_type {
295 ADV7511,
296 ADV7533,
297};
298
299struct adv7511 {
300 struct i2c_client *i2c_main;
301 struct i2c_client *i2c_edid;
302 struct i2c_client *i2c_cec;
303
304 struct regmap *regmap;
305 struct regmap *regmap_cec;
306 enum drm_connector_status status;
307 bool powered;
308
309 struct drm_display_mode curr_mode;
310
311 unsigned int f_tmds;
312
313 unsigned int current_edid_segment;
314 uint8_t edid_buf[256];
315 bool edid_read;
316
317 wait_queue_head_t wq;
318 struct drm_bridge bridge;
319 struct drm_connector connector;
320
321 bool embedded_sync;
322 enum adv7511_sync_polarity vsync_polarity;
323 enum adv7511_sync_polarity hsync_polarity;
324 bool rgb;
325
326 struct edid *edid;
327
328 struct gpio_desc *gpio_pd;
329
330 /* ADV7533 DSI RX related params */
331 struct device_node *host_node;
332 struct mipi_dsi_device *dsi;
333 u8 num_dsi_lanes;
334 bool use_timing_gen;
335
336 enum adv7511_type type;
337};
338
339#ifdef CONFIG_DRM_I2C_ADV7533
340void adv7533_dsi_power_on(struct adv7511 *adv);
341void adv7533_dsi_power_off(struct adv7511 *adv);
342void adv7533_mode_set(struct adv7511 *adv, struct drm_display_mode *mode);
343int adv7533_patch_registers(struct adv7511 *adv);
344void adv7533_uninit_cec(struct adv7511 *adv);
345int adv7533_init_cec(struct adv7511 *adv);
346int adv7533_attach_dsi(struct adv7511 *adv);
347void adv7533_detach_dsi(struct adv7511 *adv);
348int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv);
349#else
350static inline void adv7533_dsi_power_on(struct adv7511 *adv)
351{
352}
353
354static inline void adv7533_dsi_power_off(struct adv7511 *adv)
355{
356}
357
358static inline void adv7533_mode_set(struct adv7511 *adv,
359 struct drm_display_mode *mode)
360{
361}
362
363static inline int adv7533_patch_registers(struct adv7511 *adv)
364{
365 return -ENODEV;
366}
367
368static inline void adv7533_uninit_cec(struct adv7511 *adv)
369{
370}
371
372static inline int adv7533_init_cec(struct adv7511 *adv)
373{
374 return -ENODEV;
375}
376
377static inline int adv7533_attach_dsi(struct adv7511 *adv)
378{
379 return -ENODEV;
380}
381
382static inline void adv7533_detach_dsi(struct adv7511 *adv)
383{
384}
385
386static inline int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv)
387{
388 return -ENODEV;
389}
390#endif
391
289#endif /* __DRM_I2C_ADV7511_H__ */ 392#endif /* __DRM_I2C_ADV7511_H__ */
diff --git a/drivers/gpu/drm/i2c/adv7511.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index a02112ba1c3d..ec8fb2ed3275 100644
--- a/drivers/gpu/drm/i2c/adv7511.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
@@ -8,51 +8,17 @@
8 8
9#include <linux/device.h> 9#include <linux/device.h>
10#include <linux/gpio/consumer.h> 10#include <linux/gpio/consumer.h>
11#include <linux/i2c.h>
12#include <linux/module.h> 11#include <linux/module.h>
13#include <linux/regmap.h> 12#include <linux/of_device.h>
14#include <linux/slab.h> 13#include <linux/slab.h>
15 14
16#include <drm/drmP.h> 15#include <drm/drmP.h>
17#include <drm/drm_crtc_helper.h> 16#include <drm/drm_atomic.h>
17#include <drm/drm_atomic_helper.h>
18#include <drm/drm_edid.h> 18#include <drm/drm_edid.h>
19#include <drm/drm_encoder_slave.h>
20 19
21#include "adv7511.h" 20#include "adv7511.h"
22 21
23struct adv7511 {
24 struct i2c_client *i2c_main;
25 struct i2c_client *i2c_edid;
26
27 struct regmap *regmap;
28 struct regmap *packet_memory_regmap;
29 enum drm_connector_status status;
30 bool powered;
31
32 unsigned int f_tmds;
33
34 unsigned int current_edid_segment;
35 uint8_t edid_buf[256];
36 bool edid_read;
37
38 wait_queue_head_t wq;
39 struct drm_encoder *encoder;
40
41 bool embedded_sync;
42 enum adv7511_sync_polarity vsync_polarity;
43 enum adv7511_sync_polarity hsync_polarity;
44 bool rgb;
45
46 struct edid *edid;
47
48 struct gpio_desc *gpio_pd;
49};
50
51static struct adv7511 *encoder_to_adv7511(struct drm_encoder *encoder)
52{
53 return to_encoder_slave(encoder)->slave_priv;
54}
55
56/* ADI recommended values for proper operation. */ 22/* ADI recommended values for proper operation. */
57static const struct reg_sequence adv7511_fixed_registers[] = { 23static const struct reg_sequence adv7511_fixed_registers[] = {
58 { 0x98, 0x03 }, 24 { 0x98, 0x03 },
@@ -394,6 +360,9 @@ static void adv7511_power_on(struct adv7511 *adv7511)
394 */ 360 */
395 regcache_sync(adv7511->regmap); 361 regcache_sync(adv7511->regmap);
396 362
363 if (adv7511->type == ADV7533)
364 adv7533_dsi_power_on(adv7511);
365
397 adv7511->powered = true; 366 adv7511->powered = true;
398} 367}
399 368
@@ -405,6 +374,9 @@ static void adv7511_power_off(struct adv7511 *adv7511)
405 ADV7511_POWER_POWER_DOWN); 374 ADV7511_POWER_POWER_DOWN);
406 regcache_mark_dirty(adv7511->regmap); 375 regcache_mark_dirty(adv7511->regmap);
407 376
377 if (adv7511->type == ADV7533)
378 adv7533_dsi_power_off(adv7511);
379
408 adv7511->powered = false; 380 adv7511->powered = false;
409} 381}
410 382
@@ -430,7 +402,7 @@ static bool adv7511_hpd(struct adv7511 *adv7511)
430 return false; 402 return false;
431} 403}
432 404
433static int adv7511_irq_process(struct adv7511 *adv7511) 405static int adv7511_irq_process(struct adv7511 *adv7511, bool process_hpd)
434{ 406{
435 unsigned int irq0, irq1; 407 unsigned int irq0, irq1;
436 int ret; 408 int ret;
@@ -446,8 +418,8 @@ static int adv7511_irq_process(struct adv7511 *adv7511)
446 regmap_write(adv7511->regmap, ADV7511_REG_INT(0), irq0); 418 regmap_write(adv7511->regmap, ADV7511_REG_INT(0), irq0);
447 regmap_write(adv7511->regmap, ADV7511_REG_INT(1), irq1); 419 regmap_write(adv7511->regmap, ADV7511_REG_INT(1), irq1);
448 420
449 if (irq0 & ADV7511_INT0_HPD && adv7511->encoder) 421 if (process_hpd && irq0 & ADV7511_INT0_HPD && adv7511->bridge.encoder)
450 drm_helper_hpd_irq_event(adv7511->encoder->dev); 422 drm_helper_hpd_irq_event(adv7511->connector.dev);
451 423
452 if (irq0 & ADV7511_INT0_EDID_READY || irq1 & ADV7511_INT1_DDC_ERROR) { 424 if (irq0 & ADV7511_INT0_EDID_READY || irq1 & ADV7511_INT1_DDC_ERROR) {
453 adv7511->edid_read = true; 425 adv7511->edid_read = true;
@@ -464,7 +436,7 @@ static irqreturn_t adv7511_irq_handler(int irq, void *devid)
464 struct adv7511 *adv7511 = devid; 436 struct adv7511 *adv7511 = devid;
465 int ret; 437 int ret;
466 438
467 ret = adv7511_irq_process(adv7511); 439 ret = adv7511_irq_process(adv7511, true);
468 return ret < 0 ? IRQ_NONE : IRQ_HANDLED; 440 return ret < 0 ? IRQ_NONE : IRQ_HANDLED;
469} 441}
470 442
@@ -481,7 +453,7 @@ static int adv7511_wait_for_edid(struct adv7511 *adv7511, int timeout)
481 adv7511->edid_read, msecs_to_jiffies(timeout)); 453 adv7511->edid_read, msecs_to_jiffies(timeout));
482 } else { 454 } else {
483 for (; timeout > 0; timeout -= 25) { 455 for (; timeout > 0; timeout -= 25) {
484 ret = adv7511_irq_process(adv7511); 456 ret = adv7511_irq_process(adv7511, false);
485 if (ret < 0) 457 if (ret < 0)
486 break; 458 break;
487 459
@@ -563,13 +535,12 @@ static int adv7511_get_edid_block(void *data, u8 *buf, unsigned int block,
563} 535}
564 536
565/* ----------------------------------------------------------------------------- 537/* -----------------------------------------------------------------------------
566 * Encoder operations 538 * ADV75xx helpers
567 */ 539 */
568 540
569static int adv7511_get_modes(struct drm_encoder *encoder, 541static int adv7511_get_modes(struct adv7511 *adv7511,
570 struct drm_connector *connector) 542 struct drm_connector *connector)
571{ 543{
572 struct adv7511 *adv7511 = encoder_to_adv7511(encoder);
573 struct edid *edid; 544 struct edid *edid;
574 unsigned int count; 545 unsigned int count;
575 546
@@ -606,21 +577,9 @@ static int adv7511_get_modes(struct drm_encoder *encoder,
606 return count; 577 return count;
607} 578}
608 579
609static void adv7511_encoder_dpms(struct drm_encoder *encoder, int mode)
610{
611 struct adv7511 *adv7511 = encoder_to_adv7511(encoder);
612
613 if (mode == DRM_MODE_DPMS_ON)
614 adv7511_power_on(adv7511);
615 else
616 adv7511_power_off(adv7511);
617}
618
619static enum drm_connector_status 580static enum drm_connector_status
620adv7511_encoder_detect(struct drm_encoder *encoder, 581adv7511_detect(struct adv7511 *adv7511, struct drm_connector *connector)
621 struct drm_connector *connector)
622{ 582{
623 struct adv7511 *adv7511 = encoder_to_adv7511(encoder);
624 enum drm_connector_status status; 583 enum drm_connector_status status;
625 unsigned int val; 584 unsigned int val;
626 bool hpd; 585 bool hpd;
@@ -644,7 +603,7 @@ adv7511_encoder_detect(struct drm_encoder *encoder,
644 if (status == connector_status_connected && hpd && adv7511->powered) { 603 if (status == connector_status_connected && hpd && adv7511->powered) {
645 regcache_mark_dirty(adv7511->regmap); 604 regcache_mark_dirty(adv7511->regmap);
646 adv7511_power_on(adv7511); 605 adv7511_power_on(adv7511);
647 adv7511_get_modes(encoder, connector); 606 adv7511_get_modes(adv7511, connector);
648 if (adv7511->status == connector_status_connected) 607 if (adv7511->status == connector_status_connected)
649 status = connector_status_disconnected; 608 status = connector_status_disconnected;
650 } else { 609 } else {
@@ -658,8 +617,8 @@ adv7511_encoder_detect(struct drm_encoder *encoder,
658 return status; 617 return status;
659} 618}
660 619
661static int adv7511_encoder_mode_valid(struct drm_encoder *encoder, 620static int adv7511_mode_valid(struct adv7511 *adv7511,
662 struct drm_display_mode *mode) 621 struct drm_display_mode *mode)
663{ 622{
664 if (mode->clock > 165000) 623 if (mode->clock > 165000)
665 return MODE_CLOCK_HIGH; 624 return MODE_CLOCK_HIGH;
@@ -667,11 +626,10 @@ static int adv7511_encoder_mode_valid(struct drm_encoder *encoder,
667 return MODE_OK; 626 return MODE_OK;
668} 627}
669 628
670static void adv7511_encoder_mode_set(struct drm_encoder *encoder, 629static void adv7511_mode_set(struct adv7511 *adv7511,
671 struct drm_display_mode *mode, 630 struct drm_display_mode *mode,
672 struct drm_display_mode *adj_mode) 631 struct drm_display_mode *adj_mode)
673{ 632{
674 struct adv7511 *adv7511 = encoder_to_adv7511(encoder);
675 unsigned int low_refresh_rate; 633 unsigned int low_refresh_rate;
676 unsigned int hsync_polarity = 0; 634 unsigned int hsync_polarity = 0;
677 unsigned int vsync_polarity = 0; 635 unsigned int vsync_polarity = 0;
@@ -754,6 +712,11 @@ static void adv7511_encoder_mode_set(struct drm_encoder *encoder,
754 regmap_update_bits(adv7511->regmap, 0x17, 712 regmap_update_bits(adv7511->regmap, 0x17,
755 0x60, (vsync_polarity << 6) | (hsync_polarity << 5)); 713 0x60, (vsync_polarity << 6) | (hsync_polarity << 5));
756 714
715 if (adv7511->type == ADV7533)
716 adv7533_mode_set(adv7511, adj_mode);
717
718 drm_mode_copy(&adv7511->curr_mode, adj_mode);
719
757 /* 720 /*
758 * TODO Test first order 4:2:2 to 4:4:4 up conversion method, which is 721 * TODO Test first order 4:2:2 to 4:4:4 up conversion method, which is
759 * supposed to give better results. 722 * supposed to give better results.
@@ -762,12 +725,114 @@ static void adv7511_encoder_mode_set(struct drm_encoder *encoder,
762 adv7511->f_tmds = mode->clock; 725 adv7511->f_tmds = mode->clock;
763} 726}
764 727
765static const struct drm_encoder_slave_funcs adv7511_encoder_funcs = { 728/* Connector funcs */
766 .dpms = adv7511_encoder_dpms, 729static struct adv7511 *connector_to_adv7511(struct drm_connector *connector)
767 .mode_valid = adv7511_encoder_mode_valid, 730{
768 .mode_set = adv7511_encoder_mode_set, 731 return container_of(connector, struct adv7511, connector);
769 .detect = adv7511_encoder_detect, 732}
770 .get_modes = adv7511_get_modes, 733
734static int adv7511_connector_get_modes(struct drm_connector *connector)
735{
736 struct adv7511 *adv = connector_to_adv7511(connector);
737
738 return adv7511_get_modes(adv, connector);
739}
740
741static enum drm_mode_status
742adv7511_connector_mode_valid(struct drm_connector *connector,
743 struct drm_display_mode *mode)
744{
745 struct adv7511 *adv = connector_to_adv7511(connector);
746
747 return adv7511_mode_valid(adv, mode);
748}
749
750static struct drm_connector_helper_funcs adv7511_connector_helper_funcs = {
751 .get_modes = adv7511_connector_get_modes,
752 .mode_valid = adv7511_connector_mode_valid,
753};
754
755static enum drm_connector_status
756adv7511_connector_detect(struct drm_connector *connector, bool force)
757{
758 struct adv7511 *adv = connector_to_adv7511(connector);
759
760 return adv7511_detect(adv, connector);
761}
762
763static struct drm_connector_funcs adv7511_connector_funcs = {
764 .dpms = drm_atomic_helper_connector_dpms,
765 .fill_modes = drm_helper_probe_single_connector_modes,
766 .detect = adv7511_connector_detect,
767 .destroy = drm_connector_cleanup,
768 .reset = drm_atomic_helper_connector_reset,
769 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
770 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
771};
772
773/* Bridge funcs */
774static struct adv7511 *bridge_to_adv7511(struct drm_bridge *bridge)
775{
776 return container_of(bridge, struct adv7511, bridge);
777}
778
779static void adv7511_bridge_enable(struct drm_bridge *bridge)
780{
781 struct adv7511 *adv = bridge_to_adv7511(bridge);
782
783 adv7511_power_on(adv);
784}
785
786static void adv7511_bridge_disable(struct drm_bridge *bridge)
787{
788 struct adv7511 *adv = bridge_to_adv7511(bridge);
789
790 adv7511_power_off(adv);
791}
792
793static void adv7511_bridge_mode_set(struct drm_bridge *bridge,
794 struct drm_display_mode *mode,
795 struct drm_display_mode *adj_mode)
796{
797 struct adv7511 *adv = bridge_to_adv7511(bridge);
798
799 adv7511_mode_set(adv, mode, adj_mode);
800}
801
802static int adv7511_bridge_attach(struct drm_bridge *bridge)
803{
804 struct adv7511 *adv = bridge_to_adv7511(bridge);
805 int ret;
806
807 if (!bridge->encoder) {
808 DRM_ERROR("Parent encoder object not found");
809 return -ENODEV;
810 }
811
812 adv->connector.polled = DRM_CONNECTOR_POLL_HPD;
813
814 ret = drm_connector_init(bridge->dev, &adv->connector,
815 &adv7511_connector_funcs,
816 DRM_MODE_CONNECTOR_HDMIA);
817 if (ret) {
818 DRM_ERROR("Failed to initialize connector with drm\n");
819 return ret;
820 }
821 drm_connector_helper_add(&adv->connector,
822 &adv7511_connector_helper_funcs);
823 drm_mode_connector_attach_encoder(&adv->connector, bridge->encoder);
824
825 if (adv->type == ADV7533)
826 ret = adv7533_attach_dsi(adv);
827
828 return ret;
829}
830
831static struct drm_bridge_funcs adv7511_bridge_funcs = {
832 .enable = adv7511_bridge_enable,
833 .disable = adv7511_bridge_disable,
834 .mode_set = adv7511_bridge_mode_set,
835 .attach = adv7511_bridge_attach,
771}; 836};
772 837
773/* ----------------------------------------------------------------------------- 838/* -----------------------------------------------------------------------------
@@ -780,8 +845,6 @@ static int adv7511_parse_dt(struct device_node *np,
780 const char *str; 845 const char *str;
781 int ret; 846 int ret;
782 847
783 memset(config, 0, sizeof(*config));
784
785 of_property_read_u32(np, "adi,input-depth", &config->input_color_depth); 848 of_property_read_u32(np, "adi,input-depth", &config->input_color_depth);
786 if (config->input_color_depth != 8 && config->input_color_depth != 10 && 849 if (config->input_color_depth != 8 && config->input_color_depth != 10 &&
787 config->input_color_depth != 12) 850 config->input_color_depth != 12)
@@ -881,7 +944,17 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
881 adv7511->powered = false; 944 adv7511->powered = false;
882 adv7511->status = connector_status_disconnected; 945 adv7511->status = connector_status_disconnected;
883 946
884 ret = adv7511_parse_dt(dev->of_node, &link_config); 947 if (dev->of_node)
948 adv7511->type = (enum adv7511_type)of_device_get_match_data(dev);
949 else
950 adv7511->type = id->driver_data;
951
952 memset(&link_config, 0, sizeof(link_config));
953
954 if (adv7511->type == ADV7511)
955 ret = adv7511_parse_dt(dev->of_node, &link_config);
956 else
957 ret = adv7533_parse_dt(dev->of_node, adv7511);
885 if (ret) 958 if (ret)
886 return ret; 959 return ret;
887 960
@@ -907,8 +980,12 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
907 return ret; 980 return ret;
908 dev_dbg(dev, "Rev. %d\n", val); 981 dev_dbg(dev, "Rev. %d\n", val);
909 982
910 ret = regmap_register_patch(adv7511->regmap, adv7511_fixed_registers, 983 if (adv7511->type == ADV7511)
911 ARRAY_SIZE(adv7511_fixed_registers)); 984 ret = regmap_register_patch(adv7511->regmap,
985 adv7511_fixed_registers,
986 ARRAY_SIZE(adv7511_fixed_registers));
987 else
988 ret = adv7533_patch_registers(adv7511);
912 if (ret) 989 if (ret)
913 return ret; 990 return ret;
914 991
@@ -923,6 +1000,12 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
923 if (!adv7511->i2c_edid) 1000 if (!adv7511->i2c_edid)
924 return -ENOMEM; 1001 return -ENOMEM;
925 1002
1003 if (adv7511->type == ADV7533) {
1004 ret = adv7533_init_cec(adv7511);
1005 if (ret)
1006 goto err_i2c_unregister_edid;
1007 }
1008
926 if (i2c->irq) { 1009 if (i2c->irq) {
927 init_waitqueue_head(&adv7511->wq); 1010 init_waitqueue_head(&adv7511->wq);
928 1011
@@ -931,7 +1014,7 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
931 IRQF_ONESHOT, dev_name(dev), 1014 IRQF_ONESHOT, dev_name(dev),
932 adv7511); 1015 adv7511);
933 if (ret) 1016 if (ret)
934 goto err_i2c_unregister_device; 1017 goto err_unregister_cec;
935 } 1018 }
936 1019
937 /* CEC is unused for now */ 1020 /* CEC is unused for now */
@@ -942,11 +1025,23 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
942 1025
943 i2c_set_clientdata(i2c, adv7511); 1026 i2c_set_clientdata(i2c, adv7511);
944 1027
945 adv7511_set_link_config(adv7511, &link_config); 1028 if (adv7511->type == ADV7511)
1029 adv7511_set_link_config(adv7511, &link_config);
1030
1031 adv7511->bridge.funcs = &adv7511_bridge_funcs;
1032 adv7511->bridge.of_node = dev->of_node;
1033
1034 ret = drm_bridge_add(&adv7511->bridge);
1035 if (ret) {
1036 dev_err(dev, "failed to add adv7511 bridge\n");
1037 goto err_unregister_cec;
1038 }
946 1039
947 return 0; 1040 return 0;
948 1041
949err_i2c_unregister_device: 1042err_unregister_cec:
1043 adv7533_uninit_cec(adv7511);
1044err_i2c_unregister_edid:
950 i2c_unregister_device(adv7511->i2c_edid); 1045 i2c_unregister_device(adv7511->i2c_edid);
951 1046
952 return ret; 1047 return ret;
@@ -956,66 +1051,71 @@ static int adv7511_remove(struct i2c_client *i2c)
956{ 1051{
957 struct adv7511 *adv7511 = i2c_get_clientdata(i2c); 1052 struct adv7511 *adv7511 = i2c_get_clientdata(i2c);
958 1053
959 i2c_unregister_device(adv7511->i2c_edid); 1054 if (adv7511->type == ADV7533) {
960 1055 adv7533_detach_dsi(adv7511);
961 kfree(adv7511->edid); 1056 adv7533_uninit_cec(adv7511);
962 1057 }
963 return 0;
964}
965
966static int adv7511_encoder_init(struct i2c_client *i2c, struct drm_device *dev,
967 struct drm_encoder_slave *encoder)
968{
969 1058
970 struct adv7511 *adv7511 = i2c_get_clientdata(i2c); 1059 drm_bridge_remove(&adv7511->bridge);
971 1060
972 encoder->slave_priv = adv7511; 1061 i2c_unregister_device(adv7511->i2c_edid);
973 encoder->slave_funcs = &adv7511_encoder_funcs;
974 1062
975 adv7511->encoder = &encoder->base; 1063 kfree(adv7511->edid);
976 1064
977 return 0; 1065 return 0;
978} 1066}
979 1067
980static const struct i2c_device_id adv7511_i2c_ids[] = { 1068static const struct i2c_device_id adv7511_i2c_ids[] = {
981 { "adv7511", 0 }, 1069 { "adv7511", ADV7511 },
982 { "adv7511w", 0 }, 1070 { "adv7511w", ADV7511 },
983 { "adv7513", 0 }, 1071 { "adv7513", ADV7511 },
1072#ifdef CONFIG_DRM_I2C_ADV7533
1073 { "adv7533", ADV7533 },
1074#endif
984 { } 1075 { }
985}; 1076};
986MODULE_DEVICE_TABLE(i2c, adv7511_i2c_ids); 1077MODULE_DEVICE_TABLE(i2c, adv7511_i2c_ids);
987 1078
988static const struct of_device_id adv7511_of_ids[] = { 1079static const struct of_device_id adv7511_of_ids[] = {
989 { .compatible = "adi,adv7511", }, 1080 { .compatible = "adi,adv7511", .data = (void *)ADV7511 },
990 { .compatible = "adi,adv7511w", }, 1081 { .compatible = "adi,adv7511w", .data = (void *)ADV7511 },
991 { .compatible = "adi,adv7513", }, 1082 { .compatible = "adi,adv7513", .data = (void *)ADV7511 },
1083#ifdef CONFIG_DRM_I2C_ADV7533
1084 { .compatible = "adi,adv7533", .data = (void *)ADV7533 },
1085#endif
992 { } 1086 { }
993}; 1087};
994MODULE_DEVICE_TABLE(of, adv7511_of_ids); 1088MODULE_DEVICE_TABLE(of, adv7511_of_ids);
995 1089
996static struct drm_i2c_encoder_driver adv7511_driver = { 1090static struct mipi_dsi_driver adv7533_dsi_driver = {
997 .i2c_driver = { 1091 .driver.name = "adv7533",
998 .driver = { 1092};
999 .name = "adv7511",
1000 .of_match_table = adv7511_of_ids,
1001 },
1002 .id_table = adv7511_i2c_ids,
1003 .probe = adv7511_probe,
1004 .remove = adv7511_remove,
1005 },
1006 1093
1007 .encoder_init = adv7511_encoder_init, 1094static struct i2c_driver adv7511_driver = {
1095 .driver = {
1096 .name = "adv7511",
1097 .of_match_table = adv7511_of_ids,
1098 },
1099 .id_table = adv7511_i2c_ids,
1100 .probe = adv7511_probe,
1101 .remove = adv7511_remove,
1008}; 1102};
1009 1103
1010static int __init adv7511_init(void) 1104static int __init adv7511_init(void)
1011{ 1105{
1012 return drm_i2c_encoder_register(THIS_MODULE, &adv7511_driver); 1106 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1107 mipi_dsi_driver_register(&adv7533_dsi_driver);
1108
1109 return i2c_add_driver(&adv7511_driver);
1013} 1110}
1014module_init(adv7511_init); 1111module_init(adv7511_init);
1015 1112
1016static void __exit adv7511_exit(void) 1113static void __exit adv7511_exit(void)
1017{ 1114{
1018 drm_i2c_encoder_unregister(&adv7511_driver); 1115 i2c_del_driver(&adv7511_driver);
1116
1117 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1118 mipi_dsi_driver_unregister(&adv7533_dsi_driver);
1019} 1119}
1020module_exit(adv7511_exit); 1120module_exit(adv7511_exit);
1021 1121
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7533.c b/drivers/gpu/drm/bridge/adv7511/adv7533.c
new file mode 100644
index 000000000000..5eebd15899b1
--- /dev/null
+++ b/drivers/gpu/drm/bridge/adv7511/adv7533.c
@@ -0,0 +1,265 @@
1/*
2 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/of_graph.h>
15
16#include "adv7511.h"
17
18static const struct reg_sequence adv7533_fixed_registers[] = {
19 { 0x16, 0x20 },
20 { 0x9a, 0xe0 },
21 { 0xba, 0x70 },
22 { 0xde, 0x82 },
23 { 0xe4, 0x40 },
24 { 0xe5, 0x80 },
25};
26
27static const struct reg_sequence adv7533_cec_fixed_registers[] = {
28 { 0x15, 0xd0 },
29 { 0x17, 0xd0 },
30 { 0x24, 0x20 },
31 { 0x57, 0x11 },
32};
33
34static const struct regmap_config adv7533_cec_regmap_config = {
35 .reg_bits = 8,
36 .val_bits = 8,
37
38 .max_register = 0xff,
39 .cache_type = REGCACHE_RBTREE,
40};
41
42static void adv7511_dsi_config_timing_gen(struct adv7511 *adv)
43{
44 struct mipi_dsi_device *dsi = adv->dsi;
45 struct drm_display_mode *mode = &adv->curr_mode;
46 unsigned int hsw, hfp, hbp, vsw, vfp, vbp;
47 u8 clock_div_by_lanes[] = { 6, 4, 3 }; /* 2, 3, 4 lanes */
48
49 hsw = mode->hsync_end - mode->hsync_start;
50 hfp = mode->hsync_start - mode->hdisplay;
51 hbp = mode->htotal - mode->hsync_end;
52 vsw = mode->vsync_end - mode->vsync_start;
53 vfp = mode->vsync_start - mode->vdisplay;
54 vbp = mode->vtotal - mode->vsync_end;
55
56 /* set pixel clock divider mode */
57 regmap_write(adv->regmap_cec, 0x16,
58 clock_div_by_lanes[dsi->lanes - 2] << 3);
59
60 /* horizontal porch params */
61 regmap_write(adv->regmap_cec, 0x28, mode->htotal >> 4);
62 regmap_write(adv->regmap_cec, 0x29, (mode->htotal << 4) & 0xff);
63 regmap_write(adv->regmap_cec, 0x2a, hsw >> 4);
64 regmap_write(adv->regmap_cec, 0x2b, (hsw << 4) & 0xff);
65 regmap_write(adv->regmap_cec, 0x2c, hfp >> 4);
66 regmap_write(adv->regmap_cec, 0x2d, (hfp << 4) & 0xff);
67 regmap_write(adv->regmap_cec, 0x2e, hbp >> 4);
68 regmap_write(adv->regmap_cec, 0x2f, (hbp << 4) & 0xff);
69
70 /* vertical porch params */
71 regmap_write(adv->regmap_cec, 0x30, mode->vtotal >> 4);
72 regmap_write(adv->regmap_cec, 0x31, (mode->vtotal << 4) & 0xff);
73 regmap_write(adv->regmap_cec, 0x32, vsw >> 4);
74 regmap_write(adv->regmap_cec, 0x33, (vsw << 4) & 0xff);
75 regmap_write(adv->regmap_cec, 0x34, vfp >> 4);
76 regmap_write(adv->regmap_cec, 0x35, (vfp << 4) & 0xff);
77 regmap_write(adv->regmap_cec, 0x36, vbp >> 4);
78 regmap_write(adv->regmap_cec, 0x37, (vbp << 4) & 0xff);
79}
80
81void adv7533_dsi_power_on(struct adv7511 *adv)
82{
83 struct mipi_dsi_device *dsi = adv->dsi;
84
85 if (adv->use_timing_gen)
86 adv7511_dsi_config_timing_gen(adv);
87
88 /* set number of dsi lanes */
89 regmap_write(adv->regmap_cec, 0x1c, dsi->lanes << 4);
90
91 if (adv->use_timing_gen) {
92 /* reset internal timing generator */
93 regmap_write(adv->regmap_cec, 0x27, 0xcb);
94 regmap_write(adv->regmap_cec, 0x27, 0x8b);
95 regmap_write(adv->regmap_cec, 0x27, 0xcb);
96 } else {
97 /* disable internal timing generator */
98 regmap_write(adv->regmap_cec, 0x27, 0x0b);
99 }
100
101 /* enable hdmi */
102 regmap_write(adv->regmap_cec, 0x03, 0x89);
103 /* disable test mode */
104 regmap_write(adv->regmap_cec, 0x55, 0x00);
105
106 regmap_register_patch(adv->regmap_cec, adv7533_cec_fixed_registers,
107 ARRAY_SIZE(adv7533_cec_fixed_registers));
108}
109
110void adv7533_dsi_power_off(struct adv7511 *adv)
111{
112 /* disable hdmi */
113 regmap_write(adv->regmap_cec, 0x03, 0x0b);
114 /* disable internal timing generator */
115 regmap_write(adv->regmap_cec, 0x27, 0x0b);
116}
117
118void adv7533_mode_set(struct adv7511 *adv, struct drm_display_mode *mode)
119{
120 struct mipi_dsi_device *dsi = adv->dsi;
121 int lanes, ret;
122
123 if (adv->num_dsi_lanes != 4)
124 return;
125
126 if (mode->clock > 80000)
127 lanes = 4;
128 else
129 lanes = 3;
130
131 if (lanes != dsi->lanes) {
132 mipi_dsi_detach(dsi);
133 dsi->lanes = lanes;
134 ret = mipi_dsi_attach(dsi);
135 if (ret)
136 dev_err(&dsi->dev, "failed to change host lanes\n");
137 }
138}
139
140int adv7533_patch_registers(struct adv7511 *adv)
141{
142 return regmap_register_patch(adv->regmap,
143 adv7533_fixed_registers,
144 ARRAY_SIZE(adv7533_fixed_registers));
145}
146
147void adv7533_uninit_cec(struct adv7511 *adv)
148{
149 i2c_unregister_device(adv->i2c_cec);
150}
151
152static const int cec_i2c_addr = 0x78;
153
154int adv7533_init_cec(struct adv7511 *adv)
155{
156 int ret;
157
158 adv->i2c_cec = i2c_new_dummy(adv->i2c_main->adapter, cec_i2c_addr >> 1);
159 if (!adv->i2c_cec)
160 return -ENOMEM;
161
162 adv->regmap_cec = devm_regmap_init_i2c(adv->i2c_cec,
163 &adv7533_cec_regmap_config);
164 if (IS_ERR(adv->regmap_cec)) {
165 ret = PTR_ERR(adv->regmap_cec);
166 goto err;
167 }
168
169 ret = regmap_register_patch(adv->regmap_cec,
170 adv7533_cec_fixed_registers,
171 ARRAY_SIZE(adv7533_cec_fixed_registers));
172 if (ret)
173 goto err;
174
175 return 0;
176err:
177 adv7533_uninit_cec(adv);
178 return ret;
179}
180
181int adv7533_attach_dsi(struct adv7511 *adv)
182{
183 struct device *dev = &adv->i2c_main->dev;
184 struct mipi_dsi_host *host;
185 struct mipi_dsi_device *dsi;
186 int ret = 0;
187 const struct mipi_dsi_device_info info = { .type = "adv7533",
188 .channel = 0,
189 .node = NULL,
190 };
191
192 host = of_find_mipi_dsi_host_by_node(adv->host_node);
193 if (!host) {
194 dev_err(dev, "failed to find dsi host\n");
195 return -EPROBE_DEFER;
196 }
197
198 dsi = mipi_dsi_device_register_full(host, &info);
199 if (IS_ERR(dsi)) {
200 dev_err(dev, "failed to create dsi device\n");
201 ret = PTR_ERR(dsi);
202 goto err_dsi_device;
203 }
204
205 adv->dsi = dsi;
206
207 dsi->lanes = adv->num_dsi_lanes;
208 dsi->format = MIPI_DSI_FMT_RGB888;
209 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
210 MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;
211
212 ret = mipi_dsi_attach(dsi);
213 if (ret < 0) {
214 dev_err(dev, "failed to attach dsi to host\n");
215 goto err_dsi_attach;
216 }
217
218 return 0;
219
220err_dsi_attach:
221 mipi_dsi_device_unregister(dsi);
222err_dsi_device:
223 return ret;
224}
225
226void adv7533_detach_dsi(struct adv7511 *adv)
227{
228 mipi_dsi_detach(adv->dsi);
229 mipi_dsi_device_unregister(adv->dsi);
230}
231
232int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv)
233{
234 u32 num_lanes;
235 struct device_node *endpoint;
236
237 of_property_read_u32(np, "adi,dsi-lanes", &num_lanes);
238
239 if (num_lanes < 1 || num_lanes > 4)
240 return -EINVAL;
241
242 adv->num_dsi_lanes = num_lanes;
243
244 endpoint = of_graph_get_next_endpoint(np, NULL);
245 if (!endpoint)
246 return -ENODEV;
247
248 adv->host_node = of_graph_get_remote_port_parent(endpoint);
249 if (!adv->host_node) {
250 of_node_put(endpoint);
251 return -ENODEV;
252 }
253
254 of_node_put(endpoint);
255 of_node_put(adv->host_node);
256
257 adv->use_timing_gen = !of_property_read_bool(np,
258 "adi,disable-timing-generator");
259
260 /* TODO: Check if these need to be parsed by DT or not */
261 adv->rgb = true;
262 adv->embedded_sync = false;
263
264 return 0;
265}
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
new file mode 100644
index 000000000000..a09825d8c94a
--- /dev/null
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -0,0 +1,1413 @@
1/*
2 * tc358767 eDP bridge driver
3 *
4 * Copyright (C) 2016 CogentEmbedded Inc
5 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
6 *
7 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
8 *
9 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
10 *
11 * Copyright (C) 2012 Texas Instruments
12 * Author: Rob Clark <robdclark@gmail.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 */
24
25#include <linux/clk.h>
26#include <linux/device.h>
27#include <linux/gpio/consumer.h>
28#include <linux/i2c.h>
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/regmap.h>
32#include <linux/slab.h>
33
34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_dp_helper.h>
37#include <drm/drm_edid.h>
38#include <drm/drm_of.h>
39#include <drm/drm_panel.h>
40
41/* Registers */
42
43/* Display Parallel Interface */
44#define DPIPXLFMT 0x0440
45#define VS_POL_ACTIVE_LOW (1 << 10)
46#define HS_POL_ACTIVE_LOW (1 << 9)
47#define DE_POL_ACTIVE_HIGH (0 << 8)
48#define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */
49#define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */
50#define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
51#define DPI_BPP_RGB888 (0 << 0)
52#define DPI_BPP_RGB666 (1 << 0)
53#define DPI_BPP_RGB565 (2 << 0)
54
55/* Video Path */
56#define VPCTRL0 0x0450
57#define OPXLFMT_RGB666 (0 << 8)
58#define OPXLFMT_RGB888 (1 << 8)
59#define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
60#define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
61#define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
62#define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
63#define HTIM01 0x0454
64#define HTIM02 0x0458
65#define VTIM01 0x045c
66#define VTIM02 0x0460
67#define VFUEN0 0x0464
68#define VFUEN BIT(0) /* Video Frame Timing Upload */
69
70/* System */
71#define TC_IDREG 0x0500
72#define SYSCTRL 0x0510
73#define DP0_AUDSRC_NO_INPUT (0 << 3)
74#define DP0_AUDSRC_I2S_RX (1 << 3)
75#define DP0_VIDSRC_NO_INPUT (0 << 0)
76#define DP0_VIDSRC_DSI_RX (1 << 0)
77#define DP0_VIDSRC_DPI_RX (2 << 0)
78#define DP0_VIDSRC_COLOR_BAR (3 << 0)
79
80/* Control */
81#define DP0CTL 0x0600
82#define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
83#define EF_EN BIT(5) /* Enable Enhanced Framing */
84#define VID_EN BIT(1) /* Video transmission enable */
85#define DP_EN BIT(0) /* Enable DPTX function */
86
87/* Clocks */
88#define DP0_VIDMNGEN0 0x0610
89#define DP0_VIDMNGEN1 0x0614
90#define DP0_VMNGENSTATUS 0x0618
91
92/* Main Channel */
93#define DP0_SECSAMPLE 0x0640
94#define DP0_VIDSYNCDELAY 0x0644
95#define DP0_TOTALVAL 0x0648
96#define DP0_STARTVAL 0x064c
97#define DP0_ACTIVEVAL 0x0650
98#define DP0_SYNCVAL 0x0654
99#define DP0_MISC 0x0658
100#define TU_SIZE_RECOMMENDED (0x3f << 16) /* LSCLK cycles per TU */
101#define BPC_6 (0 << 5)
102#define BPC_8 (1 << 5)
103
104/* AUX channel */
105#define DP0_AUXCFG0 0x0660
106#define DP0_AUXCFG1 0x0664
107#define AUX_RX_FILTER_EN BIT(16)
108
109#define DP0_AUXADDR 0x0668
110#define DP0_AUXWDATA(i) (0x066c + (i) * 4)
111#define DP0_AUXRDATA(i) (0x067c + (i) * 4)
112#define DP0_AUXSTATUS 0x068c
113#define AUX_STATUS_MASK 0xf0
114#define AUX_STATUS_SHIFT 4
115#define AUX_TIMEOUT BIT(1)
116#define AUX_BUSY BIT(0)
117#define DP0_AUXI2CADR 0x0698
118
119/* Link Training */
120#define DP0_SRCCTRL 0x06a0
121#define DP0_SRCCTRL_SCRMBLDIS BIT(13)
122#define DP0_SRCCTRL_EN810B BIT(12)
123#define DP0_SRCCTRL_NOTP (0 << 8)
124#define DP0_SRCCTRL_TP1 (1 << 8)
125#define DP0_SRCCTRL_TP2 (2 << 8)
126#define DP0_SRCCTRL_LANESKEW BIT(7)
127#define DP0_SRCCTRL_SSCG BIT(3)
128#define DP0_SRCCTRL_LANES_1 (0 << 2)
129#define DP0_SRCCTRL_LANES_2 (1 << 2)
130#define DP0_SRCCTRL_BW27 (1 << 1)
131#define DP0_SRCCTRL_BW162 (0 << 1)
132#define DP0_SRCCTRL_AUTOCORRECT BIT(0)
133#define DP0_LTSTAT 0x06d0
134#define LT_LOOPDONE BIT(13)
135#define LT_STATUS_MASK (0x1f << 8)
136#define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
137#define LT_INTERLANE_ALIGN_DONE BIT(3)
138#define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
139#define DP0_SNKLTCHGREQ 0x06d4
140#define DP0_LTLOOPCTRL 0x06d8
141#define DP0_SNKLTCTRL 0x06e4
142
143/* PHY */
144#define DP_PHY_CTRL 0x0800
145#define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
146#define BGREN BIT(25) /* AUX PHY BGR Enable */
147#define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
148#define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
149#define PHY_RDY BIT(16) /* PHY Main Channels Ready */
150#define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
151#define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
152#define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
153
154/* PLL */
155#define DP0_PLLCTRL 0x0900
156#define DP1_PLLCTRL 0x0904 /* not defined in DS */
157#define PXL_PLLCTRL 0x0908
158#define PLLUPDATE BIT(2)
159#define PLLBYP BIT(1)
160#define PLLEN BIT(0)
161#define PXL_PLLPARAM 0x0914
162#define IN_SEL_REFCLK (0 << 14)
163#define SYS_PLLPARAM 0x0918
164#define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */
165#define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */
166#define REF_FREQ_26M (2 << 8) /* 26 MHz */
167#define REF_FREQ_13M (3 << 8) /* 13 MHz */
168#define SYSCLK_SEL_LSCLK (0 << 4)
169#define LSCLK_DIV_1 (0 << 0)
170#define LSCLK_DIV_2 (1 << 0)
171
172/* Test & Debug */
173#define TSTCTL 0x0a00
174#define PLL_DBG 0x0a04
175
176static bool tc_test_pattern;
177module_param_named(test, tc_test_pattern, bool, 0644);
178
179struct tc_edp_link {
180 struct drm_dp_link base;
181 u8 assr;
182 int scrambler_dis;
183 int spread;
184 int coding8b10b;
185 u8 swing;
186 u8 preemp;
187};
188
189struct tc_data {
190 struct device *dev;
191 struct regmap *regmap;
192 struct drm_dp_aux aux;
193
194 struct drm_bridge bridge;
195 struct drm_connector connector;
196 struct drm_panel *panel;
197
198 /* link settings */
199 struct tc_edp_link link;
200
201 /* display edid */
202 struct edid *edid;
203 /* current mode */
204 struct drm_display_mode *mode;
205
206 u32 rev;
207 u8 assr;
208
209 struct gpio_desc *sd_gpio;
210 struct gpio_desc *reset_gpio;
211 struct clk *refclk;
212};
213
214static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
215{
216 return container_of(a, struct tc_data, aux);
217}
218
219static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
220{
221 return container_of(b, struct tc_data, bridge);
222}
223
224static inline struct tc_data *connector_to_tc(struct drm_connector *c)
225{
226 return container_of(c, struct tc_data, connector);
227}
228
229/* Simple macros to avoid repeated error checks */
230#define tc_write(reg, var) \
231 do { \
232 ret = regmap_write(tc->regmap, reg, var); \
233 if (ret) \
234 goto err; \
235 } while (0)
236#define tc_read(reg, var) \
237 do { \
238 ret = regmap_read(tc->regmap, reg, var); \
239 if (ret) \
240 goto err; \
241 } while (0)
242
243static inline int tc_poll_timeout(struct regmap *map, unsigned int addr,
244 unsigned int cond_mask,
245 unsigned int cond_value,
246 unsigned long sleep_us, u64 timeout_us)
247{
248 ktime_t timeout = ktime_add_us(ktime_get(), timeout_us);
249 unsigned int val;
250 int ret;
251
252 for (;;) {
253 ret = regmap_read(map, addr, &val);
254 if (ret)
255 break;
256 if ((val & cond_mask) == cond_value)
257 break;
258 if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) {
259 ret = regmap_read(map, addr, &val);
260 break;
261 }
262 if (sleep_us)
263 usleep_range((sleep_us >> 2) + 1, sleep_us);
264 }
265 return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT);
266}
267
268static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms)
269{
270 return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0,
271 1000, 1000 * timeout_ms);
272}
273
274static int tc_aux_get_status(struct tc_data *tc, u8 *reply)
275{
276 int ret;
277 u32 value;
278
279 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value);
280 if (ret < 0)
281 return ret;
282 if (value & AUX_BUSY) {
283 if (value & AUX_TIMEOUT) {
284 dev_err(tc->dev, "i2c access timeout!\n");
285 return -ETIMEDOUT;
286 }
287 return -EBUSY;
288 }
289
290 *reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT;
291 return 0;
292}
293
294static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
295 struct drm_dp_aux_msg *msg)
296{
297 struct tc_data *tc = aux_to_tc(aux);
298 size_t size = min_t(size_t, 8, msg->size);
299 u8 request = msg->request & ~DP_AUX_I2C_MOT;
300 u8 *buf = msg->buffer;
301 u32 tmp = 0;
302 int i = 0;
303 int ret;
304
305 if (size == 0)
306 return 0;
307
308 ret = tc_aux_wait_busy(tc, 100);
309 if (ret)
310 goto err;
311
312 if (request == DP_AUX_I2C_WRITE || request == DP_AUX_NATIVE_WRITE) {
313 /* Store data */
314 while (i < size) {
315 if (request == DP_AUX_NATIVE_WRITE)
316 tmp = tmp | (buf[i] << (8 * (i & 0x3)));
317 else
318 tmp = (tmp << 8) | buf[i];
319 i++;
320 if (((i % 4) == 0) || (i == size)) {
321 tc_write(DP0_AUXWDATA(i >> 2), tmp);
322 tmp = 0;
323 }
324 }
325 } else if (request != DP_AUX_I2C_READ &&
326 request != DP_AUX_NATIVE_READ) {
327 return -EINVAL;
328 }
329
330 /* Store address */
331 tc_write(DP0_AUXADDR, msg->address);
332 /* Start transfer */
333 tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request);
334
335 ret = tc_aux_wait_busy(tc, 100);
336 if (ret)
337 goto err;
338
339 ret = tc_aux_get_status(tc, &msg->reply);
340 if (ret)
341 goto err;
342
343 if (request == DP_AUX_I2C_READ || request == DP_AUX_NATIVE_READ) {
344 /* Read data */
345 while (i < size) {
346 if ((i % 4) == 0)
347 tc_read(DP0_AUXRDATA(i >> 2), &tmp);
348 buf[i] = tmp & 0xff;
349 tmp = tmp >> 8;
350 i++;
351 }
352 }
353
354 return size;
355err:
356 return ret;
357}
358
359static const char * const training_pattern1_errors[] = {
360 "No errors",
361 "Aux write error",
362 "Aux read error",
363 "Max voltage reached error",
364 "Loop counter expired error",
365 "res", "res", "res"
366};
367
368static const char * const training_pattern2_errors[] = {
369 "No errors",
370 "Aux write error",
371 "Aux read error",
372 "Clock recovery failed error",
373 "Loop counter expired error",
374 "res", "res", "res"
375};
376
377static u32 tc_srcctrl(struct tc_data *tc)
378{
379 /*
380 * No training pattern, skew lane 1 data by two LSCLK cycles with
381 * respect to lane 0 data, AutoCorrect Mode = 0
382 */
383 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW;
384
385 if (tc->link.scrambler_dis)
386 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */
387 if (tc->link.coding8b10b)
388 /* Enable 8/10B Encoder (TxData[19:16] not used) */
389 reg |= DP0_SRCCTRL_EN810B;
390 if (tc->link.spread)
391 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */
392 if (tc->link.base.num_lanes == 2)
393 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
394 if (tc->link.base.rate != 162000)
395 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */
396 return reg;
397}
398
399static void tc_wait_pll_lock(struct tc_data *tc)
400{
401 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
402 usleep_range(3000, 6000);
403}
404
405static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
406{
407 int ret;
408 int i_pre, best_pre = 1;
409 int i_post, best_post = 1;
410 int div, best_div = 1;
411 int mul, best_mul = 1;
412 int delta, best_delta;
413 int ext_div[] = {1, 2, 3, 5, 7};
414 int best_pixelclock = 0;
415 int vco_hi = 0;
416
417 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
418 refclk);
419 best_delta = pixelclock;
420 /* Loop over all possible ext_divs, skipping invalid configurations */
421 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
422 /*
423 * refclk / ext_pre_div should be in the 1 to 200 MHz range.
424 * We don't allow any refclk > 200 MHz, only check lower bounds.
425 */
426 if (refclk / ext_div[i_pre] < 1000000)
427 continue;
428 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
429 for (div = 1; div <= 16; div++) {
430 u32 clk;
431 u64 tmp;
432
433 tmp = pixelclock * ext_div[i_pre] *
434 ext_div[i_post] * div;
435 do_div(tmp, refclk);
436 mul = tmp;
437
438 /* Check limits */
439 if ((mul < 1) || (mul > 128))
440 continue;
441
442 clk = (refclk / ext_div[i_pre] / div) * mul;
443 /*
444 * refclk * mul / (ext_pre_div * pre_div)
445 * should be in the 150 to 650 MHz range
446 */
447 if ((clk > 650000000) || (clk < 150000000))
448 continue;
449
450 clk = clk / ext_div[i_post];
451 delta = clk - pixelclock;
452
453 if (abs(delta) < abs(best_delta)) {
454 best_pre = i_pre;
455 best_post = i_post;
456 best_div = div;
457 best_mul = mul;
458 best_delta = delta;
459 best_pixelclock = clk;
460 }
461 }
462 }
463 }
464 if (best_pixelclock == 0) {
465 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
466 pixelclock);
467 return -EINVAL;
468 }
469
470 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
471 best_delta);
472 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
473 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
474
475 /* if VCO >= 300 MHz */
476 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
477 vco_hi = 1;
478 /* see DS */
479 if (best_div == 16)
480 best_div = 0;
481 if (best_mul == 128)
482 best_mul = 0;
483
484 /* Power up PLL and switch to bypass */
485 tc_write(PXL_PLLCTRL, PLLBYP | PLLEN);
486
487 tc_write(PXL_PLLPARAM,
488 (vco_hi << 24) | /* For PLL VCO >= 300 MHz = 1 */
489 (ext_div[best_pre] << 20) | /* External Pre-divider */
490 (ext_div[best_post] << 16) | /* External Post-divider */
491 IN_SEL_REFCLK | /* Use RefClk as PLL input */
492 (best_div << 8) | /* Divider for PLL RefClk */
493 (best_mul << 0)); /* Multiplier for PLL */
494
495 /* Force PLL parameter update and disable bypass */
496 tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN);
497
498 tc_wait_pll_lock(tc);
499
500 return 0;
501err:
502 return ret;
503}
504
505static int tc_pxl_pll_dis(struct tc_data *tc)
506{
507 /* Enable PLL bypass, power down PLL */
508 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
509}
510
511static int tc_stream_clock_calc(struct tc_data *tc)
512{
513 int ret;
514 /*
515 * If the Stream clock and Link Symbol clock are
516 * asynchronous with each other, the value of M changes over
517 * time. This way of generating link clock and stream
518 * clock is called Asynchronous Clock mode. The value M
519 * must change while the value N stays constant. The
520 * value of N in this Asynchronous Clock mode must be set
521 * to 2^15 or 32,768.
522 *
523 * LSCLK = 1/10 of high speed link clock
524 *
525 * f_STRMCLK = M/N * f_LSCLK
526 * M/N = f_STRMCLK / f_LSCLK
527 *
528 */
529 tc_write(DP0_VIDMNGEN1, 32768);
530
531 return 0;
532err:
533 return ret;
534}
535
536static int tc_aux_link_setup(struct tc_data *tc)
537{
538 unsigned long rate;
539 u32 value;
540 int ret;
541
542 rate = clk_get_rate(tc->refclk);
543 switch (rate) {
544 case 38400000:
545 value = REF_FREQ_38M4;
546 break;
547 case 26000000:
548 value = REF_FREQ_26M;
549 break;
550 case 19200000:
551 value = REF_FREQ_19M2;
552 break;
553 case 13000000:
554 value = REF_FREQ_13M;
555 break;
556 default:
557 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
558 return -EINVAL;
559 }
560
561 /* Setup DP-PHY / PLL */
562 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
563 tc_write(SYS_PLLPARAM, value);
564
565 tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN);
566
567 /*
568 * Initially PLLs are in bypass. Force PLL parameter update,
569 * disable PLL bypass, enable PLL
570 */
571 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
572 tc_wait_pll_lock(tc);
573
574 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
575 tc_wait_pll_lock(tc);
576
577 ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1,
578 1000);
579 if (ret == -ETIMEDOUT) {
580 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
581 return ret;
582 } else if (ret)
583 goto err;
584
585 /* Setup AUX link */
586 tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN |
587 (0x06 << 8) | /* Aux Bit Period Calculator Threshold */
588 (0x3f << 0)); /* Aux Response Timeout Timer */
589
590 return 0;
591err:
592 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
593 return ret;
594}
595
596static int tc_get_display_props(struct tc_data *tc)
597{
598 int ret;
599 /* temp buffer */
600 u8 tmp[8];
601
602 /* Read DP Rx Link Capability */
603 ret = drm_dp_link_probe(&tc->aux, &tc->link.base);
604 if (ret < 0)
605 goto err_dpcd_read;
606 if ((tc->link.base.rate != 162000) && (tc->link.base.rate != 270000))
607 goto err_dpcd_inval;
608
609 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp);
610 if (ret < 0)
611 goto err_dpcd_read;
612 tc->link.spread = tmp[0] & BIT(0); /* 0.5% down spread */
613
614 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp);
615 if (ret < 0)
616 goto err_dpcd_read;
617 tc->link.coding8b10b = tmp[0] & BIT(0);
618 tc->link.scrambler_dis = 0;
619 /* read assr */
620 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp);
621 if (ret < 0)
622 goto err_dpcd_read;
623 tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
624
625 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
626 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f,
627 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
628 tc->link.base.num_lanes,
629 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ?
630 "enhanced" : "non-enhanced");
631 dev_dbg(tc->dev, "ANSI 8B/10B: %d\n", tc->link.coding8b10b);
632 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
633 tc->link.assr, tc->assr);
634
635 return 0;
636
637err_dpcd_read:
638 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
639 return ret;
640err_dpcd_inval:
641 dev_err(tc->dev, "invalid DPCD\n");
642 return -EINVAL;
643}
644
645static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
646{
647 int ret;
648 int vid_sync_dly;
649 int max_tu_symbol;
650
651 int left_margin = mode->htotal - mode->hsync_end;
652 int right_margin = mode->hsync_start - mode->hdisplay;
653 int hsync_len = mode->hsync_end - mode->hsync_start;
654 int upper_margin = mode->vtotal - mode->vsync_end;
655 int lower_margin = mode->vsync_start - mode->vdisplay;
656 int vsync_len = mode->vsync_end - mode->vsync_start;
657
658 dev_dbg(tc->dev, "set mode %dx%d\n",
659 mode->hdisplay, mode->vdisplay);
660 dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
661 left_margin, right_margin, hsync_len);
662 dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
663 upper_margin, lower_margin, vsync_len);
664 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
665
666
667 /* LCD Ctl Frame Size */
668 tc_write(VPCTRL0, (0x40 << 20) /* VSDELAY */ |
669 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
670 tc_write(HTIM01, (left_margin << 16) | /* H back porch */
671 (hsync_len << 0)); /* Hsync */
672 tc_write(HTIM02, (right_margin << 16) | /* H front porch */
673 (mode->hdisplay << 0)); /* width */
674 tc_write(VTIM01, (upper_margin << 16) | /* V back porch */
675 (vsync_len << 0)); /* Vsync */
676 tc_write(VTIM02, (lower_margin << 16) | /* V front porch */
677 (mode->vdisplay << 0)); /* height */
678 tc_write(VFUEN0, VFUEN); /* update settings */
679
680 /* Test pattern settings */
681 tc_write(TSTCTL,
682 (120 << 24) | /* Red Color component value */
683 (20 << 16) | /* Green Color component value */
684 (99 << 8) | /* Blue Color component value */
685 (1 << 4) | /* Enable I2C Filter */
686 (2 << 0) | /* Color bar Mode */
687 0);
688
689 /* DP Main Stream Attributes */
690 vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
691 tc_write(DP0_VIDSYNCDELAY,
692 (0x003e << 16) | /* thresh_dly */
693 (vid_sync_dly << 0));
694
695 tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal));
696
697 tc_write(DP0_STARTVAL,
698 ((upper_margin + vsync_len) << 16) |
699 ((left_margin + hsync_len) << 0));
700
701 tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay));
702
703 tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0));
704
705 tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
706 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
707
708 /*
709 * Recommended maximum number of symbols transferred in a transfer unit:
710 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
711 * (output active video bandwidth in bytes))
712 * Must be less than tu_size.
713 */
714 max_tu_symbol = TU_SIZE_RECOMMENDED - 1;
715 tc_write(DP0_MISC, (max_tu_symbol << 23) | TU_SIZE_RECOMMENDED | BPC_8);
716
717 return 0;
718err:
719 return ret;
720}
721
722static int tc_link_training(struct tc_data *tc, int pattern)
723{
724 const char * const *errors;
725 u32 srcctrl = tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
726 DP0_SRCCTRL_AUTOCORRECT;
727 int timeout;
728 int retry;
729 u32 value;
730 int ret;
731
732 if (pattern == DP_TRAINING_PATTERN_1) {
733 srcctrl |= DP0_SRCCTRL_TP1;
734 errors = training_pattern1_errors;
735 } else {
736 srcctrl |= DP0_SRCCTRL_TP2;
737 errors = training_pattern2_errors;
738 }
739
740 /* Set DPCD 0x102 for Training Part 1 or 2 */
741 tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | pattern);
742
743 tc_write(DP0_LTLOOPCTRL,
744 (0x0f << 28) | /* Defer Iteration Count */
745 (0x0f << 24) | /* Loop Iteration Count */
746 (0x0d << 0)); /* Loop Timer Delay */
747
748 retry = 5;
749 do {
750 /* Set DP0 Training Pattern */
751 tc_write(DP0_SRCCTRL, srcctrl);
752
753 /* Enable DP0 to start Link Training */
754 tc_write(DP0CTL, DP_EN);
755
756 /* wait */
757 timeout = 1000;
758 do {
759 tc_read(DP0_LTSTAT, &value);
760 udelay(1);
761 } while ((!(value & LT_LOOPDONE)) && (--timeout));
762 if (timeout == 0) {
763 dev_err(tc->dev, "Link training timeout!\n");
764 } else {
765 int pattern = (value >> 11) & 0x3;
766 int error = (value >> 8) & 0x7;
767
768 dev_dbg(tc->dev,
769 "Link training phase %d done after %d uS: %s\n",
770 pattern, 1000 - timeout, errors[error]);
771 if (pattern == DP_TRAINING_PATTERN_1 && error == 0)
772 break;
773 if (pattern == DP_TRAINING_PATTERN_2) {
774 value &= LT_CHANNEL1_EQ_BITS |
775 LT_INTERLANE_ALIGN_DONE |
776 LT_CHANNEL0_EQ_BITS;
777 /* in case of two lanes */
778 if ((tc->link.base.num_lanes == 2) &&
779 (value == (LT_CHANNEL1_EQ_BITS |
780 LT_INTERLANE_ALIGN_DONE |
781 LT_CHANNEL0_EQ_BITS)))
782 break;
783 /* in case of one line */
784 if ((tc->link.base.num_lanes == 1) &&
785 (value == (LT_INTERLANE_ALIGN_DONE |
786 LT_CHANNEL0_EQ_BITS)))
787 break;
788 }
789 }
790 /* restart */
791 tc_write(DP0CTL, 0);
792 usleep_range(10, 20);
793 } while (--retry);
794 if (retry == 0) {
795 dev_err(tc->dev, "Failed to finish training phase %d\n",
796 pattern);
797 }
798
799 return 0;
800err:
801 return ret;
802}
803
804static int tc_main_link_setup(struct tc_data *tc)
805{
806 struct drm_dp_aux *aux = &tc->aux;
807 struct device *dev = tc->dev;
808 unsigned int rate;
809 u32 dp_phy_ctrl;
810 int timeout;
811 bool aligned;
812 bool ready;
813 u32 value;
814 int ret;
815 u8 tmp[8];
816
817 /* display mode should be set at this point */
818 if (!tc->mode)
819 return -EINVAL;
820
821 /* from excel file - DP0_SrcCtrl */
822 tc_write(DP0_SRCCTRL, DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_EN810B |
823 DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_LANES_2 |
824 DP0_SRCCTRL_BW27 | DP0_SRCCTRL_AUTOCORRECT);
825 /* from excel file - DP1_SrcCtrl */
826 tc_write(0x07a0, 0x00003083);
827
828 rate = clk_get_rate(tc->refclk);
829 switch (rate) {
830 case 38400000:
831 value = REF_FREQ_38M4;
832 break;
833 case 26000000:
834 value = REF_FREQ_26M;
835 break;
836 case 19200000:
837 value = REF_FREQ_19M2;
838 break;
839 case 13000000:
840 value = REF_FREQ_13M;
841 break;
842 default:
843 return -EINVAL;
844 }
845 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
846 tc_write(SYS_PLLPARAM, value);
847 /* Setup Main Link */
848 dp_phy_ctrl = BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN | PHY_M0_EN;
849 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
850 msleep(100);
851
852 /* PLL setup */
853 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
854 tc_wait_pll_lock(tc);
855
856 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
857 tc_wait_pll_lock(tc);
858
859 /* PXL PLL setup */
860 if (tc_test_pattern) {
861 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
862 1000 * tc->mode->clock);
863 if (ret)
864 goto err;
865 }
866
867 /* Reset/Enable Main Links */
868 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
869 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
870 usleep_range(100, 200);
871 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
872 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
873
874 timeout = 1000;
875 do {
876 tc_read(DP_PHY_CTRL, &value);
877 udelay(1);
878 } while ((!(value & PHY_RDY)) && (--timeout));
879
880 if (timeout == 0) {
881 dev_err(dev, "timeout waiting for phy become ready");
882 return -ETIMEDOUT;
883 }
884
885 /* Set misc: 8 bits per color */
886 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
887 if (ret)
888 goto err;
889
890 /*
891 * ASSR mode
892 * on TC358767 side ASSR configured through strap pin
893 * seems there is no way to change this setting from SW
894 *
895 * check is tc configured for same mode
896 */
897 if (tc->assr != tc->link.assr) {
898 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
899 tc->assr);
900 /* try to set ASSR on display side */
901 tmp[0] = tc->assr;
902 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
903 if (ret < 0)
904 goto err_dpcd_read;
905 /* read back */
906 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
907 if (ret < 0)
908 goto err_dpcd_read;
909
910 if (tmp[0] != tc->assr) {
911 dev_warn(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
912 tc->assr);
913 /* trying with disabled scrambler */
914 tc->link.scrambler_dis = 1;
915 }
916 }
917
918 /* Setup Link & DPRx Config for Training */
919 ret = drm_dp_link_configure(aux, &tc->link.base);
920 if (ret < 0)
921 goto err_dpcd_write;
922
923 /* DOWNSPREAD_CTRL */
924 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
925 /* MAIN_LINK_CHANNEL_CODING_SET */
926 tmp[1] = tc->link.coding8b10b ? DP_SET_ANSI_8B10B : 0x00;
927 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
928 if (ret < 0)
929 goto err_dpcd_write;
930
931 ret = tc_link_training(tc, DP_TRAINING_PATTERN_1);
932 if (ret)
933 goto err;
934
935 ret = tc_link_training(tc, DP_TRAINING_PATTERN_2);
936 if (ret)
937 goto err;
938
939 /* Clear DPCD 0x102 */
940 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
941 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
942 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
943 if (ret < 0)
944 goto err_dpcd_write;
945
946 /* Clear Training Pattern, set AutoCorrect Mode = 1 */
947 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT);
948
949 /* Wait */
950 timeout = 100;
951 do {
952 udelay(1);
953 /* Read DPCD 0x202-0x207 */
954 ret = drm_dp_dpcd_read_link_status(aux, tmp + 2);
955 if (ret < 0)
956 goto err_dpcd_read;
957 ready = (tmp[2] == ((DP_CHANNEL_EQ_BITS << 4) | /* Lane1 */
958 DP_CHANNEL_EQ_BITS)); /* Lane0 */
959 aligned = tmp[4] & DP_INTERLANE_ALIGN_DONE;
960 } while ((--timeout) && !(ready && aligned));
961
962 if (timeout == 0) {
963 /* Read DPCD 0x200-0x201 */
964 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT, tmp, 2);
965 if (ret < 0)
966 goto err_dpcd_read;
967 dev_info(dev, "0x0200 SINK_COUNT: 0x%02x\n", tmp[0]);
968 dev_info(dev, "0x0201 DEVICE_SERVICE_IRQ_VECTOR: 0x%02x\n",
969 tmp[1]);
970 dev_info(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[2]);
971 dev_info(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n",
972 tmp[4]);
973 dev_info(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[5]);
974 dev_info(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n",
975 tmp[6]);
976
977 if (!ready)
978 dev_err(dev, "Lane0/1 not ready\n");
979 if (!aligned)
980 dev_err(dev, "Lane0/1 not aligned\n");
981 return -EAGAIN;
982 }
983
984 ret = tc_set_video_mode(tc, tc->mode);
985 if (ret)
986 goto err;
987
988 /* Set M/N */
989 ret = tc_stream_clock_calc(tc);
990 if (ret)
991 goto err;
992
993 return 0;
994err_dpcd_read:
995 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
996 return ret;
997err_dpcd_write:
998 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
999err:
1000 return ret;
1001}
1002
1003static int tc_main_link_stream(struct tc_data *tc, int state)
1004{
1005 int ret;
1006 u32 value;
1007
1008 dev_dbg(tc->dev, "stream: %d\n", state);
1009
1010 if (state) {
1011 value = VID_MN_GEN | DP_EN;
1012 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1013 value |= EF_EN;
1014 tc_write(DP0CTL, value);
1015 /*
1016 * VID_EN assertion should be delayed by at least N * LSCLK
1017 * cycles from the time VID_MN_GEN is enabled in order to
1018 * generate stable values for VID_M. LSCLK is 270 MHz or
1019 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1020 * so a delay of at least 203 us should suffice.
1021 */
1022 usleep_range(500, 1000);
1023 value |= VID_EN;
1024 tc_write(DP0CTL, value);
1025 /* Set input interface */
1026 value = DP0_AUDSRC_NO_INPUT;
1027 if (tc_test_pattern)
1028 value |= DP0_VIDSRC_COLOR_BAR;
1029 else
1030 value |= DP0_VIDSRC_DPI_RX;
1031 tc_write(SYSCTRL, value);
1032 } else {
1033 tc_write(DP0CTL, 0);
1034 }
1035
1036 return 0;
1037err:
1038 return ret;
1039}
1040
1041static enum drm_connector_status
1042tc_connector_detect(struct drm_connector *connector, bool force)
1043{
1044 return connector_status_connected;
1045}
1046
1047static void tc_bridge_pre_enable(struct drm_bridge *bridge)
1048{
1049 struct tc_data *tc = bridge_to_tc(bridge);
1050
1051 drm_panel_prepare(tc->panel);
1052}
1053
1054static void tc_bridge_enable(struct drm_bridge *bridge)
1055{
1056 struct tc_data *tc = bridge_to_tc(bridge);
1057 int ret;
1058
1059 ret = tc_main_link_setup(tc);
1060 if (ret < 0) {
1061 dev_err(tc->dev, "main link setup error: %d\n", ret);
1062 return;
1063 }
1064
1065 ret = tc_main_link_stream(tc, 1);
1066 if (ret < 0) {
1067 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1068 return;
1069 }
1070
1071 drm_panel_enable(tc->panel);
1072}
1073
1074static void tc_bridge_disable(struct drm_bridge *bridge)
1075{
1076 struct tc_data *tc = bridge_to_tc(bridge);
1077 int ret;
1078
1079 drm_panel_disable(tc->panel);
1080
1081 ret = tc_main_link_stream(tc, 0);
1082 if (ret < 0)
1083 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1084}
1085
1086static void tc_bridge_post_disable(struct drm_bridge *bridge)
1087{
1088 struct tc_data *tc = bridge_to_tc(bridge);
1089
1090 drm_panel_unprepare(tc->panel);
1091}
1092
1093static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
1094 const struct drm_display_mode *mode,
1095 struct drm_display_mode *adj)
1096{
1097 /* Fixup sync polarities, both hsync and vsync are active low */
1098 adj->flags = mode->flags;
1099 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1100 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1101
1102 return true;
1103}
1104
1105static int tc_connector_mode_valid(struct drm_connector *connector,
1106 struct drm_display_mode *mode)
1107{
1108 /* Accept any mode */
1109 return MODE_OK;
1110}
1111
1112static void tc_bridge_mode_set(struct drm_bridge *bridge,
1113 struct drm_display_mode *mode,
1114 struct drm_display_mode *adj)
1115{
1116 struct tc_data *tc = bridge_to_tc(bridge);
1117
1118 tc->mode = mode;
1119}
1120
1121static int tc_connector_get_modes(struct drm_connector *connector)
1122{
1123 struct tc_data *tc = connector_to_tc(connector);
1124 struct edid *edid;
1125 unsigned int count;
1126
1127 if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) {
1128 count = tc->panel->funcs->get_modes(tc->panel);
1129 if (count > 0)
1130 return count;
1131 }
1132
1133 edid = drm_get_edid(connector, &tc->aux.ddc);
1134
1135 kfree(tc->edid);
1136 tc->edid = edid;
1137 if (!edid)
1138 return 0;
1139
1140 drm_mode_connector_update_edid_property(connector, edid);
1141 count = drm_add_edid_modes(connector, edid);
1142
1143 return count;
1144}
1145
1146static void tc_connector_set_polling(struct tc_data *tc,
1147 struct drm_connector *connector)
1148{
1149 /* TODO: add support for HPD */
1150 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1151 DRM_CONNECTOR_POLL_DISCONNECT;
1152}
1153
1154static struct drm_encoder *
1155tc_connector_best_encoder(struct drm_connector *connector)
1156{
1157 struct tc_data *tc = connector_to_tc(connector);
1158
1159 return tc->bridge.encoder;
1160}
1161
1162static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1163 .get_modes = tc_connector_get_modes,
1164 .mode_valid = tc_connector_mode_valid,
1165 .best_encoder = tc_connector_best_encoder,
1166};
1167
1168static void tc_connector_destroy(struct drm_connector *connector)
1169{
1170 drm_connector_unregister(connector);
1171 drm_connector_cleanup(connector);
1172}
1173
1174static const struct drm_connector_funcs tc_connector_funcs = {
1175 .dpms = drm_atomic_helper_connector_dpms,
1176 .fill_modes = drm_helper_probe_single_connector_modes,
1177 .detect = tc_connector_detect,
1178 .destroy = tc_connector_destroy,
1179 .reset = drm_atomic_helper_connector_reset,
1180 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1181 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1182};
1183
1184static int tc_bridge_attach(struct drm_bridge *bridge)
1185{
1186 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1187 struct tc_data *tc = bridge_to_tc(bridge);
1188 struct drm_device *drm = bridge->dev;
1189 int ret;
1190
1191 /* Create eDP connector */
1192 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1193 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
1194 DRM_MODE_CONNECTOR_eDP);
1195 if (ret)
1196 return ret;
1197
1198 if (tc->panel)
1199 drm_panel_attach(tc->panel, &tc->connector);
1200
1201 drm_display_info_set_bus_formats(&tc->connector.display_info,
1202 &bus_format, 1);
1203 drm_mode_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1204
1205 return 0;
1206}
1207
1208static const struct drm_bridge_funcs tc_bridge_funcs = {
1209 .attach = tc_bridge_attach,
1210 .mode_set = tc_bridge_mode_set,
1211 .pre_enable = tc_bridge_pre_enable,
1212 .enable = tc_bridge_enable,
1213 .disable = tc_bridge_disable,
1214 .post_disable = tc_bridge_post_disable,
1215 .mode_fixup = tc_bridge_mode_fixup,
1216};
1217
1218static bool tc_readable_reg(struct device *dev, unsigned int reg)
1219{
1220 return reg != SYSCTRL;
1221}
1222
1223static const struct regmap_range tc_volatile_ranges[] = {
1224 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1225 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1226 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1227 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1228 regmap_reg_range(VFUEN0, VFUEN0),
1229};
1230
1231static const struct regmap_access_table tc_volatile_table = {
1232 .yes_ranges = tc_volatile_ranges,
1233 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1234};
1235
1236static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1237{
1238 return (reg != TC_IDREG) &&
1239 (reg != DP0_LTSTAT) &&
1240 (reg != DP0_SNKLTCHGREQ);
1241}
1242
1243static const struct regmap_config tc_regmap_config = {
1244 .name = "tc358767",
1245 .reg_bits = 16,
1246 .val_bits = 32,
1247 .reg_stride = 4,
1248 .max_register = PLL_DBG,
1249 .cache_type = REGCACHE_RBTREE,
1250 .readable_reg = tc_readable_reg,
1251 .volatile_table = &tc_volatile_table,
1252 .writeable_reg = tc_writeable_reg,
1253 .reg_format_endian = REGMAP_ENDIAN_BIG,
1254 .val_format_endian = REGMAP_ENDIAN_LITTLE,
1255};
1256
1257static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
1258{
1259 struct device *dev = &client->dev;
1260 struct device_node *ep;
1261 struct tc_data *tc;
1262 int ret;
1263
1264 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
1265 if (!tc)
1266 return -ENOMEM;
1267
1268 tc->dev = dev;
1269
1270 /* port@2 is the output port */
1271 ep = of_graph_get_endpoint_by_regs(dev->of_node, 2, -1);
1272 if (ep) {
1273 struct device_node *remote;
1274
1275 remote = of_graph_get_remote_port_parent(ep);
1276 if (!remote) {
1277 dev_warn(dev, "endpoint %s not connected\n",
1278 ep->full_name);
1279 of_node_put(ep);
1280 return -ENODEV;
1281 }
1282 of_node_put(ep);
1283 tc->panel = of_drm_find_panel(remote);
1284 if (tc->panel) {
1285 dev_dbg(dev, "found panel %s\n", remote->full_name);
1286 } else {
1287 dev_dbg(dev, "waiting for panel %s\n",
1288 remote->full_name);
1289 of_node_put(remote);
1290 return -EPROBE_DEFER;
1291 }
1292 of_node_put(remote);
1293 }
1294
1295 /* Shut down GPIO is optional */
1296 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
1297 if (IS_ERR(tc->sd_gpio))
1298 return PTR_ERR(tc->sd_gpio);
1299
1300 if (tc->sd_gpio) {
1301 gpiod_set_value_cansleep(tc->sd_gpio, 0);
1302 usleep_range(5000, 10000);
1303 }
1304
1305 /* Reset GPIO is optional */
1306 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1307 if (IS_ERR(tc->reset_gpio))
1308 return PTR_ERR(tc->reset_gpio);
1309
1310 if (tc->reset_gpio) {
1311 gpiod_set_value_cansleep(tc->reset_gpio, 1);
1312 usleep_range(5000, 10000);
1313 }
1314
1315 tc->refclk = devm_clk_get(dev, "ref");
1316 if (IS_ERR(tc->refclk)) {
1317 ret = PTR_ERR(tc->refclk);
1318 dev_err(dev, "Failed to get refclk: %d\n", ret);
1319 return ret;
1320 }
1321
1322 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1323 if (IS_ERR(tc->regmap)) {
1324 ret = PTR_ERR(tc->regmap);
1325 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
1326 return ret;
1327 }
1328
1329 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
1330 if (ret) {
1331 dev_err(tc->dev, "can not read device ID: %d\n", ret);
1332 return ret;
1333 }
1334
1335 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
1336 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
1337 return -EINVAL;
1338 }
1339
1340 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1341
1342 ret = tc_aux_link_setup(tc);
1343 if (ret)
1344 return ret;
1345
1346 /* Register DP AUX channel */
1347 tc->aux.name = "TC358767 AUX i2c adapter";
1348 tc->aux.dev = tc->dev;
1349 tc->aux.transfer = tc_aux_transfer;
1350 ret = drm_dp_aux_register(&tc->aux);
1351 if (ret)
1352 return ret;
1353
1354 ret = tc_get_display_props(tc);
1355 if (ret)
1356 goto err_unregister_aux;
1357
1358 tc_connector_set_polling(tc, &tc->connector);
1359
1360 tc->bridge.funcs = &tc_bridge_funcs;
1361 tc->bridge.of_node = dev->of_node;
1362 ret = drm_bridge_add(&tc->bridge);
1363 if (ret) {
1364 dev_err(dev, "Failed to add drm_bridge: %d\n", ret);
1365 goto err_unregister_aux;
1366 }
1367
1368 i2c_set_clientdata(client, tc);
1369
1370 return 0;
1371err_unregister_aux:
1372 drm_dp_aux_unregister(&tc->aux);
1373 return ret;
1374}
1375
1376static int tc_remove(struct i2c_client *client)
1377{
1378 struct tc_data *tc = i2c_get_clientdata(client);
1379
1380 drm_bridge_remove(&tc->bridge);
1381 drm_dp_aux_unregister(&tc->aux);
1382
1383 tc_pxl_pll_dis(tc);
1384
1385 return 0;
1386}
1387
1388static const struct i2c_device_id tc358767_i2c_ids[] = {
1389 { "tc358767", 0 },
1390 { }
1391};
1392MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
1393
1394static const struct of_device_id tc358767_of_ids[] = {
1395 { .compatible = "toshiba,tc358767", },
1396 { }
1397};
1398MODULE_DEVICE_TABLE(of, tc358767_of_ids);
1399
1400static struct i2c_driver tc358767_driver = {
1401 .driver = {
1402 .name = "tc358767",
1403 .of_match_table = tc358767_of_ids,
1404 },
1405 .id_table = tc358767_i2c_ids,
1406 .probe = tc_probe,
1407 .remove = tc_remove,
1408};
1409module_i2c_driver(tc358767_driver);
1410
1411MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
1412MODULE_DESCRIPTION("tc358767 eDP encoder driver");
1413MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/i2c/Kconfig b/drivers/gpu/drm/i2c/Kconfig
index 22c7ed63a001..4d341db462a2 100644
--- a/drivers/gpu/drm/i2c/Kconfig
+++ b/drivers/gpu/drm/i2c/Kconfig
@@ -1,12 +1,6 @@
1menu "I2C encoder or helper chips" 1menu "I2C encoder or helper chips"
2 depends on DRM && DRM_KMS_HELPER && I2C 2 depends on DRM && DRM_KMS_HELPER && I2C
3 3
4config DRM_I2C_ADV7511
5 tristate "AV7511 encoder"
6 select REGMAP_I2C
7 help
8 Support for the Analog Device ADV7511(W) and ADV7513 HDMI encoders.
9
10config DRM_I2C_CH7006 4config DRM_I2C_CH7006
11 tristate "Chrontel ch7006 TV encoder" 5 tristate "Chrontel ch7006 TV encoder"
12 default m if DRM_NOUVEAU 6 default m if DRM_NOUVEAU
diff --git a/drivers/gpu/drm/i2c/Makefile b/drivers/gpu/drm/i2c/Makefile
index 2c72eb584ab7..43aa33baebed 100644
--- a/drivers/gpu/drm/i2c/Makefile
+++ b/drivers/gpu/drm/i2c/Makefile
@@ -1,7 +1,5 @@
1ccflags-y := -Iinclude/drm 1ccflags-y := -Iinclude/drm
2 2
3obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511.o
4
5ch7006-y := ch7006_drv.o ch7006_mode.o 3ch7006-y := ch7006_drv.o ch7006_mode.o
6obj-$(CONFIG_DRM_I2C_CH7006) += ch7006.o 4obj-$(CONFIG_DRM_I2C_CH7006) += ch7006.o
7 5
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index 827711e28226..d3b44651061a 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -7,8 +7,8 @@ rcar-du-drm-y := rcar_du_crtc.o \
7 rcar_du_plane.o \ 7 rcar_du_plane.o \
8 rcar_du_vgacon.o 8 rcar_du_vgacon.o
9 9
10rcar-du-drm-$(CONFIG_DRM_RCAR_HDMI) += rcar_du_hdmicon.o \ 10rcar-du-drm-$(CONFIG_DRM_RCAR_HDMI) += rcar_du_hdmienc.o
11 rcar_du_hdmienc.o 11
12rcar-du-drm-$(CONFIG_DRM_RCAR_LVDS) += rcar_du_lvdsenc.o 12rcar-du-drm-$(CONFIG_DRM_RCAR_LVDS) += rcar_du_lvdsenc.o
13 13
14rcar-du-drm-$(CONFIG_DRM_RCAR_VSP) += rcar_du_vsp.o 14rcar-du-drm-$(CONFIG_DRM_RCAR_VSP) += rcar_du_vsp.o
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
index 55149e9ce28e..ab8645c57e2d 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
@@ -19,7 +19,6 @@
19 19
20#include "rcar_du_drv.h" 20#include "rcar_du_drv.h"
21#include "rcar_du_encoder.h" 21#include "rcar_du_encoder.h"
22#include "rcar_du_hdmicon.h"
23#include "rcar_du_hdmienc.h" 22#include "rcar_du_hdmienc.h"
24#include "rcar_du_kms.h" 23#include "rcar_du_kms.h"
25#include "rcar_du_lvdscon.h" 24#include "rcar_du_lvdscon.h"
@@ -174,7 +173,7 @@ int rcar_du_encoder_init(struct rcar_du_device *rcdu,
174 break; 173 break;
175 174
176 case DRM_MODE_ENCODER_TMDS: 175 case DRM_MODE_ENCODER_TMDS:
177 ret = rcar_du_hdmi_connector_init(rcdu, renc); 176 /* connector managed by the bridge driver */
178 break; 177 break;
179 178
180 default: 179 default:
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h
index a8669c3e0dd5..7fc10a9c34c3 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h
@@ -15,7 +15,6 @@
15#define __RCAR_DU_ENCODER_H__ 15#define __RCAR_DU_ENCODER_H__
16 16
17#include <drm/drm_crtc.h> 17#include <drm/drm_crtc.h>
18#include <drm/drm_encoder_slave.h>
19 18
20struct rcar_du_device; 19struct rcar_du_device;
21struct rcar_du_hdmienc; 20struct rcar_du_hdmienc;
@@ -30,16 +29,16 @@ enum rcar_du_encoder_type {
30}; 29};
31 30
32struct rcar_du_encoder { 31struct rcar_du_encoder {
33 struct drm_encoder_slave slave; 32 struct drm_encoder base;
34 enum rcar_du_output output; 33 enum rcar_du_output output;
35 struct rcar_du_hdmienc *hdmi; 34 struct rcar_du_hdmienc *hdmi;
36 struct rcar_du_lvdsenc *lvds; 35 struct rcar_du_lvdsenc *lvds;
37}; 36};
38 37
39#define to_rcar_encoder(e) \ 38#define to_rcar_encoder(e) \
40 container_of(e, struct rcar_du_encoder, slave.base) 39 container_of(e, struct rcar_du_encoder, base)
41 40
42#define rcar_encoder_to_drm_encoder(e) (&(e)->slave.base) 41#define rcar_encoder_to_drm_encoder(e) (&(e)->base)
43 42
44struct rcar_du_connector { 43struct rcar_du_connector {
45 struct drm_connector connector; 44 struct drm_connector connector;
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c b/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c
deleted file mode 100644
index 612b4d5ae098..000000000000
--- a/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * R-Car Display Unit HDMI Connector
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 *
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <drm/drmP.h>
15#include <drm/drm_atomic_helper.h>
16#include <drm/drm_crtc.h>
17#include <drm/drm_crtc_helper.h>
18#include <drm/drm_encoder_slave.h>
19
20#include "rcar_du_drv.h"
21#include "rcar_du_encoder.h"
22#include "rcar_du_hdmicon.h"
23#include "rcar_du_kms.h"
24
25#define to_slave_funcs(e) (to_rcar_encoder(e)->slave.slave_funcs)
26
27static int rcar_du_hdmi_connector_get_modes(struct drm_connector *connector)
28{
29 struct rcar_du_connector *con = to_rcar_connector(connector);
30 struct drm_encoder *encoder = rcar_encoder_to_drm_encoder(con->encoder);
31 const struct drm_encoder_slave_funcs *sfuncs = to_slave_funcs(encoder);
32
33 if (sfuncs->get_modes == NULL)
34 return 0;
35
36 return sfuncs->get_modes(encoder, connector);
37}
38
39static int rcar_du_hdmi_connector_mode_valid(struct drm_connector *connector,
40 struct drm_display_mode *mode)
41{
42 struct rcar_du_connector *con = to_rcar_connector(connector);
43 struct drm_encoder *encoder = rcar_encoder_to_drm_encoder(con->encoder);
44 const struct drm_encoder_slave_funcs *sfuncs = to_slave_funcs(encoder);
45
46 if (sfuncs->mode_valid == NULL)
47 return MODE_OK;
48
49 return sfuncs->mode_valid(encoder, mode);
50}
51
52static const struct drm_connector_helper_funcs connector_helper_funcs = {
53 .get_modes = rcar_du_hdmi_connector_get_modes,
54 .mode_valid = rcar_du_hdmi_connector_mode_valid,
55};
56
57static enum drm_connector_status
58rcar_du_hdmi_connector_detect(struct drm_connector *connector, bool force)
59{
60 struct rcar_du_connector *con = to_rcar_connector(connector);
61 struct drm_encoder *encoder = rcar_encoder_to_drm_encoder(con->encoder);
62 const struct drm_encoder_slave_funcs *sfuncs = to_slave_funcs(encoder);
63
64 if (sfuncs->detect == NULL)
65 return connector_status_unknown;
66
67 return sfuncs->detect(encoder, connector);
68}
69
70static const struct drm_connector_funcs connector_funcs = {
71 .dpms = drm_atomic_helper_connector_dpms,
72 .reset = drm_atomic_helper_connector_reset,
73 .detect = rcar_du_hdmi_connector_detect,
74 .fill_modes = drm_helper_probe_single_connector_modes,
75 .destroy = drm_connector_cleanup,
76 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
77 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
78};
79
80int rcar_du_hdmi_connector_init(struct rcar_du_device *rcdu,
81 struct rcar_du_encoder *renc)
82{
83 struct drm_encoder *encoder = rcar_encoder_to_drm_encoder(renc);
84 struct rcar_du_connector *rcon;
85 struct drm_connector *connector;
86 int ret;
87
88 rcon = devm_kzalloc(rcdu->dev, sizeof(*rcon), GFP_KERNEL);
89 if (rcon == NULL)
90 return -ENOMEM;
91
92 connector = &rcon->connector;
93 connector->display_info.width_mm = 0;
94 connector->display_info.height_mm = 0;
95 connector->interlace_allowed = true;
96 connector->polled = DRM_CONNECTOR_POLL_HPD;
97
98 ret = drm_connector_init(rcdu->ddev, connector, &connector_funcs,
99 DRM_MODE_CONNECTOR_HDMIA);
100 if (ret < 0)
101 return ret;
102
103 drm_connector_helper_add(connector, &connector_helper_funcs);
104
105 connector->dpms = DRM_MODE_DPMS_OFF;
106 drm_object_property_set_value(&connector->base,
107 rcdu->ddev->mode_config.dpms_property, DRM_MODE_DPMS_OFF);
108
109 ret = drm_mode_connector_attach_encoder(connector, encoder);
110 if (ret < 0)
111 return ret;
112
113 rcon->encoder = renc;
114
115 return 0;
116}
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.h b/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.h
deleted file mode 100644
index 87daa949227f..000000000000
--- a/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * R-Car Display Unit HDMI Connector
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 *
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef __RCAR_DU_HDMICON_H__
15#define __RCAR_DU_HDMICON_H__
16
17struct rcar_du_device;
18struct rcar_du_encoder;
19
20#if IS_ENABLED(CONFIG_DRM_RCAR_HDMI)
21int rcar_du_hdmi_connector_init(struct rcar_du_device *rcdu,
22 struct rcar_du_encoder *renc);
23#else
24static inline int rcar_du_hdmi_connector_init(struct rcar_du_device *rcdu,
25 struct rcar_du_encoder *renc)
26{
27 return -ENOSYS;
28}
29#endif
30
31#endif /* __RCAR_DU_HDMICON_H__ */
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c b/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c
index 461662d231e2..4de3ff0dbebd 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c
@@ -16,7 +16,6 @@
16#include <drm/drmP.h> 16#include <drm/drmP.h>
17#include <drm/drm_crtc.h> 17#include <drm/drm_crtc.h>
18#include <drm/drm_crtc_helper.h> 18#include <drm/drm_crtc_helper.h>
19#include <drm/drm_encoder_slave.h>
20 19
21#include "rcar_du_drv.h" 20#include "rcar_du_drv.h"
22#include "rcar_du_encoder.h" 21#include "rcar_du_encoder.h"
@@ -25,20 +24,14 @@
25 24
26struct rcar_du_hdmienc { 25struct rcar_du_hdmienc {
27 struct rcar_du_encoder *renc; 26 struct rcar_du_encoder *renc;
28 struct device *dev;
29 bool enabled; 27 bool enabled;
30}; 28};
31 29
32#define to_rcar_hdmienc(e) (to_rcar_encoder(e)->hdmi) 30#define to_rcar_hdmienc(e) (to_rcar_encoder(e)->hdmi)
33#define to_slave_funcs(e) (to_rcar_encoder(e)->slave.slave_funcs)
34 31
35static void rcar_du_hdmienc_disable(struct drm_encoder *encoder) 32static void rcar_du_hdmienc_disable(struct drm_encoder *encoder)
36{ 33{
37 struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder); 34 struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder);
38 const struct drm_encoder_slave_funcs *sfuncs = to_slave_funcs(encoder);
39
40 if (sfuncs->dpms)
41 sfuncs->dpms(encoder, DRM_MODE_DPMS_OFF);
42 35
43 if (hdmienc->renc->lvds) 36 if (hdmienc->renc->lvds)
44 rcar_du_lvdsenc_enable(hdmienc->renc->lvds, encoder->crtc, 37 rcar_du_lvdsenc_enable(hdmienc->renc->lvds, encoder->crtc,
@@ -50,15 +43,11 @@ static void rcar_du_hdmienc_disable(struct drm_encoder *encoder)
50static void rcar_du_hdmienc_enable(struct drm_encoder *encoder) 43static void rcar_du_hdmienc_enable(struct drm_encoder *encoder)
51{ 44{
52 struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder); 45 struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder);
53 const struct drm_encoder_slave_funcs *sfuncs = to_slave_funcs(encoder);
54 46
55 if (hdmienc->renc->lvds) 47 if (hdmienc->renc->lvds)
56 rcar_du_lvdsenc_enable(hdmienc->renc->lvds, encoder->crtc, 48 rcar_du_lvdsenc_enable(hdmienc->renc->lvds, encoder->crtc,
57 true); 49 true);
58 50
59 if (sfuncs->dpms)
60 sfuncs->dpms(encoder, DRM_MODE_DPMS_ON);
61
62 hdmienc->enabled = true; 51 hdmienc->enabled = true;
63} 52}
64 53
@@ -67,29 +56,21 @@ static int rcar_du_hdmienc_atomic_check(struct drm_encoder *encoder,
67 struct drm_connector_state *conn_state) 56 struct drm_connector_state *conn_state)
68{ 57{
69 struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder); 58 struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder);
70 const struct drm_encoder_slave_funcs *sfuncs = to_slave_funcs(encoder);
71 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 59 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
72 const struct drm_display_mode *mode = &crtc_state->mode;
73 60
74 if (hdmienc->renc->lvds) 61 if (hdmienc->renc->lvds)
75 rcar_du_lvdsenc_atomic_check(hdmienc->renc->lvds, 62 rcar_du_lvdsenc_atomic_check(hdmienc->renc->lvds,
76 adjusted_mode); 63 adjusted_mode);
77 64
78 if (sfuncs->mode_fixup == NULL) 65 return 0;
79 return 0;
80
81 return sfuncs->mode_fixup(encoder, mode, adjusted_mode) ? 0 : -EINVAL;
82} 66}
83 67
68
84static void rcar_du_hdmienc_mode_set(struct drm_encoder *encoder, 69static void rcar_du_hdmienc_mode_set(struct drm_encoder *encoder,
85 struct drm_display_mode *mode, 70 struct drm_display_mode *mode,
86 struct drm_display_mode *adjusted_mode) 71 struct drm_display_mode *adjusted_mode)
87{ 72{
88 struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder); 73 struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder);
89 const struct drm_encoder_slave_funcs *sfuncs = to_slave_funcs(encoder);
90
91 if (sfuncs->mode_set)
92 sfuncs->mode_set(encoder, mode, adjusted_mode);
93 74
94 rcar_du_crtc_route_output(encoder->crtc, hdmienc->renc->output); 75 rcar_du_crtc_route_output(encoder->crtc, hdmienc->renc->output);
95} 76}
@@ -109,7 +90,6 @@ static void rcar_du_hdmienc_cleanup(struct drm_encoder *encoder)
109 rcar_du_hdmienc_disable(encoder); 90 rcar_du_hdmienc_disable(encoder);
110 91
111 drm_encoder_cleanup(encoder); 92 drm_encoder_cleanup(encoder);
112 put_device(hdmienc->dev);
113} 93}
114 94
115static const struct drm_encoder_funcs encoder_funcs = { 95static const struct drm_encoder_funcs encoder_funcs = {
@@ -120,8 +100,7 @@ int rcar_du_hdmienc_init(struct rcar_du_device *rcdu,
120 struct rcar_du_encoder *renc, struct device_node *np) 100 struct rcar_du_encoder *renc, struct device_node *np)
121{ 101{
122 struct drm_encoder *encoder = rcar_encoder_to_drm_encoder(renc); 102 struct drm_encoder *encoder = rcar_encoder_to_drm_encoder(renc);
123 struct drm_i2c_encoder_driver *driver; 103 struct drm_bridge *bridge;
124 struct i2c_client *i2c_slave;
125 struct rcar_du_hdmienc *hdmienc; 104 struct rcar_du_hdmienc *hdmienc;
126 int ret; 105 int ret;
127 106
@@ -129,44 +108,29 @@ int rcar_du_hdmienc_init(struct rcar_du_device *rcdu,
129 if (hdmienc == NULL) 108 if (hdmienc == NULL)
130 return -ENOMEM; 109 return -ENOMEM;
131 110
132 /* Locate the slave I2C device and driver. */ 111 /* Locate drm bridge from the hdmi encoder DT node */
133 i2c_slave = of_find_i2c_device_by_node(np); 112 bridge = of_drm_find_bridge(np);
134 if (!i2c_slave || !i2c_get_clientdata(i2c_slave)) { 113 if (!bridge)
135 dev_dbg(rcdu->dev,
136 "can't get I2C slave for %s, deferring probe\n",
137 of_node_full_name(np));
138 return -EPROBE_DEFER; 114 return -EPROBE_DEFER;
139 }
140
141 hdmienc->dev = &i2c_slave->dev;
142
143 if (hdmienc->dev->driver == NULL) {
144 dev_dbg(rcdu->dev,
145 "I2C slave %s not probed yet, deferring probe\n",
146 dev_name(hdmienc->dev));
147 ret = -EPROBE_DEFER;
148 goto error;
149 }
150
151 /* Initialize the slave encoder. */
152 driver = to_drm_i2c_encoder_driver(to_i2c_driver(hdmienc->dev->driver));
153 ret = driver->encoder_init(i2c_slave, rcdu->ddev, &renc->slave);
154 if (ret < 0)
155 goto error;
156 115
157 ret = drm_encoder_init(rcdu->ddev, encoder, &encoder_funcs, 116 ret = drm_encoder_init(rcdu->ddev, encoder, &encoder_funcs,
158 DRM_MODE_ENCODER_TMDS, NULL); 117 DRM_MODE_ENCODER_TMDS, NULL);
159 if (ret < 0) 118 if (ret < 0)
160 goto error; 119 return ret;
161 120
162 drm_encoder_helper_add(encoder, &encoder_helper_funcs); 121 drm_encoder_helper_add(encoder, &encoder_helper_funcs);
163 122
164 renc->hdmi = hdmienc; 123 renc->hdmi = hdmienc;
165 hdmienc->renc = renc; 124 hdmienc->renc = renc;
166 125
167 return 0; 126 /* Link drm_bridge to encoder */
127 bridge->encoder = encoder;
128
129 ret = drm_bridge_attach(rcdu->ddev, bridge);
130 if (ret) {
131 drm_encoder_cleanup(encoder);
132 return ret;
133 }
168 134
169error: 135 return 0;
170 put_device(hdmienc->dev);
171 return ret;
172} 136}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-25 22:54:10 -0400