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authorKrzysztof Kozlowski <krzk@kernel.org>2018-04-24 16:32:36 -0400
committerKrzysztof Kozlowski <krzk@kernel.org>2018-05-02 13:08:55 -0400
commit0ca0557e3727951bdc44ea47bc6135b37f90338c (patch)
tree6ffb66400a3a8b2fc66107b7ad1c43fbca40b9b6
parent938a10bb49131f08a0b30cb26648844ec748131e (diff)
pinctrl: samsung: Remove support for Exynos5440
The Exynos5440 is not actively developed, there are no development boards available and probably there are no real products with it. Remove wide-tree support for Exynos5440. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Diffstat
-rw-r--r--drivers/pinctrl/samsung/Kconfig10
-rw-r--r--drivers/pinctrl/samsung/Makefile1
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos5440.c1005
3 files changed, 2 insertions, 1014 deletions
diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig
index 11b5eeb14c4a..425fadd6c346 100644
--- a/drivers/pinctrl/samsung/Kconfig
+++ b/drivers/pinctrl/samsung/Kconfig
@@ -8,26 +8,20 @@ config PINCTRL_SAMSUNG
8 select PINCONF 8 select PINCONF
9 9
10config PINCTRL_EXYNOS 10config PINCTRL_EXYNOS
11 bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440" 11 bool "Pinctrl driver data for Samsung EXYNOS SoCs"
12 depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210) 12 depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210)
13 select PINCTRL_SAMSUNG 13 select PINCTRL_SAMSUNG
14 select PINCTRL_EXYNOS_ARM if ARM && (ARCH_EXYNOS || ARCH_S5PV210) 14 select PINCTRL_EXYNOS_ARM if ARM && (ARCH_EXYNOS || ARCH_S5PV210)
15 select PINCTRL_EXYNOS_ARM64 if ARM64 && ARCH_EXYNOS 15 select PINCTRL_EXYNOS_ARM64 if ARM64 && ARCH_EXYNOS
16 16
17config PINCTRL_EXYNOS_ARM 17config PINCTRL_EXYNOS_ARM
18 bool "ARMv7-specific pinctrl driver data for Exynos (except Exynos5440)" if COMPILE_TEST 18 bool "ARMv7-specific pinctrl driver data for Exynos" if COMPILE_TEST
19 depends on PINCTRL_EXYNOS 19 depends on PINCTRL_EXYNOS
20 20
21config PINCTRL_EXYNOS_ARM64 21config PINCTRL_EXYNOS_ARM64
22 bool "ARMv8-specific pinctrl driver data for Exynos" if COMPILE_TEST 22 bool "ARMv8-specific pinctrl driver data for Exynos" if COMPILE_TEST
23 depends on PINCTRL_EXYNOS 23 depends on PINCTRL_EXYNOS
24 24
25config PINCTRL_EXYNOS5440
26 bool "Samsung EXYNOS5440 SoC pinctrl driver"
27 depends on SOC_EXYNOS5440
28 select PINMUX
29 select PINCONF
30
31config PINCTRL_S3C24XX 25config PINCTRL_S3C24XX
32 bool "Samsung S3C24XX SoC pinctrl driver" 26 bool "Samsung S3C24XX SoC pinctrl driver"
33 depends on ARCH_S3C24XX && OF 27 depends on ARCH_S3C24XX && OF
diff --git a/drivers/pinctrl/samsung/Makefile b/drivers/pinctrl/samsung/Makefile
index df426561d067..ed951df6a112 100644
--- a/drivers/pinctrl/samsung/Makefile
+++ b/drivers/pinctrl/samsung/Makefile
@@ -5,6 +5,5 @@ obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
5obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o 5obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o
6obj-$(CONFIG_PINCTRL_EXYNOS_ARM) += pinctrl-exynos-arm.o 6obj-$(CONFIG_PINCTRL_EXYNOS_ARM) += pinctrl-exynos-arm.o
7obj-$(CONFIG_PINCTRL_EXYNOS_ARM64) += pinctrl-exynos-arm64.o 7obj-$(CONFIG_PINCTRL_EXYNOS_ARM64) += pinctrl-exynos-arm64.o
8obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o
9obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o 8obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o
10obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o 9obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
deleted file mode 100644
index 3d8d5e812839..000000000000
--- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c
+++ /dev/null
@@ -1,1005 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
4//
5// Author: Thomas Abraham <thomas.ab@samsung.com>
6//
7// Copyright (c) 2012 Samsung Electronics Co., Ltd.
8// http://www.samsung.com
9
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/io.h>
13#include <linux/slab.h>
14#include <linux/err.h>
15#include <linux/gpio/driver.h>
16#include <linux/device.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/interrupt.h>
21#include <linux/irqdomain.h>
22#include <linux/of_irq.h>
23#include "../core.h"
24
25/* EXYNOS5440 GPIO and Pinctrl register offsets */
26#define GPIO_MUX 0x00
27#define GPIO_IE 0x04
28#define GPIO_INT 0x08
29#define GPIO_TYPE 0x0C
30#define GPIO_VAL 0x10
31#define GPIO_OE 0x14
32#define GPIO_IN 0x18
33#define GPIO_PE 0x1C
34#define GPIO_PS 0x20
35#define GPIO_SR 0x24
36#define GPIO_DS0 0x28
37#define GPIO_DS1 0x2C
38
39#define EXYNOS5440_MAX_PINS 23
40#define EXYNOS5440_MAX_GPIO_INT 8
41#define PIN_NAME_LENGTH 10
42
43#define GROUP_SUFFIX "-grp"
44#define FUNCTION_SUFFIX "-mux"
45
46/*
47 * pin configuration type and its value are packed together into a 16-bits.
48 * The upper 8-bits represent the configuration type and the lower 8-bits
49 * hold the value of the configuration type.
50 */
51#define PINCFG_TYPE_MASK 0xFF
52#define PINCFG_VALUE_SHIFT 8
53#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
54#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
55#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
56#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
57 PINCFG_VALUE_SHIFT)
58
59/**
60 * enum pincfg_type - possible pin configuration types supported.
61 * @PINCFG_TYPE_PUD: Pull up/down configuration.
62 * @PINCFG_TYPE_DRV: Drive strength configuration.
63 * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration.
64 * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration.
65 */
66enum pincfg_type {
67 PINCFG_TYPE_PUD,
68 PINCFG_TYPE_DRV,
69 PINCFG_TYPE_SKEW_RATE,
70 PINCFG_TYPE_INPUT_TYPE
71};
72
73/**
74 * struct exynos5440_pin_group: represent group of pins for pincfg setting.
75 * @name: name of the pin group, used to lookup the group.
76 * @pins: the pins included in this group.
77 * @num_pins: number of pins included in this group.
78 */
79struct exynos5440_pin_group {
80 const char *name;
81 const unsigned int *pins;
82 u8 num_pins;
83};
84
85/**
86 * struct exynos5440_pmx_func: represent a pin function.
87 * @name: name of the pin function, used to lookup the function.
88 * @groups: one or more names of pin groups that provide this function.
89 * @num_groups: number of groups included in @groups.
90 * @function: the function number to be programmed when selected.
91 */
92struct exynos5440_pmx_func {
93 const char *name;
94 const char **groups;
95 u8 num_groups;
96 unsigned long function;
97};
98
99/**
100 * struct exynos5440_pinctrl_priv_data: driver's private runtime data.
101 * @reg_base: ioremapped based address of the register space.
102 * @gc: gpio chip registered with gpiolib.
103 * @pin_groups: list of pin groups parsed from device tree.
104 * @nr_groups: number of pin groups available.
105 * @pmx_functions: list of pin functions parsed from device tree.
106 * @nr_functions: number of pin functions available.
107 * @range: gpio range to register with pinctrl
108 */
109struct exynos5440_pinctrl_priv_data {
110 void __iomem *reg_base;
111 struct gpio_chip *gc;
112 struct irq_domain *irq_domain;
113
114 const struct exynos5440_pin_group *pin_groups;
115 unsigned int nr_groups;
116 const struct exynos5440_pmx_func *pmx_functions;
117 unsigned int nr_functions;
118 struct pinctrl_gpio_range range;
119};
120
121/**
122 * struct exynos5440_gpio_intr_data: private data for gpio interrupts.
123 * @priv: driver's private runtime data.
124 * @gpio_int: gpio interrupt number.
125 */
126struct exynos5440_gpio_intr_data {
127 struct exynos5440_pinctrl_priv_data *priv;
128 unsigned int gpio_int;
129};
130
131/* list of all possible config options supported */
132static struct pin_config {
133 char *prop_cfg;
134 unsigned int cfg_type;
135} pcfgs[] = {
136 { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD },
137 { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV },
138 { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE },
139 { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE },
140};
141
142/* check if the selector is a valid pin group selector */
143static int exynos5440_get_group_count(struct pinctrl_dev *pctldev)
144{
145 struct exynos5440_pinctrl_priv_data *priv;
146
147 priv = pinctrl_dev_get_drvdata(pctldev);
148 return priv->nr_groups;
149}
150
151/* return the name of the group selected by the group selector */
152static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev,
153 unsigned selector)
154{
155 struct exynos5440_pinctrl_priv_data *priv;
156
157 priv = pinctrl_dev_get_drvdata(pctldev);
158 return priv->pin_groups[selector].name;
159}
160
161/* return the pin numbers associated with the specified group */
162static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev,
163 unsigned selector, const unsigned **pins, unsigned *num_pins)
164{
165 struct exynos5440_pinctrl_priv_data *priv;
166
167 priv = pinctrl_dev_get_drvdata(pctldev);
168 *pins = priv->pin_groups[selector].pins;
169 *num_pins = priv->pin_groups[selector].num_pins;
170 return 0;
171}
172
173/* create pinctrl_map entries by parsing device tree nodes */
174static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
175 struct device_node *np, struct pinctrl_map **maps,
176 unsigned *nmaps)
177{
178 struct device *dev = pctldev->dev;
179 struct pinctrl_map *map;
180 unsigned long *cfg = NULL;
181 char *gname, *fname;
182 int cfg_cnt = 0, map_cnt = 0, idx = 0;
183
184 /* count the number of config options specfied in the node */
185 for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++)
186 if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
187 cfg_cnt++;
188
189 /*
190 * Find out the number of map entries to create. All the config options
191 * can be accomadated into a single config map entry.
192 */
193 if (cfg_cnt)
194 map_cnt = 1;
195 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL))
196 map_cnt++;
197 if (!map_cnt) {
198 dev_err(dev, "node %s does not have either config or function "
199 "configurations\n", np->name);
200 return -EINVAL;
201 }
202
203 /* Allocate memory for pin-map entries */
204 map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
205 if (!map)
206 return -ENOMEM;
207 *nmaps = 0;
208
209 /*
210 * Allocate memory for pin group name. The pin group name is derived
211 * from the node name from which these map entries are be created.
212 */
213 gname = kasprintf(GFP_KERNEL, "%s%s", np->name, GROUP_SUFFIX);
214 if (!gname)
215 goto free_map;
216
217 /*
218 * don't have config options? then skip over to creating function
219 * map entries.
220 */
221 if (!cfg_cnt)
222 goto skip_cfgs;
223
224 /* Allocate memory for config entries */
225 cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
226 if (!cfg)
227 goto free_gname;
228
229 /* Prepare a list of config settings */
230 for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
231 u32 value;
232 if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value))
233 cfg[cfg_cnt++] =
234 PINCFG_PACK(pcfgs[idx].cfg_type, value);
235 }
236
237 /* create the config map entry */
238 map[*nmaps].data.configs.group_or_pin = gname;
239 map[*nmaps].data.configs.configs = cfg;
240 map[*nmaps].data.configs.num_configs = cfg_cnt;
241 map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
242 *nmaps += 1;
243
244skip_cfgs:
245 /* create the function map entry */
246 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) {
247 fname = kasprintf(GFP_KERNEL,
248 "%s%s", np->name, FUNCTION_SUFFIX);
249 if (!fname)
250 goto free_cfg;
251
252 map[*nmaps].data.mux.group = gname;
253 map[*nmaps].data.mux.function = fname;
254 map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
255 *nmaps += 1;
256 }
257
258 *maps = map;
259 return 0;
260
261free_cfg:
262 kfree(cfg);
263free_gname:
264 kfree(gname);
265free_map:
266 kfree(map);
267 return -ENOMEM;
268}
269
270/* free the memory allocated to hold the pin-map table */
271static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
272 struct pinctrl_map *map, unsigned num_maps)
273{
274 int idx;
275
276 for (idx = 0; idx < num_maps; idx++) {
277 if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) {
278 kfree(map[idx].data.mux.function);
279 if (!idx)
280 kfree(map[idx].data.mux.group);
281 } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) {
282 kfree(map[idx].data.configs.configs);
283 if (!idx)
284 kfree(map[idx].data.configs.group_or_pin);
285 }
286 }
287
288 kfree(map);
289}
290
291/* list of pinctrl callbacks for the pinctrl core */
292static const struct pinctrl_ops exynos5440_pctrl_ops = {
293 .get_groups_count = exynos5440_get_group_count,
294 .get_group_name = exynos5440_get_group_name,
295 .get_group_pins = exynos5440_get_group_pins,
296 .dt_node_to_map = exynos5440_dt_node_to_map,
297 .dt_free_map = exynos5440_dt_free_map,
298};
299
300/* check if the selector is a valid pin function selector */
301static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev)
302{
303 struct exynos5440_pinctrl_priv_data *priv;
304
305 priv = pinctrl_dev_get_drvdata(pctldev);
306 return priv->nr_functions;
307}
308
309/* return the name of the pin function specified */
310static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev,
311 unsigned selector)
312{
313 struct exynos5440_pinctrl_priv_data *priv;
314
315 priv = pinctrl_dev_get_drvdata(pctldev);
316 return priv->pmx_functions[selector].name;
317}
318
319/* return the groups associated for the specified function selector */
320static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev,
321 unsigned selector, const char * const **groups,
322 unsigned * const num_groups)
323{
324 struct exynos5440_pinctrl_priv_data *priv;
325
326 priv = pinctrl_dev_get_drvdata(pctldev);
327 *groups = priv->pmx_functions[selector].groups;
328 *num_groups = priv->pmx_functions[selector].num_groups;
329 return 0;
330}
331
332/* enable or disable a pinmux function */
333static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
334 unsigned group, bool enable)
335{
336 struct exynos5440_pinctrl_priv_data *priv;
337 void __iomem *base;
338 u32 function;
339 u32 data;
340
341 priv = pinctrl_dev_get_drvdata(pctldev);
342 base = priv->reg_base;
343 function = priv->pmx_functions[selector].function;
344
345 data = readl(base + GPIO_MUX);
346 if (enable)
347 data |= (1 << function);
348 else
349 data &= ~(1 << function);
350 writel(data, base + GPIO_MUX);
351}
352
353/* enable a specified pinmux by writing to registers */
354static int exynos5440_pinmux_set_mux(struct pinctrl_dev *pctldev,
355 unsigned selector,
356 unsigned group)
357{
358 exynos5440_pinmux_setup(pctldev, selector, group, true);
359 return 0;
360}
361
362/*
363 * The calls to gpio_direction_output() and gpio_direction_input()
364 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
365 * function called from the gpiolib interface).
366 */
367static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
368 struct pinctrl_gpio_range *range, unsigned offset, bool input)
369{
370 return 0;
371}
372
373/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
374static const struct pinmux_ops exynos5440_pinmux_ops = {
375 .get_functions_count = exynos5440_get_functions_count,
376 .get_function_name = exynos5440_pinmux_get_fname,
377 .get_function_groups = exynos5440_pinmux_get_groups,
378 .set_mux = exynos5440_pinmux_set_mux,
379 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
380};
381
382/* set the pin config settings for a specified pin */
383static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
384 unsigned long *configs,
385 unsigned num_configs)
386{
387 struct exynos5440_pinctrl_priv_data *priv;
388 void __iomem *base;
389 enum pincfg_type cfg_type;
390 u32 cfg_value;
391 u32 data;
392 int i;
393
394 priv = pinctrl_dev_get_drvdata(pctldev);
395 base = priv->reg_base;
396
397 for (i = 0; i < num_configs; i++) {
398 cfg_type = PINCFG_UNPACK_TYPE(configs[i]);
399 cfg_value = PINCFG_UNPACK_VALUE(configs[i]);
400
401 switch (cfg_type) {
402 case PINCFG_TYPE_PUD:
403 /* first set pull enable/disable bit */
404 data = readl(base + GPIO_PE);
405 data &= ~(1 << pin);
406 if (cfg_value)
407 data |= (1 << pin);
408 writel(data, base + GPIO_PE);
409
410 /* then set pull up/down bit */
411 data = readl(base + GPIO_PS);
412 data &= ~(1 << pin);
413 if (cfg_value == 2)
414 data |= (1 << pin);
415 writel(data, base + GPIO_PS);
416 break;
417
418 case PINCFG_TYPE_DRV:
419 /* set the first bit of the drive strength */
420 data = readl(base + GPIO_DS0);
421 data &= ~(1 << pin);
422 data |= ((cfg_value & 1) << pin);
423 writel(data, base + GPIO_DS0);
424 cfg_value >>= 1;
425
426 /* set the second bit of the driver strength */
427 data = readl(base + GPIO_DS1);
428 data &= ~(1 << pin);
429 data |= ((cfg_value & 1) << pin);
430 writel(data, base + GPIO_DS1);
431 break;
432 case PINCFG_TYPE_SKEW_RATE:
433 data = readl(base + GPIO_SR);
434 data &= ~(1 << pin);
435 data |= ((cfg_value & 1) << pin);
436 writel(data, base + GPIO_SR);
437 break;
438 case PINCFG_TYPE_INPUT_TYPE:
439 data = readl(base + GPIO_TYPE);
440 data &= ~(1 << pin);
441 data |= ((cfg_value & 1) << pin);
442 writel(data, base + GPIO_TYPE);
443 break;
444 default:
445 WARN_ON(1);
446 return -EINVAL;
447 }
448 } /* for each config */
449
450 return 0;
451}
452
453/* get the pin config settings for a specified pin */
454static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
455 unsigned long *config)
456{
457 struct exynos5440_pinctrl_priv_data *priv;
458 void __iomem *base;
459 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config);
460 u32 data;
461
462 priv = pinctrl_dev_get_drvdata(pctldev);
463 base = priv->reg_base;
464
465 switch (cfg_type) {
466 case PINCFG_TYPE_PUD:
467 data = readl(base + GPIO_PE);
468 data = (data >> pin) & 1;
469 if (!data)
470 *config = 0;
471 else
472 *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1;
473 break;
474 case PINCFG_TYPE_DRV:
475 data = readl(base + GPIO_DS0);
476 data = (data >> pin) & 1;
477 *config = data;
478 data = readl(base + GPIO_DS1);
479 data = (data >> pin) & 1;
480 *config |= (data << 1);
481 break;
482 case PINCFG_TYPE_SKEW_RATE:
483 data = readl(base + GPIO_SR);
484 *config = (data >> pin) & 1;
485 break;
486 case PINCFG_TYPE_INPUT_TYPE:
487 data = readl(base + GPIO_TYPE);
488 *config = (data >> pin) & 1;
489 break;
490 default:
491 WARN_ON(1);
492 return -EINVAL;
493 }
494
495 return 0;
496}
497
498/* set the pin config settings for a specified pin group */
499static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
500 unsigned group, unsigned long *configs,
501 unsigned num_configs)
502{
503 struct exynos5440_pinctrl_priv_data *priv;
504 const unsigned int *pins;
505 unsigned int cnt;
506
507 priv = pinctrl_dev_get_drvdata(pctldev);
508 pins = priv->pin_groups[group].pins;
509
510 for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++)
511 exynos5440_pinconf_set(pctldev, pins[cnt], configs,
512 num_configs);
513
514 return 0;
515}
516
517/* get the pin config settings for a specified pin group */
518static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
519 unsigned int group, unsigned long *config)
520{
521 struct exynos5440_pinctrl_priv_data *priv;
522 const unsigned int *pins;
523
524 priv = pinctrl_dev_get_drvdata(pctldev);
525 pins = priv->pin_groups[group].pins;
526 exynos5440_pinconf_get(pctldev, pins[0], config);
527 return 0;
528}
529
530/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
531static const struct pinconf_ops exynos5440_pinconf_ops = {
532 .pin_config_get = exynos5440_pinconf_get,
533 .pin_config_set = exynos5440_pinconf_set,
534 .pin_config_group_get = exynos5440_pinconf_group_get,
535 .pin_config_group_set = exynos5440_pinconf_group_set,
536};
537
538/* gpiolib gpio_set callback function */
539static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
540{
541 struct exynos5440_pinctrl_priv_data *priv = gpiochip_get_data(gc);
542 void __iomem *base = priv->reg_base;
543 u32 data;
544
545 data = readl(base + GPIO_VAL);
546 data &= ~(1 << offset);
547 if (value)
548 data |= 1 << offset;
549 writel(data, base + GPIO_VAL);
550}
551
552/* gpiolib gpio_get callback function */
553static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset)
554{
555 struct exynos5440_pinctrl_priv_data *priv = gpiochip_get_data(gc);
556 void __iomem *base = priv->reg_base;
557 u32 data;
558
559 data = readl(base + GPIO_IN);
560 data >>= offset;
561 data &= 1;
562 return data;
563}
564
565/* gpiolib gpio_direction_input callback function */
566static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
567{
568 struct exynos5440_pinctrl_priv_data *priv = gpiochip_get_data(gc);
569 void __iomem *base = priv->reg_base;
570 u32 data;
571
572 /* first disable the data output enable on this pin */
573 data = readl(base + GPIO_OE);
574 data &= ~(1 << offset);
575 writel(data, base + GPIO_OE);
576
577 /* now enable input on this pin */
578 data = readl(base + GPIO_IE);
579 data |= 1 << offset;
580 writel(data, base + GPIO_IE);
581 return 0;
582}
583
584/* gpiolib gpio_direction_output callback function */
585static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
586 int value)
587{
588 struct exynos5440_pinctrl_priv_data *priv = gpiochip_get_data(gc);
589 void __iomem *base = priv->reg_base;
590 u32 data;
591
592 exynos5440_gpio_set(gc, offset, value);
593
594 /* first disable the data input enable on this pin */
595 data = readl(base + GPIO_IE);
596 data &= ~(1 << offset);
597 writel(data, base + GPIO_IE);
598
599 /* now enable output on this pin */
600 data = readl(base + GPIO_OE);
601 data |= 1 << offset;
602 writel(data, base + GPIO_OE);
603 return 0;
604}
605
606/* gpiolib gpio_to_irq callback function */
607static int exynos5440_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
608{
609 struct exynos5440_pinctrl_priv_data *priv = gpiochip_get_data(gc);
610 unsigned int virq;
611
612 if (offset < 16 || offset > 23)
613 return -ENXIO;
614
615 if (!priv->irq_domain)
616 return -ENXIO;
617
618 virq = irq_create_mapping(priv->irq_domain, offset - 16);
619 return virq ? : -ENXIO;
620}
621
622/* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */
623static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev,
624 struct device_node *cfg_np, unsigned int **pin_list,
625 unsigned int *npins)
626{
627 struct device *dev = &pdev->dev;
628 struct property *prop;
629
630 prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL);
631 if (!prop)
632 return -ENOENT;
633
634 *npins = prop->length / sizeof(unsigned long);
635 if (!*npins) {
636 dev_err(dev, "invalid pin list in %s node", cfg_np->name);
637 return -EINVAL;
638 }
639
640 *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
641 if (!*pin_list)
642 return -ENOMEM;
643
644 return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins",
645 *pin_list, *npins);
646}
647
648/*
649 * Parse the information about all the available pin groups and pin functions
650 * from device node of the pin-controller.
651 */
652static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
653 struct exynos5440_pinctrl_priv_data *priv)
654{
655 struct device *dev = &pdev->dev;
656 struct device_node *dev_np = dev->of_node;
657 struct device_node *cfg_np;
658 struct exynos5440_pin_group *groups, *grp;
659 struct exynos5440_pmx_func *functions, *func;
660 unsigned *pin_list;
661 unsigned int npins, grp_cnt, func_idx = 0;
662 char *gname, *fname;
663 int ret;
664
665 grp_cnt = of_get_child_count(dev_np);
666 if (!grp_cnt)
667 return -EINVAL;
668
669 groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
670 if (!groups)
671 return -EINVAL;
672
673 grp = groups;
674
675 functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
676 if (!functions)
677 return -EINVAL;
678
679 func = functions;
680
681 /*
682 * Iterate over all the child nodes of the pin controller node
683 * and create pin groups and pin function lists.
684 */
685 for_each_child_of_node(dev_np, cfg_np) {
686 u32 function;
687
688 ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np,
689 &pin_list, &npins);
690 if (ret) {
691 gname = NULL;
692 goto skip_to_pin_function;
693 }
694
695 /* derive pin group name from the node name */
696 gname = devm_kasprintf(dev, GFP_KERNEL,
697 "%s%s", cfg_np->name, GROUP_SUFFIX);
698 if (!gname)
699 return -ENOMEM;
700
701 grp->name = gname;
702 grp->pins = pin_list;
703 grp->num_pins = npins;
704 grp++;
705
706skip_to_pin_function:
707 ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function",
708 &function);
709 if (ret)
710 continue;
711
712 /* derive function name from the node name */
713 fname = devm_kasprintf(dev, GFP_KERNEL,
714 "%s%s", cfg_np->name, FUNCTION_SUFFIX);
715 if (!fname)
716 return -ENOMEM;
717
718 func->name = fname;
719 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
720 if (!func->groups)
721 return -ENOMEM;
722 func->groups[0] = gname;
723 func->num_groups = gname ? 1 : 0;
724 func->function = function;
725 func++;
726 func_idx++;
727 }
728
729 priv->pin_groups = groups;
730 priv->nr_groups = grp_cnt;
731 priv->pmx_functions = functions;
732 priv->nr_functions = func_idx;
733 return 0;
734}
735
736/* register the pinctrl interface with the pinctrl subsystem */
737static int exynos5440_pinctrl_register(struct platform_device *pdev,
738 struct exynos5440_pinctrl_priv_data *priv)
739{
740 struct device *dev = &pdev->dev;
741 struct pinctrl_desc *ctrldesc;
742 struct pinctrl_dev *pctl_dev;
743 struct pinctrl_pin_desc *pindesc, *pdesc;
744 char *pin_names;
745 int pin, ret;
746
747 ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL);
748 if (!ctrldesc)
749 return -ENOMEM;
750
751 ctrldesc->name = "exynos5440-pinctrl";
752 ctrldesc->owner = THIS_MODULE;
753 ctrldesc->pctlops = &exynos5440_pctrl_ops;
754 ctrldesc->pmxops = &exynos5440_pinmux_ops;
755 ctrldesc->confops = &exynos5440_pinconf_ops;
756
757 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
758 EXYNOS5440_MAX_PINS, GFP_KERNEL);
759 if (!pindesc)
760 return -ENOMEM;
761 ctrldesc->pins = pindesc;
762 ctrldesc->npins = EXYNOS5440_MAX_PINS;
763
764 /* dynamically populate the pin number and pin name for pindesc */
765 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
766 pdesc->number = pin;
767
768 /*
769 * allocate space for storing the dynamically generated names for all
770 * the pins which belong to this pin-controller.
771 */
772 pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
773 ctrldesc->npins, GFP_KERNEL);
774 if (!pin_names)
775 return -ENOMEM;
776
777 /* for each pin, set the name of the pin */
778 for (pin = 0; pin < ctrldesc->npins; pin++) {
779 snprintf(pin_names, 6, "gpio%02d", pin);
780 pdesc = pindesc + pin;
781 pdesc->name = pin_names;
782 pin_names += PIN_NAME_LENGTH;
783 }
784
785 ret = exynos5440_pinctrl_parse_dt(pdev, priv);
786 if (ret)
787 return ret;
788
789 pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, priv);
790 if (IS_ERR(pctl_dev)) {
791 dev_err(&pdev->dev, "could not register pinctrl driver\n");
792 return PTR_ERR(pctl_dev);
793 }
794
795 priv->range.name = "exynos5440-pctrl-gpio-range";
796 priv->range.id = 0;
797 priv->range.base = 0;
798 priv->range.npins = EXYNOS5440_MAX_PINS;
799 priv->range.gc = priv->gc;
800 pinctrl_add_gpio_range(pctl_dev, &priv->range);
801 return 0;
802}
803
804/* register the gpiolib interface with the gpiolib subsystem */
805static int exynos5440_gpiolib_register(struct platform_device *pdev,
806 struct exynos5440_pinctrl_priv_data *priv)
807{
808 struct gpio_chip *gc;
809 int ret;
810
811 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
812 if (!gc)
813 return -ENOMEM;
814
815 priv->gc = gc;
816 gc->base = 0;
817 gc->ngpio = EXYNOS5440_MAX_PINS;
818 gc->parent = &pdev->dev;
819 gc->set = exynos5440_gpio_set;
820 gc->get = exynos5440_gpio_get;
821 gc->direction_input = exynos5440_gpio_direction_input;
822 gc->direction_output = exynos5440_gpio_direction_output;
823 gc->to_irq = exynos5440_gpio_to_irq;
824 gc->label = "gpiolib-exynos5440";
825 gc->owner = THIS_MODULE;
826 ret = gpiochip_add_data(gc, priv);
827 if (ret) {
828 dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
829 "code: %d\n", gc->label, ret);
830 return ret;
831 }
832
833 return 0;
834}
835
836/* unregister the gpiolib interface with the gpiolib subsystem */
837static int exynos5440_gpiolib_unregister(struct platform_device *pdev,
838 struct exynos5440_pinctrl_priv_data *priv)
839{
840 gpiochip_remove(priv->gc);
841 return 0;
842}
843
844static void exynos5440_gpio_irq_unmask(struct irq_data *irqd)
845{
846 struct exynos5440_pinctrl_priv_data *d;
847 unsigned long gpio_int;
848
849 d = irq_data_get_irq_chip_data(irqd);
850 gpio_int = readl(d->reg_base + GPIO_INT);
851 gpio_int |= 1 << irqd->hwirq;
852 writel(gpio_int, d->reg_base + GPIO_INT);
853}
854
855static void exynos5440_gpio_irq_mask(struct irq_data *irqd)
856{
857 struct exynos5440_pinctrl_priv_data *d;
858 unsigned long gpio_int;
859
860 d = irq_data_get_irq_chip_data(irqd);
861 gpio_int = readl(d->reg_base + GPIO_INT);
862 gpio_int &= ~(1 << irqd->hwirq);
863 writel(gpio_int, d->reg_base + GPIO_INT);
864}
865
866/* irq_chip for gpio interrupts */
867static struct irq_chip exynos5440_gpio_irq_chip = {
868 .name = "exynos5440_gpio_irq_chip",
869 .irq_unmask = exynos5440_gpio_irq_unmask,
870 .irq_mask = exynos5440_gpio_irq_mask,
871};
872
873/* interrupt handler for GPIO interrupts 0..7 */
874static irqreturn_t exynos5440_gpio_irq(int irq, void *data)
875{
876 struct exynos5440_gpio_intr_data *intd = data;
877 struct exynos5440_pinctrl_priv_data *d = intd->priv;
878 int virq;
879
880 virq = irq_linear_revmap(d->irq_domain, intd->gpio_int);
881 if (!virq)
882 return IRQ_NONE;
883 generic_handle_irq(virq);
884 return IRQ_HANDLED;
885}
886
887static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq,
888 irq_hw_number_t hw)
889{
890 struct exynos5440_pinctrl_priv_data *d = h->host_data;
891
892 irq_set_chip_data(virq, d);
893 irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip,
894 handle_level_irq);
895 return 0;
896}
897
898/* irq domain callbacks for gpio interrupt controller */
899static const struct irq_domain_ops exynos5440_gpio_irqd_ops = {
900 .map = exynos5440_gpio_irq_map,
901 .xlate = irq_domain_xlate_twocell,
902};
903
904/* setup handling of gpio interrupts */
905static int exynos5440_gpio_irq_init(struct platform_device *pdev,
906 struct exynos5440_pinctrl_priv_data *priv)
907{
908 struct device *dev = &pdev->dev;
909 struct exynos5440_gpio_intr_data *intd;
910 int i, irq, ret;
911
912 intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT,
913 GFP_KERNEL);
914 if (!intd)
915 return -ENOMEM;
916
917 for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) {
918 irq = irq_of_parse_and_map(dev->of_node, i);
919 if (irq <= 0) {
920 dev_err(dev, "irq parsing failed\n");
921 return -EINVAL;
922 }
923
924 intd->gpio_int = i;
925 intd->priv = priv;
926 ret = devm_request_irq(dev, irq, exynos5440_gpio_irq,
927 0, dev_name(dev), intd++);
928 if (ret) {
929 dev_err(dev, "irq request failed\n");
930 return -ENXIO;
931 }
932 }
933
934 priv->irq_domain = irq_domain_add_linear(dev->of_node,
935 EXYNOS5440_MAX_GPIO_INT,
936 &exynos5440_gpio_irqd_ops, priv);
937 if (!priv->irq_domain) {
938 dev_err(dev, "failed to create irq domain\n");
939 return -ENXIO;
940 }
941
942 return 0;
943}
944
945static int exynos5440_pinctrl_probe(struct platform_device *pdev)
946{
947 struct device *dev = &pdev->dev;
948 struct exynos5440_pinctrl_priv_data *priv;
949 struct resource *res;
950 int ret;
951
952 if (!dev->of_node) {
953 dev_err(dev, "device tree node not found\n");
954 return -ENODEV;
955 }
956
957 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
958 if (!priv)
959 return -ENOMEM;
960
961 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
962 priv->reg_base = devm_ioremap_resource(&pdev->dev, res);
963 if (IS_ERR(priv->reg_base))
964 return PTR_ERR(priv->reg_base);
965
966 ret = exynos5440_gpiolib_register(pdev, priv);
967 if (ret)
968 return ret;
969
970 ret = exynos5440_pinctrl_register(pdev, priv);
971 if (ret) {
972 exynos5440_gpiolib_unregister(pdev, priv);
973 return ret;
974 }
975
976 ret = exynos5440_gpio_irq_init(pdev, priv);
977 if (ret) {
978 dev_err(dev, "failed to setup gpio interrupts\n");
979 return ret;
980 }
981
982 platform_set_drvdata(pdev, priv);
983 dev_info(dev, "EXYNOS5440 pinctrl driver registered\n");
984 return 0;
985}
986
987static const struct of_device_id exynos5440_pinctrl_dt_match[] = {
988 { .compatible = "samsung,exynos5440-pinctrl" },
989 {},
990};
991
992static struct platform_driver exynos5440_pinctrl_driver = {
993 .probe = exynos5440_pinctrl_probe,
994 .driver = {
995 .name = "exynos5440-pinctrl",
996 .of_match_table = exynos5440_pinctrl_dt_match,
997 .suppress_bind_attrs = true,
998 },
999};
1000
1001static int __init exynos5440_pinctrl_drv_register(void)
1002{
1003 return platform_driver_register(&exynos5440_pinctrl_driver);
1004}
1005postcore_initcall(exynos5440_pinctrl_drv_register);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 05:15:14 -0400