diff options
author | Nickey Yang <nickey.yang@rock-chips.com> | 2017-09-26 03:55:22 -0400 |
---|---|---|
committer | Heiko Stuebner <heiko@sntech.de> | 2017-09-26 09:59:17 -0400 |
commit | 0bc15d85d97d44e8979ff91d0c1fbafe6fd4172c (patch) | |
tree | 22f0eb6808d26ab5562aca9b05df1bc2c97f10e4 | |
parent | bb4e6ff01ac356f82327d980e45fee8a65491328 (diff) |
arm64: dts: rockchip: add the grf clk for dw-mipi-dsi on rk3399
The clk of grf must be enabled before writing grf
register for rk3399.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
[the grf clock is already part of the binding since march 2017]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 6aa43fd47148..ab7629c5b856 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi | |||
@@ -1630,8 +1630,8 @@ | |||
1630 | reg = <0x0 0xff960000 0x0 0x8000>; | 1630 | reg = <0x0 0xff960000 0x0 0x8000>; |
1631 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; | 1631 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; |
1632 | clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, | 1632 | clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, |
1633 | <&cru SCLK_DPHY_TX0_CFG>; | 1633 | <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; |
1634 | clock-names = "ref", "pclk", "phy_cfg"; | 1634 | clock-names = "ref", "pclk", "phy_cfg", "grf"; |
1635 | power-domains = <&power RK3399_PD_VIO>; | 1635 | power-domains = <&power RK3399_PD_VIO>; |
1636 | rockchip,grf = <&grf>; | 1636 | rockchip,grf = <&grf>; |
1637 | status = "disabled"; | 1637 | status = "disabled"; |