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authorLinus Torvalds <torvalds@linux-foundation.org>2014-01-23 21:49:36 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-01-23 21:49:36 -0500
commit0ba3307a8ec35252f7b1e222e32889a6f3d9ceb3 (patch)
tree26126ed7a2080a706f0488c215549fc9f5f76a59
parent903a9f77d1d00c8621bc37afd959ac45a4b3ebec (diff)
parentcd2f43a1f7400a74a084094502f70df2e169c6e8 (diff)
Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM driver updates from Olof Johansson: "Updates of SoC-near drivers and other driver updates that makes more sense to take through our tree. The largest part of this is a conversion of device registration for some renesas shmobile/sh devices over to use resources. This has required coordination with the corresponding arch/sh changes, and we've agreed to merge the arch/sh changes through our tree. Added in this branch is support for Trusted Foundations secure firmware, which is what is used on many of the commercial Nvidia Tegra products that are in the market, including the Nvidia Shield. The code is local to arch/arm at this time since it's uncertain whether it will be shared with arm64 longer-term, if needed we will refactor later. A couple of new RTC drivers used on ARM boards, merged through our tree on request by the RTC maintainer. ... plus a bunch of smaller updates across the board, gpio conversions for davinci, etc" * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (45 commits) watchdog: davinci: rename platform driver to davinci-wdt tty: serial: Limit msm_serial_hs driver to platforms that use it mmc: msm_sdcc: Limit driver to platforms that use it usb: phy: msm: Move mach dependent code to platform data clk: versatile: fixup IM-PD1 clock implementation clk: versatile: pass a name to ICST clock provider ARM: integrator: pass parent IRQ to the SIC irqchip: versatile FPGA: support cascaded interrupts from DT gpio: davinci: don't create irq_domain in case of unbanked irqs gpio: davinci: use chained_irq_enter/chained_irq_exit API gpio: davinci: add OF support gpio: davinci: remove unused variable intc_irq_num gpio: davinci: convert to use irqdomain support. gpio: introduce GPIO_DAVINCI kconfig option gpio: davinci: get rid of DAVINCI_N_GPIO gpio: davinci: use {readl|writel}_relaxed() instead of __raw_* serial: sh-sci: Add OF support serial: sh-sci: Add device tree bindings documentation serial: sh-sci: Remove platform data mapbase and irqs fields serial: sh-sci: Remove platform data scbrr_algo_id field ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt20
-rw-r--r--Documentation/devicetree/bindings/arm/tegra.txt5
-rw-r--r--Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt5
-rw-r--r--Documentation/devicetree/bindings/crypto/atmel-crypto.txt68
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-davinci.txt41
-rw-r--r--Documentation/devicetree/bindings/i2c/trivial-devices.txt1
-rw-r--r--Documentation/devicetree/bindings/rtc/sunxi-rtc.txt17
-rw-r--r--Documentation/devicetree/bindings/serial/renesas,sci-serial.txt46
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.txt2
-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/dts/integratorcp.dts3
-rw-r--r--arch/arm/configs/tegra_defconfig1
-rw-r--r--arch/arm/firmware/Kconfig28
-rw-r--r--arch/arm/firmware/Makefile1
-rw-r--r--arch/arm/firmware/trusted_foundations.c81
-rw-r--r--arch/arm/include/asm/trusted_foundations.h67
-rw-r--r--arch/arm/mach-davinci/da830.c3
-rw-r--r--arch/arm/mach-davinci/da850.c3
-rw-r--r--arch/arm/mach-davinci/da8xx-dt.c2
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c4
-rw-r--r--arch/arm/mach-davinci/devices.c2
-rw-r--r--arch/arm/mach-davinci/dm355.c3
-rw-r--r--arch/arm/mach-davinci/dm365.c3
-rw-r--r--arch/arm/mach-davinci/dm644x.c3
-rw-r--r--arch/arm/mach-davinci/dm646x.c3
-rw-r--r--arch/arm/mach-msm/board-msm7x30.c35
-rw-r--r--arch/arm/mach-msm/board-qsd8x50.c35
-rw-r--r--arch/arm/mach-tegra/Kconfig1
-rw-r--r--arch/arm/mach-tegra/reset.c40
-rw-r--r--arch/arm/mach-tegra/tegra.c2
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c30
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c10
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c80
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c40
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c40
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7264.c104
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7269.c104
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c20
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c30
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c20
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c20
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh4-202.c16
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c20
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c62
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c40
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c10
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c30
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c63
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c63
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7734.c72
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c30
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c30
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c100
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c22
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c60
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c88
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c48
-rw-r--r--arch/sh/kernel/cpu/sh5/setup-sh5.c12
-rw-r--r--drivers/bus/mvebu-mbus.c10
-rw-r--r--drivers/clk/versatile/clk-icst.c3
-rw-r--r--drivers/clk/versatile/clk-icst.h1
-rw-r--r--drivers/clk/versatile/clk-impd1.c88
-rw-r--r--drivers/clk/versatile/clk-integrator.c2
-rw-r--r--drivers/clk/versatile/clk-realview.c6
-rw-r--r--drivers/crypto/atmel-aes.c143
-rw-r--r--drivers/crypto/atmel-sha.c103
-rw-r--r--drivers/crypto/atmel-tdes.c143
-rw-r--r--drivers/gpio/Kconfig7
-rw-r--r--drivers/gpio/Makefile2
-rw-r--r--drivers/gpio/gpio-davinci.c185
-rw-r--r--drivers/irqchip/exynos-combiner.c15
-rw-r--r--drivers/irqchip/irq-renesas-irqc.c21
-rw-r--r--drivers/irqchip/irq-versatile-fpga.c15
-rw-r--r--drivers/mmc/host/Kconfig2
-rw-r--r--drivers/rtc/Kconfig18
-rw-r--r--drivers/rtc/Makefile2
-rw-r--r--drivers/rtc/rtc-isl12057.c310
-rw-r--r--drivers/rtc/rtc-sunxi.c523
-rw-r--r--drivers/tty/serial/Kconfig2
-rw-r--r--drivers/tty/serial/sh-sci.c187
-rw-r--r--drivers/usb/host/r8a66597-hcd.c4
-rw-r--r--drivers/usb/phy/phy-msm-usb.c35
-rw-r--r--drivers/watchdog/davinci_wdt.c4
-rw-r--r--include/linux/platform_data/gpio-davinci.h3
-rw-r--r--include/linux/serial_sci.h36
-rw-r--r--include/linux/usb/msm_hsusb.h3
87 files changed, 2914 insertions, 753 deletions
diff --git a/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt b/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt
new file mode 100644
index 000000000000..780d0392a66b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt
@@ -0,0 +1,20 @@
1Trusted Foundations
2-------------------
3
4Boards that use the Trusted Foundations secure monitor can signal its
5presence by declaring a node compatible with "tlm,trusted-foundations"
6under the /firmware/ node
7
8Required properties:
9- compatible: "tlm,trusted-foundations"
10- tlm,version-major: major version number of Trusted Foundations firmware
11- tlm,version-minor: minor version number of Trusted Foundations firmware
12
13Example:
14 firmware {
15 trusted-foundations {
16 compatible = "tlm,trusted-foundations";
17 tlm,version-major = <2>;
18 tlm,version-minor = <8>;
19 };
20 };
diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index ed9c85334436..558ed4b4ef39 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -32,3 +32,8 @@ board-specific compatible values:
32 nvidia,whistler 32 nvidia,whistler
33 toradex,colibri_t20-512 33 toradex,colibri_t20-512
34 toradex,iris 34 toradex,iris
35
36Trusted Foundations
37-------------------------------------------
38Tegra supports the Trusted Foundation secure monitor. See the
39"tlm,trusted-foundations" binding's documentation for more details.
diff --git a/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt
index 9989eda755d9..c9cf605bb995 100644
--- a/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt
+++ b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt
@@ -29,3 +29,8 @@ pic: pic@14000000 {
29 clear-mask = <0xffffffff>; 29 clear-mask = <0xffffffff>;
30 valid-mask = <0x003fffff>; 30 valid-mask = <0x003fffff>;
31}; 31};
32
33Optional properties:
34- interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
35 output is simply connected to the input of another IRQ controller,
36 then the parent IRQ shall be specified in this property.
diff --git a/Documentation/devicetree/bindings/crypto/atmel-crypto.txt b/Documentation/devicetree/bindings/crypto/atmel-crypto.txt
new file mode 100644
index 000000000000..f2aab3dc2b52
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/atmel-crypto.txt
@@ -0,0 +1,68 @@
1* Atmel HW cryptographic accelerators
2
3These are the HW cryptographic accelerators found on some Atmel products.
4
5* Advanced Encryption Standard (AES)
6
7Required properties:
8- compatible : Should be "atmel,at91sam9g46-aes".
9- reg: Should contain AES registers location and length.
10- interrupts: Should contain the IRQ line for the AES.
11- dmas: List of two DMA specifiers as described in
12 atmel-dma.txt and dma.txt files.
13- dma-names: Contains one identifier string for each DMA specifier
14 in the dmas property.
15
16Example:
17aes@f8038000 {
18 compatible = "atmel,at91sam9g46-aes";
19 reg = <0xf8038000 0x100>;
20 interrupts = <43 4 0>;
21 dmas = <&dma1 2 18>,
22 <&dma1 2 19>;
23 dma-names = "tx", "rx";
24
25* Triple Data Encryption Standard (Triple DES)
26
27Required properties:
28- compatible : Should be "atmel,at91sam9g46-tdes".
29- reg: Should contain TDES registers location and length.
30- interrupts: Should contain the IRQ line for the TDES.
31
32Optional properties:
33- dmas: List of two DMA specifiers as described in
34 atmel-dma.txt and dma.txt files.
35- dma-names: Contains one identifier string for each DMA specifier
36 in the dmas property.
37
38Example:
39tdes@f803c000 {
40 compatible = "atmel,at91sam9g46-tdes";
41 reg = <0xf803c000 0x100>;
42 interrupts = <44 4 0>;
43 dmas = <&dma1 2 20>,
44 <&dma1 2 21>;
45 dma-names = "tx", "rx";
46};
47
48* Secure Hash Algorithm (SHA)
49
50Required properties:
51- compatible : Should be "atmel,at91sam9g46-sha".
52- reg: Should contain SHA registers location and length.
53- interrupts: Should contain the IRQ line for the SHA.
54
55Optional properties:
56- dmas: One DMA specifiers as described in
57 atmel-dma.txt and dma.txt files.
58- dma-names: Contains one identifier string for each DMA specifier
59 in the dmas property. Only one "tx" string needed.
60
61Example:
62sha@f8034000 {
63 compatible = "atmel,at91sam9g46-sha";
64 reg = <0xf8034000 0x100>;
65 interrupts = <42 4 0>;
66 dmas = <&dma1 2 17>;
67 dma-names = "tx";
68};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
new file mode 100644
index 000000000000..a2e839d6e338
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
@@ -0,0 +1,41 @@
1Davinci GPIO controller bindings
2
3Required Properties:
4- compatible: should be "ti,dm6441-gpio"
5
6- reg: Physical base address of the controller and the size of memory mapped
7 registers.
8
9- gpio-controller : Marks the device node as a gpio controller.
10
11- interrupt-parent: phandle of the parent interrupt controller.
12
13- interrupts: Array of GPIO interrupt number. Only banked or unbanked IRQs are
14 supported at a time.
15
16- ti,ngpio: The number of GPIO pins supported.
17
18- ti,davinci-gpio-unbanked: The number of GPIOs that have an individual interrupt
19 line to processor.
20
21The GPIO controller also acts as an interrupt controller. It uses the default
22two cells specifier as described in Documentation/devicetree/bindings/
23interrupt-controller/interrupts.txt.
24
25Example:
26
27gpio: gpio@1e26000 {
28 compatible = "ti,dm6441-gpio";
29 gpio-controller;
30 reg = <0x226000 0x1000>;
31 interrupt-parent = <&intc>;
32 interrupts = <42 IRQ_TYPE_EDGE_BOTH 43 IRQ_TYPE_EDGE_BOTH
33 44 IRQ_TYPE_EDGE_BOTH 45 IRQ_TYPE_EDGE_BOTH
34 46 IRQ_TYPE_EDGE_BOTH 47 IRQ_TYPE_EDGE_BOTH
35 48 IRQ_TYPE_EDGE_BOTH 49 IRQ_TYPE_EDGE_BOTH
36 50 IRQ_TYPE_EDGE_BOTH>;
37 ti,ngpio = <144>;
38 ti,davinci-gpio-unbanked = <0>;
39 interrupt-controller;
40 #interrupt-cells = <2>;
41};
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index c65f71cfaa5c..1a1ac2e560e9 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -40,6 +40,7 @@ fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec
40gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface 40gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface
41infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) 41infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz)
42infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) 42infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz)
43isl,isl12057 Intersil ISL12057 I2C RTC Chip
43maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator 44maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator
44maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs 45maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
45maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface 46maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
diff --git a/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt b/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt
new file mode 100644
index 000000000000..7cb9dbf34878
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt
@@ -0,0 +1,17 @@
1* sun4i/sun7i Real Time Clock
2
3RTC controller for the Allwinner A10/A20
4
5Required properties:
6- compatible : Should be "allwinner,sun4i-rtc" or "allwinner,sun7i-a20-rtc"
7- reg: physical base address of the controller and length of memory mapped
8 region.
9- interrupts: IRQ line for the RTC.
10
11Example:
12
13rtc: rtc@01c20d00 {
14 compatible = "allwinner,sun4i-rtc";
15 reg = <0x01c20d00 0x20>;
16 interrupts = <24>;
17};
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
new file mode 100644
index 000000000000..f372cf29068d
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -0,0 +1,46 @@
1* Renesas SH-Mobile Serial Communication Interface
2
3Required properties:
4
5 - compatible: Must contain one of the following:
6
7 - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART.
8 - "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART.
9 - "renesas,scifb-r8a7790" for R8A7790 (R-Car H2) SCIFB compatible UART.
10 - "renesas,hscif-r8a7790" for R8A7790 (R-Car H2) HSCIF compatible UART.
11 - "renesas,scif-r8a7791" for R8A7791 (R-Car M2) SCIF compatible UART.
12 - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2) SCIFA compatible UART.
13 - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2) SCIFB compatible UART.
14 - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2) HSCIF compatible UART.
15 - "renesas,scif" for generic SCIF compatible UART.
16 - "renesas,scifa" for generic SCIFA compatible UART.
17 - "renesas,scifb" for generic SCIFB compatible UART.
18 - "renesas,hscif" for generic HSCIF compatible UART.
19
20 When compatible with the generic version, nodes must list the
21 SoC-specific version corresponding to the platform first followed by the
22 generic version.
23
24 - reg: Base address and length of the I/O registers used by the UART.
25 - interrupts: Must contain an interrupt-specifier for the SCIx interrupt.
26
27 - clocks: Must contain a phandle and clock-specifier pair for each entry
28 in clock-names.
29 - clock-names: Must contain "sci_ick" for the SCIx UART interface clock.
30
31Note: Each enabled SCIx UART should have an alias correctly numbered in the
32"aliases" node.
33
34Example:
35 aliases {
36 serial0 = &scifa0;
37 };
38
39 scifa0: serial@e6c40000 {
40 compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
41 reg = <0 0xe6c40000 0 64>;
42 interrupt-parent = <&gic>;
43 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
44 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
45 clock-names = "sci_ick";
46 };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index f29cd78b6698..ff415d183352 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -40,6 +40,7 @@ ibm International Business Machines (IBM)
40idt Integrated Device Technologies, Inc. 40idt Integrated Device Technologies, Inc.
41img Imagination Technologies Ltd. 41img Imagination Technologies Ltd.
42intercontrol Inter Control Group 42intercontrol Inter Control Group
43isl Intersil
43lg LG Corporation 44lg LG Corporation
44linux Linux-specific binding 45linux Linux-specific binding
45lsi LSI Corp. (LSI Logic) 46lsi LSI Corp. (LSI Logic)
@@ -74,6 +75,7 @@ st STMicroelectronics
74ste ST-Ericsson 75ste ST-Ericsson
75stericsson ST-Ericsson 76stericsson ST-Ericsson
76ti Texas Instruments 77ti Texas Instruments
78tlm Trusted Logic Mobility
77toshiba Toshiba Corporation 79toshiba Toshiba Corporation
78toumaz Toumaz 80toumaz Toumaz
79v3 V3 Semiconductor 81v3 V3 Semiconductor
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 35e6d6b5d7d1..f9b0fd387c6f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -317,6 +317,8 @@ config ARCH_INTEGRATOR
317 bool "ARM Ltd. Integrator family" 317 bool "ARM Ltd. Integrator family"
318 select ARCH_HAS_CPUFREQ 318 select ARCH_HAS_CPUFREQ
319 select ARM_AMBA 319 select ARM_AMBA
320 select ARM_PATCH_PHYS_VIRT
321 select AUTO_ZRELADDR
320 select COMMON_CLK 322 select COMMON_CLK
321 select COMMON_CLK_VERSATILE 323 select COMMON_CLK_VERSATILE
322 select GENERIC_CLOCKEVENTS 324 select GENERIC_CLOCKEVENTS
@@ -1084,6 +1086,8 @@ config ARM_TIMER_SP804
1084 select CLKSRC_MMIO 1086 select CLKSRC_MMIO
1085 select CLKSRC_OF if OF 1087 select CLKSRC_OF if OF
1086 1088
1089source "arch/arm/firmware/Kconfig"
1090
1087source arch/arm/mm/Kconfig 1091source arch/arm/mm/Kconfig
1088 1092
1089config ARM_NR_BANKS 1093config ARM_NR_BANKS
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index d8605046792c..23d5e3946589 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -267,6 +267,7 @@ core-$(CONFIG_KVM_ARM_HOST) += arch/arm/kvm/
267core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/ 267core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
268core-y += arch/arm/net/ 268core-y += arch/arm/net/
269core-y += arch/arm/crypto/ 269core-y += arch/arm/crypto/
270core-y += arch/arm/firmware/
270core-y += $(machdirs) $(platdirs) 271core-y += $(machdirs) $(platdirs)
271 272
272drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ 273drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 7deb3a3182b4..a21c17de9a5e 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -47,8 +47,11 @@
47 valid-mask = <0x00000007>; 47 valid-mask = <0x00000007>;
48 }; 48 };
49 49
50 /* The SIC is cascaded off IRQ 26 on the PIC */
50 sic: sic@ca000000 { 51 sic: sic@ca000000 {
51 compatible = "arm,versatile-fpga-irq"; 52 compatible = "arm,versatile-fpga-irq";
53 interrupt-parent = <&pic>;
54 interrupts = <26>;
52 #interrupt-cells = <1>; 55 #interrupt-cells = <1>;
53 interrupt-controller; 56 interrupt-controller;
54 reg = <0xca000000 0x100>; 57 reg = <0xca000000 0x100>;
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index e38653876541..5fdc9a09d339 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -33,6 +33,7 @@ CONFIG_PCI=y
33CONFIG_PCI_MSI=y 33CONFIG_PCI_MSI=y
34CONFIG_PCI_TEGRA=y 34CONFIG_PCI_TEGRA=y
35CONFIG_PCIEPORTBUS=y 35CONFIG_PCIEPORTBUS=y
36CONFIG_TRUSTED_FOUNDATIONS=y
36CONFIG_SMP=y 37CONFIG_SMP=y
37CONFIG_PREEMPT=y 38CONFIG_PREEMPT=y
38CONFIG_AEABI=y 39CONFIG_AEABI=y
diff --git a/arch/arm/firmware/Kconfig b/arch/arm/firmware/Kconfig
new file mode 100644
index 000000000000..bb00ccf00d66
--- /dev/null
+++ b/arch/arm/firmware/Kconfig
@@ -0,0 +1,28 @@
1config ARCH_SUPPORTS_FIRMWARE
2 bool
3
4config ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
5 bool
6 select ARCH_SUPPORTS_FIRMWARE
7
8menu "Firmware options"
9 depends on ARCH_SUPPORTS_FIRMWARE
10
11config TRUSTED_FOUNDATIONS
12 bool "Trusted Foundations secure monitor support"
13 depends on ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
14 help
15 Some devices (including most Tegra-based consumer devices on the
16 market) are booted with the Trusted Foundations secure monitor
17 active, requiring some core operations to be performed by the secure
18 monitor instead of the kernel.
19
20 This option allows the kernel to invoke the secure monitor whenever
21 required on devices using Trusted Foundations. See
22 arch/arm/include/asm/trusted_foundations.h or the
23 tl,trusted-foundations device tree binding documentation for details
24 on how to use it.
25
26 Say n if you don't know what this is about.
27
28endmenu
diff --git a/arch/arm/firmware/Makefile b/arch/arm/firmware/Makefile
new file mode 100644
index 000000000000..a71f16536b6c
--- /dev/null
+++ b/arch/arm/firmware/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o
diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c
new file mode 100644
index 000000000000..ef1e3d8f4af0
--- /dev/null
+++ b/arch/arm/firmware/trusted_foundations.c
@@ -0,0 +1,81 @@
1/*
2 * Trusted Foundations support for ARM CPUs
3 *
4 * Copyright (c) 2013, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/of.h>
20#include <asm/firmware.h>
21#include <asm/trusted_foundations.h>
22
23#define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
24
25static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2)
26{
27 asm volatile(
28 ".arch_extension sec\n\t"
29 "stmfd sp!, {r4 - r11, lr}\n\t"
30 __asmeq("%0", "r0")
31 __asmeq("%1", "r1")
32 __asmeq("%2", "r2")
33 "mov r3, #0\n\t"
34 "mov r4, #0\n\t"
35 "smc #0\n\t"
36 "ldmfd sp!, {r4 - r11, pc}"
37 :
38 : "r" (type), "r" (arg1), "r" (arg2)
39 : "memory");
40}
41
42static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
43{
44 tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, boot_addr, 0);
45
46 return 0;
47}
48
49static const struct firmware_ops trusted_foundations_ops = {
50 .set_cpu_boot_addr = tf_set_cpu_boot_addr,
51};
52
53void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
54{
55 /*
56 * we are not using version information for now since currently
57 * supported SMCs are compatible with all TF releases
58 */
59 register_firmware_ops(&trusted_foundations_ops);
60}
61
62void of_register_trusted_foundations(void)
63{
64 struct device_node *node;
65 struct trusted_foundations_platform_data pdata;
66 int err;
67
68 node = of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations");
69 if (!node)
70 return;
71
72 err = of_property_read_u32(node, "tlm,version-major",
73 &pdata.version_major);
74 if (err != 0)
75 panic("Trusted Foundation: missing version-major property\n");
76 err = of_property_read_u32(node, "tlm,version-minor",
77 &pdata.version_minor);
78 if (err != 0)
79 panic("Trusted Foundation: missing version-minor property\n");
80 register_trusted_foundations(&pdata);
81}
diff --git a/arch/arm/include/asm/trusted_foundations.h b/arch/arm/include/asm/trusted_foundations.h
new file mode 100644
index 000000000000..3bd36e2c5f2e
--- /dev/null
+++ b/arch/arm/include/asm/trusted_foundations.h
@@ -0,0 +1,67 @@
1/*
2 * Copyright (c) 2013, NVIDIA Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15/*
16 * Support for the Trusted Foundations secure monitor.
17 *
18 * Trusted Foundation comes active on some ARM consumer devices (most
19 * Tegra-based devices sold on the market are concerned). Such devices can only
20 * perform some basic operations, like setting the CPU reset vector, through
21 * SMC calls to the secure monitor. The calls are completely specific to
22 * Trusted Foundations, and do *not* follow the SMC calling convention or the
23 * PSCI standard.
24 */
25
26#ifndef __ASM_ARM_TRUSTED_FOUNDATIONS_H
27#define __ASM_ARM_TRUSTED_FOUNDATIONS_H
28
29#include <linux/kconfig.h>
30#include <linux/printk.h>
31#include <linux/bug.h>
32#include <linux/of.h>
33
34struct trusted_foundations_platform_data {
35 unsigned int version_major;
36 unsigned int version_minor;
37};
38
39#if IS_ENABLED(CONFIG_TRUSTED_FOUNDATIONS)
40
41void register_trusted_foundations(struct trusted_foundations_platform_data *pd);
42void of_register_trusted_foundations(void);
43
44#else /* CONFIG_TRUSTED_FOUNDATIONS */
45
46static inline void register_trusted_foundations(
47 struct trusted_foundations_platform_data *pd)
48{
49 /*
50 * If we try to register TF, this means the system needs it to continue.
51 * Its absence if thus a fatal error.
52 */
53 panic("No support for Trusted Foundations, stopping...\n");
54}
55
56static inline void of_register_trusted_foundations(void)
57{
58 /*
59 * If we find the target should enable TF but does not support it,
60 * fail as the system won't be able to do much anyway
61 */
62 if (of_find_compatible_node(NULL, NULL, "tl,trusted-foundations"))
63 register_trusted_foundations(NULL);
64}
65#endif /* CONFIG_TRUSTED_FOUNDATIONS */
66
67#endif
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 0813b5167e05..115d5736da80 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -385,7 +385,7 @@ static struct clk_lookup da830_clks[] = {
385 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), 385 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
386 CLK("i2c_davinci.1", NULL, &i2c0_clk), 386 CLK("i2c_davinci.1", NULL, &i2c0_clk),
387 CLK(NULL, "timer0", &timerp64_0_clk), 387 CLK(NULL, "timer0", &timerp64_0_clk),
388 CLK("watchdog", NULL, &timerp64_1_clk), 388 CLK("davinci-wdt", NULL, &timerp64_1_clk),
389 CLK(NULL, "arm_rom", &arm_rom_clk), 389 CLK(NULL, "arm_rom", &arm_rom_clk),
390 CLK(NULL, "scr0_ss", &scr0_ss_clk), 390 CLK(NULL, "scr0_ss", &scr0_ss_clk),
391 CLK(NULL, "scr1_ss", &scr1_ss_clk), 391 CLK(NULL, "scr1_ss", &scr1_ss_clk),
@@ -1153,7 +1153,6 @@ static struct davinci_id da830_ids[] = {
1153 1153
1154static struct davinci_gpio_platform_data da830_gpio_platform_data = { 1154static struct davinci_gpio_platform_data da830_gpio_platform_data = {
1155 .ngpio = 128, 1155 .ngpio = 128,
1156 .intc_irq_num = DA830_N_CP_INTC_IRQ,
1157}; 1156};
1158 1157
1159int __init da830_register_gpio(void) 1158int __init da830_register_gpio(void)
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 352984e1528a..2ab00434b2eb 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -443,7 +443,7 @@ static struct clk_lookup da850_clks[] = {
443 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), 443 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
444 CLK("i2c_davinci.1", NULL, &i2c0_clk), 444 CLK("i2c_davinci.1", NULL, &i2c0_clk),
445 CLK(NULL, "timer0", &timerp64_0_clk), 445 CLK(NULL, "timer0", &timerp64_0_clk),
446 CLK("watchdog", NULL, &timerp64_1_clk), 446 CLK("davinci-wdt", NULL, &timerp64_1_clk),
447 CLK(NULL, "arm_rom", &arm_rom_clk), 447 CLK(NULL, "arm_rom", &arm_rom_clk),
448 CLK(NULL, "tpcc0", &tpcc0_clk), 448 CLK(NULL, "tpcc0", &tpcc0_clk),
449 CLK(NULL, "tptc0", &tptc0_clk), 449 CLK(NULL, "tptc0", &tptc0_clk),
@@ -1283,7 +1283,6 @@ int __init da850_register_vpif_capture(struct vpif_capture_config
1283 1283
1284static struct davinci_gpio_platform_data da850_gpio_platform_data = { 1284static struct davinci_gpio_platform_data da850_gpio_platform_data = {
1285 .ngpio = 144, 1285 .ngpio = 144,
1286 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1287}; 1286};
1288 1287
1289int __init da850_register_gpio(void) 1288int __init da850_register_gpio(void)
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index d2bc574ae172..ed1928740b5f 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -32,7 +32,7 @@ static void __init da8xx_init_irq(void)
32 32
33static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { 33static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
34 OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL), 34 OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL),
35 OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "watchdog", NULL), 35 OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "davinci-wdt", NULL),
36 OF_DEV_AUXDATA("ti,da830-mmc", 0x01c40000, "da830-mmc.0", NULL), 36 OF_DEV_AUXDATA("ti,da830-mmc", 0x01c40000, "da830-mmc.0", NULL),
37 OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f00000, "ehrpwm", NULL), 37 OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f00000, "ehrpwm", NULL),
38 OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f02000, "ehrpwm", NULL), 38 OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f02000, "ehrpwm", NULL),
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 78829c513fdc..0486cdf28c8d 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -389,7 +389,7 @@ static struct resource da8xx_watchdog_resources[] = {
389}; 389};
390 390
391static struct platform_device da8xx_wdt_device = { 391static struct platform_device da8xx_wdt_device = {
392 .name = "watchdog", 392 .name = "davinci-wdt",
393 .id = -1, 393 .id = -1,
394 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), 394 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
395 .resource = da8xx_watchdog_resources, 395 .resource = da8xx_watchdog_resources,
@@ -399,7 +399,7 @@ void da8xx_restart(enum reboot_mode mode, const char *cmd)
399{ 399{
400 struct device *dev; 400 struct device *dev;
401 401
402 dev = bus_find_device_by_name(&platform_bus_type, NULL, "watchdog"); 402 dev = bus_find_device_by_name(&platform_bus_type, NULL, "davinci-wdt");
403 if (!dev) { 403 if (!dev) {
404 pr_err("%s: failed to find watchdog device\n", __func__); 404 pr_err("%s: failed to find watchdog device\n", __func__);
405 return; 405 return;
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 3996e98f52fb..5cf9a027dcc6 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -302,7 +302,7 @@ static struct resource wdt_resources[] = {
302}; 302};
303 303
304struct platform_device davinci_wdt_device = { 304struct platform_device davinci_wdt_device = {
305 .name = "watchdog", 305 .name = "davinci-wdt",
306 .id = -1, 306 .id = -1,
307 .num_resources = ARRAY_SIZE(wdt_resources), 307 .num_resources = ARRAY_SIZE(wdt_resources),
308 .resource = wdt_resources, 308 .resource = wdt_resources,
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 6117fc644188..4668c0e19767 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -375,7 +375,7 @@ static struct clk_lookup dm355_clks[] = {
375 CLK(NULL, "pwm3", &pwm3_clk), 375 CLK(NULL, "pwm3", &pwm3_clk),
376 CLK(NULL, "timer0", &timer0_clk), 376 CLK(NULL, "timer0", &timer0_clk),
377 CLK(NULL, "timer1", &timer1_clk), 377 CLK(NULL, "timer1", &timer1_clk),
378 CLK("watchdog", NULL, &timer2_clk), 378 CLK("davinci-wdt", NULL, &timer2_clk),
379 CLK(NULL, "timer3", &timer3_clk), 379 CLK(NULL, "timer3", &timer3_clk),
380 CLK(NULL, "rto", &rto_clk), 380 CLK(NULL, "rto", &rto_clk),
381 CLK(NULL, "usb", &usb_clk), 381 CLK(NULL, "usb", &usb_clk),
@@ -901,7 +901,6 @@ static struct resource dm355_gpio_resources[] = {
901 901
902static struct davinci_gpio_platform_data dm355_gpio_platform_data = { 902static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
903 .ngpio = 104, 903 .ngpio = 104,
904 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
905}; 904};
906 905
907int __init dm355_gpio_register(void) 906int __init dm355_gpio_register(void)
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index d7c6f85d3fc9..b44b49e2801a 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -473,7 +473,7 @@ static struct clk_lookup dm365_clks[] = {
473 CLK(NULL, "pwm3", &pwm3_clk), 473 CLK(NULL, "pwm3", &pwm3_clk),
474 CLK(NULL, "timer0", &timer0_clk), 474 CLK(NULL, "timer0", &timer0_clk),
475 CLK(NULL, "timer1", &timer1_clk), 475 CLK(NULL, "timer1", &timer1_clk),
476 CLK("watchdog", NULL, &timer2_clk), 476 CLK("davinci-wdt", NULL, &timer2_clk),
477 CLK(NULL, "timer3", &timer3_clk), 477 CLK(NULL, "timer3", &timer3_clk),
478 CLK(NULL, "usb", &usb_clk), 478 CLK(NULL, "usb", &usb_clk),
479 CLK("davinci_emac.1", NULL, &emac_clk), 479 CLK("davinci_emac.1", NULL, &emac_clk),
@@ -713,7 +713,6 @@ static struct resource dm365_gpio_resources[] = {
713 713
714static struct davinci_gpio_platform_data dm365_gpio_platform_data = { 714static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
715 .ngpio = 104, 715 .ngpio = 104,
716 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
717 .gpio_unbanked = 8, 716 .gpio_unbanked = 8,
718}; 717};
719 718
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 3ce47997bb46..5c3e0be95ef3 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -322,7 +322,7 @@ static struct clk_lookup dm644x_clks[] = {
322 CLK(NULL, "pwm2", &pwm2_clk), 322 CLK(NULL, "pwm2", &pwm2_clk),
323 CLK(NULL, "timer0", &timer0_clk), 323 CLK(NULL, "timer0", &timer0_clk),
324 CLK(NULL, "timer1", &timer1_clk), 324 CLK(NULL, "timer1", &timer1_clk),
325 CLK("watchdog", NULL, &timer2_clk), 325 CLK("davinci-wdt", NULL, &timer2_clk),
326 CLK(NULL, NULL, NULL), 326 CLK(NULL, NULL, NULL),
327}; 327};
328 328
@@ -787,7 +787,6 @@ static struct resource dm644_gpio_resources[] = {
787 787
788static struct davinci_gpio_platform_data dm644_gpio_platform_data = { 788static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
789 .ngpio = 71, 789 .ngpio = 71,
790 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
791}; 790};
792 791
793int __init dm644x_gpio_register(void) 792int __init dm644x_gpio_register(void)
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 0e81fea65e7f..81768dd47096 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -356,7 +356,7 @@ static struct clk_lookup dm646x_clks[] = {
356 CLK(NULL, "pwm1", &pwm1_clk), 356 CLK(NULL, "pwm1", &pwm1_clk),
357 CLK(NULL, "timer0", &timer0_clk), 357 CLK(NULL, "timer0", &timer0_clk),
358 CLK(NULL, "timer1", &timer1_clk), 358 CLK(NULL, "timer1", &timer1_clk),
359 CLK("watchdog", NULL, &timer2_clk), 359 CLK("davinci-wdt", NULL, &timer2_clk),
360 CLK("palm_bk3710", NULL, &ide_clk), 360 CLK("palm_bk3710", NULL, &ide_clk),
361 CLK(NULL, "vpif0", &vpif0_clk), 361 CLK(NULL, "vpif0", &vpif0_clk),
362 CLK(NULL, "vpif1", &vpif1_clk), 362 CLK(NULL, "vpif1", &vpif1_clk),
@@ -763,7 +763,6 @@ static struct resource dm646x_gpio_resources[] = {
763 763
764static struct davinci_gpio_platform_data dm646x_gpio_platform_data = { 764static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
765 .ngpio = 43, 765 .ngpio = 43,
766 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
767}; 766};
768 767
769int __init dm646x_gpio_register(void) 768int __init dm646x_gpio_register(void)
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index f9af5a46e8b6..46de789ad3ae 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -30,6 +30,7 @@
30#include <asm/memory.h> 30#include <asm/memory.h>
31#include <asm/setup.h> 31#include <asm/setup.h>
32 32
33#include <mach/clk.h>
33#include <mach/msm_iomap.h> 34#include <mach/msm_iomap.h>
34#include <mach/dma.h> 35#include <mach/dma.h>
35 36
@@ -60,10 +61,44 @@ static int hsusb_phy_init_seq[] = {
60 -1 61 -1
61}; 62};
62 63
64static int hsusb_link_clk_reset(struct clk *link_clk, bool assert)
65{
66 int ret;
67
68 if (assert) {
69 ret = clk_reset(link_clk, CLK_RESET_ASSERT);
70 if (ret)
71 pr_err("usb hs_clk assert failed\n");
72 } else {
73 ret = clk_reset(link_clk, CLK_RESET_DEASSERT);
74 if (ret)
75 pr_err("usb hs_clk deassert failed\n");
76 }
77 return ret;
78}
79
80static int hsusb_phy_clk_reset(struct clk *phy_clk)
81{
82 int ret;
83
84 ret = clk_reset(phy_clk, CLK_RESET_ASSERT);
85 if (ret) {
86 pr_err("usb phy clk assert failed\n");
87 return ret;
88 }
89 usleep_range(10000, 12000);
90 ret = clk_reset(phy_clk, CLK_RESET_DEASSERT);
91 if (ret)
92 pr_err("usb phy clk deassert failed\n");
93 return ret;
94}
95
63static struct msm_otg_platform_data msm_otg_pdata = { 96static struct msm_otg_platform_data msm_otg_pdata = {
64 .phy_init_seq = hsusb_phy_init_seq, 97 .phy_init_seq = hsusb_phy_init_seq,
65 .mode = USB_PERIPHERAL, 98 .mode = USB_PERIPHERAL,
66 .otg_control = OTG_PHY_CONTROL, 99 .otg_control = OTG_PHY_CONTROL,
100 .link_clk_reset = hsusb_link_clk_reset,
101 .phy_clk_reset = hsusb_phy_clk_reset,
67}; 102};
68 103
69struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { 104struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 5f933bc50783..9169ec324a43 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -31,6 +31,7 @@
31#include <mach/irqs.h> 31#include <mach/irqs.h>
32#include <mach/sirc.h> 32#include <mach/sirc.h>
33#include <mach/vreg.h> 33#include <mach/vreg.h>
34#include <mach/clk.h>
34#include <linux/platform_data/mmc-msm_sdcc.h> 35#include <linux/platform_data/mmc-msm_sdcc.h>
35 36
36#include "devices.h" 37#include "devices.h"
@@ -81,10 +82,44 @@ static int hsusb_phy_init_seq[] = {
81 -1 82 -1
82}; 83};
83 84
85static int hsusb_link_clk_reset(struct clk *link_clk, bool assert)
86{
87 int ret;
88
89 if (assert) {
90 ret = clk_reset(link_clk, CLK_RESET_ASSERT);
91 if (ret)
92 pr_err("usb hs_clk assert failed\n");
93 } else {
94 ret = clk_reset(link_clk, CLK_RESET_DEASSERT);
95 if (ret)
96 pr_err("usb hs_clk deassert failed\n");
97 }
98 return ret;
99}
100
101static int hsusb_phy_clk_reset(struct clk *phy_clk)
102{
103 int ret;
104
105 ret = clk_reset(phy_clk, CLK_RESET_ASSERT);
106 if (ret) {
107 pr_err("usb phy clk assert failed\n");
108 return ret;
109 }
110 usleep_range(10000, 12000);
111 ret = clk_reset(phy_clk, CLK_RESET_DEASSERT);
112 if (ret)
113 pr_err("usb phy clk deassert failed\n");
114 return ret;
115}
116
84static struct msm_otg_platform_data msm_otg_pdata = { 117static struct msm_otg_platform_data msm_otg_pdata = {
85 .phy_init_seq = hsusb_phy_init_seq, 118 .phy_init_seq = hsusb_phy_init_seq,
86 .mode = USB_PERIPHERAL, 119 .mode = USB_PERIPHERAL,
87 .otg_control = OTG_PHY_CONTROL, 120 .otg_control = OTG_PHY_CONTROL,
121 .link_clk_reset = hsusb_link_clk_reset,
122 .phy_clk_reset = hsusb_phy_clk_reset,
88}; 123};
89 124
90static struct platform_device *devices[] __initdata = { 125static struct platform_device *devices[] __initdata = {
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index d1a12a496525..b1232d8be6f5 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -2,6 +2,7 @@ config ARCH_TEGRA
2 bool "NVIDIA Tegra" if ARCH_MULTI_V7 2 bool "NVIDIA Tegra" if ARCH_MULTI_V7
3 select ARCH_HAS_CPUFREQ 3 select ARCH_HAS_CPUFREQ
4 select ARCH_REQUIRE_GPIOLIB 4 select ARCH_REQUIRE_GPIOLIB
5 select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
5 select ARM_GIC 6 select ARM_GIC
6 select CLKSRC_MMIO 7 select CLKSRC_MMIO
7 select CLKSRC_OF 8 select CLKSRC_OF
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 568f5bbf979d..146fe8e0ae7c 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -21,6 +21,7 @@
21 21
22#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
23#include <asm/hardware/cache-l2x0.h> 23#include <asm/hardware/cache-l2x0.h>
24#include <asm/firmware.h>
24 25
25#include "iomap.h" 26#include "iomap.h"
26#include "irammap.h" 27#include "irammap.h"
@@ -33,26 +34,18 @@
33 34
34static bool is_enabled; 35static bool is_enabled;
35 36
36static void __init tegra_cpu_reset_handler_enable(void) 37static void __init tegra_cpu_reset_handler_set(const u32 reset_address)
37{ 38{
38 void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
39 void __iomem *evp_cpu_reset = 39 void __iomem *evp_cpu_reset =
40 IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); 40 IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
41 void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); 41 void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
42 u32 reg; 42 u32 reg;
43 43
44 BUG_ON(is_enabled);
45 BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
46
47 memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
48 tegra_cpu_reset_handler_size);
49
50 /* 44 /*
51 * NOTE: This must be the one and only write to the EVP CPU reset 45 * NOTE: This must be the one and only write to the EVP CPU reset
52 * vector in the entire system. 46 * vector in the entire system.
53 */ 47 */
54 writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset, 48 writel(reset_address, evp_cpu_reset);
55 evp_cpu_reset);
56 wmb(); 49 wmb();
57 reg = readl(evp_cpu_reset); 50 reg = readl(evp_cpu_reset);
58 51
@@ -66,8 +59,33 @@ static void __init tegra_cpu_reset_handler_enable(void)
66 writel(reg, sb_ctrl); 59 writel(reg, sb_ctrl);
67 wmb(); 60 wmb();
68 } 61 }
62}
63
64static void __init tegra_cpu_reset_handler_enable(void)
65{
66 void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
67 const u32 reset_address = TEGRA_IRAM_RESET_BASE +
68 tegra_cpu_reset_handler_offset;
69 int err;
70
71 BUG_ON(is_enabled);
72 BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
69 73
70 is_enabled = true; 74 memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
75 tegra_cpu_reset_handler_size);
76
77 err = call_firmware_op(set_cpu_boot_addr, 0, reset_address);
78 switch (err) {
79 case -ENOSYS:
80 tegra_cpu_reset_handler_set(reset_address);
81 /* pass-through */
82 case 0:
83 is_enabled = true;
84 break;
85 default:
86 pr_crit("Cannot set CPU reset handler: %d\n", err);
87 BUG();
88 }
71} 89}
72 90
73void __init tegra_cpu_reset_handler_init(void) 91void __init tegra_cpu_reset_handler_init(void)
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index ea14d380fc0c..303a285d80fd 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -40,6 +40,7 @@
40#include <asm/mach/arch.h> 40#include <asm/mach/arch.h>
41#include <asm/mach/time.h> 41#include <asm/mach/time.h>
42#include <asm/setup.h> 42#include <asm/setup.h>
43#include <asm/trusted_foundations.h>
43 44
44#include "apbio.h" 45#include "apbio.h"
45#include "board.h" 46#include "board.h"
@@ -88,6 +89,7 @@ static void __init tegra_init_cache(void)
88 89
89static void __init tegra_init_early(void) 90static void __init tegra_init_early(void)
90{ 91{
92 of_register_trusted_foundations();
91 tegra_apb_io_init(); 93 tegra_apb_io_init();
92 tegra_init_fuse(); 94 tegra_init_fuse();
93 tegra_cpu_reset_handler_init(); 95 tegra_cpu_reset_handler_init();
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 4df4d4ffe39b..3860b0be56c7 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -61,51 +61,63 @@ static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
61 NULL, prio_registers, NULL); 61 NULL, prio_registers, NULL);
62 62
63static struct plat_sci_port scif0_platform_data = { 63static struct plat_sci_port scif0_platform_data = {
64 .mapbase = 0xf8400000,
65 .flags = UPF_BOOT_AUTOCONF, 64 .flags = UPF_BOOT_AUTOCONF,
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 65 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2,
68 .type = PORT_SCIF, 66 .type = PORT_SCIF,
69 .irqs = SCIx_IRQ_MUXED(88), 67};
68
69static struct resource scif0_resources[] = {
70 DEFINE_RES_MEM(0xf8400000, 0x100),
71 DEFINE_RES_IRQ(88),
70}; 72};
71 73
72static struct platform_device scif0_device = { 74static struct platform_device scif0_device = {
73 .name = "sh-sci", 75 .name = "sh-sci",
74 .id = 0, 76 .id = 0,
77 .resource = scif0_resources,
78 .num_resources = ARRAY_SIZE(scif0_resources),
75 .dev = { 79 .dev = {
76 .platform_data = &scif0_platform_data, 80 .platform_data = &scif0_platform_data,
77 }, 81 },
78}; 82};
79 83
80static struct plat_sci_port scif1_platform_data = { 84static struct plat_sci_port scif1_platform_data = {
81 .mapbase = 0xf8410000,
82 .flags = UPF_BOOT_AUTOCONF, 85 .flags = UPF_BOOT_AUTOCONF,
83 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 86 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
84 .scbrr_algo_id = SCBRR_ALGO_2,
85 .type = PORT_SCIF, 87 .type = PORT_SCIF,
86 .irqs = SCIx_IRQ_MUXED(92), 88};
89
90static struct resource scif1_resources[] = {
91 DEFINE_RES_MEM(0xf8410000, 0x100),
92 DEFINE_RES_IRQ(92),
87}; 93};
88 94
89static struct platform_device scif1_device = { 95static struct platform_device scif1_device = {
90 .name = "sh-sci", 96 .name = "sh-sci",
91 .id = 1, 97 .id = 1,
98 .resource = scif1_resources,
99 .num_resources = ARRAY_SIZE(scif1_resources),
92 .dev = { 100 .dev = {
93 .platform_data = &scif1_platform_data, 101 .platform_data = &scif1_platform_data,
94 }, 102 },
95}; 103};
96 104
97static struct plat_sci_port scif2_platform_data = { 105static struct plat_sci_port scif2_platform_data = {
98 .mapbase = 0xf8420000,
99 .flags = UPF_BOOT_AUTOCONF, 106 .flags = UPF_BOOT_AUTOCONF,
100 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 107 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
101 .scbrr_algo_id = SCBRR_ALGO_2,
102 .type = PORT_SCIF, 108 .type = PORT_SCIF,
103 .irqs = SCIx_IRQ_MUXED(96), 109};
110
111static struct resource scif2_resources[] = {
112 DEFINE_RES_MEM(0xf8420000, 0x100),
113 DEFINE_RES_IRQ(96),
104}; 114};
105 115
106static struct platform_device scif2_device = { 116static struct platform_device scif2_device = {
107 .name = "sh-sci", 117 .name = "sh-sci",
108 .id = 2, 118 .id = 2,
119 .resource = scif2_resources,
120 .num_resources = ARRAY_SIZE(scif2_resources),
109 .dev = { 121 .dev = {
110 .platform_data = &scif2_platform_data, 122 .platform_data = &scif2_platform_data,
111 }, 123 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index f7f1cf2af302..63e996f9a7ed 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -199,17 +199,21 @@ static struct platform_device mtu2_2_device = {
199}; 199};
200 200
201static struct plat_sci_port scif0_platform_data = { 201static struct plat_sci_port scif0_platform_data = {
202 .mapbase = 0xff804000,
203 .flags = UPF_BOOT_AUTOCONF, 202 .flags = UPF_BOOT_AUTOCONF,
204 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 203 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
205 .scbrr_algo_id = SCBRR_ALGO_2,
206 .type = PORT_SCIF, 204 .type = PORT_SCIF,
207 .irqs = SCIx_IRQ_MUXED(220), 205};
206
207static struct resource scif0_resources[] = {
208 DEFINE_RES_MEM(0xff804000, 0x100),
209 DEFINE_RES_IRQ(220),
208}; 210};
209 211
210static struct platform_device scif0_device = { 212static struct platform_device scif0_device = {
211 .name = "sh-sci", 213 .name = "sh-sci",
212 .id = 0, 214 .id = 0,
215 .resource = scif0_resources,
216 .num_resources = ARRAY_SIZE(scif0_resources),
213 .dev = { 217 .dev = {
214 .platform_data = &scif0_platform_data, 218 .platform_data = &scif0_platform_data,
215 }, 219 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 7b84785b8962..2c6874461536 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -178,136 +178,168 @@ static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
178 mask_registers, prio_registers, NULL); 178 mask_registers, prio_registers, NULL);
179 179
180static struct plat_sci_port scif0_platform_data = { 180static struct plat_sci_port scif0_platform_data = {
181 .mapbase = 0xfffe8000,
182 .flags = UPF_BOOT_AUTOCONF, 181 .flags = UPF_BOOT_AUTOCONF,
183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 182 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
184 .scbrr_algo_id = SCBRR_ALGO_2,
185 .type = PORT_SCIF, 183 .type = PORT_SCIF,
186 .irqs = SCIx_IRQ_MUXED(180), 184};
185
186static struct resource scif0_resources[] = {
187 DEFINE_RES_MEM(0xfffe8000, 0x100),
188 DEFINE_RES_IRQ(180),
187}; 189};
188 190
189static struct platform_device scif0_device = { 191static struct platform_device scif0_device = {
190 .name = "sh-sci", 192 .name = "sh-sci",
191 .id = 0, 193 .id = 0,
194 .resource = scif0_resources,
195 .num_resources = ARRAY_SIZE(scif0_resources),
192 .dev = { 196 .dev = {
193 .platform_data = &scif0_platform_data, 197 .platform_data = &scif0_platform_data,
194 }, 198 },
195}; 199};
196 200
197static struct plat_sci_port scif1_platform_data = { 201static struct plat_sci_port scif1_platform_data = {
198 .mapbase = 0xfffe8800,
199 .flags = UPF_BOOT_AUTOCONF, 202 .flags = UPF_BOOT_AUTOCONF,
200 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 203 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
201 .scbrr_algo_id = SCBRR_ALGO_2,
202 .type = PORT_SCIF, 204 .type = PORT_SCIF,
203 .irqs = SCIx_IRQ_MUXED(184), 205};
206
207static struct resource scif1_resources[] = {
208 DEFINE_RES_MEM(0xfffe8800, 0x100),
209 DEFINE_RES_IRQ(184),
204}; 210};
205 211
206static struct platform_device scif1_device = { 212static struct platform_device scif1_device = {
207 .name = "sh-sci", 213 .name = "sh-sci",
208 .id = 1, 214 .id = 1,
215 .resource = scif1_resources,
216 .num_resources = ARRAY_SIZE(scif1_resources),
209 .dev = { 217 .dev = {
210 .platform_data = &scif1_platform_data, 218 .platform_data = &scif1_platform_data,
211 }, 219 },
212}; 220};
213 221
214static struct plat_sci_port scif2_platform_data = { 222static struct plat_sci_port scif2_platform_data = {
215 .mapbase = 0xfffe9000,
216 .flags = UPF_BOOT_AUTOCONF, 223 .flags = UPF_BOOT_AUTOCONF,
217 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 224 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
218 .scbrr_algo_id = SCBRR_ALGO_2,
219 .type = PORT_SCIF, 225 .type = PORT_SCIF,
220 .irqs = SCIx_IRQ_MUXED(188), 226};
227
228static struct resource scif2_resources[] = {
229 DEFINE_RES_MEM(0xfffe9000, 0x100),
230 DEFINE_RES_IRQ(188),
221}; 231};
222 232
223static struct platform_device scif2_device = { 233static struct platform_device scif2_device = {
224 .name = "sh-sci", 234 .name = "sh-sci",
225 .id = 2, 235 .id = 2,
236 .resource = scif2_resources,
237 .num_resources = ARRAY_SIZE(scif2_resources),
226 .dev = { 238 .dev = {
227 .platform_data = &scif2_platform_data, 239 .platform_data = &scif2_platform_data,
228 }, 240 },
229}; 241};
230 242
231static struct plat_sci_port scif3_platform_data = { 243static struct plat_sci_port scif3_platform_data = {
232 .mapbase = 0xfffe9800,
233 .flags = UPF_BOOT_AUTOCONF, 244 .flags = UPF_BOOT_AUTOCONF,
234 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 245 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
235 .scbrr_algo_id = SCBRR_ALGO_2,
236 .type = PORT_SCIF, 246 .type = PORT_SCIF,
237 .irqs = SCIx_IRQ_MUXED(192), 247};
248
249static struct resource scif3_resources[] = {
250 DEFINE_RES_MEM(0xfffe9800, 0x100),
251 DEFINE_RES_IRQ(192),
238}; 252};
239 253
240static struct platform_device scif3_device = { 254static struct platform_device scif3_device = {
241 .name = "sh-sci", 255 .name = "sh-sci",
242 .id = 3, 256 .id = 3,
257 .resource = scif3_resources,
258 .num_resources = ARRAY_SIZE(scif3_resources),
243 .dev = { 259 .dev = {
244 .platform_data = &scif3_platform_data, 260 .platform_data = &scif3_platform_data,
245 }, 261 },
246}; 262};
247 263
248static struct plat_sci_port scif4_platform_data = { 264static struct plat_sci_port scif4_platform_data = {
249 .mapbase = 0xfffea000,
250 .flags = UPF_BOOT_AUTOCONF, 265 .flags = UPF_BOOT_AUTOCONF,
251 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 266 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
252 .scbrr_algo_id = SCBRR_ALGO_2,
253 .type = PORT_SCIF, 267 .type = PORT_SCIF,
254 .irqs = SCIx_IRQ_MUXED(196), 268};
269
270static struct resource scif4_resources[] = {
271 DEFINE_RES_MEM(0xfffea000, 0x100),
272 DEFINE_RES_IRQ(196),
255}; 273};
256 274
257static struct platform_device scif4_device = { 275static struct platform_device scif4_device = {
258 .name = "sh-sci", 276 .name = "sh-sci",
259 .id = 4, 277 .id = 4,
278 .resource = scif4_resources,
279 .num_resources = ARRAY_SIZE(scif4_resources),
260 .dev = { 280 .dev = {
261 .platform_data = &scif4_platform_data, 281 .platform_data = &scif4_platform_data,
262 }, 282 },
263}; 283};
264 284
265static struct plat_sci_port scif5_platform_data = { 285static struct plat_sci_port scif5_platform_data = {
266 .mapbase = 0xfffea800,
267 .flags = UPF_BOOT_AUTOCONF, 286 .flags = UPF_BOOT_AUTOCONF,
268 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 287 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
269 .scbrr_algo_id = SCBRR_ALGO_2,
270 .type = PORT_SCIF, 288 .type = PORT_SCIF,
271 .irqs = SCIx_IRQ_MUXED(200), 289};
290
291static struct resource scif5_resources[] = {
292 DEFINE_RES_MEM(0xfffea800, 0x100),
293 DEFINE_RES_IRQ(200),
272}; 294};
273 295
274static struct platform_device scif5_device = { 296static struct platform_device scif5_device = {
275 .name = "sh-sci", 297 .name = "sh-sci",
276 .id = 5, 298 .id = 5,
299 .resource = scif5_resources,
300 .num_resources = ARRAY_SIZE(scif5_resources),
277 .dev = { 301 .dev = {
278 .platform_data = &scif5_platform_data, 302 .platform_data = &scif5_platform_data,
279 }, 303 },
280}; 304};
281 305
282static struct plat_sci_port scif6_platform_data = { 306static struct plat_sci_port scif6_platform_data = {
283 .mapbase = 0xfffeb000,
284 .flags = UPF_BOOT_AUTOCONF, 307 .flags = UPF_BOOT_AUTOCONF,
285 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 308 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
286 .scbrr_algo_id = SCBRR_ALGO_2,
287 .type = PORT_SCIF, 309 .type = PORT_SCIF,
288 .irqs = SCIx_IRQ_MUXED(204), 310};
311
312static struct resource scif6_resources[] = {
313 DEFINE_RES_MEM(0xfffeb000, 0x100),
314 DEFINE_RES_IRQ(204),
289}; 315};
290 316
291static struct platform_device scif6_device = { 317static struct platform_device scif6_device = {
292 .name = "sh-sci", 318 .name = "sh-sci",
293 .id = 6, 319 .id = 6,
320 .resource = scif6_resources,
321 .num_resources = ARRAY_SIZE(scif6_resources),
294 .dev = { 322 .dev = {
295 .platform_data = &scif6_platform_data, 323 .platform_data = &scif6_platform_data,
296 }, 324 },
297}; 325};
298 326
299static struct plat_sci_port scif7_platform_data = { 327static struct plat_sci_port scif7_platform_data = {
300 .mapbase = 0xfffeb800,
301 .flags = UPF_BOOT_AUTOCONF, 328 .flags = UPF_BOOT_AUTOCONF,
302 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 329 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
303 .scbrr_algo_id = SCBRR_ALGO_2,
304 .type = PORT_SCIF, 330 .type = PORT_SCIF,
305 .irqs = SCIx_IRQ_MUXED(208), 331};
332
333static struct resource scif7_resources[] = {
334 DEFINE_RES_MEM(0xfffeb800, 0x100),
335 DEFINE_RES_IRQ(208),
306}; 336};
307 337
308static struct platform_device scif7_device = { 338static struct platform_device scif7_device = {
309 .name = "sh-sci", 339 .name = "sh-sci",
310 .id = 7, 340 .id = 7,
341 .resource = scif7_resources,
342 .num_resources = ARRAY_SIZE(scif7_resources),
311 .dev = { 343 .dev = {
312 .platform_data = &scif7_platform_data, 344 .platform_data = &scif7_platform_data,
313 }, 345 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index bfc33f6a28c3..d55a0f30ada3 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -174,76 +174,92 @@ static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
174 mask_registers, prio_registers, NULL); 174 mask_registers, prio_registers, NULL);
175 175
176static struct plat_sci_port scif0_platform_data = { 176static struct plat_sci_port scif0_platform_data = {
177 .mapbase = 0xfffe8000,
178 .flags = UPF_BOOT_AUTOCONF, 177 .flags = UPF_BOOT_AUTOCONF,
179 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 178 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
180 SCSCR_REIE, 179 SCSCR_REIE,
181 .scbrr_algo_id = SCBRR_ALGO_2,
182 .type = PORT_SCIF, 180 .type = PORT_SCIF,
183 .irqs = SCIx_IRQ_MUXED(192),
184 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 181 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
185}; 182};
186 183
184static struct resource scif0_resources[] = {
185 DEFINE_RES_MEM(0xfffe8000, 0x100),
186 DEFINE_RES_IRQ(192),
187};
188
187static struct platform_device scif0_device = { 189static struct platform_device scif0_device = {
188 .name = "sh-sci", 190 .name = "sh-sci",
189 .id = 0, 191 .id = 0,
192 .resource = scif0_resources,
193 .num_resources = ARRAY_SIZE(scif0_resources),
190 .dev = { 194 .dev = {
191 .platform_data = &scif0_platform_data, 195 .platform_data = &scif0_platform_data,
192 }, 196 },
193}; 197};
194 198
195static struct plat_sci_port scif1_platform_data = { 199static struct plat_sci_port scif1_platform_data = {
196 .mapbase = 0xfffe8800,
197 .flags = UPF_BOOT_AUTOCONF, 200 .flags = UPF_BOOT_AUTOCONF,
198 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 201 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
199 SCSCR_REIE, 202 SCSCR_REIE,
200 .scbrr_algo_id = SCBRR_ALGO_2,
201 .type = PORT_SCIF, 203 .type = PORT_SCIF,
202 .irqs = SCIx_IRQ_MUXED(196),
203 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 204 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
204}; 205};
205 206
207static struct resource scif1_resources[] = {
208 DEFINE_RES_MEM(0xfffe8800, 0x100),
209 DEFINE_RES_IRQ(196),
210};
211
206static struct platform_device scif1_device = { 212static struct platform_device scif1_device = {
207 .name = "sh-sci", 213 .name = "sh-sci",
208 .id = 1, 214 .id = 1,
215 .resource = scif1_resources,
216 .num_resources = ARRAY_SIZE(scif1_resources),
209 .dev = { 217 .dev = {
210 .platform_data = &scif1_platform_data, 218 .platform_data = &scif1_platform_data,
211 }, 219 },
212}; 220};
213 221
214static struct plat_sci_port scif2_platform_data = { 222static struct plat_sci_port scif2_platform_data = {
215 .mapbase = 0xfffe9000,
216 .flags = UPF_BOOT_AUTOCONF, 223 .flags = UPF_BOOT_AUTOCONF,
217 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 224 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
218 SCSCR_REIE, 225 SCSCR_REIE,
219 .scbrr_algo_id = SCBRR_ALGO_2,
220 .type = PORT_SCIF, 226 .type = PORT_SCIF,
221 .irqs = SCIx_IRQ_MUXED(200),
222 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 227 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
223}; 228};
224 229
230static struct resource scif2_resources[] = {
231 DEFINE_RES_MEM(0xfffe9000, 0x100),
232 DEFINE_RES_IRQ(200),
233};
234
225static struct platform_device scif2_device = { 235static struct platform_device scif2_device = {
226 .name = "sh-sci", 236 .name = "sh-sci",
227 .id = 2, 237 .id = 2,
238 .resource = scif2_resources,
239 .num_resources = ARRAY_SIZE(scif2_resources),
228 .dev = { 240 .dev = {
229 .platform_data = &scif2_platform_data, 241 .platform_data = &scif2_platform_data,
230 }, 242 },
231}; 243};
232 244
233static struct plat_sci_port scif3_platform_data = { 245static struct plat_sci_port scif3_platform_data = {
234 .mapbase = 0xfffe9800,
235 .flags = UPF_BOOT_AUTOCONF, 246 .flags = UPF_BOOT_AUTOCONF,
236 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 247 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
237 SCSCR_REIE, 248 SCSCR_REIE,
238 .scbrr_algo_id = SCBRR_ALGO_2,
239 .type = PORT_SCIF, 249 .type = PORT_SCIF,
240 .irqs = SCIx_IRQ_MUXED(204),
241 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 250 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
242}; 251};
243 252
253static struct resource scif3_resources[] = {
254 DEFINE_RES_MEM(0xfffe9800, 0x100),
255 DEFINE_RES_IRQ(204),
256};
257
244static struct platform_device scif3_device = { 258static struct platform_device scif3_device = {
245 .name = "sh-sci", 259 .name = "sh-sci",
246 .id = 3, 260 .id = 3,
261 .resource = scif3_resources,
262 .num_resources = ARRAY_SIZE(scif3_resources),
247 .dev = { 263 .dev = {
248 .platform_data = &scif3_platform_data, 264 .platform_data = &scif3_platform_data,
249 }, 265 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index a5010741de85..241e745e3ced 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -134,68 +134,84 @@ static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
134 mask_registers, prio_registers, NULL); 134 mask_registers, prio_registers, NULL);
135 135
136static struct plat_sci_port scif0_platform_data = { 136static struct plat_sci_port scif0_platform_data = {
137 .mapbase = 0xfffe8000,
138 .flags = UPF_BOOT_AUTOCONF, 137 .flags = UPF_BOOT_AUTOCONF,
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 138 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
140 .scbrr_algo_id = SCBRR_ALGO_2,
141 .type = PORT_SCIF, 139 .type = PORT_SCIF,
142 .irqs = SCIx_IRQ_MUXED(240), 140};
141
142static struct resource scif0_resources[] = {
143 DEFINE_RES_MEM(0xfffe8000, 0x100),
144 DEFINE_RES_IRQ(240),
143}; 145};
144 146
145static struct platform_device scif0_device = { 147static struct platform_device scif0_device = {
146 .name = "sh-sci", 148 .name = "sh-sci",
147 .id = 0, 149 .id = 0,
150 .resource = scif0_resources,
151 .num_resources = ARRAY_SIZE(scif0_resources),
148 .dev = { 152 .dev = {
149 .platform_data = &scif0_platform_data, 153 .platform_data = &scif0_platform_data,
150 }, 154 },
151}; 155};
152 156
153static struct plat_sci_port scif1_platform_data = { 157static struct plat_sci_port scif1_platform_data = {
154 .mapbase = 0xfffe8800,
155 .flags = UPF_BOOT_AUTOCONF, 158 .flags = UPF_BOOT_AUTOCONF,
156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 159 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
157 .scbrr_algo_id = SCBRR_ALGO_2,
158 .type = PORT_SCIF, 160 .type = PORT_SCIF,
159 .irqs = SCIx_IRQ_MUXED(244), 161};
162
163static struct resource scif1_resources[] = {
164 DEFINE_RES_MEM(0xfffe8800, 0x100),
165 DEFINE_RES_IRQ(244),
160}; 166};
161 167
162static struct platform_device scif1_device = { 168static struct platform_device scif1_device = {
163 .name = "sh-sci", 169 .name = "sh-sci",
164 .id = 1, 170 .id = 1,
171 .resource = scif1_resources,
172 .num_resources = ARRAY_SIZE(scif1_resources),
165 .dev = { 173 .dev = {
166 .platform_data = &scif1_platform_data, 174 .platform_data = &scif1_platform_data,
167 }, 175 },
168}; 176};
169 177
170static struct plat_sci_port scif2_platform_data = { 178static struct plat_sci_port scif2_platform_data = {
171 .mapbase = 0xfffe9000,
172 .flags = UPF_BOOT_AUTOCONF, 179 .flags = UPF_BOOT_AUTOCONF,
173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 180 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
174 .scbrr_algo_id = SCBRR_ALGO_2,
175 .type = PORT_SCIF, 181 .type = PORT_SCIF,
176 .irqs = SCIx_IRQ_MUXED(248), 182};
183
184static struct resource scif2_resources[] = {
185 DEFINE_RES_MEM(0xfffe9000, 0x100),
186 DEFINE_RES_IRQ(248),
177}; 187};
178 188
179static struct platform_device scif2_device = { 189static struct platform_device scif2_device = {
180 .name = "sh-sci", 190 .name = "sh-sci",
181 .id = 2, 191 .id = 2,
192 .resource = scif2_resources,
193 .num_resources = ARRAY_SIZE(scif2_resources),
182 .dev = { 194 .dev = {
183 .platform_data = &scif2_platform_data, 195 .platform_data = &scif2_platform_data,
184 }, 196 },
185}; 197};
186 198
187static struct plat_sci_port scif3_platform_data = { 199static struct plat_sci_port scif3_platform_data = {
188 .mapbase = 0xfffe9800,
189 .flags = UPF_BOOT_AUTOCONF, 200 .flags = UPF_BOOT_AUTOCONF,
190 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 201 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
191 .scbrr_algo_id = SCBRR_ALGO_2,
192 .type = PORT_SCIF, 202 .type = PORT_SCIF,
193 .irqs = SCIx_IRQ_MUXED(252), 203};
204
205static struct resource scif3_resources[] = {
206 DEFINE_RES_MEM(0xfffe9800, 0x100),
207 DEFINE_RES_IRQ(252),
194}; 208};
195 209
196static struct platform_device scif3_device = { 210static struct platform_device scif3_device = {
197 .name = "sh-sci", 211 .name = "sh-sci",
198 .id = 3, 212 .id = 3,
213 .resource = scif3_resources,
214 .num_resources = ARRAY_SIZE(scif3_resources),
199 .dev = { 215 .dev = {
200 .platform_data = &scif3_platform_data, 216 .platform_data = &scif3_platform_data,
201 }, 217 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
index ce5c1b5aebfa..ad5b0f429882 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
@@ -226,152 +226,208 @@ static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups,
226 mask_registers, prio_registers, NULL); 226 mask_registers, prio_registers, NULL);
227 227
228static struct plat_sci_port scif0_platform_data = { 228static struct plat_sci_port scif0_platform_data = {
229 .mapbase = 0xfffe8000,
230 .flags = UPF_BOOT_AUTOCONF, 229 .flags = UPF_BOOT_AUTOCONF,
231 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 230 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
232 SCSCR_REIE | SCSCR_TOIE, 231 SCSCR_REIE | SCSCR_TOIE,
233 .scbrr_algo_id = SCBRR_ALGO_2,
234 .type = PORT_SCIF, 232 .type = PORT_SCIF,
235 .irqs = { 233, 234, 235, 232 },
236 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 233 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
237}; 234};
238 235
236static struct resource scif0_resources[] = {
237 DEFINE_RES_MEM(0xfffe8000, 0x100),
238 DEFINE_RES_IRQ(233),
239 DEFINE_RES_IRQ(234),
240 DEFINE_RES_IRQ(235),
241 DEFINE_RES_IRQ(232),
242};
243
239static struct platform_device scif0_device = { 244static struct platform_device scif0_device = {
240 .name = "sh-sci", 245 .name = "sh-sci",
241 .id = 0, 246 .id = 0,
247 .resource = scif0_resources,
248 .num_resources = ARRAY_SIZE(scif0_resources),
242 .dev = { 249 .dev = {
243 .platform_data = &scif0_platform_data, 250 .platform_data = &scif0_platform_data,
244 }, 251 },
245}; 252};
246 253
247static struct plat_sci_port scif1_platform_data = { 254static struct plat_sci_port scif1_platform_data = {
248 .mapbase = 0xfffe8800,
249 .flags = UPF_BOOT_AUTOCONF, 255 .flags = UPF_BOOT_AUTOCONF,
250 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 256 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
251 SCSCR_REIE | SCSCR_TOIE, 257 SCSCR_REIE | SCSCR_TOIE,
252 .scbrr_algo_id = SCBRR_ALGO_2,
253 .type = PORT_SCIF, 258 .type = PORT_SCIF,
254 .irqs = { 237, 238, 239, 236 },
255 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 259 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
256}; 260};
257 261
262static struct resource scif1_resources[] = {
263 DEFINE_RES_MEM(0xfffe8800, 0x100),
264 DEFINE_RES_IRQ(237),
265 DEFINE_RES_IRQ(238),
266 DEFINE_RES_IRQ(239),
267 DEFINE_RES_IRQ(236),
268};
269
258static struct platform_device scif1_device = { 270static struct platform_device scif1_device = {
259 .name = "sh-sci", 271 .name = "sh-sci",
260 .id = 1, 272 .id = 1,
273 .resource = scif1_resources,
274 .num_resources = ARRAY_SIZE(scif1_resources),
261 .dev = { 275 .dev = {
262 .platform_data = &scif1_platform_data, 276 .platform_data = &scif1_platform_data,
263 }, 277 },
264}; 278};
265 279
266static struct plat_sci_port scif2_platform_data = { 280static struct plat_sci_port scif2_platform_data = {
267 .mapbase = 0xfffe9000,
268 .flags = UPF_BOOT_AUTOCONF, 281 .flags = UPF_BOOT_AUTOCONF,
269 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 282 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
270 SCSCR_REIE | SCSCR_TOIE, 283 SCSCR_REIE | SCSCR_TOIE,
271 .scbrr_algo_id = SCBRR_ALGO_2,
272 .type = PORT_SCIF, 284 .type = PORT_SCIF,
273 .irqs = { 241, 242, 243, 240 },
274 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 285 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
275}; 286};
276 287
288static struct resource scif2_resources[] = {
289 DEFINE_RES_MEM(0xfffe9000, 0x100),
290 DEFINE_RES_IRQ(241),
291 DEFINE_RES_IRQ(242),
292 DEFINE_RES_IRQ(243),
293 DEFINE_RES_IRQ(240),
294};
295
277static struct platform_device scif2_device = { 296static struct platform_device scif2_device = {
278 .name = "sh-sci", 297 .name = "sh-sci",
279 .id = 2, 298 .id = 2,
299 .resource = scif2_resources,
300 .num_resources = ARRAY_SIZE(scif2_resources),
280 .dev = { 301 .dev = {
281 .platform_data = &scif2_platform_data, 302 .platform_data = &scif2_platform_data,
282 }, 303 },
283}; 304};
284 305
285static struct plat_sci_port scif3_platform_data = { 306static struct plat_sci_port scif3_platform_data = {
286 .mapbase = 0xfffe9800,
287 .flags = UPF_BOOT_AUTOCONF, 307 .flags = UPF_BOOT_AUTOCONF,
288 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 308 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
289 SCSCR_REIE | SCSCR_TOIE, 309 SCSCR_REIE | SCSCR_TOIE,
290 .scbrr_algo_id = SCBRR_ALGO_2,
291 .type = PORT_SCIF, 310 .type = PORT_SCIF,
292 .irqs = { 245, 246, 247, 244 },
293 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 311 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
294}; 312};
295 313
314static struct resource scif3_resources[] = {
315 DEFINE_RES_MEM(0xfffe9800, 0x100),
316 DEFINE_RES_IRQ(245),
317 DEFINE_RES_IRQ(246),
318 DEFINE_RES_IRQ(247),
319 DEFINE_RES_IRQ(244),
320};
321
296static struct platform_device scif3_device = { 322static struct platform_device scif3_device = {
297 .name = "sh-sci", 323 .name = "sh-sci",
298 .id = 3, 324 .id = 3,
325 .resource = scif3_resources,
326 .num_resources = ARRAY_SIZE(scif3_resources),
299 .dev = { 327 .dev = {
300 .platform_data = &scif3_platform_data, 328 .platform_data = &scif3_platform_data,
301 }, 329 },
302}; 330};
303 331
304static struct plat_sci_port scif4_platform_data = { 332static struct plat_sci_port scif4_platform_data = {
305 .mapbase = 0xfffea000,
306 .flags = UPF_BOOT_AUTOCONF, 333 .flags = UPF_BOOT_AUTOCONF,
307 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 334 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
308 SCSCR_REIE | SCSCR_TOIE, 335 SCSCR_REIE | SCSCR_TOIE,
309 .scbrr_algo_id = SCBRR_ALGO_2,
310 .type = PORT_SCIF, 336 .type = PORT_SCIF,
311 .irqs = { 249, 250, 251, 248 },
312 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 337 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
313}; 338};
314 339
340static struct resource scif4_resources[] = {
341 DEFINE_RES_MEM(0xfffea000, 0x100),
342 DEFINE_RES_IRQ(249),
343 DEFINE_RES_IRQ(250),
344 DEFINE_RES_IRQ(251),
345 DEFINE_RES_IRQ(248),
346};
347
315static struct platform_device scif4_device = { 348static struct platform_device scif4_device = {
316 .name = "sh-sci", 349 .name = "sh-sci",
317 .id = 4, 350 .id = 4,
351 .resource = scif4_resources,
352 .num_resources = ARRAY_SIZE(scif4_resources),
318 .dev = { 353 .dev = {
319 .platform_data = &scif4_platform_data, 354 .platform_data = &scif4_platform_data,
320 }, 355 },
321}; 356};
322 357
323static struct plat_sci_port scif5_platform_data = { 358static struct plat_sci_port scif5_platform_data = {
324 .mapbase = 0xfffea800,
325 .flags = UPF_BOOT_AUTOCONF, 359 .flags = UPF_BOOT_AUTOCONF,
326 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 360 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
327 SCSCR_REIE | SCSCR_TOIE, 361 SCSCR_REIE | SCSCR_TOIE,
328 .scbrr_algo_id = SCBRR_ALGO_2,
329 .type = PORT_SCIF, 362 .type = PORT_SCIF,
330 .irqs = { 253, 254, 255, 252 },
331 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 363 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
332}; 364};
333 365
366static struct resource scif5_resources[] = {
367 DEFINE_RES_MEM(0xfffea800, 0x100),
368 DEFINE_RES_IRQ(253),
369 DEFINE_RES_IRQ(254),
370 DEFINE_RES_IRQ(255),
371 DEFINE_RES_IRQ(252),
372};
373
334static struct platform_device scif5_device = { 374static struct platform_device scif5_device = {
335 .name = "sh-sci", 375 .name = "sh-sci",
336 .id = 5, 376 .id = 5,
377 .resource = scif5_resources,
378 .num_resources = ARRAY_SIZE(scif5_resources),
337 .dev = { 379 .dev = {
338 .platform_data = &scif5_platform_data, 380 .platform_data = &scif5_platform_data,
339 }, 381 },
340}; 382};
341 383
342static struct plat_sci_port scif6_platform_data = { 384static struct plat_sci_port scif6_platform_data = {
343 .mapbase = 0xfffeb000,
344 .flags = UPF_BOOT_AUTOCONF, 385 .flags = UPF_BOOT_AUTOCONF,
345 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 386 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
346 SCSCR_REIE | SCSCR_TOIE, 387 SCSCR_REIE | SCSCR_TOIE,
347 .scbrr_algo_id = SCBRR_ALGO_2,
348 .type = PORT_SCIF, 388 .type = PORT_SCIF,
349 .irqs = { 257, 258, 259, 256 },
350 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 389 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
351}; 390};
352 391
392static struct resource scif6_resources[] = {
393 DEFINE_RES_MEM(0xfffeb000, 0x100),
394 DEFINE_RES_IRQ(257),
395 DEFINE_RES_IRQ(258),
396 DEFINE_RES_IRQ(259),
397 DEFINE_RES_IRQ(256),
398};
399
353static struct platform_device scif6_device = { 400static struct platform_device scif6_device = {
354 .name = "sh-sci", 401 .name = "sh-sci",
355 .id = 6, 402 .id = 6,
403 .resource = scif6_resources,
404 .num_resources = ARRAY_SIZE(scif6_resources),
356 .dev = { 405 .dev = {
357 .platform_data = &scif6_platform_data, 406 .platform_data = &scif6_platform_data,
358 }, 407 },
359}; 408};
360 409
361static struct plat_sci_port scif7_platform_data = { 410static struct plat_sci_port scif7_platform_data = {
362 .mapbase = 0xfffeb800,
363 .flags = UPF_BOOT_AUTOCONF, 411 .flags = UPF_BOOT_AUTOCONF,
364 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 412 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
365 SCSCR_REIE | SCSCR_TOIE, 413 SCSCR_REIE | SCSCR_TOIE,
366 .scbrr_algo_id = SCBRR_ALGO_2,
367 .type = PORT_SCIF, 414 .type = PORT_SCIF,
368 .irqs = { 261, 262, 263, 260 },
369 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 415 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
370}; 416};
371 417
418static struct resource scif7_resources[] = {
419 DEFINE_RES_MEM(0xfffeb800, 0x100),
420 DEFINE_RES_IRQ(261),
421 DEFINE_RES_IRQ(262),
422 DEFINE_RES_IRQ(263),
423 DEFINE_RES_IRQ(260),
424};
425
372static struct platform_device scif7_device = { 426static struct platform_device scif7_device = {
373 .name = "sh-sci", 427 .name = "sh-sci",
374 .id = 7, 428 .id = 7,
429 .resource = scif7_resources,
430 .num_resources = ARRAY_SIZE(scif7_resources),
375 .dev = { 431 .dev = {
376 .platform_data = &scif7_platform_data, 432 .platform_data = &scif7_platform_data,
377 }, 433 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c
index e82ae9d8d3bc..3995119f65dc 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c
@@ -248,152 +248,208 @@ static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups,
248 mask_registers, prio_registers, NULL); 248 mask_registers, prio_registers, NULL);
249 249
250static struct plat_sci_port scif0_platform_data = { 250static struct plat_sci_port scif0_platform_data = {
251 .mapbase = 0xe8007000,
252 .flags = UPF_BOOT_AUTOCONF, 251 .flags = UPF_BOOT_AUTOCONF,
253 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 252 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
254 SCSCR_REIE | SCSCR_TOIE, 253 SCSCR_REIE | SCSCR_TOIE,
255 .scbrr_algo_id = SCBRR_ALGO_2,
256 .type = PORT_SCIF, 254 .type = PORT_SCIF,
257 .irqs = { 259, 260, 261, 258 },
258 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 255 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
259}; 256};
260 257
258static struct resource scif0_resources[] = {
259 DEFINE_RES_MEM(0xe8007000, 0x100),
260 DEFINE_RES_IRQ(259),
261 DEFINE_RES_IRQ(260),
262 DEFINE_RES_IRQ(261),
263 DEFINE_RES_IRQ(258),
264};
265
261static struct platform_device scif0_device = { 266static struct platform_device scif0_device = {
262 .name = "sh-sci", 267 .name = "sh-sci",
263 .id = 0, 268 .id = 0,
269 .resource = scif0_resources,
270 .num_resources = ARRAY_SIZE(scif0_resources),
264 .dev = { 271 .dev = {
265 .platform_data = &scif0_platform_data, 272 .platform_data = &scif0_platform_data,
266 }, 273 },
267}; 274};
268 275
269static struct plat_sci_port scif1_platform_data = { 276static struct plat_sci_port scif1_platform_data = {
270 .mapbase = 0xe8007800,
271 .flags = UPF_BOOT_AUTOCONF, 277 .flags = UPF_BOOT_AUTOCONF,
272 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 278 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
273 SCSCR_REIE | SCSCR_TOIE, 279 SCSCR_REIE | SCSCR_TOIE,
274 .scbrr_algo_id = SCBRR_ALGO_2,
275 .type = PORT_SCIF, 280 .type = PORT_SCIF,
276 .irqs = { 263, 264, 265, 262 },
277 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 281 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
278}; 282};
279 283
284static struct resource scif1_resources[] = {
285 DEFINE_RES_MEM(0xe8007800, 0x100),
286 DEFINE_RES_IRQ(263),
287 DEFINE_RES_IRQ(264),
288 DEFINE_RES_IRQ(265),
289 DEFINE_RES_IRQ(262),
290};
291
280static struct platform_device scif1_device = { 292static struct platform_device scif1_device = {
281 .name = "sh-sci", 293 .name = "sh-sci",
282 .id = 1, 294 .id = 1,
295 .resource = scif1_resources,
296 .num_resources = ARRAY_SIZE(scif1_resources),
283 .dev = { 297 .dev = {
284 .platform_data = &scif1_platform_data, 298 .platform_data = &scif1_platform_data,
285 }, 299 },
286}; 300};
287 301
288static struct plat_sci_port scif2_platform_data = { 302static struct plat_sci_port scif2_platform_data = {
289 .mapbase = 0xe8008000,
290 .flags = UPF_BOOT_AUTOCONF, 303 .flags = UPF_BOOT_AUTOCONF,
291 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 304 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
292 SCSCR_REIE | SCSCR_TOIE, 305 SCSCR_REIE | SCSCR_TOIE,
293 .scbrr_algo_id = SCBRR_ALGO_2,
294 .type = PORT_SCIF, 306 .type = PORT_SCIF,
295 .irqs = { 267, 268, 269, 266 },
296 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 307 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
297}; 308};
298 309
310static struct resource scif2_resources[] = {
311 DEFINE_RES_MEM(0xe8008000, 0x100),
312 DEFINE_RES_IRQ(267),
313 DEFINE_RES_IRQ(268),
314 DEFINE_RES_IRQ(269),
315 DEFINE_RES_IRQ(266),
316};
317
299static struct platform_device scif2_device = { 318static struct platform_device scif2_device = {
300 .name = "sh-sci", 319 .name = "sh-sci",
301 .id = 2, 320 .id = 2,
321 .resource = scif2_resources,
322 .num_resources = ARRAY_SIZE(scif2_resources),
302 .dev = { 323 .dev = {
303 .platform_data = &scif2_platform_data, 324 .platform_data = &scif2_platform_data,
304 }, 325 },
305}; 326};
306 327
307static struct plat_sci_port scif3_platform_data = { 328static struct plat_sci_port scif3_platform_data = {
308 .mapbase = 0xe8008800,
309 .flags = UPF_BOOT_AUTOCONF, 329 .flags = UPF_BOOT_AUTOCONF,
310 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 330 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
311 SCSCR_REIE | SCSCR_TOIE, 331 SCSCR_REIE | SCSCR_TOIE,
312 .scbrr_algo_id = SCBRR_ALGO_2,
313 .type = PORT_SCIF, 332 .type = PORT_SCIF,
314 .irqs = { 271, 272, 273, 270 },
315 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 333 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
316}; 334};
317 335
336static struct resource scif3_resources[] = {
337 DEFINE_RES_MEM(0xe8008800, 0x100),
338 DEFINE_RES_IRQ(271),
339 DEFINE_RES_IRQ(272),
340 DEFINE_RES_IRQ(273),
341 DEFINE_RES_IRQ(270),
342};
343
318static struct platform_device scif3_device = { 344static struct platform_device scif3_device = {
319 .name = "sh-sci", 345 .name = "sh-sci",
320 .id = 3, 346 .id = 3,
347 .resource = scif3_resources,
348 .num_resources = ARRAY_SIZE(scif3_resources),
321 .dev = { 349 .dev = {
322 .platform_data = &scif3_platform_data, 350 .platform_data = &scif3_platform_data,
323 }, 351 },
324}; 352};
325 353
326static struct plat_sci_port scif4_platform_data = { 354static struct plat_sci_port scif4_platform_data = {
327 .mapbase = 0xe8009000,
328 .flags = UPF_BOOT_AUTOCONF, 355 .flags = UPF_BOOT_AUTOCONF,
329 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 356 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
330 SCSCR_REIE | SCSCR_TOIE, 357 SCSCR_REIE | SCSCR_TOIE,
331 .scbrr_algo_id = SCBRR_ALGO_2,
332 .type = PORT_SCIF, 358 .type = PORT_SCIF,
333 .irqs = { 275, 276, 277, 274 },
334 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 359 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
335}; 360};
336 361
362static struct resource scif4_resources[] = {
363 DEFINE_RES_MEM(0xe8009000, 0x100),
364 DEFINE_RES_IRQ(275),
365 DEFINE_RES_IRQ(276),
366 DEFINE_RES_IRQ(277),
367 DEFINE_RES_IRQ(274),
368};
369
337static struct platform_device scif4_device = { 370static struct platform_device scif4_device = {
338 .name = "sh-sci", 371 .name = "sh-sci",
339 .id = 4, 372 .id = 4,
373 .resource = scif4_resources,
374 .num_resources = ARRAY_SIZE(scif4_resources),
340 .dev = { 375 .dev = {
341 .platform_data = &scif4_platform_data, 376 .platform_data = &scif4_platform_data,
342 }, 377 },
343}; 378};
344 379
345static struct plat_sci_port scif5_platform_data = { 380static struct plat_sci_port scif5_platform_data = {
346 .mapbase = 0xe8009800,
347 .flags = UPF_BOOT_AUTOCONF, 381 .flags = UPF_BOOT_AUTOCONF,
348 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 382 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
349 SCSCR_REIE | SCSCR_TOIE, 383 SCSCR_REIE | SCSCR_TOIE,
350 .scbrr_algo_id = SCBRR_ALGO_2,
351 .type = PORT_SCIF, 384 .type = PORT_SCIF,
352 .irqs = { 279, 280, 281, 278 },
353 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 385 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
354}; 386};
355 387
388static struct resource scif5_resources[] = {
389 DEFINE_RES_MEM(0xe8009800, 0x100),
390 DEFINE_RES_IRQ(279),
391 DEFINE_RES_IRQ(280),
392 DEFINE_RES_IRQ(281),
393 DEFINE_RES_IRQ(278),
394};
395
356static struct platform_device scif5_device = { 396static struct platform_device scif5_device = {
357 .name = "sh-sci", 397 .name = "sh-sci",
358 .id = 5, 398 .id = 5,
399 .resource = scif5_resources,
400 .num_resources = ARRAY_SIZE(scif5_resources),
359 .dev = { 401 .dev = {
360 .platform_data = &scif5_platform_data, 402 .platform_data = &scif5_platform_data,
361 }, 403 },
362}; 404};
363 405
364static struct plat_sci_port scif6_platform_data = { 406static struct plat_sci_port scif6_platform_data = {
365 .mapbase = 0xe800a000,
366 .flags = UPF_BOOT_AUTOCONF, 407 .flags = UPF_BOOT_AUTOCONF,
367 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 408 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
368 SCSCR_REIE | SCSCR_TOIE, 409 SCSCR_REIE | SCSCR_TOIE,
369 .scbrr_algo_id = SCBRR_ALGO_2,
370 .type = PORT_SCIF, 410 .type = PORT_SCIF,
371 .irqs = { 283, 284, 285, 282 },
372 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 411 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
373}; 412};
374 413
414static struct resource scif6_resources[] = {
415 DEFINE_RES_MEM(0xe800a000, 0x100),
416 DEFINE_RES_IRQ(283),
417 DEFINE_RES_IRQ(284),
418 DEFINE_RES_IRQ(285),
419 DEFINE_RES_IRQ(282),
420};
421
375static struct platform_device scif6_device = { 422static struct platform_device scif6_device = {
376 .name = "sh-sci", 423 .name = "sh-sci",
377 .id = 6, 424 .id = 6,
425 .resource = scif6_resources,
426 .num_resources = ARRAY_SIZE(scif6_resources),
378 .dev = { 427 .dev = {
379 .platform_data = &scif6_platform_data, 428 .platform_data = &scif6_platform_data,
380 }, 429 },
381}; 430};
382 431
383static struct plat_sci_port scif7_platform_data = { 432static struct plat_sci_port scif7_platform_data = {
384 .mapbase = 0xe800a800,
385 .flags = UPF_BOOT_AUTOCONF, 433 .flags = UPF_BOOT_AUTOCONF,
386 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 434 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
387 SCSCR_REIE | SCSCR_TOIE, 435 SCSCR_REIE | SCSCR_TOIE,
388 .scbrr_algo_id = SCBRR_ALGO_2,
389 .type = PORT_SCIF, 436 .type = PORT_SCIF,
390 .irqs = { 287, 288, 289, 286 },
391 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 437 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
392}; 438};
393 439
440static struct resource scif7_resources[] = {
441 DEFINE_RES_MEM(0xe800a800, 0x100),
442 DEFINE_RES_IRQ(287),
443 DEFINE_RES_IRQ(288),
444 DEFINE_RES_IRQ(289),
445 DEFINE_RES_IRQ(286),
446};
447
394static struct platform_device scif7_device = { 448static struct platform_device scif7_device = {
395 .name = "sh-sci", 449 .name = "sh-sci",
396 .id = 7, 450 .id = 7,
451 .resource = scif7_resources,
452 .num_resources = ARRAY_SIZE(scif7_resources),
397 .dev = { 453 .dev = {
398 .platform_data = &scif7_platform_data, 454 .platform_data = &scif7_platform_data,
399 }, 455 },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 03e4c96f2b11..c76b2543b85f 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -70,39 +70,47 @@ static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
70 NULL, prio_registers, NULL); 70 NULL, prio_registers, NULL);
71 71
72static struct plat_sci_port scif0_platform_data = { 72static struct plat_sci_port scif0_platform_data = {
73 .mapbase = 0xa4410000,
74 .flags = UPF_BOOT_AUTOCONF, 73 .flags = UPF_BOOT_AUTOCONF,
75 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | 74 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE |
76 SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, 75 SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,
77 .scbrr_algo_id = SCBRR_ALGO_4,
78 .type = PORT_SCIF, 76 .type = PORT_SCIF,
79 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
80 .ops = &sh770x_sci_port_ops, 77 .ops = &sh770x_sci_port_ops,
81 .regtype = SCIx_SH7705_SCIF_REGTYPE, 78 .regtype = SCIx_SH7705_SCIF_REGTYPE,
82}; 79};
83 80
81static struct resource scif0_resources[] = {
82 DEFINE_RES_MEM(0xa4410000, 0x100),
83 DEFINE_RES_IRQ(evt2irq(0x900)),
84};
85
84static struct platform_device scif0_device = { 86static struct platform_device scif0_device = {
85 .name = "sh-sci", 87 .name = "sh-sci",
86 .id = 0, 88 .id = 0,
89 .resource = scif0_resources,
90 .num_resources = ARRAY_SIZE(scif0_resources),
87 .dev = { 91 .dev = {
88 .platform_data = &scif0_platform_data, 92 .platform_data = &scif0_platform_data,
89 }, 93 },
90}; 94};
91 95
92static struct plat_sci_port scif1_platform_data = { 96static struct plat_sci_port scif1_platform_data = {
93 .mapbase = 0xa4400000,
94 .flags = UPF_BOOT_AUTOCONF, 97 .flags = UPF_BOOT_AUTOCONF,
95 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, 98 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
96 .scbrr_algo_id = SCBRR_ALGO_4,
97 .type = PORT_SCIF, 99 .type = PORT_SCIF,
98 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
99 .ops = &sh770x_sci_port_ops, 100 .ops = &sh770x_sci_port_ops,
100 .regtype = SCIx_SH7705_SCIF_REGTYPE, 101 .regtype = SCIx_SH7705_SCIF_REGTYPE,
101}; 102};
102 103
104static struct resource scif1_resources[] = {
105 DEFINE_RES_MEM(0xa4400000, 0x100),
106 DEFINE_RES_IRQ(evt2irq(0x880)),
107};
108
103static struct platform_device scif1_device = { 109static struct platform_device scif1_device = {
104 .name = "sh-sci", 110 .name = "sh-sci",
105 .id = 1, 111 .id = 1,
112 .resource = scif1_resources,
113 .num_resources = ARRAY_SIZE(scif1_resources),
106 .dev = { 114 .dev = {
107 .platform_data = &scif1_platform_data, 115 .platform_data = &scif1_platform_data,
108 }, 116 },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index ba26cd9ce69b..ff1465c0519c 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -109,20 +109,24 @@ static struct platform_device rtc_device = {
109}; 109};
110 110
111static struct plat_sci_port scif0_platform_data = { 111static struct plat_sci_port scif0_platform_data = {
112 .mapbase = 0xfffffe80,
113 .port_reg = 0xa4000136, 112 .port_reg = 0xa4000136,
114 .flags = UPF_BOOT_AUTOCONF, 113 .flags = UPF_BOOT_AUTOCONF,
115 .scscr = SCSCR_TE | SCSCR_RE, 114 .scscr = SCSCR_TE | SCSCR_RE,
116 .scbrr_algo_id = SCBRR_ALGO_2,
117 .type = PORT_SCI, 115 .type = PORT_SCI,
118 .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)),
119 .ops = &sh770x_sci_port_ops, 116 .ops = &sh770x_sci_port_ops,
120 .regshift = 1, 117 .regshift = 1,
121}; 118};
122 119
120static struct resource scif0_resources[] = {
121 DEFINE_RES_MEM(0xfffffe80, 0x100),
122 DEFINE_RES_IRQ(evt2irq(0x4e0)),
123};
124
123static struct platform_device scif0_device = { 125static struct platform_device scif0_device = {
124 .name = "sh-sci", 126 .name = "sh-sci",
125 .id = 0, 127 .id = 0,
128 .resource = scif0_resources,
129 .num_resources = ARRAY_SIZE(scif0_resources),
126 .dev = { 130 .dev = {
127 .platform_data = &scif0_platform_data, 131 .platform_data = &scif0_platform_data,
128 }, 132 },
@@ -131,19 +135,23 @@ static struct platform_device scif0_device = {
131 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 135 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
132 defined(CONFIG_CPU_SUBTYPE_SH7709) 136 defined(CONFIG_CPU_SUBTYPE_SH7709)
133static struct plat_sci_port scif1_platform_data = { 137static struct plat_sci_port scif1_platform_data = {
134 .mapbase = 0xa4000150,
135 .flags = UPF_BOOT_AUTOCONF, 138 .flags = UPF_BOOT_AUTOCONF,
136 .scscr = SCSCR_TE | SCSCR_RE, 139 .scscr = SCSCR_TE | SCSCR_RE,
137 .scbrr_algo_id = SCBRR_ALGO_2,
138 .type = PORT_SCIF, 140 .type = PORT_SCIF,
139 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
140 .ops = &sh770x_sci_port_ops, 141 .ops = &sh770x_sci_port_ops,
141 .regtype = SCIx_SH3_SCIF_REGTYPE, 142 .regtype = SCIx_SH3_SCIF_REGTYPE,
142}; 143};
143 144
145static struct resource scif1_resources[] = {
146 DEFINE_RES_MEM(0xa4000150, 0x100),
147 DEFINE_RES_IRQ(evt2irq(0x900)),
148};
149
144static struct platform_device scif1_device = { 150static struct platform_device scif1_device = {
145 .name = "sh-sci", 151 .name = "sh-sci",
146 .id = 1, 152 .id = 1,
153 .resource = scif1_resources,
154 .num_resources = ARRAY_SIZE(scif1_resources),
147 .dev = { 155 .dev = {
148 .platform_data = &scif1_platform_data, 156 .platform_data = &scif1_platform_data,
149 }, 157 },
@@ -152,20 +160,24 @@ static struct platform_device scif1_device = {
152#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 160#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
153 defined(CONFIG_CPU_SUBTYPE_SH7709) 161 defined(CONFIG_CPU_SUBTYPE_SH7709)
154static struct plat_sci_port scif2_platform_data = { 162static struct plat_sci_port scif2_platform_data = {
155 .mapbase = 0xa4000140,
156 .port_reg = SCIx_NOT_SUPPORTED, 163 .port_reg = SCIx_NOT_SUPPORTED,
157 .flags = UPF_BOOT_AUTOCONF, 164 .flags = UPF_BOOT_AUTOCONF,
158 .scscr = SCSCR_TE | SCSCR_RE, 165 .scscr = SCSCR_TE | SCSCR_RE,
159 .scbrr_algo_id = SCBRR_ALGO_2,
160 .type = PORT_IRDA, 166 .type = PORT_IRDA,
161 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
162 .ops = &sh770x_sci_port_ops, 167 .ops = &sh770x_sci_port_ops,
163 .regshift = 1, 168 .regshift = 1,
164}; 169};
165 170
171static struct resource scif2_resources[] = {
172 DEFINE_RES_MEM(0xa4000140, 0x100),
173 DEFINE_RES_IRQ(evt2irq(0x880)),
174};
175
166static struct platform_device scif2_device = { 176static struct platform_device scif2_device = {
167 .name = "sh-sci", 177 .name = "sh-sci",
168 .id = 2, 178 .id = 2,
179 .resource = scif2_resources,
180 .num_resources = ARRAY_SIZE(scif2_resources),
169 .dev = { 181 .dev = {
170 .platform_data = &scif2_platform_data, 182 .platform_data = &scif2_platform_data,
171 }, 183 },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 93c9c5e24a7a..e2ce9360ed5a 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -98,36 +98,44 @@ static struct platform_device rtc_device = {
98}; 98};
99 99
100static struct plat_sci_port scif0_platform_data = { 100static struct plat_sci_port scif0_platform_data = {
101 .mapbase = 0xa4400000,
102 .flags = UPF_BOOT_AUTOCONF, 101 .flags = UPF_BOOT_AUTOCONF,
103 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | 102 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
104 SCSCR_CKE1 | SCSCR_CKE0, 103 SCSCR_CKE1 | SCSCR_CKE0,
105 .scbrr_algo_id = SCBRR_ALGO_2,
106 .type = PORT_SCIF, 104 .type = PORT_SCIF,
107 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), 105};
106
107static struct resource scif0_resources[] = {
108 DEFINE_RES_MEM(0xa4400000, 0x100),
109 DEFINE_RES_IRQ(evt2irq(0x880)),
108}; 110};
109 111
110static struct platform_device scif0_device = { 112static struct platform_device scif0_device = {
111 .name = "sh-sci", 113 .name = "sh-sci",
112 .id = 0, 114 .id = 0,
115 .resource = scif0_resources,
116 .num_resources = ARRAY_SIZE(scif0_resources),
113 .dev = { 117 .dev = {
114 .platform_data = &scif0_platform_data, 118 .platform_data = &scif0_platform_data,
115 }, 119 },
116}; 120};
117 121
118static struct plat_sci_port scif1_platform_data = { 122static struct plat_sci_port scif1_platform_data = {
119 .mapbase = 0xa4410000,
120 .flags = UPF_BOOT_AUTOCONF, 123 .flags = UPF_BOOT_AUTOCONF,
121 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | 124 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
122 SCSCR_CKE1 | SCSCR_CKE0, 125 SCSCR_CKE1 | SCSCR_CKE0,
123 .scbrr_algo_id = SCBRR_ALGO_2,
124 .type = PORT_SCIF, 126 .type = PORT_SCIF,
125 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), 127};
128
129static struct resource scif1_resources[] = {
130 DEFINE_RES_MEM(0xa4410000, 0x100),
131 DEFINE_RES_IRQ(evt2irq(0x900)),
126}; 132};
127 133
128static struct platform_device scif1_device = { 134static struct platform_device scif1_device = {
129 .name = "sh-sci", 135 .name = "sh-sci",
130 .id = 1, 136 .id = 1,
137 .resource = scif1_resources,
138 .num_resources = ARRAY_SIZE(scif1_resources),
131 .dev = { 139 .dev = {
132 .platform_data = &scif1_platform_data, 140 .platform_data = &scif1_platform_data,
133 }, 141 },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 42d991f632b1..1d5729dc0724 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -52,38 +52,46 @@ static struct platform_device rtc_device = {
52}; 52};
53 53
54static struct plat_sci_port scif0_platform_data = { 54static struct plat_sci_port scif0_platform_data = {
55 .mapbase = 0xa4430000,
56 .flags = UPF_BOOT_AUTOCONF, 55 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE, 56 .scscr = SCSCR_RE | SCSCR_TE,
58 .scbrr_algo_id = SCBRR_ALGO_4,
59 .type = PORT_SCIF, 57 .type = PORT_SCIF,
60 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
61 .ops = &sh7720_sci_port_ops, 58 .ops = &sh7720_sci_port_ops,
62 .regtype = SCIx_SH7705_SCIF_REGTYPE, 59 .regtype = SCIx_SH7705_SCIF_REGTYPE,
63}; 60};
64 61
62static struct resource scif0_resources[] = {
63 DEFINE_RES_MEM(0xa4430000, 0x100),
64 DEFINE_RES_IRQ(evt2irq(0xc00)),
65};
66
65static struct platform_device scif0_device = { 67static struct platform_device scif0_device = {
66 .name = "sh-sci", 68 .name = "sh-sci",
67 .id = 0, 69 .id = 0,
70 .resource = scif0_resources,
71 .num_resources = ARRAY_SIZE(scif0_resources),
68 .dev = { 72 .dev = {
69 .platform_data = &scif0_platform_data, 73 .platform_data = &scif0_platform_data,
70 }, 74 },
71}; 75};
72 76
73static struct plat_sci_port scif1_platform_data = { 77static struct plat_sci_port scif1_platform_data = {
74 .mapbase = 0xa4438000,
75 .flags = UPF_BOOT_AUTOCONF, 78 .flags = UPF_BOOT_AUTOCONF,
76 .scscr = SCSCR_RE | SCSCR_TE, 79 .scscr = SCSCR_RE | SCSCR_TE,
77 .scbrr_algo_id = SCBRR_ALGO_4,
78 .type = PORT_SCIF, 80 .type = PORT_SCIF,
79 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
80 .ops = &sh7720_sci_port_ops, 81 .ops = &sh7720_sci_port_ops,
81 .regtype = SCIx_SH7705_SCIF_REGTYPE, 82 .regtype = SCIx_SH7705_SCIF_REGTYPE,
82}; 83};
83 84
85static struct resource scif1_resources[] = {
86 DEFINE_RES_MEM(0xa4438000, 0x100),
87 DEFINE_RES_IRQ(evt2irq(0xc20)),
88};
89
84static struct platform_device scif1_device = { 90static struct platform_device scif1_device = {
85 .name = "sh-sci", 91 .name = "sh-sci",
86 .id = 1, 92 .id = 1,
93 .resource = scif1_resources,
94 .num_resources = ARRAY_SIZE(scif1_resources),
87 .dev = { 95 .dev = {
88 .platform_data = &scif1_platform_data, 96 .platform_data = &scif1_platform_data,
89 }, 97 },
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index 2a5320aa73bb..a8bd778d5ac8 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -17,20 +17,24 @@
17#include <linux/io.h> 17#include <linux/io.h>
18 18
19static struct plat_sci_port scif0_platform_data = { 19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = 0xffe80000,
21 .flags = UPF_BOOT_AUTOCONF, 20 .flags = UPF_BOOT_AUTOCONF,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF, 22 .type = PORT_SCIF,
25 .irqs = { evt2irq(0x700), 23};
26 evt2irq(0x720), 24
27 evt2irq(0x760), 25static struct resource scif0_resources[] = {
28 evt2irq(0x740) }, 26 DEFINE_RES_MEM(0xffe80000, 0x100),
27 DEFINE_RES_IRQ(evt2irq(0x700)),
28 DEFINE_RES_IRQ(evt2irq(0x720)),
29 DEFINE_RES_IRQ(evt2irq(0x760)),
30 DEFINE_RES_IRQ(evt2irq(0x740)),
29}; 31};
30 32
31static struct platform_device scif0_device = { 33static struct platform_device scif0_device = {
32 .name = "sh-sci", 34 .name = "sh-sci",
33 .id = 0, 35 .id = 0,
36 .resource = scif0_resources,
37 .num_resources = ARRAY_SIZE(scif0_resources),
34 .dev = { 38 .dev = {
35 .platform_data = &scif0_platform_data, 39 .platform_data = &scif0_platform_data,
36 }, 40 },
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 04a45512596f..a447a248491f 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -38,36 +38,44 @@ static struct platform_device rtc_device = {
38}; 38};
39 39
40static struct plat_sci_port sci_platform_data = { 40static struct plat_sci_port sci_platform_data = {
41 .mapbase = 0xffe00000,
42 .port_reg = 0xffe0001C, 41 .port_reg = 0xffe0001C,
43 .flags = UPF_BOOT_AUTOCONF, 42 .flags = UPF_BOOT_AUTOCONF,
44 .scscr = SCSCR_TE | SCSCR_RE, 43 .scscr = SCSCR_TE | SCSCR_RE,
45 .scbrr_algo_id = SCBRR_ALGO_2,
46 .type = PORT_SCI, 44 .type = PORT_SCI,
47 .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)),
48 .regshift = 2, 45 .regshift = 2,
49}; 46};
50 47
48static struct resource sci_resources[] = {
49 DEFINE_RES_MEM(0xffe00000, 0x100),
50 DEFINE_RES_IRQ(evt2irq(0x4e0)),
51};
52
51static struct platform_device sci_device = { 53static struct platform_device sci_device = {
52 .name = "sh-sci", 54 .name = "sh-sci",
53 .id = 0, 55 .id = 0,
56 .resource = sci_resources,
57 .num_resources = ARRAY_SIZE(sci_resources),
54 .dev = { 58 .dev = {
55 .platform_data = &sci_platform_data, 59 .platform_data = &sci_platform_data,
56 }, 60 },
57}; 61};
58 62
59static struct plat_sci_port scif_platform_data = { 63static struct plat_sci_port scif_platform_data = {
60 .mapbase = 0xffe80000,
61 .flags = UPF_BOOT_AUTOCONF, 64 .flags = UPF_BOOT_AUTOCONF,
62 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, 65 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
63 .scbrr_algo_id = SCBRR_ALGO_2,
64 .type = PORT_SCIF, 66 .type = PORT_SCIF,
65 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), 67};
68
69static struct resource scif_resources[] = {
70 DEFINE_RES_MEM(0xffe80000, 0x100),
71 DEFINE_RES_IRQ(evt2irq(0x700)),
66}; 72};
67 73
68static struct platform_device scif_device = { 74static struct platform_device scif_device = {
69 .name = "sh-sci", 75 .name = "sh-sci",
70 .id = 1, 76 .id = 1,
77 .resource = scif_resources,
78 .num_resources = ARRAY_SIZE(scif_resources),
71 .dev = { 79 .dev = {
72 .platform_data = &scif_platform_data, 80 .platform_data = &scif_platform_data,
73 }, 81 },
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 98e075ada44e..1abd9fb4a386 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -128,83 +128,99 @@ static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
128 mask_registers, prio_registers, NULL); 128 mask_registers, prio_registers, NULL);
129 129
130static struct plat_sci_port scif0_platform_data = { 130static struct plat_sci_port scif0_platform_data = {
131 .mapbase = 0xfe600000,
132 .flags = UPF_BOOT_AUTOCONF, 131 .flags = UPF_BOOT_AUTOCONF,
133 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 132 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
134 .scbrr_algo_id = SCBRR_ALGO_2,
135 .type = PORT_SCIF, 133 .type = PORT_SCIF,
136 .irqs = { evt2irq(0x880),
137 evt2irq(0x8a0),
138 evt2irq(0x8e0),
139 evt2irq(0x8c0) },
140 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 134 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
141}; 135};
142 136
137static struct resource scif0_resources[] = {
138 DEFINE_RES_MEM(0xfe600000, 0x100),
139 DEFINE_RES_IRQ(evt2irq(0x880)),
140 DEFINE_RES_IRQ(evt2irq(0x8a0)),
141 DEFINE_RES_IRQ(evt2irq(0x8e0)),
142 DEFINE_RES_IRQ(evt2irq(0x8c0)),
143};
144
143static struct platform_device scif0_device = { 145static struct platform_device scif0_device = {
144 .name = "sh-sci", 146 .name = "sh-sci",
145 .id = 0, 147 .id = 0,
148 .resource = scif0_resources,
149 .num_resources = ARRAY_SIZE(scif0_resources),
146 .dev = { 150 .dev = {
147 .platform_data = &scif0_platform_data, 151 .platform_data = &scif0_platform_data,
148 }, 152 },
149}; 153};
150 154
151static struct plat_sci_port scif1_platform_data = { 155static struct plat_sci_port scif1_platform_data = {
152 .mapbase = 0xfe610000,
153 .flags = UPF_BOOT_AUTOCONF, 156 .flags = UPF_BOOT_AUTOCONF,
154 .type = PORT_SCIF, 157 .type = PORT_SCIF,
155 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 158 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
156 .scbrr_algo_id = SCBRR_ALGO_2,
157 .irqs = { evt2irq(0xb00),
158 evt2irq(0xb20),
159 evt2irq(0xb60),
160 evt2irq(0xb40) },
161 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 159 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
162}; 160};
163 161
162static struct resource scif1_resources[] = {
163 DEFINE_RES_MEM(0xfe610000, 0x100),
164 DEFINE_RES_IRQ(evt2irq(0xb00)),
165 DEFINE_RES_IRQ(evt2irq(0xb20)),
166 DEFINE_RES_IRQ(evt2irq(0xb60)),
167 DEFINE_RES_IRQ(evt2irq(0xb40)),
168};
169
164static struct platform_device scif1_device = { 170static struct platform_device scif1_device = {
165 .name = "sh-sci", 171 .name = "sh-sci",
166 .id = 1, 172 .id = 1,
173 .resource = scif1_resources,
174 .num_resources = ARRAY_SIZE(scif1_resources),
167 .dev = { 175 .dev = {
168 .platform_data = &scif1_platform_data, 176 .platform_data = &scif1_platform_data,
169 }, 177 },
170}; 178};
171 179
172static struct plat_sci_port scif2_platform_data = { 180static struct plat_sci_port scif2_platform_data = {
173 .mapbase = 0xfe620000,
174 .flags = UPF_BOOT_AUTOCONF, 181 .flags = UPF_BOOT_AUTOCONF,
175 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 182 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
176 .scbrr_algo_id = SCBRR_ALGO_2,
177 .type = PORT_SCIF, 183 .type = PORT_SCIF,
178 .irqs = { evt2irq(0xb80),
179 evt2irq(0xba0),
180 evt2irq(0xbe0),
181 evt2irq(0xbc0) },
182 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 184 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
183}; 185};
184 186
187static struct resource scif2_resources[] = {
188 DEFINE_RES_MEM(0xfe620000, 0x100),
189 DEFINE_RES_IRQ(evt2irq(0xb80)),
190 DEFINE_RES_IRQ(evt2irq(0xba0)),
191 DEFINE_RES_IRQ(evt2irq(0xbe0)),
192 DEFINE_RES_IRQ(evt2irq(0xbc0)),
193};
194
185static struct platform_device scif2_device = { 195static struct platform_device scif2_device = {
186 .name = "sh-sci", 196 .name = "sh-sci",
187 .id = 2, 197 .id = 2,
198 .resource = scif2_resources,
199 .num_resources = ARRAY_SIZE(scif2_resources),
188 .dev = { 200 .dev = {
189 .platform_data = &scif2_platform_data, 201 .platform_data = &scif2_platform_data,
190 }, 202 },
191}; 203};
192 204
193static struct plat_sci_port scif3_platform_data = { 205static struct plat_sci_port scif3_platform_data = {
194 .mapbase = 0xfe480000,
195 .flags = UPF_BOOT_AUTOCONF, 206 .flags = UPF_BOOT_AUTOCONF,
196 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 207 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
197 .scbrr_algo_id = SCBRR_ALGO_2,
198 .type = PORT_SCI, 208 .type = PORT_SCI,
199 .irqs = { evt2irq(0xc00),
200 evt2irq(0xc20),
201 evt2irq(0xc40), },
202 .regshift = 2, 209 .regshift = 2,
203}; 210};
204 211
212static struct resource scif3_resources[] = {
213 DEFINE_RES_MEM(0xfe480000, 0x100),
214 DEFINE_RES_IRQ(evt2irq(0xc00)),
215 DEFINE_RES_IRQ(evt2irq(0xc20)),
216 DEFINE_RES_IRQ(evt2irq(0xc40)),
217};
218
205static struct platform_device scif3_device = { 219static struct platform_device scif3_device = {
206 .name = "sh-sci", 220 .name = "sh-sci",
207 .id = 3, 221 .id = 3,
222 .resource = scif3_resources,
223 .num_resources = ARRAY_SIZE(scif3_resources),
208 .dev = { 224 .dev = {
209 .platform_data = &scif3_platform_data, 225 .platform_data = &scif3_platform_data,
210 }, 226 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index b91ea8300a3e..245d19254489 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -18,68 +18,84 @@
18 18
19/* Serial */ 19/* Serial */
20static struct plat_sci_port scif0_platform_data = { 20static struct plat_sci_port scif0_platform_data = {
21 .mapbase = 0xffe00000,
22 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
24 .scbrr_algo_id = SCBRR_ALGO_2,
25 .type = PORT_SCIF, 23 .type = PORT_SCIF,
26 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), 24};
25
26static struct resource scif0_resources[] = {
27 DEFINE_RES_MEM(0xffe00000, 0x100),
28 DEFINE_RES_IRQ(evt2irq(0xc00)),
27}; 29};
28 30
29static struct platform_device scif0_device = { 31static struct platform_device scif0_device = {
30 .name = "sh-sci", 32 .name = "sh-sci",
31 .id = 0, 33 .id = 0,
34 .resource = scif0_resources,
35 .num_resources = ARRAY_SIZE(scif0_resources),
32 .dev = { 36 .dev = {
33 .platform_data = &scif0_platform_data, 37 .platform_data = &scif0_platform_data,
34 }, 38 },
35}; 39};
36 40
37static struct plat_sci_port scif1_platform_data = { 41static struct plat_sci_port scif1_platform_data = {
38 .mapbase = 0xffe10000,
39 .flags = UPF_BOOT_AUTOCONF, 42 .flags = UPF_BOOT_AUTOCONF,
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
41 .scbrr_algo_id = SCBRR_ALGO_2,
42 .type = PORT_SCIF, 44 .type = PORT_SCIF,
43 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), 45};
46
47static struct resource scif1_resources[] = {
48 DEFINE_RES_MEM(0xffe10000, 0x100),
49 DEFINE_RES_IRQ(evt2irq(0xc20)),
44}; 50};
45 51
46static struct platform_device scif1_device = { 52static struct platform_device scif1_device = {
47 .name = "sh-sci", 53 .name = "sh-sci",
48 .id = 1, 54 .id = 1,
55 .resource = scif1_resources,
56 .num_resources = ARRAY_SIZE(scif1_resources),
49 .dev = { 57 .dev = {
50 .platform_data = &scif1_platform_data, 58 .platform_data = &scif1_platform_data,
51 }, 59 },
52}; 60};
53 61
54static struct plat_sci_port scif2_platform_data = { 62static struct plat_sci_port scif2_platform_data = {
55 .mapbase = 0xffe20000,
56 .flags = UPF_BOOT_AUTOCONF, 63 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 64 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
58 .scbrr_algo_id = SCBRR_ALGO_2,
59 .type = PORT_SCIF, 65 .type = PORT_SCIF,
60 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), 66};
67
68static struct resource scif2_resources[] = {
69 DEFINE_RES_MEM(0xffe20000, 0x100),
70 DEFINE_RES_IRQ(evt2irq(0xc40)),
61}; 71};
62 72
63static struct platform_device scif2_device = { 73static struct platform_device scif2_device = {
64 .name = "sh-sci", 74 .name = "sh-sci",
65 .id = 2, 75 .id = 2,
76 .resource = scif2_resources,
77 .num_resources = ARRAY_SIZE(scif2_resources),
66 .dev = { 78 .dev = {
67 .platform_data = &scif2_platform_data, 79 .platform_data = &scif2_platform_data,
68 }, 80 },
69}; 81};
70 82
71static struct plat_sci_port scif3_platform_data = { 83static struct plat_sci_port scif3_platform_data = {
72 .mapbase = 0xffe30000,
73 .flags = UPF_BOOT_AUTOCONF, 84 .flags = UPF_BOOT_AUTOCONF,
74 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 85 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
75 .scbrr_algo_id = SCBRR_ALGO_2,
76 .type = PORT_SCIF, 86 .type = PORT_SCIF,
77 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc60)), 87};
88
89static struct resource scif3_resources[] = {
90 DEFINE_RES_MEM(0xffe30000, 0x100),
91 DEFINE_RES_IRQ(evt2irq(0xc60)),
78}; 92};
79 93
80static struct platform_device scif3_device = { 94static struct platform_device scif3_device = {
81 .name = "sh-sci", 95 .name = "sh-sci",
82 .id = 3, 96 .id = 3,
97 .resource = scif3_resources,
98 .num_resources = ARRAY_SIZE(scif3_resources),
83 .dev = { 99 .dev = {
84 .platform_data = &scif3_platform_data, 100 .platform_data = &scif3_platform_data,
85 }, 101 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 0bd09d51419f..6f56cbd76b20 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -20,18 +20,22 @@
20#include <asm/clock.h> 20#include <asm/clock.h>
21 21
22static struct plat_sci_port scif0_platform_data = { 22static struct plat_sci_port scif0_platform_data = {
23 .mapbase = 0xffe00000,
24 .port_reg = 0xa405013e, 23 .port_reg = 0xa405013e,
25 .flags = UPF_BOOT_AUTOCONF, 24 .flags = UPF_BOOT_AUTOCONF,
26 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 25 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
27 .scbrr_algo_id = SCBRR_ALGO_2,
28 .type = PORT_SCIF, 26 .type = PORT_SCIF,
29 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), 27};
28
29static struct resource scif0_resources[] = {
30 DEFINE_RES_MEM(0xffe00000, 0x100),
31 DEFINE_RES_IRQ(evt2irq(0xc00)),
30}; 32};
31 33
32static struct platform_device scif0_device = { 34static struct platform_device scif0_device = {
33 .name = "sh-sci", 35 .name = "sh-sci",
34 .id = 0, 36 .id = 0,
37 .resource = scif0_resources,
38 .num_resources = ARRAY_SIZE(scif0_resources),
35 .dev = { 39 .dev = {
36 .platform_data = &scif0_platform_data, 40 .platform_data = &scif0_platform_data,
37 }, 41 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 6a868b091c2d..5a94efc8d4ce 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -179,57 +179,69 @@ struct platform_device dma_device = {
179 179
180/* Serial */ 180/* Serial */
181static struct plat_sci_port scif0_platform_data = { 181static struct plat_sci_port scif0_platform_data = {
182 .mapbase = 0xffe00000,
183 .flags = UPF_BOOT_AUTOCONF, 182 .flags = UPF_BOOT_AUTOCONF,
184 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
185 .scbrr_algo_id = SCBRR_ALGO_2,
186 .type = PORT_SCIF, 184 .type = PORT_SCIF,
187 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
188 .ops = &sh7722_sci_port_ops, 185 .ops = &sh7722_sci_port_ops,
189 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 186 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
190}; 187};
191 188
189static struct resource scif0_resources[] = {
190 DEFINE_RES_MEM(0xffe00000, 0x100),
191 DEFINE_RES_IRQ(evt2irq(0xc00)),
192};
193
192static struct platform_device scif0_device = { 194static struct platform_device scif0_device = {
193 .name = "sh-sci", 195 .name = "sh-sci",
194 .id = 0, 196 .id = 0,
197 .resource = scif0_resources,
198 .num_resources = ARRAY_SIZE(scif0_resources),
195 .dev = { 199 .dev = {
196 .platform_data = &scif0_platform_data, 200 .platform_data = &scif0_platform_data,
197 }, 201 },
198}; 202};
199 203
200static struct plat_sci_port scif1_platform_data = { 204static struct plat_sci_port scif1_platform_data = {
201 .mapbase = 0xffe10000,
202 .flags = UPF_BOOT_AUTOCONF, 205 .flags = UPF_BOOT_AUTOCONF,
203 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 206 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
204 .scbrr_algo_id = SCBRR_ALGO_2,
205 .type = PORT_SCIF, 207 .type = PORT_SCIF,
206 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
207 .ops = &sh7722_sci_port_ops, 208 .ops = &sh7722_sci_port_ops,
208 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 209 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
209}; 210};
210 211
212static struct resource scif1_resources[] = {
213 DEFINE_RES_MEM(0xffe10000, 0x100),
214 DEFINE_RES_IRQ(evt2irq(0xc20)),
215};
216
211static struct platform_device scif1_device = { 217static struct platform_device scif1_device = {
212 .name = "sh-sci", 218 .name = "sh-sci",
213 .id = 1, 219 .id = 1,
220 .resource = scif1_resources,
221 .num_resources = ARRAY_SIZE(scif1_resources),
214 .dev = { 222 .dev = {
215 .platform_data = &scif1_platform_data, 223 .platform_data = &scif1_platform_data,
216 }, 224 },
217}; 225};
218 226
219static struct plat_sci_port scif2_platform_data = { 227static struct plat_sci_port scif2_platform_data = {
220 .mapbase = 0xffe20000,
221 .flags = UPF_BOOT_AUTOCONF, 228 .flags = UPF_BOOT_AUTOCONF,
222 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 229 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
223 .scbrr_algo_id = SCBRR_ALGO_2,
224 .type = PORT_SCIF, 230 .type = PORT_SCIF,
225 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
226 .ops = &sh7722_sci_port_ops, 231 .ops = &sh7722_sci_port_ops,
227 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 232 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
228}; 233};
229 234
235static struct resource scif2_resources[] = {
236 DEFINE_RES_MEM(0xffe20000, 0x100),
237 DEFINE_RES_IRQ(evt2irq(0xc40)),
238};
239
230static struct platform_device scif2_device = { 240static struct platform_device scif2_device = {
231 .name = "sh-sci", 241 .name = "sh-sci",
232 .id = 2, 242 .id = 2,
243 .resource = scif2_resources,
244 .num_resources = ARRAY_SIZE(scif2_resources),
233 .dev = { 245 .dev = {
234 .platform_data = &scif2_platform_data, 246 .platform_data = &scif2_platform_data,
235 }, 247 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 28d6fd835fe0..3c5eb0993a75 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -23,111 +23,138 @@
23 23
24/* Serial */ 24/* Serial */
25static struct plat_sci_port scif0_platform_data = { 25static struct plat_sci_port scif0_platform_data = {
26 .mapbase = 0xffe00000,
27 .port_reg = 0xa4050160, 26 .port_reg = 0xa4050160,
28 .flags = UPF_BOOT_AUTOCONF, 27 .flags = UPF_BOOT_AUTOCONF,
29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
30 .scbrr_algo_id = SCBRR_ALGO_2,
31 .type = PORT_SCIF, 29 .type = PORT_SCIF,
32 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
33 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 30 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
34}; 31};
35 32
33static struct resource scif0_resources[] = {
34 DEFINE_RES_MEM(0xffe00000, 0x100),
35 DEFINE_RES_IRQ(evt2irq(0xc00)),
36};
37
36static struct platform_device scif0_device = { 38static struct platform_device scif0_device = {
37 .name = "sh-sci", 39 .name = "sh-sci",
38 .id = 0, 40 .id = 0,
41 .resource = scif0_resources,
42 .num_resources = ARRAY_SIZE(scif0_resources),
39 .dev = { 43 .dev = {
40 .platform_data = &scif0_platform_data, 44 .platform_data = &scif0_platform_data,
41 }, 45 },
42}; 46};
43 47
44static struct plat_sci_port scif1_platform_data = { 48static struct plat_sci_port scif1_platform_data = {
45 .mapbase = 0xffe10000,
46 .port_reg = SCIx_NOT_SUPPORTED, 49 .port_reg = SCIx_NOT_SUPPORTED,
47 .flags = UPF_BOOT_AUTOCONF, 50 .flags = UPF_BOOT_AUTOCONF,
48 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
49 .scbrr_algo_id = SCBRR_ALGO_2,
50 .type = PORT_SCIF, 52 .type = PORT_SCIF,
51 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
52 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 53 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
53}; 54};
54 55
56static struct resource scif1_resources[] = {
57 DEFINE_RES_MEM(0xffe10000, 0x100),
58 DEFINE_RES_IRQ(evt2irq(0xc20)),
59};
60
55static struct platform_device scif1_device = { 61static struct platform_device scif1_device = {
56 .name = "sh-sci", 62 .name = "sh-sci",
57 .id = 1, 63 .id = 1,
64 .resource = scif1_resources,
65 .num_resources = ARRAY_SIZE(scif1_resources),
58 .dev = { 66 .dev = {
59 .platform_data = &scif1_platform_data, 67 .platform_data = &scif1_platform_data,
60 }, 68 },
61}; 69};
62 70
63static struct plat_sci_port scif2_platform_data = { 71static struct plat_sci_port scif2_platform_data = {
64 .mapbase = 0xffe20000,
65 .port_reg = SCIx_NOT_SUPPORTED, 72 .port_reg = SCIx_NOT_SUPPORTED,
66 .flags = UPF_BOOT_AUTOCONF, 73 .flags = UPF_BOOT_AUTOCONF,
67 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 74 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
68 .scbrr_algo_id = SCBRR_ALGO_2,
69 .type = PORT_SCIF, 75 .type = PORT_SCIF,
70 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
71 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 76 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
72}; 77};
73 78
79static struct resource scif2_resources[] = {
80 DEFINE_RES_MEM(0xffe20000, 0x100),
81 DEFINE_RES_IRQ(evt2irq(0xc40)),
82};
83
74static struct platform_device scif2_device = { 84static struct platform_device scif2_device = {
75 .name = "sh-sci", 85 .name = "sh-sci",
76 .id = 2, 86 .id = 2,
87 .resource = scif2_resources,
88 .num_resources = ARRAY_SIZE(scif2_resources),
77 .dev = { 89 .dev = {
78 .platform_data = &scif2_platform_data, 90 .platform_data = &scif2_platform_data,
79 }, 91 },
80}; 92};
81 93
82static struct plat_sci_port scif3_platform_data = { 94static struct plat_sci_port scif3_platform_data = {
83 .mapbase = 0xa4e30000,
84 .flags = UPF_BOOT_AUTOCONF, 95 .flags = UPF_BOOT_AUTOCONF,
85 .port_reg = SCIx_NOT_SUPPORTED, 96 .port_reg = SCIx_NOT_SUPPORTED,
86 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 97 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
87 .scbrr_algo_id = SCBRR_ALGO_3, 98 .sampling_rate = 8,
88 .type = PORT_SCIFA, 99 .type = PORT_SCIFA,
89 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), 100};
101
102static struct resource scif3_resources[] = {
103 DEFINE_RES_MEM(0xa4e30000, 0x100),
104 DEFINE_RES_IRQ(evt2irq(0x900)),
90}; 105};
91 106
92static struct platform_device scif3_device = { 107static struct platform_device scif3_device = {
93 .name = "sh-sci", 108 .name = "sh-sci",
94 .id = 3, 109 .id = 3,
110 .resource = scif3_resources,
111 .num_resources = ARRAY_SIZE(scif3_resources),
95 .dev = { 112 .dev = {
96 .platform_data = &scif3_platform_data, 113 .platform_data = &scif3_platform_data,
97 }, 114 },
98}; 115};
99 116
100static struct plat_sci_port scif4_platform_data = { 117static struct plat_sci_port scif4_platform_data = {
101 .mapbase = 0xa4e40000,
102 .port_reg = SCIx_NOT_SUPPORTED, 118 .port_reg = SCIx_NOT_SUPPORTED,
103 .flags = UPF_BOOT_AUTOCONF, 119 .flags = UPF_BOOT_AUTOCONF,
104 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 120 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
105 .scbrr_algo_id = SCBRR_ALGO_3, 121 .sampling_rate = 8,
106 .type = PORT_SCIFA, 122 .type = PORT_SCIFA,
107 .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), 123};
124
125static struct resource scif4_resources[] = {
126 DEFINE_RES_MEM(0xa4e40000, 0x100),
127 DEFINE_RES_IRQ(evt2irq(0xd00)),
108}; 128};
109 129
110static struct platform_device scif4_device = { 130static struct platform_device scif4_device = {
111 .name = "sh-sci", 131 .name = "sh-sci",
112 .id = 4, 132 .id = 4,
133 .resource = scif4_resources,
134 .num_resources = ARRAY_SIZE(scif4_resources),
113 .dev = { 135 .dev = {
114 .platform_data = &scif4_platform_data, 136 .platform_data = &scif4_platform_data,
115 }, 137 },
116}; 138};
117 139
118static struct plat_sci_port scif5_platform_data = { 140static struct plat_sci_port scif5_platform_data = {
119 .mapbase = 0xa4e50000,
120 .port_reg = SCIx_NOT_SUPPORTED, 141 .port_reg = SCIx_NOT_SUPPORTED,
121 .flags = UPF_BOOT_AUTOCONF, 142 .flags = UPF_BOOT_AUTOCONF,
122 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 143 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
123 .scbrr_algo_id = SCBRR_ALGO_3, 144 .sampling_rate = 8,
124 .type = PORT_SCIFA, 145 .type = PORT_SCIFA,
125 .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), 146};
147
148static struct resource scif5_resources[] = {
149 DEFINE_RES_MEM(0xa4e50000, 0x100),
150 DEFINE_RES_IRQ(evt2irq(0xfa0)),
126}; 151};
127 152
128static struct platform_device scif5_device = { 153static struct platform_device scif5_device = {
129 .name = "sh-sci", 154 .name = "sh-sci",
130 .id = 5, 155 .id = 5,
156 .resource = scif5_resources,
157 .num_resources = ARRAY_SIZE(scif5_resources),
131 .dev = { 158 .dev = {
132 .platform_data = &scif5_platform_data, 159 .platform_data = &scif5_platform_data,
133 }, 160 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 26b74c2f9496..60ebbc6842ff 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -290,111 +290,138 @@ static struct platform_device dma1_device = {
290 290
291/* Serial */ 291/* Serial */
292static struct plat_sci_port scif0_platform_data = { 292static struct plat_sci_port scif0_platform_data = {
293 .mapbase = 0xffe00000,
294 .port_reg = SCIx_NOT_SUPPORTED, 293 .port_reg = SCIx_NOT_SUPPORTED,
295 .flags = UPF_BOOT_AUTOCONF, 294 .flags = UPF_BOOT_AUTOCONF,
296 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 295 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
297 .scbrr_algo_id = SCBRR_ALGO_2,
298 .type = PORT_SCIF, 296 .type = PORT_SCIF,
299 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
300 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 297 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
301}; 298};
302 299
300static struct resource scif0_resources[] = {
301 DEFINE_RES_MEM(0xffe00000, 0x100),
302 DEFINE_RES_IRQ(evt2irq(0xc00)),
303};
304
303static struct platform_device scif0_device = { 305static struct platform_device scif0_device = {
304 .name = "sh-sci", 306 .name = "sh-sci",
305 .id = 0, 307 .id = 0,
308 .resource = scif0_resources,
309 .num_resources = ARRAY_SIZE(scif0_resources),
306 .dev = { 310 .dev = {
307 .platform_data = &scif0_platform_data, 311 .platform_data = &scif0_platform_data,
308 }, 312 },
309}; 313};
310 314
311static struct plat_sci_port scif1_platform_data = { 315static struct plat_sci_port scif1_platform_data = {
312 .mapbase = 0xffe10000,
313 .port_reg = SCIx_NOT_SUPPORTED, 316 .port_reg = SCIx_NOT_SUPPORTED,
314 .flags = UPF_BOOT_AUTOCONF, 317 .flags = UPF_BOOT_AUTOCONF,
315 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 318 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
316 .scbrr_algo_id = SCBRR_ALGO_2,
317 .type = PORT_SCIF, 319 .type = PORT_SCIF,
318 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
319 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 320 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
320}; 321};
321 322
323static struct resource scif1_resources[] = {
324 DEFINE_RES_MEM(0xffe10000, 0x100),
325 DEFINE_RES_IRQ(evt2irq(0xc20)),
326};
327
322static struct platform_device scif1_device = { 328static struct platform_device scif1_device = {
323 .name = "sh-sci", 329 .name = "sh-sci",
324 .id = 1, 330 .id = 1,
331 .resource = scif1_resources,
332 .num_resources = ARRAY_SIZE(scif1_resources),
325 .dev = { 333 .dev = {
326 .platform_data = &scif1_platform_data, 334 .platform_data = &scif1_platform_data,
327 }, 335 },
328}; 336};
329 337
330static struct plat_sci_port scif2_platform_data = { 338static struct plat_sci_port scif2_platform_data = {
331 .mapbase = 0xffe20000,
332 .port_reg = SCIx_NOT_SUPPORTED, 339 .port_reg = SCIx_NOT_SUPPORTED,
333 .flags = UPF_BOOT_AUTOCONF, 340 .flags = UPF_BOOT_AUTOCONF,
334 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 341 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
335 .scbrr_algo_id = SCBRR_ALGO_2,
336 .type = PORT_SCIF, 342 .type = PORT_SCIF,
337 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
338 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 343 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
339}; 344};
340 345
346static struct resource scif2_resources[] = {
347 DEFINE_RES_MEM(0xffe20000, 0x100),
348 DEFINE_RES_IRQ(evt2irq(0xc40)),
349};
350
341static struct platform_device scif2_device = { 351static struct platform_device scif2_device = {
342 .name = "sh-sci", 352 .name = "sh-sci",
343 .id = 2, 353 .id = 2,
354 .resource = scif2_resources,
355 .num_resources = ARRAY_SIZE(scif2_resources),
344 .dev = { 356 .dev = {
345 .platform_data = &scif2_platform_data, 357 .platform_data = &scif2_platform_data,
346 }, 358 },
347}; 359};
348 360
349static struct plat_sci_port scif3_platform_data = { 361static struct plat_sci_port scif3_platform_data = {
350 .mapbase = 0xa4e30000,
351 .port_reg = SCIx_NOT_SUPPORTED, 362 .port_reg = SCIx_NOT_SUPPORTED,
352 .flags = UPF_BOOT_AUTOCONF, 363 .flags = UPF_BOOT_AUTOCONF,
353 .scscr = SCSCR_RE | SCSCR_TE, 364 .scscr = SCSCR_RE | SCSCR_TE,
354 .scbrr_algo_id = SCBRR_ALGO_3, 365 .sampling_rate = 8,
355 .type = PORT_SCIFA, 366 .type = PORT_SCIFA,
356 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), 367};
368
369static struct resource scif3_resources[] = {
370 DEFINE_RES_MEM(0xa4e30000, 0x100),
371 DEFINE_RES_IRQ(evt2irq(0x900)),
357}; 372};
358 373
359static struct platform_device scif3_device = { 374static struct platform_device scif3_device = {
360 .name = "sh-sci", 375 .name = "sh-sci",
361 .id = 3, 376 .id = 3,
377 .resource = scif3_resources,
378 .num_resources = ARRAY_SIZE(scif3_resources),
362 .dev = { 379 .dev = {
363 .platform_data = &scif3_platform_data, 380 .platform_data = &scif3_platform_data,
364 }, 381 },
365}; 382};
366 383
367static struct plat_sci_port scif4_platform_data = { 384static struct plat_sci_port scif4_platform_data = {
368 .mapbase = 0xa4e40000,
369 .port_reg = SCIx_NOT_SUPPORTED, 385 .port_reg = SCIx_NOT_SUPPORTED,
370 .flags = UPF_BOOT_AUTOCONF, 386 .flags = UPF_BOOT_AUTOCONF,
371 .scscr = SCSCR_RE | SCSCR_TE, 387 .scscr = SCSCR_RE | SCSCR_TE,
372 .scbrr_algo_id = SCBRR_ALGO_3, 388 .sampling_rate = 8,
373 .type = PORT_SCIFA, 389 .type = PORT_SCIFA,
374 .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), 390};
391
392static struct resource scif4_resources[] = {
393 DEFINE_RES_MEM(0xa4e40000, 0x100),
394 DEFINE_RES_IRQ(evt2irq(0xd00)),
375}; 395};
376 396
377static struct platform_device scif4_device = { 397static struct platform_device scif4_device = {
378 .name = "sh-sci", 398 .name = "sh-sci",
379 .id = 4, 399 .id = 4,
400 .resource = scif4_resources,
401 .num_resources = ARRAY_SIZE(scif4_resources),
380 .dev = { 402 .dev = {
381 .platform_data = &scif4_platform_data, 403 .platform_data = &scif4_platform_data,
382 }, 404 },
383}; 405};
384 406
385static struct plat_sci_port scif5_platform_data = { 407static struct plat_sci_port scif5_platform_data = {
386 .mapbase = 0xa4e50000,
387 .port_reg = SCIx_NOT_SUPPORTED, 408 .port_reg = SCIx_NOT_SUPPORTED,
388 .flags = UPF_BOOT_AUTOCONF, 409 .flags = UPF_BOOT_AUTOCONF,
389 .scscr = SCSCR_RE | SCSCR_TE, 410 .scscr = SCSCR_RE | SCSCR_TE,
390 .scbrr_algo_id = SCBRR_ALGO_3, 411 .sampling_rate = 8,
391 .type = PORT_SCIFA, 412 .type = PORT_SCIFA,
392 .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), 413};
414
415static struct resource scif5_resources[] = {
416 DEFINE_RES_MEM(0xa4e50000, 0x100),
417 DEFINE_RES_IRQ(evt2irq(0xfa0)),
393}; 418};
394 419
395static struct platform_device scif5_device = { 420static struct platform_device scif5_device = {
396 .name = "sh-sci", 421 .name = "sh-sci",
397 .id = 5, 422 .id = 5,
423 .resource = scif5_resources,
424 .num_resources = ARRAY_SIZE(scif5_resources),
398 .dev = { 425 .dev = {
399 .platform_data = &scif5_platform_data, 426 .platform_data = &scif5_platform_data,
400 }, 427 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
index f799971d453c..dad4ed1b2f94 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
@@ -25,108 +25,132 @@
25 25
26/* SCIF */ 26/* SCIF */
27static struct plat_sci_port scif0_platform_data = { 27static struct plat_sci_port scif0_platform_data = {
28 .mapbase = 0xFFE40000,
29 .flags = UPF_BOOT_AUTOCONF, 28 .flags = UPF_BOOT_AUTOCONF,
30 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
31 .scbrr_algo_id = SCBRR_ALGO_2,
32 .type = PORT_SCIF, 30 .type = PORT_SCIF,
33 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8C0)),
34 .regtype = SCIx_SH4_SCIF_REGTYPE, 31 .regtype = SCIx_SH4_SCIF_REGTYPE,
35}; 32};
36 33
34static struct resource scif0_resources[] = {
35 DEFINE_RES_MEM(0xffe40000, 0x100),
36 DEFINE_RES_IRQ(evt2irq(0x8c0)),
37};
38
37static struct platform_device scif0_device = { 39static struct platform_device scif0_device = {
38 .name = "sh-sci", 40 .name = "sh-sci",
39 .id = 0, 41 .id = 0,
42 .resource = scif0_resources,
43 .num_resources = ARRAY_SIZE(scif0_resources),
40 .dev = { 44 .dev = {
41 .platform_data = &scif0_platform_data, 45 .platform_data = &scif0_platform_data,
42 }, 46 },
43}; 47};
44 48
45static struct plat_sci_port scif1_platform_data = { 49static struct plat_sci_port scif1_platform_data = {
46 .mapbase = 0xFFE41000,
47 .flags = UPF_BOOT_AUTOCONF, 50 .flags = UPF_BOOT_AUTOCONF,
48 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
49 .scbrr_algo_id = SCBRR_ALGO_2,
50 .type = PORT_SCIF, 52 .type = PORT_SCIF,
51 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8E0)),
52 .regtype = SCIx_SH4_SCIF_REGTYPE, 53 .regtype = SCIx_SH4_SCIF_REGTYPE,
53}; 54};
54 55
56static struct resource scif1_resources[] = {
57 DEFINE_RES_MEM(0xffe41000, 0x100),
58 DEFINE_RES_IRQ(evt2irq(0x8e0)),
59};
60
55static struct platform_device scif1_device = { 61static struct platform_device scif1_device = {
56 .name = "sh-sci", 62 .name = "sh-sci",
57 .id = 1, 63 .id = 1,
64 .resource = scif1_resources,
65 .num_resources = ARRAY_SIZE(scif1_resources),
58 .dev = { 66 .dev = {
59 .platform_data = &scif1_platform_data, 67 .platform_data = &scif1_platform_data,
60 }, 68 },
61}; 69};
62 70
63static struct plat_sci_port scif2_platform_data = { 71static struct plat_sci_port scif2_platform_data = {
64 .mapbase = 0xFFE42000,
65 .flags = UPF_BOOT_AUTOCONF, 72 .flags = UPF_BOOT_AUTOCONF,
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2,
68 .type = PORT_SCIF, 74 .type = PORT_SCIF,
69 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
70 .regtype = SCIx_SH4_SCIF_REGTYPE, 75 .regtype = SCIx_SH4_SCIF_REGTYPE,
71}; 76};
72 77
78static struct resource scif2_resources[] = {
79 DEFINE_RES_MEM(0xffe42000, 0x100),
80 DEFINE_RES_IRQ(evt2irq(0x900)),
81};
82
73static struct platform_device scif2_device = { 83static struct platform_device scif2_device = {
74 .name = "sh-sci", 84 .name = "sh-sci",
75 .id = 2, 85 .id = 2,
86 .resource = scif2_resources,
87 .num_resources = ARRAY_SIZE(scif2_resources),
76 .dev = { 88 .dev = {
77 .platform_data = &scif2_platform_data, 89 .platform_data = &scif2_platform_data,
78 }, 90 },
79}; 91};
80 92
81static struct plat_sci_port scif3_platform_data = { 93static struct plat_sci_port scif3_platform_data = {
82 .mapbase = 0xFFE43000,
83 .flags = UPF_BOOT_AUTOCONF, 94 .flags = UPF_BOOT_AUTOCONF,
84 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 95 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
85 .scbrr_algo_id = SCBRR_ALGO_2,
86 .type = PORT_SCIF, 96 .type = PORT_SCIF,
87 .irqs = SCIx_IRQ_MUXED(evt2irq(0x920)),
88 .regtype = SCIx_SH4_SCIF_REGTYPE, 97 .regtype = SCIx_SH4_SCIF_REGTYPE,
89}; 98};
90 99
100static struct resource scif3_resources[] = {
101 DEFINE_RES_MEM(0xffe43000, 0x100),
102 DEFINE_RES_IRQ(evt2irq(0x920)),
103};
104
91static struct platform_device scif3_device = { 105static struct platform_device scif3_device = {
92 .name = "sh-sci", 106 .name = "sh-sci",
93 .id = 3, 107 .id = 3,
108 .resource = scif3_resources,
109 .num_resources = ARRAY_SIZE(scif3_resources),
94 .dev = { 110 .dev = {
95 .platform_data = &scif3_platform_data, 111 .platform_data = &scif3_platform_data,
96 }, 112 },
97}; 113};
98 114
99static struct plat_sci_port scif4_platform_data = { 115static struct plat_sci_port scif4_platform_data = {
100 .mapbase = 0xFFE44000,
101 .flags = UPF_BOOT_AUTOCONF, 116 .flags = UPF_BOOT_AUTOCONF,
102 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 117 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
103 .scbrr_algo_id = SCBRR_ALGO_2,
104 .type = PORT_SCIF, 118 .type = PORT_SCIF,
105 .irqs = SCIx_IRQ_MUXED(evt2irq(0x940)),
106 .regtype = SCIx_SH4_SCIF_REGTYPE, 119 .regtype = SCIx_SH4_SCIF_REGTYPE,
107}; 120};
108 121
122static struct resource scif4_resources[] = {
123 DEFINE_RES_MEM(0xffe44000, 0x100),
124 DEFINE_RES_IRQ(evt2irq(0x940)),
125};
126
109static struct platform_device scif4_device = { 127static struct platform_device scif4_device = {
110 .name = "sh-sci", 128 .name = "sh-sci",
111 .id = 4, 129 .id = 4,
130 .resource = scif4_resources,
131 .num_resources = ARRAY_SIZE(scif4_resources),
112 .dev = { 132 .dev = {
113 .platform_data = &scif4_platform_data, 133 .platform_data = &scif4_platform_data,
114 }, 134 },
115}; 135};
116 136
117static struct plat_sci_port scif5_platform_data = { 137static struct plat_sci_port scif5_platform_data = {
118 .mapbase = 0xFFE43000,
119 .flags = UPF_BOOT_AUTOCONF, 138 .flags = UPF_BOOT_AUTOCONF,
120 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
121 .scbrr_algo_id = SCBRR_ALGO_2,
122 .type = PORT_SCIF, 140 .type = PORT_SCIF,
123 .irqs = SCIx_IRQ_MUXED(evt2irq(0x960)),
124 .regtype = SCIx_SH4_SCIF_REGTYPE, 141 .regtype = SCIx_SH4_SCIF_REGTYPE,
125}; 142};
126 143
144static struct resource scif5_resources[] = {
145 DEFINE_RES_MEM(0xffe43000, 0x100),
146 DEFINE_RES_IRQ(evt2irq(0x960)),
147};
148
127static struct platform_device scif5_device = { 149static struct platform_device scif5_device = {
128 .name = "sh-sci", 150 .name = "sh-sci",
129 .id = 5, 151 .id = 5,
152 .resource = scif5_resources,
153 .num_resources = ARRAY_SIZE(scif5_resources),
130 .dev = { 154 .dev = {
131 .platform_data = &scif5_platform_data, 155 .platform_data = &scif5_platform_data,
132 }, 156 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 9079a0f9ea9b..e43e5db53913 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -24,51 +24,63 @@
24#include <cpu/sh7757.h> 24#include <cpu/sh7757.h>
25 25
26static struct plat_sci_port scif2_platform_data = { 26static struct plat_sci_port scif2_platform_data = {
27 .mapbase = 0xfe4b0000, /* SCIF2 */
28 .flags = UPF_BOOT_AUTOCONF, 27 .flags = UPF_BOOT_AUTOCONF,
29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
30 .scbrr_algo_id = SCBRR_ALGO_2,
31 .type = PORT_SCIF, 29 .type = PORT_SCIF,
32 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), 30};
31
32static struct resource scif2_resources[] = {
33 DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */
34 DEFINE_RES_IRQ(evt2irq(0x700)),
33}; 35};
34 36
35static struct platform_device scif2_device = { 37static struct platform_device scif2_device = {
36 .name = "sh-sci", 38 .name = "sh-sci",
37 .id = 0, 39 .id = 0,
40 .resource = scif2_resources,
41 .num_resources = ARRAY_SIZE(scif2_resources),
38 .dev = { 42 .dev = {
39 .platform_data = &scif2_platform_data, 43 .platform_data = &scif2_platform_data,
40 }, 44 },
41}; 45};
42 46
43static struct plat_sci_port scif3_platform_data = { 47static struct plat_sci_port scif3_platform_data = {
44 .mapbase = 0xfe4c0000, /* SCIF3 */
45 .flags = UPF_BOOT_AUTOCONF, 48 .flags = UPF_BOOT_AUTOCONF,
46 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 49 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
47 .scbrr_algo_id = SCBRR_ALGO_2,
48 .type = PORT_SCIF, 50 .type = PORT_SCIF,
49 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), 51};
52
53static struct resource scif3_resources[] = {
54 DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */
55 DEFINE_RES_IRQ(evt2irq(0xb80)),
50}; 56};
51 57
52static struct platform_device scif3_device = { 58static struct platform_device scif3_device = {
53 .name = "sh-sci", 59 .name = "sh-sci",
54 .id = 1, 60 .id = 1,
61 .resource = scif3_resources,
62 .num_resources = ARRAY_SIZE(scif3_resources),
55 .dev = { 63 .dev = {
56 .platform_data = &scif3_platform_data, 64 .platform_data = &scif3_platform_data,
57 }, 65 },
58}; 66};
59 67
60static struct plat_sci_port scif4_platform_data = { 68static struct plat_sci_port scif4_platform_data = {
61 .mapbase = 0xfe4d0000, /* SCIF4 */
62 .flags = UPF_BOOT_AUTOCONF, 69 .flags = UPF_BOOT_AUTOCONF,
63 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 70 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
64 .scbrr_algo_id = SCBRR_ALGO_2,
65 .type = PORT_SCIF, 71 .type = PORT_SCIF,
66 .irqs = SCIx_IRQ_MUXED(evt2irq(0xF00)), 72};
73
74static struct resource scif4_resources[] = {
75 DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */
76 DEFINE_RES_IRQ(evt2irq(0xf00)),
67}; 77};
68 78
69static struct platform_device scif4_device = { 79static struct platform_device scif4_device = {
70 .name = "sh-sci", 80 .name = "sh-sci",
71 .id = 2, 81 .id = 2,
82 .resource = scif4_resources,
83 .num_resources = ARRAY_SIZE(scif4_resources),
72 .dev = { 84 .dev = {
73 .platform_data = &scif4_platform_data, 85 .platform_data = &scif4_platform_data,
74 }, 86 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 1686acaaf45a..5eebbd7f4c21 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -19,54 +19,66 @@
19#include <linux/usb/ohci_pdriver.h> 19#include <linux/usb/ohci_pdriver.h>
20 20
21static struct plat_sci_port scif0_platform_data = { 21static struct plat_sci_port scif0_platform_data = {
22 .mapbase = 0xffe00000,
23 .flags = UPF_BOOT_AUTOCONF, 22 .flags = UPF_BOOT_AUTOCONF,
24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
25 .scbrr_algo_id = SCBRR_ALGO_2,
26 .type = PORT_SCIF, 24 .type = PORT_SCIF,
27 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
28 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 25 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
29}; 26};
30 27
28static struct resource scif0_resources[] = {
29 DEFINE_RES_MEM(0xffe00000, 0x100),
30 DEFINE_RES_IRQ(evt2irq(0x700)),
31};
32
31static struct platform_device scif0_device = { 33static struct platform_device scif0_device = {
32 .name = "sh-sci", 34 .name = "sh-sci",
33 .id = 0, 35 .id = 0,
36 .resource = scif0_resources,
37 .num_resources = ARRAY_SIZE(scif0_resources),
34 .dev = { 38 .dev = {
35 .platform_data = &scif0_platform_data, 39 .platform_data = &scif0_platform_data,
36 }, 40 },
37}; 41};
38 42
39static struct plat_sci_port scif1_platform_data = { 43static struct plat_sci_port scif1_platform_data = {
40 .mapbase = 0xffe08000,
41 .flags = UPF_BOOT_AUTOCONF, 44 .flags = UPF_BOOT_AUTOCONF,
42 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 45 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
43 .scbrr_algo_id = SCBRR_ALGO_2,
44 .type = PORT_SCIF, 46 .type = PORT_SCIF,
45 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)),
46 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 47 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
47}; 48};
48 49
50static struct resource scif1_resources[] = {
51 DEFINE_RES_MEM(0xffe08000, 0x100),
52 DEFINE_RES_IRQ(evt2irq(0xb80)),
53};
54
49static struct platform_device scif1_device = { 55static struct platform_device scif1_device = {
50 .name = "sh-sci", 56 .name = "sh-sci",
51 .id = 1, 57 .id = 1,
58 .resource = scif1_resources,
59 .num_resources = ARRAY_SIZE(scif1_resources),
52 .dev = { 60 .dev = {
53 .platform_data = &scif1_platform_data, 61 .platform_data = &scif1_platform_data,
54 }, 62 },
55}; 63};
56 64
57static struct plat_sci_port scif2_platform_data = { 65static struct plat_sci_port scif2_platform_data = {
58 .mapbase = 0xffe10000,
59 .flags = UPF_BOOT_AUTOCONF, 66 .flags = UPF_BOOT_AUTOCONF,
60 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 67 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
61 .scbrr_algo_id = SCBRR_ALGO_2,
62 .type = PORT_SCIF, 68 .type = PORT_SCIF,
63 .irqs = SCIx_IRQ_MUXED(evt2irq(0xf00)),
64 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 69 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
65}; 70};
66 71
72static struct resource scif2_resources[] = {
73 DEFINE_RES_MEM(0xffe10000, 0x100),
74 DEFINE_RES_IRQ(evt2irq(0xf00)),
75};
76
67static struct platform_device scif2_device = { 77static struct platform_device scif2_device = {
68 .name = "sh-sci", 78 .name = "sh-sci",
69 .id = 2, 79 .id = 2,
80 .resource = scif2_resources,
81 .num_resources = ARRAY_SIZE(scif2_resources),
70 .dev = { 82 .dev = {
71 .platform_data = &scif2_platform_data, 83 .platform_data = &scif2_platform_data,
72 }, 84 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 256ea7a45164..e1ba8cb74e5a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -16,170 +16,210 @@
16#include <linux/io.h> 16#include <linux/io.h>
17 17
18static struct plat_sci_port scif0_platform_data = { 18static struct plat_sci_port scif0_platform_data = {
19 .mapbase = 0xff923000,
20 .flags = UPF_BOOT_AUTOCONF, 19 .flags = UPF_BOOT_AUTOCONF,
21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 20 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
22 .scbrr_algo_id = SCBRR_ALGO_2,
23 .type = PORT_SCIF, 21 .type = PORT_SCIF,
24 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)), 22};
23
24static struct resource scif0_resources[] = {
25 DEFINE_RES_MEM(0xff923000, 0x100),
26 DEFINE_RES_IRQ(evt2irq(0x9a0)),
25}; 27};
26 28
27static struct platform_device scif0_device = { 29static struct platform_device scif0_device = {
28 .name = "sh-sci", 30 .name = "sh-sci",
29 .id = 0, 31 .id = 0,
32 .resource = scif0_resources,
33 .num_resources = ARRAY_SIZE(scif0_resources),
30 .dev = { 34 .dev = {
31 .platform_data = &scif0_platform_data, 35 .platform_data = &scif0_platform_data,
32 }, 36 },
33}; 37};
34 38
35static struct plat_sci_port scif1_platform_data = { 39static struct plat_sci_port scif1_platform_data = {
36 .mapbase = 0xff924000,
37 .flags = UPF_BOOT_AUTOCONF, 40 .flags = UPF_BOOT_AUTOCONF,
38 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
39 .scbrr_algo_id = SCBRR_ALGO_2,
40 .type = PORT_SCIF, 42 .type = PORT_SCIF,
41 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)), 43};
44
45static struct resource scif1_resources[] = {
46 DEFINE_RES_MEM(0xff924000, 0x100),
47 DEFINE_RES_IRQ(evt2irq(0x9c0)),
42}; 48};
43 49
44static struct platform_device scif1_device = { 50static struct platform_device scif1_device = {
45 .name = "sh-sci", 51 .name = "sh-sci",
46 .id = 1, 52 .id = 1,
53 .resource = scif1_resources,
54 .num_resources = ARRAY_SIZE(scif1_resources),
47 .dev = { 55 .dev = {
48 .platform_data = &scif1_platform_data, 56 .platform_data = &scif1_platform_data,
49 }, 57 },
50}; 58};
51 59
52static struct plat_sci_port scif2_platform_data = { 60static struct plat_sci_port scif2_platform_data = {
53 .mapbase = 0xff925000,
54 .flags = UPF_BOOT_AUTOCONF, 61 .flags = UPF_BOOT_AUTOCONF,
55 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 62 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
56 .scbrr_algo_id = SCBRR_ALGO_2,
57 .type = PORT_SCIF, 63 .type = PORT_SCIF,
58 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)), 64};
65
66static struct resource scif2_resources[] = {
67 DEFINE_RES_MEM(0xff925000, 0x100),
68 DEFINE_RES_IRQ(evt2irq(0x9e0)),
59}; 69};
60 70
61static struct platform_device scif2_device = { 71static struct platform_device scif2_device = {
62 .name = "sh-sci", 72 .name = "sh-sci",
63 .id = 2, 73 .id = 2,
74 .resource = scif2_resources,
75 .num_resources = ARRAY_SIZE(scif2_resources),
64 .dev = { 76 .dev = {
65 .platform_data = &scif2_platform_data, 77 .platform_data = &scif2_platform_data,
66 }, 78 },
67}; 79};
68 80
69static struct plat_sci_port scif3_platform_data = { 81static struct plat_sci_port scif3_platform_data = {
70 .mapbase = 0xff926000,
71 .flags = UPF_BOOT_AUTOCONF, 82 .flags = UPF_BOOT_AUTOCONF,
72 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 83 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
73 .scbrr_algo_id = SCBRR_ALGO_2,
74 .type = PORT_SCIF, 84 .type = PORT_SCIF,
75 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa00)), 85};
86
87static struct resource scif3_resources[] = {
88 DEFINE_RES_MEM(0xff926000, 0x100),
89 DEFINE_RES_IRQ(evt2irq(0xa00)),
76}; 90};
77 91
78static struct platform_device scif3_device = { 92static struct platform_device scif3_device = {
79 .name = "sh-sci", 93 .name = "sh-sci",
80 .id = 3, 94 .id = 3,
95 .resource = scif3_resources,
96 .num_resources = ARRAY_SIZE(scif3_resources),
81 .dev = { 97 .dev = {
82 .platform_data = &scif3_platform_data, 98 .platform_data = &scif3_platform_data,
83 }, 99 },
84}; 100};
85 101
86static struct plat_sci_port scif4_platform_data = { 102static struct plat_sci_port scif4_platform_data = {
87 .mapbase = 0xff927000,
88 .flags = UPF_BOOT_AUTOCONF, 103 .flags = UPF_BOOT_AUTOCONF,
89 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 104 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
90 .scbrr_algo_id = SCBRR_ALGO_2,
91 .type = PORT_SCIF, 105 .type = PORT_SCIF,
92 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa20)), 106};
107
108static struct resource scif4_resources[] = {
109 DEFINE_RES_MEM(0xff927000, 0x100),
110 DEFINE_RES_IRQ(evt2irq(0xa20)),
93}; 111};
94 112
95static struct platform_device scif4_device = { 113static struct platform_device scif4_device = {
96 .name = "sh-sci", 114 .name = "sh-sci",
97 .id = 4, 115 .id = 4,
116 .resource = scif4_resources,
117 .num_resources = ARRAY_SIZE(scif4_resources),
98 .dev = { 118 .dev = {
99 .platform_data = &scif4_platform_data, 119 .platform_data = &scif4_platform_data,
100 }, 120 },
101}; 121};
102 122
103static struct plat_sci_port scif5_platform_data = { 123static struct plat_sci_port scif5_platform_data = {
104 .mapbase = 0xff928000,
105 .flags = UPF_BOOT_AUTOCONF, 124 .flags = UPF_BOOT_AUTOCONF,
106 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 125 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
107 .scbrr_algo_id = SCBRR_ALGO_2,
108 .type = PORT_SCIF, 126 .type = PORT_SCIF,
109 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa40)), 127};
128
129static struct resource scif5_resources[] = {
130 DEFINE_RES_MEM(0xff928000, 0x100),
131 DEFINE_RES_IRQ(evt2irq(0xa40)),
110}; 132};
111 133
112static struct platform_device scif5_device = { 134static struct platform_device scif5_device = {
113 .name = "sh-sci", 135 .name = "sh-sci",
114 .id = 5, 136 .id = 5,
137 .resource = scif5_resources,
138 .num_resources = ARRAY_SIZE(scif5_resources),
115 .dev = { 139 .dev = {
116 .platform_data = &scif5_platform_data, 140 .platform_data = &scif5_platform_data,
117 }, 141 },
118}; 142};
119 143
120static struct plat_sci_port scif6_platform_data = { 144static struct plat_sci_port scif6_platform_data = {
121 .mapbase = 0xff929000,
122 .flags = UPF_BOOT_AUTOCONF, 145 .flags = UPF_BOOT_AUTOCONF,
123 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 146 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
124 .scbrr_algo_id = SCBRR_ALGO_2,
125 .type = PORT_SCIF, 147 .type = PORT_SCIF,
126 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa60)), 148};
149
150static struct resource scif6_resources[] = {
151 DEFINE_RES_MEM(0xff929000, 0x100),
152 DEFINE_RES_IRQ(evt2irq(0xa60)),
127}; 153};
128 154
129static struct platform_device scif6_device = { 155static struct platform_device scif6_device = {
130 .name = "sh-sci", 156 .name = "sh-sci",
131 .id = 6, 157 .id = 6,
158 .resource = scif6_resources,
159 .num_resources = ARRAY_SIZE(scif6_resources),
132 .dev = { 160 .dev = {
133 .platform_data = &scif6_platform_data, 161 .platform_data = &scif6_platform_data,
134 }, 162 },
135}; 163};
136 164
137static struct plat_sci_port scif7_platform_data = { 165static struct plat_sci_port scif7_platform_data = {
138 .mapbase = 0xff92a000,
139 .flags = UPF_BOOT_AUTOCONF, 166 .flags = UPF_BOOT_AUTOCONF,
140 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 167 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
141 .scbrr_algo_id = SCBRR_ALGO_2,
142 .type = PORT_SCIF, 168 .type = PORT_SCIF,
143 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa80)), 169};
170
171static struct resource scif7_resources[] = {
172 DEFINE_RES_MEM(0xff92a000, 0x100),
173 DEFINE_RES_IRQ(evt2irq(0xa80)),
144}; 174};
145 175
146static struct platform_device scif7_device = { 176static struct platform_device scif7_device = {
147 .name = "sh-sci", 177 .name = "sh-sci",
148 .id = 7, 178 .id = 7,
179 .resource = scif7_resources,
180 .num_resources = ARRAY_SIZE(scif7_resources),
149 .dev = { 181 .dev = {
150 .platform_data = &scif7_platform_data, 182 .platform_data = &scif7_platform_data,
151 }, 183 },
152}; 184};
153 185
154static struct plat_sci_port scif8_platform_data = { 186static struct plat_sci_port scif8_platform_data = {
155 .mapbase = 0xff92b000,
156 .flags = UPF_BOOT_AUTOCONF, 187 .flags = UPF_BOOT_AUTOCONF,
157 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 188 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
158 .scbrr_algo_id = SCBRR_ALGO_2,
159 .type = PORT_SCIF, 189 .type = PORT_SCIF,
160 .irqs = SCIx_IRQ_MUXED(evt2irq(0xaa0)), 190};
191
192static struct resource scif8_resources[] = {
193 DEFINE_RES_MEM(0xff92b000, 0x100),
194 DEFINE_RES_IRQ(evt2irq(0xaa0)),
161}; 195};
162 196
163static struct platform_device scif8_device = { 197static struct platform_device scif8_device = {
164 .name = "sh-sci", 198 .name = "sh-sci",
165 .id = 8, 199 .id = 8,
200 .resource = scif8_resources,
201 .num_resources = ARRAY_SIZE(scif8_resources),
166 .dev = { 202 .dev = {
167 .platform_data = &scif8_platform_data, 203 .platform_data = &scif8_platform_data,
168 }, 204 },
169}; 205};
170 206
171static struct plat_sci_port scif9_platform_data = { 207static struct plat_sci_port scif9_platform_data = {
172 .mapbase = 0xff92c000,
173 .flags = UPF_BOOT_AUTOCONF, 208 .flags = UPF_BOOT_AUTOCONF,
174 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 209 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
175 .scbrr_algo_id = SCBRR_ALGO_2,
176 .type = PORT_SCIF, 210 .type = PORT_SCIF,
177 .irqs = SCIx_IRQ_MUXED(evt2irq(0xac0)), 211};
212
213static struct resource scif9_resources[] = {
214 DEFINE_RES_MEM(0xff92c000, 0x100),
215 DEFINE_RES_IRQ(evt2irq(0xac0)),
178}; 216};
179 217
180static struct platform_device scif9_device = { 218static struct platform_device scif9_device = {
181 .name = "sh-sci", 219 .name = "sh-sci",
182 .id = 9, 220 .id = 9,
221 .resource = scif9_resources,
222 .num_resources = ARRAY_SIZE(scif9_resources),
183 .dev = { 223 .dev = {
184 .platform_data = &scif9_platform_data, 224 .platform_data = &scif9_platform_data,
185 }, 225 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index de45b704687a..668e54bafa86 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -18,36 +18,44 @@
18#include <cpu/dma-register.h> 18#include <cpu/dma-register.h>
19 19
20static struct plat_sci_port scif0_platform_data = { 20static struct plat_sci_port scif0_platform_data = {
21 .mapbase = 0xffe00000,
22 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
24 .scbrr_algo_id = SCBRR_ALGO_1,
25 .type = PORT_SCIF, 23 .type = PORT_SCIF,
26 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
27 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 24 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
28}; 25};
29 26
27static struct resource scif0_resources[] = {
28 DEFINE_RES_MEM(0xffe00000, 0x100),
29 DEFINE_RES_IRQ(evt2irq(0x700)),
30};
31
30static struct platform_device scif0_device = { 32static struct platform_device scif0_device = {
31 .name = "sh-sci", 33 .name = "sh-sci",
32 .id = 0, 34 .id = 0,
35 .resource = scif0_resources,
36 .num_resources = ARRAY_SIZE(scif0_resources),
33 .dev = { 37 .dev = {
34 .platform_data = &scif0_platform_data, 38 .platform_data = &scif0_platform_data,
35 }, 39 },
36}; 40};
37 41
38static struct plat_sci_port scif1_platform_data = { 42static struct plat_sci_port scif1_platform_data = {
39 .mapbase = 0xffe10000,
40 .flags = UPF_BOOT_AUTOCONF, 43 .flags = UPF_BOOT_AUTOCONF,
41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 44 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
42 .scbrr_algo_id = SCBRR_ALGO_1,
43 .type = PORT_SCIF, 45 .type = PORT_SCIF,
44 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)),
45 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 46 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
46}; 47};
47 48
49static struct resource scif1_resources[] = {
50 DEFINE_RES_MEM(0xffe10000, 0x100),
51 DEFINE_RES_IRQ(evt2irq(0xb80)),
52};
53
48static struct platform_device scif1_device = { 54static struct platform_device scif1_device = {
49 .name = "sh-sci", 55 .name = "sh-sci",
50 .id = 1, 56 .id = 1,
57 .resource = scif1_resources,
58 .num_resources = ARRAY_SIZE(scif1_resources),
51 .dev = { 59 .dev = {
52 .platform_data = &scif1_platform_data, 60 .platform_data = &scif1_platform_data,
53 }, 61 },
@@ -409,9 +417,7 @@ void __init plat_early_device_setup(void)
409{ 417{
410 if (mach_is_sh2007()) { 418 if (mach_is_sh2007()) {
411 scif0_platform_data.scscr &= ~SCSCR_CKE1; 419 scif0_platform_data.scscr &= ~SCSCR_CKE1;
412 scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
413 scif1_platform_data.scscr &= ~SCSCR_CKE1; 420 scif1_platform_data.scscr &= ~SCSCR_CKE1;
414 scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
415 } 421 }
416 422
417 early_platform_add_devices(sh7780_early_devices, 423 early_platform_add_devices(sh7780_early_devices,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 0968ecb962e6..4aa679140209 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -20,108 +20,132 @@
20#include <cpu/dma-register.h> 20#include <cpu/dma-register.h>
21 21
22static struct plat_sci_port scif0_platform_data = { 22static struct plat_sci_port scif0_platform_data = {
23 .mapbase = 0xffea0000,
24 .flags = UPF_BOOT_AUTOCONF, 23 .flags = UPF_BOOT_AUTOCONF,
25 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
26 .scbrr_algo_id = SCBRR_ALGO_1,
27 .type = PORT_SCIF, 25 .type = PORT_SCIF,
28 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
29 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 26 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
30}; 27};
31 28
29static struct resource scif0_resources[] = {
30 DEFINE_RES_MEM(0xffea0000, 0x100),
31 DEFINE_RES_IRQ(evt2irq(0x700)),
32};
33
32static struct platform_device scif0_device = { 34static struct platform_device scif0_device = {
33 .name = "sh-sci", 35 .name = "sh-sci",
34 .id = 0, 36 .id = 0,
37 .resource = scif0_resources,
38 .num_resources = ARRAY_SIZE(scif0_resources),
35 .dev = { 39 .dev = {
36 .platform_data = &scif0_platform_data, 40 .platform_data = &scif0_platform_data,
37 }, 41 },
38}; 42};
39 43
40static struct plat_sci_port scif1_platform_data = { 44static struct plat_sci_port scif1_platform_data = {
41 .mapbase = 0xffeb0000,
42 .flags = UPF_BOOT_AUTOCONF, 45 .flags = UPF_BOOT_AUTOCONF,
43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 46 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
44 .scbrr_algo_id = SCBRR_ALGO_1,
45 .type = PORT_SCIF, 47 .type = PORT_SCIF,
46 .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)),
47 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 48 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
48}; 49};
49 50
51static struct resource scif1_resources[] = {
52 DEFINE_RES_MEM(0xffeb0000, 0x100),
53 DEFINE_RES_IRQ(evt2irq(0x780)),
54};
55
50static struct platform_device scif1_device = { 56static struct platform_device scif1_device = {
51 .name = "sh-sci", 57 .name = "sh-sci",
52 .id = 1, 58 .id = 1,
59 .resource = scif1_resources,
60 .num_resources = ARRAY_SIZE(scif1_resources),
53 .dev = { 61 .dev = {
54 .platform_data = &scif1_platform_data, 62 .platform_data = &scif1_platform_data,
55 }, 63 },
56}; 64};
57 65
58static struct plat_sci_port scif2_platform_data = { 66static struct plat_sci_port scif2_platform_data = {
59 .mapbase = 0xffec0000,
60 .flags = UPF_BOOT_AUTOCONF, 67 .flags = UPF_BOOT_AUTOCONF,
61 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 68 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
62 .scbrr_algo_id = SCBRR_ALGO_1,
63 .type = PORT_SCIF, 69 .type = PORT_SCIF,
64 .irqs = SCIx_IRQ_MUXED(evt2irq(0x980)),
65 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 70 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
66}; 71};
67 72
73static struct resource scif2_resources[] = {
74 DEFINE_RES_MEM(0xffec0000, 0x100),
75 DEFINE_RES_IRQ(evt2irq(0x980)),
76};
77
68static struct platform_device scif2_device = { 78static struct platform_device scif2_device = {
69 .name = "sh-sci", 79 .name = "sh-sci",
70 .id = 2, 80 .id = 2,
81 .resource = scif2_resources,
82 .num_resources = ARRAY_SIZE(scif2_resources),
71 .dev = { 83 .dev = {
72 .platform_data = &scif2_platform_data, 84 .platform_data = &scif2_platform_data,
73 }, 85 },
74}; 86};
75 87
76static struct plat_sci_port scif3_platform_data = { 88static struct plat_sci_port scif3_platform_data = {
77 .mapbase = 0xffed0000,
78 .flags = UPF_BOOT_AUTOCONF, 89 .flags = UPF_BOOT_AUTOCONF,
79 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 90 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
80 .scbrr_algo_id = SCBRR_ALGO_1,
81 .type = PORT_SCIF, 91 .type = PORT_SCIF,
82 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)),
83 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 92 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
84}; 93};
85 94
95static struct resource scif3_resources[] = {
96 DEFINE_RES_MEM(0xffed0000, 0x100),
97 DEFINE_RES_IRQ(evt2irq(0x9a0)),
98};
99
86static struct platform_device scif3_device = { 100static struct platform_device scif3_device = {
87 .name = "sh-sci", 101 .name = "sh-sci",
88 .id = 3, 102 .id = 3,
103 .resource = scif3_resources,
104 .num_resources = ARRAY_SIZE(scif3_resources),
89 .dev = { 105 .dev = {
90 .platform_data = &scif3_platform_data, 106 .platform_data = &scif3_platform_data,
91 }, 107 },
92}; 108};
93 109
94static struct plat_sci_port scif4_platform_data = { 110static struct plat_sci_port scif4_platform_data = {
95 .mapbase = 0xffee0000,
96 .flags = UPF_BOOT_AUTOCONF, 111 .flags = UPF_BOOT_AUTOCONF,
97 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 112 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
98 .scbrr_algo_id = SCBRR_ALGO_1,
99 .type = PORT_SCIF, 113 .type = PORT_SCIF,
100 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)),
101 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 114 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
102}; 115};
103 116
117static struct resource scif4_resources[] = {
118 DEFINE_RES_MEM(0xffee0000, 0x100),
119 DEFINE_RES_IRQ(evt2irq(0x9c0)),
120};
121
104static struct platform_device scif4_device = { 122static struct platform_device scif4_device = {
105 .name = "sh-sci", 123 .name = "sh-sci",
106 .id = 4, 124 .id = 4,
125 .resource = scif4_resources,
126 .num_resources = ARRAY_SIZE(scif4_resources),
107 .dev = { 127 .dev = {
108 .platform_data = &scif4_platform_data, 128 .platform_data = &scif4_platform_data,
109 }, 129 },
110}; 130};
111 131
112static struct plat_sci_port scif5_platform_data = { 132static struct plat_sci_port scif5_platform_data = {
113 .mapbase = 0xffef0000,
114 .flags = UPF_BOOT_AUTOCONF, 133 .flags = UPF_BOOT_AUTOCONF,
115 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 134 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
116 .scbrr_algo_id = SCBRR_ALGO_1,
117 .type = PORT_SCIF, 135 .type = PORT_SCIF,
118 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)),
119 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 136 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
120}; 137};
121 138
139static struct resource scif5_resources[] = {
140 DEFINE_RES_MEM(0xffef0000, 0x100),
141 DEFINE_RES_IRQ(evt2irq(0x9e0)),
142};
143
122static struct platform_device scif5_device = { 144static struct platform_device scif5_device = {
123 .name = "sh-sci", 145 .name = "sh-sci",
124 .id = 5, 146 .id = 5,
147 .resource = scif5_resources,
148 .num_resources = ARRAY_SIZE(scif5_resources),
125 .dev = { 149 .dev = {
126 .platform_data = &scif5_platform_data, 150 .platform_data = &scif5_platform_data,
127 }, 151 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index ab52d4d4484d..5d619a551a3b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -28,21 +28,25 @@
28#include <asm/mmzone.h> 28#include <asm/mmzone.h>
29 29
30static struct plat_sci_port scif0_platform_data = { 30static struct plat_sci_port scif0_platform_data = {
31 .mapbase = 0xffea0000,
32 .flags = UPF_BOOT_AUTOCONF, 31 .flags = UPF_BOOT_AUTOCONF,
33 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
34 .scbrr_algo_id = SCBRR_ALGO_1,
35 .type = PORT_SCIF, 33 .type = PORT_SCIF,
36 .irqs = { evt2irq(0x700),
37 evt2irq(0x720),
38 evt2irq(0x760),
39 evt2irq(0x740) },
40 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 34 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
41}; 35};
42 36
37static struct resource scif0_resources[] = {
38 DEFINE_RES_MEM(0xffea0000, 0x100),
39 DEFINE_RES_IRQ(evt2irq(0x700)),
40 DEFINE_RES_IRQ(evt2irq(0x720)),
41 DEFINE_RES_IRQ(evt2irq(0x760)),
42 DEFINE_RES_IRQ(evt2irq(0x740)),
43};
44
43static struct platform_device scif0_device = { 45static struct platform_device scif0_device = {
44 .name = "sh-sci", 46 .name = "sh-sci",
45 .id = 0, 47 .id = 0,
48 .resource = scif0_resources,
49 .num_resources = ARRAY_SIZE(scif0_resources),
46 .dev = { 50 .dev = {
47 .platform_data = &scif0_platform_data, 51 .platform_data = &scif0_platform_data,
48 }, 52 },
@@ -52,90 +56,119 @@ static struct platform_device scif0_device = {
52 * The rest of these all have multiplexed IRQs 56 * The rest of these all have multiplexed IRQs
53 */ 57 */
54static struct plat_sci_port scif1_platform_data = { 58static struct plat_sci_port scif1_platform_data = {
55 .mapbase = 0xffeb0000,
56 .flags = UPF_BOOT_AUTOCONF, 59 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 60 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
58 .scbrr_algo_id = SCBRR_ALGO_1,
59 .type = PORT_SCIF, 61 .type = PORT_SCIF,
60 .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)),
61 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 62 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
62}; 63};
63 64
65static struct resource scif1_resources[] = {
66 DEFINE_RES_MEM(0xffeb0000, 0x100),
67 DEFINE_RES_IRQ(evt2irq(0x780)),
68};
69
70static struct resource scif1_demux_resources[] = {
71 DEFINE_RES_MEM(0xffeb0000, 0x100),
72 /* Placeholders, see sh7786_devices_setup() */
73 DEFINE_RES_IRQ(0),
74 DEFINE_RES_IRQ(0),
75 DEFINE_RES_IRQ(0),
76 DEFINE_RES_IRQ(0),
77};
78
64static struct platform_device scif1_device = { 79static struct platform_device scif1_device = {
65 .name = "sh-sci", 80 .name = "sh-sci",
66 .id = 1, 81 .id = 1,
82 .resource = scif1_resources,
83 .num_resources = ARRAY_SIZE(scif1_resources),
67 .dev = { 84 .dev = {
68 .platform_data = &scif1_platform_data, 85 .platform_data = &scif1_platform_data,
69 }, 86 },
70}; 87};
71 88
72static struct plat_sci_port scif2_platform_data = { 89static struct plat_sci_port scif2_platform_data = {
73 .mapbase = 0xffec0000,
74 .flags = UPF_BOOT_AUTOCONF, 90 .flags = UPF_BOOT_AUTOCONF,
75 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 91 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
76 .scbrr_algo_id = SCBRR_ALGO_1,
77 .type = PORT_SCIF, 92 .type = PORT_SCIF,
78 .irqs = SCIx_IRQ_MUXED(evt2irq(0x840)),
79 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 93 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
80}; 94};
81 95
96static struct resource scif2_resources[] = {
97 DEFINE_RES_MEM(0xffec0000, 0x100),
98 DEFINE_RES_IRQ(evt2irq(0x840)),
99};
100
82static struct platform_device scif2_device = { 101static struct platform_device scif2_device = {
83 .name = "sh-sci", 102 .name = "sh-sci",
84 .id = 2, 103 .id = 2,
104 .resource = scif2_resources,
105 .num_resources = ARRAY_SIZE(scif2_resources),
85 .dev = { 106 .dev = {
86 .platform_data = &scif2_platform_data, 107 .platform_data = &scif2_platform_data,
87 }, 108 },
88}; 109};
89 110
90static struct plat_sci_port scif3_platform_data = { 111static struct plat_sci_port scif3_platform_data = {
91 .mapbase = 0xffed0000,
92 .flags = UPF_BOOT_AUTOCONF, 112 .flags = UPF_BOOT_AUTOCONF,
93 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 113 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
94 .scbrr_algo_id = SCBRR_ALGO_1,
95 .type = PORT_SCIF, 114 .type = PORT_SCIF,
96 .irqs = SCIx_IRQ_MUXED(evt2irq(0x860)),
97 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 115 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
98}; 116};
99 117
118static struct resource scif3_resources[] = {
119 DEFINE_RES_MEM(0xffed0000, 0x100),
120 DEFINE_RES_IRQ(evt2irq(0x860)),
121};
122
100static struct platform_device scif3_device = { 123static struct platform_device scif3_device = {
101 .name = "sh-sci", 124 .name = "sh-sci",
102 .id = 3, 125 .id = 3,
126 .resource = scif3_resources,
127 .num_resources = ARRAY_SIZE(scif3_resources),
103 .dev = { 128 .dev = {
104 .platform_data = &scif3_platform_data, 129 .platform_data = &scif3_platform_data,
105 }, 130 },
106}; 131};
107 132
108static struct plat_sci_port scif4_platform_data = { 133static struct plat_sci_port scif4_platform_data = {
109 .mapbase = 0xffee0000,
110 .flags = UPF_BOOT_AUTOCONF, 134 .flags = UPF_BOOT_AUTOCONF,
111 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 135 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
112 .scbrr_algo_id = SCBRR_ALGO_1,
113 .type = PORT_SCIF, 136 .type = PORT_SCIF,
114 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
115 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 137 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
116}; 138};
117 139
140static struct resource scif4_resources[] = {
141 DEFINE_RES_MEM(0xffee0000, 0x100),
142 DEFINE_RES_IRQ(evt2irq(0x880)),
143};
144
118static struct platform_device scif4_device = { 145static struct platform_device scif4_device = {
119 .name = "sh-sci", 146 .name = "sh-sci",
120 .id = 4, 147 .id = 4,
148 .resource = scif4_resources,
149 .num_resources = ARRAY_SIZE(scif4_resources),
121 .dev = { 150 .dev = {
122 .platform_data = &scif4_platform_data, 151 .platform_data = &scif4_platform_data,
123 }, 152 },
124}; 153};
125 154
126static struct plat_sci_port scif5_platform_data = { 155static struct plat_sci_port scif5_platform_data = {
127 .mapbase = 0xffef0000,
128 .flags = UPF_BOOT_AUTOCONF, 156 .flags = UPF_BOOT_AUTOCONF,
129 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 157 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
130 .scbrr_algo_id = SCBRR_ALGO_1,
131 .type = PORT_SCIF, 158 .type = PORT_SCIF,
132 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8a0)),
133 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 159 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
134}; 160};
135 161
162static struct resource scif5_resources[] = {
163 DEFINE_RES_MEM(0xffef0000, 0x100),
164 DEFINE_RES_IRQ(evt2irq(0x8a0)),
165};
166
136static struct platform_device scif5_device = { 167static struct platform_device scif5_device = {
137 .name = "sh-sci", 168 .name = "sh-sci",
138 .id = 5, 169 .id = 5,
170 .resource = scif5_resources,
171 .num_resources = ARRAY_SIZE(scif5_resources),
139 .dev = { 172 .dev = {
140 .platform_data = &scif5_platform_data, 173 .platform_data = &scif5_platform_data,
141 }, 174 },
@@ -1037,13 +1070,16 @@ static int __init sh7786_devices_setup(void)
1037 */ 1070 */
1038 irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1); 1071 irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
1039 if (irq > 0) { 1072 if (irq > 0) {
1040 scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq; 1073 scif1_demux_resources[1].start =
1041 scif1_platform_data.irqs[SCIx_ERI_IRQ] =
1042 intc_irq_lookup(sh7786_intc_desc.name, ERI1); 1074 intc_irq_lookup(sh7786_intc_desc.name, ERI1);
1043 scif1_platform_data.irqs[SCIx_BRI_IRQ] = 1075 scif1_demux_resources[2].start =
1044 intc_irq_lookup(sh7786_intc_desc.name, BRI1);
1045 scif1_platform_data.irqs[SCIx_RXI_IRQ] =
1046 intc_irq_lookup(sh7786_intc_desc.name, RXI1); 1076 intc_irq_lookup(sh7786_intc_desc.name, RXI1);
1077 scif1_demux_resources[3].start = irq;
1078 scif1_demux_resources[4].start =
1079 intc_irq_lookup(sh7786_intc_desc.name, BRI1);
1080
1081 scif1_device.resource = scif1_demux_resources;
1082 scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources);
1047 } 1083 }
1048 1084
1049 ret = platform_add_devices(sh7786_early_devices, 1085 ret = platform_add_devices(sh7786_early_devices,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 688f7ed1bab1..0856bcbb1da0 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -28,60 +28,72 @@
28 * all rather than adding infrastructure to hack around it. 28 * all rather than adding infrastructure to hack around it.
29 */ 29 */
30static struct plat_sci_port scif0_platform_data = { 30static struct plat_sci_port scif0_platform_data = {
31 .mapbase = 0xffc30000,
32 .flags = UPF_BOOT_AUTOCONF, 31 .flags = UPF_BOOT_AUTOCONF,
33 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
34 .scbrr_algo_id = SCBRR_ALGO_2,
35 .type = PORT_SCIF, 33 .type = PORT_SCIF,
36 .irqs = { evt2irq(0x700), 34};
37 evt2irq(0x720), 35
38 evt2irq(0x760), 36static struct resource scif0_resources[] = {
39 evt2irq(0x740) }, 37 DEFINE_RES_MEM(0xffc30000, 0x100),
38 DEFINE_RES_IRQ(evt2irq(0x700)),
39 DEFINE_RES_IRQ(evt2irq(0x720)),
40 DEFINE_RES_IRQ(evt2irq(0x760)),
41 DEFINE_RES_IRQ(evt2irq(0x740)),
40}; 42};
41 43
42static struct platform_device scif0_device = { 44static struct platform_device scif0_device = {
43 .name = "sh-sci", 45 .name = "sh-sci",
44 .id = 0, 46 .id = 0,
47 .resource = scif0_resources,
48 .num_resources = ARRAY_SIZE(scif0_resources),
45 .dev = { 49 .dev = {
46 .platform_data = &scif0_platform_data, 50 .platform_data = &scif0_platform_data,
47 }, 51 },
48}; 52};
49 53
50static struct plat_sci_port scif1_platform_data = { 54static struct plat_sci_port scif1_platform_data = {
51 .mapbase = 0xffc40000,
52 .flags = UPF_BOOT_AUTOCONF, 55 .flags = UPF_BOOT_AUTOCONF,
53 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 56 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
54 .scbrr_algo_id = SCBRR_ALGO_2,
55 .type = PORT_SCIF, 57 .type = PORT_SCIF,
56 .irqs = { evt2irq(0x780), 58};
57 evt2irq(0x7a0), 59
58 evt2irq(0x7e0), 60static struct resource scif1_resources[] = {
59 evt2irq(0x7c0) }, 61 DEFINE_RES_MEM(0xffc40000, 0x100),
62 DEFINE_RES_IRQ(evt2irq(0x780)),
63 DEFINE_RES_IRQ(evt2irq(0x7a0)),
64 DEFINE_RES_IRQ(evt2irq(0x7e0)),
65 DEFINE_RES_IRQ(evt2irq(0x7c0)),
60}; 66};
61 67
62static struct platform_device scif1_device = { 68static struct platform_device scif1_device = {
63 .name = "sh-sci", 69 .name = "sh-sci",
64 .id = 1, 70 .id = 1,
71 .resource = scif1_resources,
72 .num_resources = ARRAY_SIZE(scif1_resources),
65 .dev = { 73 .dev = {
66 .platform_data = &scif1_platform_data, 74 .platform_data = &scif1_platform_data,
67 }, 75 },
68}; 76};
69 77
70static struct plat_sci_port scif2_platform_data = { 78static struct plat_sci_port scif2_platform_data = {
71 .mapbase = 0xffc60000,
72 .flags = UPF_BOOT_AUTOCONF, 79 .flags = UPF_BOOT_AUTOCONF,
73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 80 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
74 .scbrr_algo_id = SCBRR_ALGO_2,
75 .type = PORT_SCIF, 81 .type = PORT_SCIF,
76 .irqs = { evt2irq(0x880), 82};
77 evt2irq(0x8a0), 83
78 evt2irq(0x8e0), 84static struct resource scif2_resources[] = {
79 evt2irq(0x8c0) }, 85 DEFINE_RES_MEM(0xffc60000, 0x100),
86 DEFINE_RES_IRQ(evt2irq(0x880)),
87 DEFINE_RES_IRQ(evt2irq(0x8a0)),
88 DEFINE_RES_IRQ(evt2irq(0x8e0)),
89 DEFINE_RES_IRQ(evt2irq(0x8c0)),
80}; 90};
81 91
82static struct platform_device scif2_device = { 92static struct platform_device scif2_device = {
83 .name = "sh-sci", 93 .name = "sh-sci",
84 .id = 2, 94 .id = 2,
95 .resource = scif2_resources,
96 .num_resources = ARRAY_SIZE(scif2_resources),
85 .dev = { 97 .dev = {
86 .platform_data = &scif2_platform_data, 98 .platform_data = &scif2_platform_data,
87 }, 99 },
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
index 18419f1de963..14d68213d16b 100644
--- a/arch/sh/kernel/cpu/sh5/setup-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -17,17 +17,23 @@
17#include <asm/addrspace.h> 17#include <asm/addrspace.h>
18 18
19static struct plat_sci_port scif0_platform_data = { 19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000,
21 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 20 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF, 22 .type = PORT_SCIF,
25 .irqs = { 39, 40, 42, 0 }, 23};
24
25static struct resource scif0_resources[] = {
26 DEFINE_RES_MEM(PHYS_PERIPHERAL_BLOCK + 0x01030000, 0x100),
27 DEFINE_RES_IRQ(39),
28 DEFINE_RES_IRQ(40),
29 DEFINE_RES_IRQ(42),
26}; 30};
27 31
28static struct platform_device scif0_device = { 32static struct platform_device scif0_device = {
29 .name = "sh-sci", 33 .name = "sh-sci",
30 .id = 0, 34 .id = 0,
35 .resource = scif0_resources,
36 .num_resources = ARRAY_SIZE(scif0_resources),
31 .dev = { 37 .dev = {
32 .platform_data = &scif0_platform_data, 38 .platform_data = &scif0_platform_data,
33 }, 39 },
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 2394e9753ef5..725c46162bbd 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -588,12 +588,6 @@ static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
588 .show_cpu_target = mvebu_sdram_debug_show_orion, 588 .show_cpu_target = mvebu_sdram_debug_show_orion,
589}; 589};
590 590
591/*
592 * The driver doesn't yet have a DT binding because the details of
593 * this DT binding still need to be sorted out. However, as a
594 * preparation, we already use of_device_id to match a SoC description
595 * string against the SoC specific details of this driver.
596 */
597static const struct of_device_id of_mvebu_mbus_ids[] = { 591static const struct of_device_id of_mvebu_mbus_ids[] = {
598 { .compatible = "marvell,armada370-mbus", 592 { .compatible = "marvell,armada370-mbus",
599 .data = &armada_370_xp_mbus_data, }, 593 .data = &armada_370_xp_mbus_data, },
@@ -734,11 +728,11 @@ int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
734{ 728{
735 const struct of_device_id *of_id; 729 const struct of_device_id *of_id;
736 730
737 for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++) 731 for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
738 if (!strcmp(of_id->compatible, soc)) 732 if (!strcmp(of_id->compatible, soc))
739 break; 733 break;
740 734
741 if (!of_id->compatible) { 735 if (!of_id->compatible[0]) {
742 pr_err("could not find a matching SoC family\n"); 736 pr_err("could not find a matching SoC family\n");
743 return -ENODEV; 737 return -ENODEV;
744 } 738 }
diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c
index f5e4c21b301f..8cbfcf88fae3 100644
--- a/drivers/clk/versatile/clk-icst.c
+++ b/drivers/clk/versatile/clk-icst.c
@@ -119,6 +119,7 @@ static const struct clk_ops icst_ops = {
119 119
120struct clk *icst_clk_register(struct device *dev, 120struct clk *icst_clk_register(struct device *dev,
121 const struct clk_icst_desc *desc, 121 const struct clk_icst_desc *desc,
122 const char *name,
122 void __iomem *base) 123 void __iomem *base)
123{ 124{
124 struct clk *clk; 125 struct clk *clk;
@@ -130,7 +131,7 @@ struct clk *icst_clk_register(struct device *dev,
130 pr_err("could not allocate ICST clock!\n"); 131 pr_err("could not allocate ICST clock!\n");
131 return ERR_PTR(-ENOMEM); 132 return ERR_PTR(-ENOMEM);
132 } 133 }
133 init.name = "icst"; 134 init.name = name;
134 init.ops = &icst_ops; 135 init.ops = &icst_ops;
135 init.flags = CLK_IS_ROOT; 136 init.flags = CLK_IS_ROOT;
136 init.parent_names = NULL; 137 init.parent_names = NULL;
diff --git a/drivers/clk/versatile/clk-icst.h b/drivers/clk/versatile/clk-icst.h
index dad51b6ffd00..be99dd0da785 100644
--- a/drivers/clk/versatile/clk-icst.h
+++ b/drivers/clk/versatile/clk-icst.h
@@ -15,4 +15,5 @@ struct clk_icst_desc {
15 15
16struct clk *icst_clk_register(struct device *dev, 16struct clk *icst_clk_register(struct device *dev,
17 const struct clk_icst_desc *desc, 17 const struct clk_icst_desc *desc,
18 const char *name,
18 void __iomem *base); 19 void __iomem *base);
diff --git a/drivers/clk/versatile/clk-impd1.c b/drivers/clk/versatile/clk-impd1.c
index 369139af2a3b..844f8d711a12 100644
--- a/drivers/clk/versatile/clk-impd1.c
+++ b/drivers/clk/versatile/clk-impd1.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * Clock driver for the ARM Integrator/IM-PD1 board 2 * Clock driver for the ARM Integrator/IM-PD1 board
3 * Copyright (C) 2012 Linus Walleij 3 * Copyright (C) 2012-2013 Linus Walleij
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as 6 * it under the terms of the GNU General Public License version 2 as
@@ -18,20 +18,28 @@
18#include "clk-icst.h" 18#include "clk-icst.h"
19 19
20struct impd1_clk { 20struct impd1_clk {
21 struct clk *vcoclk; 21 char *vco1name;
22 struct clk *vco1clk;
23 char *vco2name;
24 struct clk *vco2clk;
25 struct clk *mmciclk;
26 char *uartname;
22 struct clk *uartclk; 27 struct clk *uartclk;
23 struct clk_lookup *clks[3]; 28 char *spiname;
29 struct clk *spiclk;
30 char *scname;
31 struct clk *scclk;
32 struct clk_lookup *clks[6];
24}; 33};
25 34
35/* One entry for each connected IM-PD1 LM */
26static struct impd1_clk impd1_clks[4]; 36static struct impd1_clk impd1_clks[4];
27 37
28/* 38/*
29 * There are two VCO's on the IM-PD1 but only one is used by the 39 * There are two VCO's on the IM-PD1
30 * kernel, that is why we are only implementing the control of
31 * IMPD1_OSC1 here.
32 */ 40 */
33 41
34static const struct icst_params impd1_vco_params = { 42static const struct icst_params impd1_vco1_params = {
35 .ref = 24000000, /* 24 MHz */ 43 .ref = 24000000, /* 24 MHz */
36 .vco_max = ICST525_VCO_MAX_3V, 44 .vco_max = ICST525_VCO_MAX_3V,
37 .vco_min = ICST525_VCO_MIN, 45 .vco_min = ICST525_VCO_MIN,
@@ -44,11 +52,29 @@ static const struct icst_params impd1_vco_params = {
44}; 52};
45 53
46static const struct clk_icst_desc impd1_icst1_desc = { 54static const struct clk_icst_desc impd1_icst1_desc = {
47 .params = &impd1_vco_params, 55 .params = &impd1_vco1_params,
48 .vco_offset = IMPD1_OSC1, 56 .vco_offset = IMPD1_OSC1,
49 .lock_offset = IMPD1_LOCK, 57 .lock_offset = IMPD1_LOCK,
50}; 58};
51 59
60static const struct icst_params impd1_vco2_params = {
61 .ref = 24000000, /* 24 MHz */
62 .vco_max = ICST525_VCO_MAX_3V,
63 .vco_min = ICST525_VCO_MIN,
64 .vd_min = 12,
65 .vd_max = 519,
66 .rd_min = 3,
67 .rd_max = 120,
68 .s2div = icst525_s2div,
69 .idx2s = icst525_idx2s,
70};
71
72static const struct clk_icst_desc impd1_icst2_desc = {
73 .params = &impd1_vco2_params,
74 .vco_offset = IMPD1_OSC2,
75 .lock_offset = IMPD1_LOCK,
76};
77
52/** 78/**
53 * integrator_impd1_clk_init() - set up the integrator clock tree 79 * integrator_impd1_clk_init() - set up the integrator clock tree
54 * @base: base address of the logic module (LM) 80 * @base: base address of the logic module (LM)
@@ -66,16 +92,39 @@ void integrator_impd1_clk_init(void __iomem *base, unsigned int id)
66 } 92 }
67 imc = &impd1_clks[id]; 93 imc = &impd1_clks[id];
68 94
69 clk = icst_clk_register(NULL, &impd1_icst1_desc, base); 95 imc->vco1name = kasprintf(GFP_KERNEL, "lm%x-vco1", id);
70 imc->vcoclk = clk; 96 clk = icst_clk_register(NULL, &impd1_icst1_desc, imc->vco1name, base);
97 imc->vco1clk = clk;
71 imc->clks[0] = clkdev_alloc(clk, NULL, "lm%x:01000", id); 98 imc->clks[0] = clkdev_alloc(clk, NULL, "lm%x:01000", id);
72 99
73 /* UART reference clock */ 100 /* VCO2 is also called "CLK2" */
74 clk = clk_register_fixed_rate(NULL, "uartclk", NULL, CLK_IS_ROOT, 101 imc->vco2name = kasprintf(GFP_KERNEL, "lm%x-vco2", id);
75 14745600); 102 clk = icst_clk_register(NULL, &impd1_icst2_desc, imc->vco2name, base);
103 imc->vco2clk = clk;
104
105 /* MMCI uses CLK2 right off */
106 imc->clks[1] = clkdev_alloc(clk, NULL, "lm%x:00700", id);
107
108 /* UART reference clock divides CLK2 by a fixed factor 4 */
109 imc->uartname = kasprintf(GFP_KERNEL, "lm%x-uartclk", id);
110 clk = clk_register_fixed_factor(NULL, imc->uartname, imc->vco2name,
111 CLK_IGNORE_UNUSED, 1, 4);
76 imc->uartclk = clk; 112 imc->uartclk = clk;
77 imc->clks[1] = clkdev_alloc(clk, NULL, "lm%x:00100", id); 113 imc->clks[2] = clkdev_alloc(clk, NULL, "lm%x:00100", id);
78 imc->clks[2] = clkdev_alloc(clk, NULL, "lm%x:00200", id); 114 imc->clks[3] = clkdev_alloc(clk, NULL, "lm%x:00200", id);
115
116 /* SPI PL022 clock divides CLK2 by a fixed factor 64 */
117 imc->spiname = kasprintf(GFP_KERNEL, "lm%x-spiclk", id);
118 clk = clk_register_fixed_factor(NULL, imc->spiname, imc->vco2name,
119 CLK_IGNORE_UNUSED, 1, 64);
120 imc->clks[4] = clkdev_alloc(clk, NULL, "lm%x:00300", id);
121
122 /* Smart Card clock divides CLK2 by a fixed factor 4 */
123 imc->scname = kasprintf(GFP_KERNEL, "lm%x-scclk", id);
124 clk = clk_register_fixed_factor(NULL, imc->scname, imc->vco2name,
125 CLK_IGNORE_UNUSED, 1, 4);
126 imc->scclk = clk;
127 imc->clks[5] = clkdev_alloc(clk, NULL, "lm%x:00600", id);
79 128
80 for (i = 0; i < ARRAY_SIZE(imc->clks); i++) 129 for (i = 0; i < ARRAY_SIZE(imc->clks); i++)
81 clkdev_add(imc->clks[i]); 130 clkdev_add(imc->clks[i]);
@@ -92,6 +141,13 @@ void integrator_impd1_clk_exit(unsigned int id)
92 141
93 for (i = 0; i < ARRAY_SIZE(imc->clks); i++) 142 for (i = 0; i < ARRAY_SIZE(imc->clks); i++)
94 clkdev_drop(imc->clks[i]); 143 clkdev_drop(imc->clks[i]);
144 clk_unregister(imc->spiclk);
95 clk_unregister(imc->uartclk); 145 clk_unregister(imc->uartclk);
96 clk_unregister(imc->vcoclk); 146 clk_unregister(imc->vco2clk);
147 clk_unregister(imc->vco1clk);
148 kfree(imc->scname);
149 kfree(imc->spiname);
150 kfree(imc->uartname);
151 kfree(imc->vco2name);
152 kfree(imc->vco1name);
97} 153}
diff --git a/drivers/clk/versatile/clk-integrator.c b/drivers/clk/versatile/clk-integrator.c
index 08593b4ee2c9..bda8967e09c2 100644
--- a/drivers/clk/versatile/clk-integrator.c
+++ b/drivers/clk/versatile/clk-integrator.c
@@ -78,7 +78,7 @@ void __init integrator_clk_init(bool is_cp)
78 clk_register_clkdev(clk, NULL, "sp804"); 78 clk_register_clkdev(clk, NULL, "sp804");
79 79
80 /* ICST VCO clock used on the Integrator/CP CLCD */ 80 /* ICST VCO clock used on the Integrator/CP CLCD */
81 clk = icst_clk_register(NULL, &cp_icst_desc, 81 clk = icst_clk_register(NULL, &cp_icst_desc, "icst",
82 __io_address(INTEGRATOR_HDR_BASE)); 82 __io_address(INTEGRATOR_HDR_BASE));
83 clk_register_clkdev(clk, NULL, "clcd"); 83 clk_register_clkdev(clk, NULL, "clcd");
84} 84}
diff --git a/drivers/clk/versatile/clk-realview.c b/drivers/clk/versatile/clk-realview.c
index cda07e70a408..747e7b31117c 100644
--- a/drivers/clk/versatile/clk-realview.c
+++ b/drivers/clk/versatile/clk-realview.c
@@ -84,9 +84,11 @@ void __init realview_clk_init(void __iomem *sysbase, bool is_pb1176)
84 84
85 /* ICST VCO clock */ 85 /* ICST VCO clock */
86 if (is_pb1176) 86 if (is_pb1176)
87 clk = icst_clk_register(NULL, &realview_osc0_desc, sysbase); 87 clk = icst_clk_register(NULL, &realview_osc0_desc,
88 "osc0", sysbase);
88 else 89 else
89 clk = icst_clk_register(NULL, &realview_osc4_desc, sysbase); 90 clk = icst_clk_register(NULL, &realview_osc4_desc,
91 "osc4", sysbase);
90 92
91 clk_register_clkdev(clk, NULL, "dev:clcd"); 93 clk_register_clkdev(clk, NULL, "dev:clcd");
92 clk_register_clkdev(clk, NULL, "issp:clcd"); 94 clk_register_clkdev(clk, NULL, "issp:clcd");
diff --git a/drivers/crypto/atmel-aes.c b/drivers/crypto/atmel-aes.c
index c1efd910d97b..d7c9e317423c 100644
--- a/drivers/crypto/atmel-aes.c
+++ b/drivers/crypto/atmel-aes.c
@@ -30,6 +30,7 @@
30#include <linux/irq.h> 30#include <linux/irq.h>
31#include <linux/scatterlist.h> 31#include <linux/scatterlist.h>
32#include <linux/dma-mapping.h> 32#include <linux/dma-mapping.h>
33#include <linux/of_device.h>
33#include <linux/delay.h> 34#include <linux/delay.h>
34#include <linux/crypto.h> 35#include <linux/crypto.h>
35#include <linux/cryptohash.h> 36#include <linux/cryptohash.h>
@@ -39,6 +40,7 @@
39#include <crypto/hash.h> 40#include <crypto/hash.h>
40#include <crypto/internal/hash.h> 41#include <crypto/internal/hash.h>
41#include <linux/platform_data/crypto-atmel.h> 42#include <linux/platform_data/crypto-atmel.h>
43#include <dt-bindings/dma/at91.h>
42#include "atmel-aes-regs.h" 44#include "atmel-aes-regs.h"
43 45
44#define CFB8_BLOCK_SIZE 1 46#define CFB8_BLOCK_SIZE 1
@@ -747,59 +749,50 @@ static int atmel_aes_dma_init(struct atmel_aes_dev *dd,
747 struct crypto_platform_data *pdata) 749 struct crypto_platform_data *pdata)
748{ 750{
749 int err = -ENOMEM; 751 int err = -ENOMEM;
750 dma_cap_mask_t mask_in, mask_out; 752 dma_cap_mask_t mask;
753
754 dma_cap_zero(mask);
755 dma_cap_set(DMA_SLAVE, mask);
756
757 /* Try to grab 2 DMA channels */
758 dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask,
759 atmel_aes_filter, &pdata->dma_slave->rxdata, dd->dev, "tx");
760 if (!dd->dma_lch_in.chan)
761 goto err_dma_in;
762
763 dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV;
764 dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
765 AES_IDATAR(0);
766 dd->dma_lch_in.dma_conf.src_maxburst = dd->caps.max_burst_size;
767 dd->dma_lch_in.dma_conf.src_addr_width =
768 DMA_SLAVE_BUSWIDTH_4_BYTES;
769 dd->dma_lch_in.dma_conf.dst_maxburst = dd->caps.max_burst_size;
770 dd->dma_lch_in.dma_conf.dst_addr_width =
771 DMA_SLAVE_BUSWIDTH_4_BYTES;
772 dd->dma_lch_in.dma_conf.device_fc = false;
773
774 dd->dma_lch_out.chan = dma_request_slave_channel_compat(mask,
775 atmel_aes_filter, &pdata->dma_slave->txdata, dd->dev, "rx");
776 if (!dd->dma_lch_out.chan)
777 goto err_dma_out;
778
779 dd->dma_lch_out.dma_conf.direction = DMA_DEV_TO_MEM;
780 dd->dma_lch_out.dma_conf.src_addr = dd->phys_base +
781 AES_ODATAR(0);
782 dd->dma_lch_out.dma_conf.src_maxburst = dd->caps.max_burst_size;
783 dd->dma_lch_out.dma_conf.src_addr_width =
784 DMA_SLAVE_BUSWIDTH_4_BYTES;
785 dd->dma_lch_out.dma_conf.dst_maxburst = dd->caps.max_burst_size;
786 dd->dma_lch_out.dma_conf.dst_addr_width =
787 DMA_SLAVE_BUSWIDTH_4_BYTES;
788 dd->dma_lch_out.dma_conf.device_fc = false;
751 789
752 if (pdata && pdata->dma_slave->txdata.dma_dev && 790 return 0;
753 pdata->dma_slave->rxdata.dma_dev) {
754
755 /* Try to grab 2 DMA channels */
756 dma_cap_zero(mask_in);
757 dma_cap_set(DMA_SLAVE, mask_in);
758
759 dd->dma_lch_in.chan = dma_request_channel(mask_in,
760 atmel_aes_filter, &pdata->dma_slave->rxdata);
761
762 if (!dd->dma_lch_in.chan)
763 goto err_dma_in;
764
765 dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV;
766 dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
767 AES_IDATAR(0);
768 dd->dma_lch_in.dma_conf.src_maxburst = dd->caps.max_burst_size;
769 dd->dma_lch_in.dma_conf.src_addr_width =
770 DMA_SLAVE_BUSWIDTH_4_BYTES;
771 dd->dma_lch_in.dma_conf.dst_maxburst = dd->caps.max_burst_size;
772 dd->dma_lch_in.dma_conf.dst_addr_width =
773 DMA_SLAVE_BUSWIDTH_4_BYTES;
774 dd->dma_lch_in.dma_conf.device_fc = false;
775
776 dma_cap_zero(mask_out);
777 dma_cap_set(DMA_SLAVE, mask_out);
778 dd->dma_lch_out.chan = dma_request_channel(mask_out,
779 atmel_aes_filter, &pdata->dma_slave->txdata);
780
781 if (!dd->dma_lch_out.chan)
782 goto err_dma_out;
783
784 dd->dma_lch_out.dma_conf.direction = DMA_DEV_TO_MEM;
785 dd->dma_lch_out.dma_conf.src_addr = dd->phys_base +
786 AES_ODATAR(0);
787 dd->dma_lch_out.dma_conf.src_maxburst = dd->caps.max_burst_size;
788 dd->dma_lch_out.dma_conf.src_addr_width =
789 DMA_SLAVE_BUSWIDTH_4_BYTES;
790 dd->dma_lch_out.dma_conf.dst_maxburst = dd->caps.max_burst_size;
791 dd->dma_lch_out.dma_conf.dst_addr_width =
792 DMA_SLAVE_BUSWIDTH_4_BYTES;
793 dd->dma_lch_out.dma_conf.device_fc = false;
794
795 return 0;
796 } else {
797 return -ENODEV;
798 }
799 791
800err_dma_out: 792err_dma_out:
801 dma_release_channel(dd->dma_lch_in.chan); 793 dma_release_channel(dd->dma_lch_in.chan);
802err_dma_in: 794err_dma_in:
795 dev_warn(dd->dev, "no DMA channel available\n");
803 return err; 796 return err;
804} 797}
805 798
@@ -1261,6 +1254,47 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
1261 } 1254 }
1262} 1255}
1263 1256
1257#if defined(CONFIG_OF)
1258static const struct of_device_id atmel_aes_dt_ids[] = {
1259 { .compatible = "atmel,at91sam9g46-aes" },
1260 { /* sentinel */ }
1261};
1262MODULE_DEVICE_TABLE(of, atmel_aes_dt_ids);
1263
1264static struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
1265{
1266 struct device_node *np = pdev->dev.of_node;
1267 struct crypto_platform_data *pdata;
1268
1269 if (!np) {
1270 dev_err(&pdev->dev, "device node not found\n");
1271 return ERR_PTR(-EINVAL);
1272 }
1273
1274 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1275 if (!pdata) {
1276 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
1277 return ERR_PTR(-ENOMEM);
1278 }
1279
1280 pdata->dma_slave = devm_kzalloc(&pdev->dev,
1281 sizeof(*(pdata->dma_slave)),
1282 GFP_KERNEL);
1283 if (!pdata->dma_slave) {
1284 dev_err(&pdev->dev, "could not allocate memory for dma_slave\n");
1285 devm_kfree(&pdev->dev, pdata);
1286 return ERR_PTR(-ENOMEM);
1287 }
1288
1289 return pdata;
1290}
1291#else
1292static inline struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
1293{
1294 return ERR_PTR(-EINVAL);
1295}
1296#endif
1297
1264static int atmel_aes_probe(struct platform_device *pdev) 1298static int atmel_aes_probe(struct platform_device *pdev)
1265{ 1299{
1266 struct atmel_aes_dev *aes_dd; 1300 struct atmel_aes_dev *aes_dd;
@@ -1272,6 +1306,14 @@ static int atmel_aes_probe(struct platform_device *pdev)
1272 1306
1273 pdata = pdev->dev.platform_data; 1307 pdata = pdev->dev.platform_data;
1274 if (!pdata) { 1308 if (!pdata) {
1309 pdata = atmel_aes_of_init(pdev);
1310 if (IS_ERR(pdata)) {
1311 err = PTR_ERR(pdata);
1312 goto aes_dd_err;
1313 }
1314 }
1315
1316 if (!pdata->dma_slave) {
1275 err = -ENXIO; 1317 err = -ENXIO;
1276 goto aes_dd_err; 1318 goto aes_dd_err;
1277 } 1319 }
@@ -1358,7 +1400,9 @@ static int atmel_aes_probe(struct platform_device *pdev)
1358 if (err) 1400 if (err)
1359 goto err_algs; 1401 goto err_algs;
1360 1402
1361 dev_info(dev, "Atmel AES\n"); 1403 dev_info(dev, "Atmel AES - Using %s, %s for DMA transfers\n",
1404 dma_chan_name(aes_dd->dma_lch_in.chan),
1405 dma_chan_name(aes_dd->dma_lch_out.chan));
1362 1406
1363 return 0; 1407 return 0;
1364 1408
@@ -1424,6 +1468,7 @@ static struct platform_driver atmel_aes_driver = {
1424 .driver = { 1468 .driver = {
1425 .name = "atmel_aes", 1469 .name = "atmel_aes",
1426 .owner = THIS_MODULE, 1470 .owner = THIS_MODULE,
1471 .of_match_table = of_match_ptr(atmel_aes_dt_ids),
1427 }, 1472 },
1428}; 1473};
1429 1474
diff --git a/drivers/crypto/atmel-sha.c b/drivers/crypto/atmel-sha.c
index eaed8bf183bc..0618be06b9fb 100644
--- a/drivers/crypto/atmel-sha.c
+++ b/drivers/crypto/atmel-sha.c
@@ -30,6 +30,7 @@
30#include <linux/irq.h> 30#include <linux/irq.h>
31#include <linux/scatterlist.h> 31#include <linux/scatterlist.h>
32#include <linux/dma-mapping.h> 32#include <linux/dma-mapping.h>
33#include <linux/of_device.h>
33#include <linux/delay.h> 34#include <linux/delay.h>
34#include <linux/crypto.h> 35#include <linux/crypto.h>
35#include <linux/cryptohash.h> 36#include <linux/cryptohash.h>
@@ -1263,32 +1264,29 @@ static int atmel_sha_dma_init(struct atmel_sha_dev *dd,
1263 int err = -ENOMEM; 1264 int err = -ENOMEM;
1264 dma_cap_mask_t mask_in; 1265 dma_cap_mask_t mask_in;
1265 1266
1266 if (pdata && pdata->dma_slave->rxdata.dma_dev) { 1267 /* Try to grab DMA channel */
1267 /* Try to grab DMA channel */ 1268 dma_cap_zero(mask_in);
1268 dma_cap_zero(mask_in); 1269 dma_cap_set(DMA_SLAVE, mask_in);
1269 dma_cap_set(DMA_SLAVE, mask_in);
1270 1270
1271 dd->dma_lch_in.chan = dma_request_channel(mask_in, 1271 dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask_in,
1272 atmel_sha_filter, &pdata->dma_slave->rxdata); 1272 atmel_sha_filter, &pdata->dma_slave->rxdata, dd->dev, "tx");
1273 1273 if (!dd->dma_lch_in.chan) {
1274 if (!dd->dma_lch_in.chan) 1274 dev_warn(dd->dev, "no DMA channel available\n");
1275 return err; 1275 return err;
1276
1277 dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV;
1278 dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
1279 SHA_REG_DIN(0);
1280 dd->dma_lch_in.dma_conf.src_maxburst = 1;
1281 dd->dma_lch_in.dma_conf.src_addr_width =
1282 DMA_SLAVE_BUSWIDTH_4_BYTES;
1283 dd->dma_lch_in.dma_conf.dst_maxburst = 1;
1284 dd->dma_lch_in.dma_conf.dst_addr_width =
1285 DMA_SLAVE_BUSWIDTH_4_BYTES;
1286 dd->dma_lch_in.dma_conf.device_fc = false;
1287
1288 return 0;
1289 } 1276 }
1290 1277
1291 return -ENODEV; 1278 dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV;
1279 dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
1280 SHA_REG_DIN(0);
1281 dd->dma_lch_in.dma_conf.src_maxburst = 1;
1282 dd->dma_lch_in.dma_conf.src_addr_width =
1283 DMA_SLAVE_BUSWIDTH_4_BYTES;
1284 dd->dma_lch_in.dma_conf.dst_maxburst = 1;
1285 dd->dma_lch_in.dma_conf.dst_addr_width =
1286 DMA_SLAVE_BUSWIDTH_4_BYTES;
1287 dd->dma_lch_in.dma_conf.device_fc = false;
1288
1289 return 0;
1292} 1290}
1293 1291
1294static void atmel_sha_dma_cleanup(struct atmel_sha_dev *dd) 1292static void atmel_sha_dma_cleanup(struct atmel_sha_dev *dd)
@@ -1326,6 +1324,48 @@ static void atmel_sha_get_cap(struct atmel_sha_dev *dd)
1326 } 1324 }
1327} 1325}
1328 1326
1327#if defined(CONFIG_OF)
1328static const struct of_device_id atmel_sha_dt_ids[] = {
1329 { .compatible = "atmel,at91sam9g46-sha" },
1330 { /* sentinel */ }
1331};
1332
1333MODULE_DEVICE_TABLE(of, atmel_sha_dt_ids);
1334
1335static struct crypto_platform_data *atmel_sha_of_init(struct platform_device *pdev)
1336{
1337 struct device_node *np = pdev->dev.of_node;
1338 struct crypto_platform_data *pdata;
1339
1340 if (!np) {
1341 dev_err(&pdev->dev, "device node not found\n");
1342 return ERR_PTR(-EINVAL);
1343 }
1344
1345 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1346 if (!pdata) {
1347 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
1348 return ERR_PTR(-ENOMEM);
1349 }
1350
1351 pdata->dma_slave = devm_kzalloc(&pdev->dev,
1352 sizeof(*(pdata->dma_slave)),
1353 GFP_KERNEL);
1354 if (!pdata->dma_slave) {
1355 dev_err(&pdev->dev, "could not allocate memory for dma_slave\n");
1356 devm_kfree(&pdev->dev, pdata);
1357 return ERR_PTR(-ENOMEM);
1358 }
1359
1360 return pdata;
1361}
1362#else /* CONFIG_OF */
1363static inline struct crypto_platform_data *atmel_sha_of_init(struct platform_device *dev)
1364{
1365 return ERR_PTR(-EINVAL);
1366}
1367#endif
1368
1329static int atmel_sha_probe(struct platform_device *pdev) 1369static int atmel_sha_probe(struct platform_device *pdev)
1330{ 1370{
1331 struct atmel_sha_dev *sha_dd; 1371 struct atmel_sha_dev *sha_dd;
@@ -1402,13 +1442,23 @@ static int atmel_sha_probe(struct platform_device *pdev)
1402 if (sha_dd->caps.has_dma) { 1442 if (sha_dd->caps.has_dma) {
1403 pdata = pdev->dev.platform_data; 1443 pdata = pdev->dev.platform_data;
1404 if (!pdata) { 1444 if (!pdata) {
1405 dev_err(&pdev->dev, "platform data not available\n"); 1445 pdata = atmel_sha_of_init(pdev);
1446 if (IS_ERR(pdata)) {
1447 dev_err(&pdev->dev, "platform data not available\n");
1448 err = PTR_ERR(pdata);
1449 goto err_pdata;
1450 }
1451 }
1452 if (!pdata->dma_slave) {
1406 err = -ENXIO; 1453 err = -ENXIO;
1407 goto err_pdata; 1454 goto err_pdata;
1408 } 1455 }
1409 err = atmel_sha_dma_init(sha_dd, pdata); 1456 err = atmel_sha_dma_init(sha_dd, pdata);
1410 if (err) 1457 if (err)
1411 goto err_sha_dma; 1458 goto err_sha_dma;
1459
1460 dev_info(dev, "using %s for DMA transfers\n",
1461 dma_chan_name(sha_dd->dma_lch_in.chan));
1412 } 1462 }
1413 1463
1414 spin_lock(&atmel_sha.lock); 1464 spin_lock(&atmel_sha.lock);
@@ -1419,7 +1469,9 @@ static int atmel_sha_probe(struct platform_device *pdev)
1419 if (err) 1469 if (err)
1420 goto err_algs; 1470 goto err_algs;
1421 1471
1422 dev_info(dev, "Atmel SHA1/SHA256\n"); 1472 dev_info(dev, "Atmel SHA1/SHA256%s%s\n",
1473 sha_dd->caps.has_sha224 ? "/SHA224" : "",
1474 sha_dd->caps.has_sha_384_512 ? "/SHA384/SHA512" : "");
1423 1475
1424 return 0; 1476 return 0;
1425 1477
@@ -1483,6 +1535,7 @@ static struct platform_driver atmel_sha_driver = {
1483 .driver = { 1535 .driver = {
1484 .name = "atmel_sha", 1536 .name = "atmel_sha",
1485 .owner = THIS_MODULE, 1537 .owner = THIS_MODULE,
1538 .of_match_table = of_match_ptr(atmel_sha_dt_ids),
1486 }, 1539 },
1487}; 1540};
1488 1541
diff --git a/drivers/crypto/atmel-tdes.c b/drivers/crypto/atmel-tdes.c
index 4a99564a08e6..6cde5b530c69 100644
--- a/drivers/crypto/atmel-tdes.c
+++ b/drivers/crypto/atmel-tdes.c
@@ -30,6 +30,7 @@
30#include <linux/irq.h> 30#include <linux/irq.h>
31#include <linux/scatterlist.h> 31#include <linux/scatterlist.h>
32#include <linux/dma-mapping.h> 32#include <linux/dma-mapping.h>
33#include <linux/of_device.h>
33#include <linux/delay.h> 34#include <linux/delay.h>
34#include <linux/crypto.h> 35#include <linux/crypto.h>
35#include <linux/cryptohash.h> 36#include <linux/cryptohash.h>
@@ -716,59 +717,50 @@ static int atmel_tdes_dma_init(struct atmel_tdes_dev *dd,
716 struct crypto_platform_data *pdata) 717 struct crypto_platform_data *pdata)
717{ 718{
718 int err = -ENOMEM; 719 int err = -ENOMEM;
719 dma_cap_mask_t mask_in, mask_out; 720 dma_cap_mask_t mask;
721
722 dma_cap_zero(mask);
723 dma_cap_set(DMA_SLAVE, mask);
724
725 /* Try to grab 2 DMA channels */
726 dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask,
727 atmel_tdes_filter, &pdata->dma_slave->rxdata, dd->dev, "tx");
728 if (!dd->dma_lch_in.chan)
729 goto err_dma_in;
730
731 dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV;
732 dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
733 TDES_IDATA1R;
734 dd->dma_lch_in.dma_conf.src_maxburst = 1;
735 dd->dma_lch_in.dma_conf.src_addr_width =
736 DMA_SLAVE_BUSWIDTH_4_BYTES;
737 dd->dma_lch_in.dma_conf.dst_maxburst = 1;
738 dd->dma_lch_in.dma_conf.dst_addr_width =
739 DMA_SLAVE_BUSWIDTH_4_BYTES;
740 dd->dma_lch_in.dma_conf.device_fc = false;
741
742 dd->dma_lch_out.chan = dma_request_slave_channel_compat(mask,
743 atmel_tdes_filter, &pdata->dma_slave->txdata, dd->dev, "rx");
744 if (!dd->dma_lch_out.chan)
745 goto err_dma_out;
746
747 dd->dma_lch_out.dma_conf.direction = DMA_DEV_TO_MEM;
748 dd->dma_lch_out.dma_conf.src_addr = dd->phys_base +
749 TDES_ODATA1R;
750 dd->dma_lch_out.dma_conf.src_maxburst = 1;
751 dd->dma_lch_out.dma_conf.src_addr_width =
752 DMA_SLAVE_BUSWIDTH_4_BYTES;
753 dd->dma_lch_out.dma_conf.dst_maxburst = 1;
754 dd->dma_lch_out.dma_conf.dst_addr_width =
755 DMA_SLAVE_BUSWIDTH_4_BYTES;
756 dd->dma_lch_out.dma_conf.device_fc = false;
720 757
721 if (pdata && pdata->dma_slave->txdata.dma_dev && 758 return 0;
722 pdata->dma_slave->rxdata.dma_dev) {
723
724 /* Try to grab 2 DMA channels */
725 dma_cap_zero(mask_in);
726 dma_cap_set(DMA_SLAVE, mask_in);
727
728 dd->dma_lch_in.chan = dma_request_channel(mask_in,
729 atmel_tdes_filter, &pdata->dma_slave->rxdata);
730
731 if (!dd->dma_lch_in.chan)
732 goto err_dma_in;
733
734 dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV;
735 dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
736 TDES_IDATA1R;
737 dd->dma_lch_in.dma_conf.src_maxburst = 1;
738 dd->dma_lch_in.dma_conf.src_addr_width =
739 DMA_SLAVE_BUSWIDTH_4_BYTES;
740 dd->dma_lch_in.dma_conf.dst_maxburst = 1;
741 dd->dma_lch_in.dma_conf.dst_addr_width =
742 DMA_SLAVE_BUSWIDTH_4_BYTES;
743 dd->dma_lch_in.dma_conf.device_fc = false;
744
745 dma_cap_zero(mask_out);
746 dma_cap_set(DMA_SLAVE, mask_out);
747 dd->dma_lch_out.chan = dma_request_channel(mask_out,
748 atmel_tdes_filter, &pdata->dma_slave->txdata);
749
750 if (!dd->dma_lch_out.chan)
751 goto err_dma_out;
752
753 dd->dma_lch_out.dma_conf.direction = DMA_DEV_TO_MEM;
754 dd->dma_lch_out.dma_conf.src_addr = dd->phys_base +
755 TDES_ODATA1R;
756 dd->dma_lch_out.dma_conf.src_maxburst = 1;
757 dd->dma_lch_out.dma_conf.src_addr_width =
758 DMA_SLAVE_BUSWIDTH_4_BYTES;
759 dd->dma_lch_out.dma_conf.dst_maxburst = 1;
760 dd->dma_lch_out.dma_conf.dst_addr_width =
761 DMA_SLAVE_BUSWIDTH_4_BYTES;
762 dd->dma_lch_out.dma_conf.device_fc = false;
763
764 return 0;
765 } else {
766 return -ENODEV;
767 }
768 759
769err_dma_out: 760err_dma_out:
770 dma_release_channel(dd->dma_lch_in.chan); 761 dma_release_channel(dd->dma_lch_in.chan);
771err_dma_in: 762err_dma_in:
763 dev_warn(dd->dev, "no DMA channel available\n");
772 return err; 764 return err;
773} 765}
774 766
@@ -1317,6 +1309,47 @@ static void atmel_tdes_get_cap(struct atmel_tdes_dev *dd)
1317 } 1309 }
1318} 1310}
1319 1311
1312#if defined(CONFIG_OF)
1313static const struct of_device_id atmel_tdes_dt_ids[] = {
1314 { .compatible = "atmel,at91sam9g46-tdes" },
1315 { /* sentinel */ }
1316};
1317MODULE_DEVICE_TABLE(of, atmel_tdes_dt_ids);
1318
1319static struct crypto_platform_data *atmel_tdes_of_init(struct platform_device *pdev)
1320{
1321 struct device_node *np = pdev->dev.of_node;
1322 struct crypto_platform_data *pdata;
1323
1324 if (!np) {
1325 dev_err(&pdev->dev, "device node not found\n");
1326 return ERR_PTR(-EINVAL);
1327 }
1328
1329 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1330 if (!pdata) {
1331 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
1332 return ERR_PTR(-ENOMEM);
1333 }
1334
1335 pdata->dma_slave = devm_kzalloc(&pdev->dev,
1336 sizeof(*(pdata->dma_slave)),
1337 GFP_KERNEL);
1338 if (!pdata->dma_slave) {
1339 dev_err(&pdev->dev, "could not allocate memory for dma_slave\n");
1340 devm_kfree(&pdev->dev, pdata);
1341 return ERR_PTR(-ENOMEM);
1342 }
1343
1344 return pdata;
1345}
1346#else /* CONFIG_OF */
1347static inline struct crypto_platform_data *atmel_tdes_of_init(struct platform_device *pdev)
1348{
1349 return ERR_PTR(-EINVAL);
1350}
1351#endif
1352
1320static int atmel_tdes_probe(struct platform_device *pdev) 1353static int atmel_tdes_probe(struct platform_device *pdev)
1321{ 1354{
1322 struct atmel_tdes_dev *tdes_dd; 1355 struct atmel_tdes_dev *tdes_dd;
@@ -1399,13 +1432,24 @@ static int atmel_tdes_probe(struct platform_device *pdev)
1399 if (tdes_dd->caps.has_dma) { 1432 if (tdes_dd->caps.has_dma) {
1400 pdata = pdev->dev.platform_data; 1433 pdata = pdev->dev.platform_data;
1401 if (!pdata) { 1434 if (!pdata) {
1402 dev_err(&pdev->dev, "platform data not available\n"); 1435 pdata = atmel_tdes_of_init(pdev);
1436 if (IS_ERR(pdata)) {
1437 dev_err(&pdev->dev, "platform data not available\n");
1438 err = PTR_ERR(pdata);
1439 goto err_pdata;
1440 }
1441 }
1442 if (!pdata->dma_slave) {
1403 err = -ENXIO; 1443 err = -ENXIO;
1404 goto err_pdata; 1444 goto err_pdata;
1405 } 1445 }
1406 err = atmel_tdes_dma_init(tdes_dd, pdata); 1446 err = atmel_tdes_dma_init(tdes_dd, pdata);
1407 if (err) 1447 if (err)
1408 goto err_tdes_dma; 1448 goto err_tdes_dma;
1449
1450 dev_info(dev, "using %s, %s for DMA transfers\n",
1451 dma_chan_name(tdes_dd->dma_lch_in.chan),
1452 dma_chan_name(tdes_dd->dma_lch_out.chan));
1409 } 1453 }
1410 1454
1411 spin_lock(&atmel_tdes.lock); 1455 spin_lock(&atmel_tdes.lock);
@@ -1487,6 +1531,7 @@ static struct platform_driver atmel_tdes_driver = {
1487 .driver = { 1531 .driver = {
1488 .name = "atmel_tdes", 1532 .name = "atmel_tdes",
1489 .owner = THIS_MODULE, 1533 .owner = THIS_MODULE,
1534 .of_match_table = of_match_ptr(atmel_tdes_dt_ids),
1490 }, 1535 },
1491}; 1536};
1492 1537
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 50cc557abe41..697338772b64 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -115,6 +115,13 @@ config GPIO_CLPS711X
115 help 115 help
116 Say yes here to support GPIO on CLPS711X SoCs. 116 Say yes here to support GPIO on CLPS711X SoCs.
117 117
118config GPIO_DAVINCI
119 bool "TI Davinci/Keystone GPIO support"
120 default y if ARCH_DAVINCI
121 depends on ARM && (ARCH_DAVINCI || ARCH_KEYSTONE)
122 help
123 Say yes here to enable GPIO support for TI Davinci/Keystone SoCs.
124
118config GPIO_GENERIC_PLATFORM 125config GPIO_GENERIC_PLATFORM
119 tristate "Generic memory-mapped GPIO controller support (MMIO platform device)" 126 tristate "Generic memory-mapped GPIO controller support (MMIO platform device)"
120 select GPIO_GENERIC 127 select GPIO_GENERIC
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 0248471402e4..5d50179ece16 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o
22obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o 22obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o
23obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o 23obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o
24obj-$(CONFIG_GPIO_DA9055) += gpio-da9055.o 24obj-$(CONFIG_GPIO_DA9055) += gpio-da9055.o
25obj-$(CONFIG_ARCH_DAVINCI) += gpio-davinci.o 25obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o
26obj-$(CONFIG_GPIO_EM) += gpio-em.o 26obj-$(CONFIG_GPIO_EM) += gpio-em.o
27obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o 27obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
28obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o 28obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o
diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
index 84be70157ad6..7629b4f12b7f 100644
--- a/drivers/gpio/gpio-davinci.c
+++ b/drivers/gpio/gpio-davinci.c
@@ -16,8 +16,13 @@
16#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/irq.h> 18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
19#include <linux/platform_device.h> 23#include <linux/platform_device.h>
20#include <linux/platform_data/gpio-davinci.h> 24#include <linux/platform_data/gpio-davinci.h>
25#include <linux/irqchip/chained_irq.h>
21 26
22struct davinci_gpio_regs { 27struct davinci_gpio_regs {
23 u32 dir; 28 u32 dir;
@@ -82,14 +87,14 @@ static inline int __davinci_direction(struct gpio_chip *chip,
82 u32 mask = 1 << offset; 87 u32 mask = 1 << offset;
83 88
84 spin_lock_irqsave(&d->lock, flags); 89 spin_lock_irqsave(&d->lock, flags);
85 temp = __raw_readl(&g->dir); 90 temp = readl_relaxed(&g->dir);
86 if (out) { 91 if (out) {
87 temp &= ~mask; 92 temp &= ~mask;
88 __raw_writel(mask, value ? &g->set_data : &g->clr_data); 93 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
89 } else { 94 } else {
90 temp |= mask; 95 temp |= mask;
91 } 96 }
92 __raw_writel(temp, &g->dir); 97 writel_relaxed(temp, &g->dir);
93 spin_unlock_irqrestore(&d->lock, flags); 98 spin_unlock_irqrestore(&d->lock, flags);
94 99
95 return 0; 100 return 0;
@@ -118,7 +123,7 @@ static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
118 struct davinci_gpio_controller *d = chip2controller(chip); 123 struct davinci_gpio_controller *d = chip2controller(chip);
119 struct davinci_gpio_regs __iomem *g = d->regs; 124 struct davinci_gpio_regs __iomem *g = d->regs;
120 125
121 return (1 << offset) & __raw_readl(&g->in_data); 126 return (1 << offset) & readl_relaxed(&g->in_data);
122} 127}
123 128
124/* 129/*
@@ -130,7 +135,41 @@ davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
130 struct davinci_gpio_controller *d = chip2controller(chip); 135 struct davinci_gpio_controller *d = chip2controller(chip);
131 struct davinci_gpio_regs __iomem *g = d->regs; 136 struct davinci_gpio_regs __iomem *g = d->regs;
132 137
133 __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); 138 writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
139}
140
141static struct davinci_gpio_platform_data *
142davinci_gpio_get_pdata(struct platform_device *pdev)
143{
144 struct device_node *dn = pdev->dev.of_node;
145 struct davinci_gpio_platform_data *pdata;
146 int ret;
147 u32 val;
148
149 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
150 return pdev->dev.platform_data;
151
152 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
153 if (!pdata)
154 return NULL;
155
156 ret = of_property_read_u32(dn, "ti,ngpio", &val);
157 if (ret)
158 goto of_err;
159
160 pdata->ngpio = val;
161
162 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
163 if (ret)
164 goto of_err;
165
166 pdata->gpio_unbanked = val;
167
168 return pdata;
169
170of_err:
171 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
172 return NULL;
134} 173}
135 174
136static int davinci_gpio_probe(struct platform_device *pdev) 175static int davinci_gpio_probe(struct platform_device *pdev)
@@ -143,12 +182,14 @@ static int davinci_gpio_probe(struct platform_device *pdev)
143 struct device *dev = &pdev->dev; 182 struct device *dev = &pdev->dev;
144 struct resource *res; 183 struct resource *res;
145 184
146 pdata = dev->platform_data; 185 pdata = davinci_gpio_get_pdata(pdev);
147 if (!pdata) { 186 if (!pdata) {
148 dev_err(dev, "No platform data found\n"); 187 dev_err(dev, "No platform data found\n");
149 return -EINVAL; 188 return -EINVAL;
150 } 189 }
151 190
191 dev->platform_data = pdata;
192
152 /* 193 /*
153 * The gpio banks conceptually expose a segmented bitmap, 194 * The gpio banks conceptually expose a segmented bitmap,
154 * and "ngpio" is one more than the largest zero-based 195 * and "ngpio" is one more than the largest zero-based
@@ -160,8 +201,8 @@ static int davinci_gpio_probe(struct platform_device *pdev)
160 return -EINVAL; 201 return -EINVAL;
161 } 202 }
162 203
163 if (WARN_ON(DAVINCI_N_GPIO < ngpio)) 204 if (WARN_ON(ARCH_NR_GPIOS < ngpio))
164 ngpio = DAVINCI_N_GPIO; 205 ngpio = ARCH_NR_GPIOS;
165 206
166 chips = devm_kzalloc(dev, 207 chips = devm_kzalloc(dev,
167 ngpio * sizeof(struct davinci_gpio_controller), 208 ngpio * sizeof(struct davinci_gpio_controller),
@@ -194,6 +235,9 @@ static int davinci_gpio_probe(struct platform_device *pdev)
194 if (chips[i].chip.ngpio > 32) 235 if (chips[i].chip.ngpio > 32)
195 chips[i].chip.ngpio = 32; 236 chips[i].chip.ngpio = 32;
196 237
238#ifdef CONFIG_OF_GPIO
239 chips[i].chip.of_node = dev->of_node;
240#endif
197 spin_lock_init(&chips[i].lock); 241 spin_lock_init(&chips[i].lock);
198 242
199 regs = gpio2regs(base); 243 regs = gpio2regs(base);
@@ -227,8 +271,8 @@ static void gpio_irq_disable(struct irq_data *d)
227 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); 271 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
228 u32 mask = (u32) irq_data_get_irq_handler_data(d); 272 u32 mask = (u32) irq_data_get_irq_handler_data(d);
229 273
230 __raw_writel(mask, &g->clr_falling); 274 writel_relaxed(mask, &g->clr_falling);
231 __raw_writel(mask, &g->clr_rising); 275 writel_relaxed(mask, &g->clr_rising);
232} 276}
233 277
234static void gpio_irq_enable(struct irq_data *d) 278static void gpio_irq_enable(struct irq_data *d)
@@ -242,9 +286,9 @@ static void gpio_irq_enable(struct irq_data *d)
242 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; 286 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
243 287
244 if (status & IRQ_TYPE_EDGE_FALLING) 288 if (status & IRQ_TYPE_EDGE_FALLING)
245 __raw_writel(mask, &g->set_falling); 289 writel_relaxed(mask, &g->set_falling);
246 if (status & IRQ_TYPE_EDGE_RISING) 290 if (status & IRQ_TYPE_EDGE_RISING)
247 __raw_writel(mask, &g->set_rising); 291 writel_relaxed(mask, &g->set_rising);
248} 292}
249 293
250static int gpio_irq_type(struct irq_data *d, unsigned trigger) 294static int gpio_irq_type(struct irq_data *d, unsigned trigger)
@@ -278,34 +322,28 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
278 mask <<= 16; 322 mask <<= 16;
279 323
280 /* temporarily mask (level sensitive) parent IRQ */ 324 /* temporarily mask (level sensitive) parent IRQ */
281 desc->irq_data.chip->irq_mask(&desc->irq_data); 325 chained_irq_enter(irq_desc_get_chip(desc), desc);
282 desc->irq_data.chip->irq_ack(&desc->irq_data);
283 while (1) { 326 while (1) {
284 u32 status; 327 u32 status;
285 int n; 328 int bit;
286 int res;
287 329
288 /* ack any irqs */ 330 /* ack any irqs */
289 status = __raw_readl(&g->intstat) & mask; 331 status = readl_relaxed(&g->intstat) & mask;
290 if (!status) 332 if (!status)
291 break; 333 break;
292 __raw_writel(status, &g->intstat); 334 writel_relaxed(status, &g->intstat);
293 335
294 /* now demux them to the right lowlevel handler */ 336 /* now demux them to the right lowlevel handler */
295 n = d->irq_base;
296 if (irq & 1) {
297 n += 16;
298 status >>= 16;
299 }
300 337
301 while (status) { 338 while (status) {
302 res = ffs(status); 339 bit = __ffs(status);
303 n += res; 340 status &= ~BIT(bit);
304 generic_handle_irq(n - 1); 341 generic_handle_irq(
305 status >>= res; 342 irq_find_mapping(d->irq_domain,
343 d->chip.base + bit));
306 } 344 }
307 } 345 }
308 desc->irq_data.chip->irq_unmask(&desc->irq_data); 346 chained_irq_exit(irq_desc_get_chip(desc), desc);
309 /* now it may re-trigger */ 347 /* now it may re-trigger */
310} 348}
311 349
@@ -313,10 +351,10 @@ static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
313{ 351{
314 struct davinci_gpio_controller *d = chip2controller(chip); 352 struct davinci_gpio_controller *d = chip2controller(chip);
315 353
316 if (d->irq_base >= 0) 354 if (d->irq_domain)
317 return d->irq_base + offset; 355 return irq_create_mapping(d->irq_domain, d->chip.base + offset);
318 else 356 else
319 return -ENODEV; 357 return -ENXIO;
320} 358}
321 359
322static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) 360static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
@@ -346,14 +384,35 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
346 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 384 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
347 return -EINVAL; 385 return -EINVAL;
348 386
349 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) 387 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
350 ? &g->set_falling : &g->clr_falling); 388 ? &g->set_falling : &g->clr_falling);
351 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) 389 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
352 ? &g->set_rising : &g->clr_rising); 390 ? &g->set_rising : &g->clr_rising);
353 391
354 return 0; 392 return 0;
355} 393}
356 394
395static int
396davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
397 irq_hw_number_t hw)
398{
399 struct davinci_gpio_regs __iomem *g = gpio2regs(hw);
400
401 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
402 "davinci_gpio");
403 irq_set_irq_type(irq, IRQ_TYPE_NONE);
404 irq_set_chip_data(irq, (__force void *)g);
405 irq_set_handler_data(irq, (void *)__gpio_mask(hw));
406 set_irq_flags(irq, IRQF_VALID);
407
408 return 0;
409}
410
411static const struct irq_domain_ops davinci_gpio_irq_ops = {
412 .map = davinci_gpio_irq_map,
413 .xlate = irq_domain_xlate_onetwocell,
414};
415
357/* 416/*
358 * NOTE: for suspend/resume, probably best to make a platform_device with 417 * NOTE: for suspend/resume, probably best to make a platform_device with
359 * suspend_late/resume_resume calls hooking into results of the set_wake() 418 * suspend_late/resume_resume calls hooking into results of the set_wake()
@@ -373,6 +432,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
373 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); 432 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
374 struct davinci_gpio_platform_data *pdata = dev->platform_data; 433 struct davinci_gpio_platform_data *pdata = dev->platform_data;
375 struct davinci_gpio_regs __iomem *g; 434 struct davinci_gpio_regs __iomem *g;
435 struct irq_domain *irq_domain = NULL;
376 436
377 ngpio = pdata->ngpio; 437 ngpio = pdata->ngpio;
378 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 438 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -396,6 +456,22 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
396 } 456 }
397 clk_prepare_enable(clk); 457 clk_prepare_enable(clk);
398 458
459 if (!pdata->gpio_unbanked) {
460 irq = irq_alloc_descs(-1, 0, ngpio, 0);
461 if (irq < 0) {
462 dev_err(dev, "Couldn't allocate IRQ numbers\n");
463 return irq;
464 }
465
466 irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0,
467 &davinci_gpio_irq_ops,
468 chips);
469 if (!irq_domain) {
470 dev_err(dev, "Couldn't register an IRQ domain\n");
471 return -ENODEV;
472 }
473 }
474
399 /* 475 /*
400 * Arrange gpio_to_irq() support, handling either direct IRQs or 476 * Arrange gpio_to_irq() support, handling either direct IRQs or
401 * banked IRQs. Having GPIOs in the first GPIO bank use direct 477 * banked IRQs. Having GPIOs in the first GPIO bank use direct
@@ -404,9 +480,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
404 */ 480 */
405 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { 481 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
406 chips[bank].chip.to_irq = gpio_to_irq_banked; 482 chips[bank].chip.to_irq = gpio_to_irq_banked;
407 chips[bank].irq_base = pdata->gpio_unbanked 483 chips[bank].irq_domain = irq_domain;
408 ? -EINVAL
409 : (pdata->intc_irq_num + gpio);
410 } 484 }
411 485
412 /* 486 /*
@@ -432,8 +506,8 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
432 506
433 /* default trigger: both edges */ 507 /* default trigger: both edges */
434 g = gpio2regs(0); 508 g = gpio2regs(0);
435 __raw_writel(~0, &g->set_falling); 509 writel_relaxed(~0, &g->set_falling);
436 __raw_writel(~0, &g->set_rising); 510 writel_relaxed(~0, &g->set_rising);
437 511
438 /* set the direct IRQs up to use that irqchip */ 512 /* set the direct IRQs up to use that irqchip */
439 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) { 513 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
@@ -449,15 +523,11 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
449 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we 523 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
450 * then chain through our own handler. 524 * then chain through our own handler.
451 */ 525 */
452 for (gpio = 0, irq = gpio_to_irq(0), bank = 0; 526 for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
453 gpio < ngpio;
454 bank++, bank_irq++) {
455 unsigned i;
456
457 /* disabled by default, enabled only as needed */ 527 /* disabled by default, enabled only as needed */
458 g = gpio2regs(gpio); 528 g = gpio2regs(gpio);
459 __raw_writel(~0, &g->clr_falling); 529 writel_relaxed(~0, &g->clr_falling);
460 __raw_writel(~0, &g->clr_rising); 530 writel_relaxed(~0, &g->clr_rising);
461 531
462 /* set up all irqs in this bank */ 532 /* set up all irqs in this bank */
463 irq_set_chained_handler(bank_irq, gpio_irq_handler); 533 irq_set_chained_handler(bank_irq, gpio_irq_handler);
@@ -469,14 +539,6 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
469 */ 539 */
470 irq_set_handler_data(bank_irq, &chips[gpio / 32]); 540 irq_set_handler_data(bank_irq, &chips[gpio / 32]);
471 541
472 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
473 irq_set_chip(irq, &gpio_irqchip);
474 irq_set_chip_data(irq, (__force void *)g);
475 irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
476 irq_set_handler(irq, handle_simple_irq);
477 set_irq_flags(irq, IRQF_VALID);
478 }
479
480 binten |= BIT(bank); 542 binten |= BIT(bank);
481 } 543 }
482 544
@@ -485,18 +547,25 @@ done:
485 * BINTEN -- per-bank interrupt enable. genirq would also let these 547 * BINTEN -- per-bank interrupt enable. genirq would also let these
486 * bits be set/cleared dynamically. 548 * bits be set/cleared dynamically.
487 */ 549 */
488 __raw_writel(binten, gpio_base + BINTEN); 550 writel_relaxed(binten, gpio_base + BINTEN);
489
490 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
491 551
492 return 0; 552 return 0;
493} 553}
494 554
555#if IS_ENABLED(CONFIG_OF)
556static const struct of_device_id davinci_gpio_ids[] = {
557 { .compatible = "ti,dm6441-gpio", },
558 { /* sentinel */ },
559};
560MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
561#endif
562
495static struct platform_driver davinci_gpio_driver = { 563static struct platform_driver davinci_gpio_driver = {
496 .probe = davinci_gpio_probe, 564 .probe = davinci_gpio_probe,
497 .driver = { 565 .driver = {
498 .name = "davinci_gpio", 566 .name = "davinci_gpio",
499 .owner = THIS_MODULE, 567 .owner = THIS_MODULE,
568 .of_match_table = of_match_ptr(davinci_gpio_ids),
500 }, 569 },
501}; 570};
502 571
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
index 868ed40cb6bf..40e6440348ff 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -171,8 +171,7 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
171 171
172static void __init combiner_init(void __iomem *combiner_base, 172static void __init combiner_init(void __iomem *combiner_base,
173 struct device_node *np, 173 struct device_node *np,
174 unsigned int max_nr, 174 unsigned int max_nr)
175 int irq_base)
176{ 175{
177 int i, irq; 176 int i, irq;
178 unsigned int nr_irq; 177 unsigned int nr_irq;
@@ -186,7 +185,7 @@ static void __init combiner_init(void __iomem *combiner_base,
186 return; 185 return;
187 } 186 }
188 187
189 combiner_irq_domain = irq_domain_add_simple(np, nr_irq, irq_base, 188 combiner_irq_domain = irq_domain_add_linear(np, nr_irq,
190 &combiner_irq_domain_ops, combiner_data); 189 &combiner_irq_domain_ops, combiner_data);
191 if (WARN_ON(!combiner_irq_domain)) { 190 if (WARN_ON(!combiner_irq_domain)) {
192 pr_warning("%s: irq domain init failed\n", __func__); 191 pr_warning("%s: irq domain init failed\n", __func__);
@@ -207,7 +206,6 @@ static int __init combiner_of_init(struct device_node *np,
207{ 206{
208 void __iomem *combiner_base; 207 void __iomem *combiner_base;
209 unsigned int max_nr = 20; 208 unsigned int max_nr = 20;
210 int irq_base = -1;
211 209
212 combiner_base = of_iomap(np, 0); 210 combiner_base = of_iomap(np, 0);
213 if (!combiner_base) { 211 if (!combiner_base) {
@@ -221,14 +219,7 @@ static int __init combiner_of_init(struct device_node *np,
221 __func__, max_nr); 219 __func__, max_nr);
222 } 220 }
223 221
224 /* 222 combiner_init(combiner_base, np, max_nr);
225 * FIXME: This is a hardwired COMBINER_IRQ(0,0). Once all devices
226 * get their IRQ from DT, remove this in order to get dynamic
227 * allocation.
228 */
229 irq_base = 160;
230
231 combiner_init(combiner_base, np, max_nr, irq_base);
232 223
233 return 0; 224 return 0;
234} 225}
diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c
index 2f404ba61c6c..8777065012a5 100644
--- a/drivers/irqchip/irq-renesas-irqc.c
+++ b/drivers/irqchip/irq-renesas-irqc.c
@@ -81,15 +81,12 @@ static void irqc_irq_disable(struct irq_data *d)
81 iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS); 81 iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS);
82} 82}
83 83
84#define INTC_IRQ_SENSE_VALID 0x10
85#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
86
87static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = { 84static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
88 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x01), 85 [IRQ_TYPE_LEVEL_LOW] = 0x01,
89 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x02), 86 [IRQ_TYPE_LEVEL_HIGH] = 0x02,
90 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x04), /* Synchronous */ 87 [IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */
91 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x08), /* Synchronous */ 88 [IRQ_TYPE_EDGE_RISING] = 0x08, /* Synchronous */
92 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x0c), /* Synchronous */ 89 [IRQ_TYPE_EDGE_BOTH] = 0x0c, /* Synchronous */
93}; 90};
94 91
95static int irqc_irq_set_type(struct irq_data *d, unsigned int type) 92static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
@@ -101,12 +98,12 @@ static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
101 98
102 irqc_dbg(&p->irq[hw_irq], "sense"); 99 irqc_dbg(&p->irq[hw_irq], "sense");
103 100
104 if (!(value & INTC_IRQ_SENSE_VALID)) 101 if (!value)
105 return -EINVAL; 102 return -EINVAL;
106 103
107 tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq)); 104 tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
108 tmp &= ~0x3f; 105 tmp &= ~0x3f;
109 tmp |= value ^ INTC_IRQ_SENSE_VALID; 106 tmp |= value;
110 iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq)); 107 iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
111 return 0; 108 return 0;
112} 109}
@@ -212,10 +209,8 @@ static int irqc_probe(struct platform_device *pdev)
212 irq_chip->name = name; 209 irq_chip->name = name;
213 irq_chip->irq_mask = irqc_irq_disable; 210 irq_chip->irq_mask = irqc_irq_disable;
214 irq_chip->irq_unmask = irqc_irq_enable; 211 irq_chip->irq_unmask = irqc_irq_enable;
215 irq_chip->irq_enable = irqc_irq_enable;
216 irq_chip->irq_disable = irqc_irq_disable;
217 irq_chip->irq_set_type = irqc_irq_set_type; 212 irq_chip->irq_set_type = irqc_irq_set_type;
218 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE; 213 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
219 214
220 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, 215 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
221 p->number_of_irqs, 216 p->number_of_irqs,
diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c
index 47a52ab580d8..3ae2bb8d9cf2 100644
--- a/drivers/irqchip/irq-versatile-fpga.c
+++ b/drivers/irqchip/irq-versatile-fpga.c
@@ -9,6 +9,7 @@
9#include <linux/module.h> 9#include <linux/module.h>
10#include <linux/of.h> 10#include <linux/of.h>
11#include <linux/of_address.h> 11#include <linux/of_address.h>
12#include <linux/of_irq.h>
12 13
13#include <asm/exception.h> 14#include <asm/exception.h>
14#include <asm/mach/irq.h> 15#include <asm/mach/irq.h>
@@ -167,8 +168,12 @@ void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
167 f->used_irqs++; 168 f->used_irqs++;
168 } 169 }
169 170
170 pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n", 171 pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs",
171 fpga_irq_id, name, base, f->used_irqs); 172 fpga_irq_id, name, base, f->used_irqs);
173 if (parent_irq != -1)
174 pr_cont(", parent IRQ: %d\n", parent_irq);
175 else
176 pr_cont("\n");
172 177
173 fpga_irq_id++; 178 fpga_irq_id++;
174} 179}
@@ -180,6 +185,7 @@ int __init fpga_irq_of_init(struct device_node *node,
180 void __iomem *base; 185 void __iomem *base;
181 u32 clear_mask; 186 u32 clear_mask;
182 u32 valid_mask; 187 u32 valid_mask;
188 int parent_irq;
183 189
184 if (WARN_ON(!node)) 190 if (WARN_ON(!node))
185 return -ENODEV; 191 return -ENODEV;
@@ -193,7 +199,12 @@ int __init fpga_irq_of_init(struct device_node *node,
193 if (of_property_read_u32(node, "valid-mask", &valid_mask)) 199 if (of_property_read_u32(node, "valid-mask", &valid_mask))
194 valid_mask = 0; 200 valid_mask = 0;
195 201
196 fpga_irq_init(base, node->name, 0, -1, valid_mask, node); 202 /* Some chips are cascaded from a parent IRQ */
203 parent_irq = irq_of_parse_and_map(node, 0);
204 if (!parent_irq)
205 parent_irq = -1;
206
207 fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
197 208
198 writel(clear_mask, base + IRQ_ENABLE_CLEAR); 209 writel(clear_mask, base + IRQ_ENABLE_CLEAR);
199 writel(clear_mask, base + FIQ_ENABLE_CLEAR); 210 writel(clear_mask, base + FIQ_ENABLE_CLEAR);
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 7fc5099e44b2..4e8ca9d5570f 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -324,7 +324,7 @@ config MMC_ATMELMCI
324 324
325config MMC_MSM 325config MMC_MSM
326 tristate "Qualcomm SDCC Controller Support" 326 tristate "Qualcomm SDCC Controller Support"
327 depends on MMC && ARCH_MSM 327 depends on MMC && (ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50)
328 help 328 help
329 This provides support for the SD/MMC cell found in the 329 This provides support for the SD/MMC cell found in the
330 MSM and QSD SOCs from Qualcomm. The controller also has 330 MSM and QSD SOCs from Qualcomm. The controller also has
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 007730222116..b1328a45b095 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -304,6 +304,17 @@ config RTC_DRV_ISL12022
304 This driver can also be built as a module. If so, the module 304 This driver can also be built as a module. If so, the module
305 will be called rtc-isl12022. 305 will be called rtc-isl12022.
306 306
307config RTC_DRV_ISL12057
308 depends on I2C
309 select REGMAP_I2C
310 tristate "Intersil ISL12057"
311 help
312 If you say yes here you get support for the Intersil ISL12057
313 I2C RTC chip.
314
315 This driver can also be built as a module. If so, the module
316 will be called rtc-isl12057.
317
307config RTC_DRV_X1205 318config RTC_DRV_X1205
308 tristate "Xicor/Intersil X1205" 319 tristate "Xicor/Intersil X1205"
309 help 320 help
@@ -1104,6 +1115,13 @@ config RTC_DRV_SUN4V
1104 If you say Y here you will get support for the Hypervisor 1115 If you say Y here you will get support for the Hypervisor
1105 based RTC on SUN4V systems. 1116 based RTC on SUN4V systems.
1106 1117
1118config RTC_DRV_SUNXI
1119 tristate "Allwinner sun4i/sun7i RTC"
1120 depends on ARCH_SUNXI
1121 help
1122 If you say Y here you will get support for the RTC found on
1123 Allwinner A10/A20.
1124
1107config RTC_DRV_STARFIRE 1125config RTC_DRV_STARFIRE
1108 bool "Starfire RTC" 1126 bool "Starfire RTC"
1109 depends on SPARC64 1127 depends on SPARC64
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 27b4bd884066..c00741a0bf10 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o
58obj-$(CONFIG_RTC_DRV_IMXDI) += rtc-imxdi.o 58obj-$(CONFIG_RTC_DRV_IMXDI) += rtc-imxdi.o
59obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o 59obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o
60obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o 60obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o
61obj-$(CONFIG_RTC_DRV_ISL12057) += rtc-isl12057.o
61obj-$(CONFIG_RTC_DRV_JZ4740) += rtc-jz4740.o 62obj-$(CONFIG_RTC_DRV_JZ4740) += rtc-jz4740.o
62obj-$(CONFIG_RTC_DRV_LP8788) += rtc-lp8788.o 63obj-$(CONFIG_RTC_DRV_LP8788) += rtc-lp8788.o
63obj-$(CONFIG_RTC_DRV_LPC32XX) += rtc-lpc32xx.o 64obj-$(CONFIG_RTC_DRV_LPC32XX) += rtc-lpc32xx.o
@@ -117,6 +118,7 @@ obj-$(CONFIG_RTC_DRV_STARFIRE) += rtc-starfire.o
117obj-$(CONFIG_RTC_DRV_STK17TA8) += rtc-stk17ta8.o 118obj-$(CONFIG_RTC_DRV_STK17TA8) += rtc-stk17ta8.o
118obj-$(CONFIG_RTC_DRV_STMP) += rtc-stmp3xxx.o 119obj-$(CONFIG_RTC_DRV_STMP) += rtc-stmp3xxx.o
119obj-$(CONFIG_RTC_DRV_SUN4V) += rtc-sun4v.o 120obj-$(CONFIG_RTC_DRV_SUN4V) += rtc-sun4v.o
121obj-$(CONFIG_RTC_DRV_SUNXI) += rtc-sunxi.o
120obj-$(CONFIG_RTC_DRV_TEGRA) += rtc-tegra.o 122obj-$(CONFIG_RTC_DRV_TEGRA) += rtc-tegra.o
121obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o 123obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o
122obj-$(CONFIG_RTC_DRV_TILE) += rtc-tile.o 124obj-$(CONFIG_RTC_DRV_TILE) += rtc-tile.o
diff --git a/drivers/rtc/rtc-isl12057.c b/drivers/rtc/rtc-isl12057.c
new file mode 100644
index 000000000000..7854a656628f
--- /dev/null
+++ b/drivers/rtc/rtc-isl12057.c
@@ -0,0 +1,310 @@
1/*
2 * rtc-isl12057 - Driver for Intersil ISL12057 I2C Real Time Clock
3 *
4 * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
5 *
6 * This work is largely based on Intersil ISL1208 driver developed by
7 * Hebert Valerio Riedel <hvr@gnu.org>.
8 *
9 * Detailed datasheet on which this development is based is available here:
10 *
11 * http://natisbad.org/NAS2/refs/ISL12057.pdf
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24#include <linux/module.h>
25#include <linux/mutex.h>
26#include <linux/rtc.h>
27#include <linux/i2c.h>
28#include <linux/bcd.h>
29#include <linux/rtc.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <linux/regmap.h>
33
34#define DRV_NAME "rtc-isl12057"
35
36/* RTC section */
37#define ISL12057_REG_RTC_SC 0x00 /* Seconds */
38#define ISL12057_REG_RTC_MN 0x01 /* Minutes */
39#define ISL12057_REG_RTC_HR 0x02 /* Hours */
40#define ISL12057_REG_RTC_HR_PM BIT(5) /* AM/PM bit in 12h format */
41#define ISL12057_REG_RTC_HR_MIL BIT(6) /* 24h/12h format */
42#define ISL12057_REG_RTC_DW 0x03 /* Day of the Week */
43#define ISL12057_REG_RTC_DT 0x04 /* Date */
44#define ISL12057_REG_RTC_MO 0x05 /* Month */
45#define ISL12057_REG_RTC_YR 0x06 /* Year */
46#define ISL12057_RTC_SEC_LEN 7
47
48/* Alarm 1 section */
49#define ISL12057_REG_A1_SC 0x07 /* Alarm 1 Seconds */
50#define ISL12057_REG_A1_MN 0x08 /* Alarm 1 Minutes */
51#define ISL12057_REG_A1_HR 0x09 /* Alarm 1 Hours */
52#define ISL12057_REG_A1_HR_PM BIT(5) /* AM/PM bit in 12h format */
53#define ISL12057_REG_A1_HR_MIL BIT(6) /* 24h/12h format */
54#define ISL12057_REG_A1_DWDT 0x0A /* Alarm 1 Date / Day of the week */
55#define ISL12057_REG_A1_DWDT_B BIT(6) /* DW / DT selection bit */
56#define ISL12057_A1_SEC_LEN 4
57
58/* Alarm 2 section */
59#define ISL12057_REG_A2_MN 0x0B /* Alarm 2 Minutes */
60#define ISL12057_REG_A2_HR 0x0C /* Alarm 2 Hours */
61#define ISL12057_REG_A2_DWDT 0x0D /* Alarm 2 Date / Day of the week */
62#define ISL12057_A2_SEC_LEN 3
63
64/* Control/Status registers */
65#define ISL12057_REG_INT 0x0E
66#define ISL12057_REG_INT_A1IE BIT(0) /* Alarm 1 interrupt enable bit */
67#define ISL12057_REG_INT_A2IE BIT(1) /* Alarm 2 interrupt enable bit */
68#define ISL12057_REG_INT_INTCN BIT(2) /* Interrupt control enable bit */
69#define ISL12057_REG_INT_RS1 BIT(3) /* Freq out control bit 1 */
70#define ISL12057_REG_INT_RS2 BIT(4) /* Freq out control bit 2 */
71#define ISL12057_REG_INT_EOSC BIT(7) /* Oscillator enable bit */
72
73#define ISL12057_REG_SR 0x0F
74#define ISL12057_REG_SR_A1F BIT(0) /* Alarm 1 interrupt bit */
75#define ISL12057_REG_SR_A2F BIT(1) /* Alarm 2 interrupt bit */
76#define ISL12057_REG_SR_OSF BIT(7) /* Oscillator failure bit */
77
78/* Register memory map length */
79#define ISL12057_MEM_MAP_LEN 0x10
80
81struct isl12057_rtc_data {
82 struct regmap *regmap;
83 struct mutex lock;
84};
85
86static void isl12057_rtc_regs_to_tm(struct rtc_time *tm, u8 *regs)
87{
88 tm->tm_sec = bcd2bin(regs[ISL12057_REG_RTC_SC]);
89 tm->tm_min = bcd2bin(regs[ISL12057_REG_RTC_MN]);
90
91 if (regs[ISL12057_REG_RTC_HR] & ISL12057_REG_RTC_HR_MIL) { /* AM/PM */
92 tm->tm_hour = bcd2bin(regs[ISL12057_REG_RTC_HR] & 0x0f);
93 if (regs[ISL12057_REG_RTC_HR] & ISL12057_REG_RTC_HR_PM)
94 tm->tm_hour += 12;
95 } else { /* 24 hour mode */
96 tm->tm_hour = bcd2bin(regs[ISL12057_REG_RTC_HR] & 0x3f);
97 }
98
99 tm->tm_mday = bcd2bin(regs[ISL12057_REG_RTC_DT]);
100 tm->tm_wday = bcd2bin(regs[ISL12057_REG_RTC_DW]) - 1; /* starts at 1 */
101 tm->tm_mon = bcd2bin(regs[ISL12057_REG_RTC_MO]) - 1; /* starts at 1 */
102 tm->tm_year = bcd2bin(regs[ISL12057_REG_RTC_YR]) + 100;
103}
104
105static int isl12057_rtc_tm_to_regs(u8 *regs, struct rtc_time *tm)
106{
107 /*
108 * The clock has an 8 bit wide bcd-coded register for the year.
109 * tm_year is an offset from 1900 and we are interested in the
110 * 2000-2099 range, so any value less than 100 is invalid.
111 */
112 if (tm->tm_year < 100)
113 return -EINVAL;
114
115 regs[ISL12057_REG_RTC_SC] = bin2bcd(tm->tm_sec);
116 regs[ISL12057_REG_RTC_MN] = bin2bcd(tm->tm_min);
117 regs[ISL12057_REG_RTC_HR] = bin2bcd(tm->tm_hour); /* 24-hour format */
118 regs[ISL12057_REG_RTC_DT] = bin2bcd(tm->tm_mday);
119 regs[ISL12057_REG_RTC_MO] = bin2bcd(tm->tm_mon + 1);
120 regs[ISL12057_REG_RTC_YR] = bin2bcd(tm->tm_year - 100);
121 regs[ISL12057_REG_RTC_DW] = bin2bcd(tm->tm_wday + 1);
122
123 return 0;
124}
125
126/*
127 * Try and match register bits w/ fixed null values to see whether we
128 * are dealing with an ISL12057. Note: this function is called early
129 * during init and hence does need mutex protection.
130 */
131static int isl12057_i2c_validate_chip(struct regmap *regmap)
132{
133 u8 regs[ISL12057_MEM_MAP_LEN];
134 static const u8 mask[ISL12057_MEM_MAP_LEN] = { 0x80, 0x80, 0x80, 0xf8,
135 0xc0, 0x60, 0x00, 0x00,
136 0x00, 0x00, 0x00, 0x00,
137 0x00, 0x00, 0x60, 0x7c };
138 int ret, i;
139
140 ret = regmap_bulk_read(regmap, 0, regs, ISL12057_MEM_MAP_LEN);
141 if (ret)
142 return ret;
143
144 for (i = 0; i < ISL12057_MEM_MAP_LEN; ++i) {
145 if (regs[i] & mask[i]) /* check if bits are cleared */
146 return -ENODEV;
147 }
148
149 return 0;
150}
151
152static int isl12057_rtc_read_time(struct device *dev, struct rtc_time *tm)
153{
154 struct isl12057_rtc_data *data = dev_get_drvdata(dev);
155 u8 regs[ISL12057_RTC_SEC_LEN];
156 int ret;
157
158 mutex_lock(&data->lock);
159 ret = regmap_bulk_read(data->regmap, ISL12057_REG_RTC_SC, regs,
160 ISL12057_RTC_SEC_LEN);
161 mutex_unlock(&data->lock);
162
163 if (ret) {
164 dev_err(dev, "%s: RTC read failed\n", __func__);
165 return ret;
166 }
167
168 isl12057_rtc_regs_to_tm(tm, regs);
169
170 return rtc_valid_tm(tm);
171}
172
173static int isl12057_rtc_set_time(struct device *dev, struct rtc_time *tm)
174{
175 struct isl12057_rtc_data *data = dev_get_drvdata(dev);
176 u8 regs[ISL12057_RTC_SEC_LEN];
177 int ret;
178
179 ret = isl12057_rtc_tm_to_regs(regs, tm);
180 if (ret)
181 return ret;
182
183 mutex_lock(&data->lock);
184 ret = regmap_bulk_write(data->regmap, ISL12057_REG_RTC_SC, regs,
185 ISL12057_RTC_SEC_LEN);
186 mutex_unlock(&data->lock);
187
188 if (ret)
189 dev_err(dev, "%s: RTC write failed\n", __func__);
190
191 return ret;
192}
193
194/*
195 * Check current RTC status and enable/disable what needs to be. Return 0 if
196 * everything went ok and a negative value upon error. Note: this function
197 * is called early during init and hence does need mutex protection.
198 */
199static int isl12057_check_rtc_status(struct device *dev, struct regmap *regmap)
200{
201 int ret;
202
203 /* Enable oscillator if not already running */
204 ret = regmap_update_bits(regmap, ISL12057_REG_INT,
205 ISL12057_REG_INT_EOSC, 0);
206 if (ret < 0) {
207 dev_err(dev, "Unable to enable oscillator\n");
208 return ret;
209 }
210
211 /* Clear oscillator failure bit if needed */
212 ret = regmap_update_bits(regmap, ISL12057_REG_SR,
213 ISL12057_REG_SR_OSF, 0);
214 if (ret < 0) {
215 dev_err(dev, "Unable to clear oscillator failure bit\n");
216 return ret;
217 }
218
219 /* Clear alarm bit if needed */
220 ret = regmap_update_bits(regmap, ISL12057_REG_SR,
221 ISL12057_REG_SR_A1F, 0);
222 if (ret < 0) {
223 dev_err(dev, "Unable to clear alarm bit\n");
224 return ret;
225 }
226
227 return 0;
228}
229
230static const struct rtc_class_ops rtc_ops = {
231 .read_time = isl12057_rtc_read_time,
232 .set_time = isl12057_rtc_set_time,
233};
234
235static struct regmap_config isl12057_rtc_regmap_config = {
236 .reg_bits = 8,
237 .val_bits = 8,
238};
239
240static int isl12057_probe(struct i2c_client *client,
241 const struct i2c_device_id *id)
242{
243 struct device *dev = &client->dev;
244 struct isl12057_rtc_data *data;
245 struct rtc_device *rtc;
246 struct regmap *regmap;
247 int ret;
248
249 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
250 I2C_FUNC_SMBUS_BYTE_DATA |
251 I2C_FUNC_SMBUS_I2C_BLOCK))
252 return -ENODEV;
253
254 regmap = devm_regmap_init_i2c(client, &isl12057_rtc_regmap_config);
255 if (IS_ERR(regmap)) {
256 ret = PTR_ERR(regmap);
257 dev_err(dev, "regmap allocation failed: %d\n", ret);
258 return ret;
259 }
260
261 ret = isl12057_i2c_validate_chip(regmap);
262 if (ret)
263 return ret;
264
265 ret = isl12057_check_rtc_status(dev, regmap);
266 if (ret)
267 return ret;
268
269 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
270 if (!data)
271 return -ENOMEM;
272
273 mutex_init(&data->lock);
274 data->regmap = regmap;
275 dev_set_drvdata(dev, data);
276
277 rtc = devm_rtc_device_register(dev, DRV_NAME, &rtc_ops, THIS_MODULE);
278 if (IS_ERR(rtc))
279 return PTR_ERR(rtc);
280
281 return 0;
282}
283
284#ifdef CONFIG_OF
285static struct of_device_id isl12057_dt_match[] = {
286 { .compatible = "isl,isl12057" },
287 { },
288};
289#endif
290
291static const struct i2c_device_id isl12057_id[] = {
292 { "isl12057", 0 },
293 { }
294};
295MODULE_DEVICE_TABLE(i2c, isl12057_id);
296
297static struct i2c_driver isl12057_driver = {
298 .driver = {
299 .name = DRV_NAME,
300 .owner = THIS_MODULE,
301 .of_match_table = of_match_ptr(isl12057_dt_match),
302 },
303 .probe = isl12057_probe,
304 .id_table = isl12057_id,
305};
306module_i2c_driver(isl12057_driver);
307
308MODULE_AUTHOR("Arnaud EBALARD <arno@natisbad.org>");
309MODULE_DESCRIPTION("Intersil ISL12057 RTC driver");
310MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-sunxi.c b/drivers/rtc/rtc-sunxi.c
new file mode 100644
index 000000000000..68a35284e5ad
--- /dev/null
+++ b/drivers/rtc/rtc-sunxi.c
@@ -0,0 +1,523 @@
1/*
2 * An RTC driver for Allwinner A10/A20
3 *
4 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/delay.h>
22#include <linux/err.h>
23#include <linux/fs.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/of.h>
30#include <linux/of_address.h>
31#include <linux/of_device.h>
32#include <linux/platform_device.h>
33#include <linux/rtc.h>
34#include <linux/types.h>
35
36#define SUNXI_LOSC_CTRL 0x0000
37#define SUNXI_LOSC_CTRL_RTC_HMS_ACC BIT(8)
38#define SUNXI_LOSC_CTRL_RTC_YMD_ACC BIT(7)
39
40#define SUNXI_RTC_YMD 0x0004
41
42#define SUNXI_RTC_HMS 0x0008
43
44#define SUNXI_ALRM_DHMS 0x000c
45
46#define SUNXI_ALRM_EN 0x0014
47#define SUNXI_ALRM_EN_CNT_EN BIT(8)
48
49#define SUNXI_ALRM_IRQ_EN 0x0018
50#define SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
51
52#define SUNXI_ALRM_IRQ_STA 0x001c
53#define SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
54
55#define SUNXI_MASK_DH 0x0000001f
56#define SUNXI_MASK_SM 0x0000003f
57#define SUNXI_MASK_M 0x0000000f
58#define SUNXI_MASK_LY 0x00000001
59#define SUNXI_MASK_D 0x00000ffe
60#define SUNXI_MASK_M 0x0000000f
61
62#define SUNXI_GET(x, mask, shift) (((x) & ((mask) << (shift))) \
63 >> (shift))
64
65#define SUNXI_SET(x, mask, shift) (((x) & (mask)) << (shift))
66
67/*
68 * Get date values
69 */
70#define SUNXI_DATE_GET_DAY_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 0)
71#define SUNXI_DATE_GET_MON_VALUE(x) SUNXI_GET(x, SUNXI_MASK_M, 8)
72#define SUNXI_DATE_GET_YEAR_VALUE(x, mask) SUNXI_GET(x, mask, 16)
73
74/*
75 * Get time values
76 */
77#define SUNXI_TIME_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0)
78#define SUNXI_TIME_GET_MIN_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 8)
79#define SUNXI_TIME_GET_HOUR_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 16)
80
81/*
82 * Get alarm values
83 */
84#define SUNXI_ALRM_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0)
85#define SUNXI_ALRM_GET_MIN_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 8)
86#define SUNXI_ALRM_GET_HOUR_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 16)
87
88/*
89 * Set date values
90 */
91#define SUNXI_DATE_SET_DAY_VALUE(x) SUNXI_DATE_GET_DAY_VALUE(x)
92#define SUNXI_DATE_SET_MON_VALUE(x) SUNXI_SET(x, SUNXI_MASK_M, 8)
93#define SUNXI_DATE_SET_YEAR_VALUE(x, mask) SUNXI_SET(x, mask, 16)
94#define SUNXI_LEAP_SET_VALUE(x, shift) SUNXI_SET(x, SUNXI_MASK_LY, shift)
95
96/*
97 * Set time values
98 */
99#define SUNXI_TIME_SET_SEC_VALUE(x) SUNXI_TIME_GET_SEC_VALUE(x)
100#define SUNXI_TIME_SET_MIN_VALUE(x) SUNXI_SET(x, SUNXI_MASK_SM, 8)
101#define SUNXI_TIME_SET_HOUR_VALUE(x) SUNXI_SET(x, SUNXI_MASK_DH, 16)
102
103/*
104 * Set alarm values
105 */
106#define SUNXI_ALRM_SET_SEC_VALUE(x) SUNXI_ALRM_GET_SEC_VALUE(x)
107#define SUNXI_ALRM_SET_MIN_VALUE(x) SUNXI_SET(x, SUNXI_MASK_SM, 8)
108#define SUNXI_ALRM_SET_HOUR_VALUE(x) SUNXI_SET(x, SUNXI_MASK_DH, 16)
109#define SUNXI_ALRM_SET_DAY_VALUE(x) SUNXI_SET(x, SUNXI_MASK_D, 21)
110
111/*
112 * Time unit conversions
113 */
114#define SEC_IN_MIN 60
115#define SEC_IN_HOUR (60 * SEC_IN_MIN)
116#define SEC_IN_DAY (24 * SEC_IN_HOUR)
117
118/*
119 * The year parameter passed to the driver is usually an offset relative to
120 * the year 1900. This macro is used to convert this offset to another one
121 * relative to the minimum year allowed by the hardware.
122 */
123#define SUNXI_YEAR_OFF(x) ((x)->min - 1900)
124
125/*
126 * min and max year are arbitrary set considering the limited range of the
127 * hardware register field
128 */
129struct sunxi_rtc_data_year {
130 unsigned int min; /* min year allowed */
131 unsigned int max; /* max year allowed */
132 unsigned int mask; /* mask for the year field */
133 unsigned char leap_shift; /* bit shift to get the leap year */
134};
135
136static struct sunxi_rtc_data_year data_year_param[] = {
137 [0] = {
138 .min = 2010,
139 .max = 2073,
140 .mask = 0x3f,
141 .leap_shift = 22,
142 },
143 [1] = {
144 .min = 1970,
145 .max = 2225,
146 .mask = 0xff,
147 .leap_shift = 24,
148 },
149};
150
151struct sunxi_rtc_dev {
152 struct rtc_device *rtc;
153 struct device *dev;
154 struct sunxi_rtc_data_year *data_year;
155 void __iomem *base;
156 int irq;
157};
158
159static irqreturn_t sunxi_rtc_alarmirq(int irq, void *id)
160{
161 struct sunxi_rtc_dev *chip = (struct sunxi_rtc_dev *) id;
162 u32 val;
163
164 val = readl(chip->base + SUNXI_ALRM_IRQ_STA);
165
166 if (val & SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND) {
167 val |= SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND;
168 writel(val, chip->base + SUNXI_ALRM_IRQ_STA);
169
170 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
171
172 return IRQ_HANDLED;
173 }
174
175 return IRQ_NONE;
176}
177
178static void sunxi_rtc_setaie(int to, struct sunxi_rtc_dev *chip)
179{
180 u32 alrm_val = 0;
181 u32 alrm_irq_val = 0;
182
183 if (to) {
184 alrm_val = readl(chip->base + SUNXI_ALRM_EN);
185 alrm_val |= SUNXI_ALRM_EN_CNT_EN;
186
187 alrm_irq_val = readl(chip->base + SUNXI_ALRM_IRQ_EN);
188 alrm_irq_val |= SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN;
189 } else {
190 writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND,
191 chip->base + SUNXI_ALRM_IRQ_STA);
192 }
193
194 writel(alrm_val, chip->base + SUNXI_ALRM_EN);
195 writel(alrm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN);
196}
197
198static int sunxi_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
199{
200 struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
201 struct rtc_time *alrm_tm = &wkalrm->time;
202 u32 alrm;
203 u32 alrm_en;
204 u32 date;
205
206 alrm = readl(chip->base + SUNXI_ALRM_DHMS);
207 date = readl(chip->base + SUNXI_RTC_YMD);
208
209 alrm_tm->tm_sec = SUNXI_ALRM_GET_SEC_VALUE(alrm);
210 alrm_tm->tm_min = SUNXI_ALRM_GET_MIN_VALUE(alrm);
211 alrm_tm->tm_hour = SUNXI_ALRM_GET_HOUR_VALUE(alrm);
212
213 alrm_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
214 alrm_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
215 alrm_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
216 chip->data_year->mask);
217
218 alrm_tm->tm_mon -= 1;
219
220 /*
221 * switch from (data_year->min)-relative offset to
222 * a (1900)-relative one
223 */
224 alrm_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
225
226 alrm_en = readl(chip->base + SUNXI_ALRM_IRQ_EN);
227 if (alrm_en & SUNXI_ALRM_EN_CNT_EN)
228 wkalrm->enabled = 1;
229
230 return 0;
231}
232
233static int sunxi_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
234{
235 struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
236 u32 date, time;
237
238 /*
239 * read again in case it changes
240 */
241 do {
242 date = readl(chip->base + SUNXI_RTC_YMD);
243 time = readl(chip->base + SUNXI_RTC_HMS);
244 } while ((date != readl(chip->base + SUNXI_RTC_YMD)) ||
245 (time != readl(chip->base + SUNXI_RTC_HMS)));
246
247 rtc_tm->tm_sec = SUNXI_TIME_GET_SEC_VALUE(time);
248 rtc_tm->tm_min = SUNXI_TIME_GET_MIN_VALUE(time);
249 rtc_tm->tm_hour = SUNXI_TIME_GET_HOUR_VALUE(time);
250
251 rtc_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
252 rtc_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
253 rtc_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
254 chip->data_year->mask);
255
256 rtc_tm->tm_mon -= 1;
257
258 /*
259 * switch from (data_year->min)-relative offset to
260 * a (1900)-relative one
261 */
262 rtc_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
263
264 return rtc_valid_tm(rtc_tm);
265}
266
267static int sunxi_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
268{
269 struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
270 struct rtc_time *alrm_tm = &wkalrm->time;
271 struct rtc_time tm_now;
272 u32 alrm = 0;
273 unsigned long time_now = 0;
274 unsigned long time_set = 0;
275 unsigned long time_gap = 0;
276 unsigned long time_gap_day = 0;
277 unsigned long time_gap_hour = 0;
278 unsigned long time_gap_min = 0;
279 int ret = 0;
280
281 ret = sunxi_rtc_gettime(dev, &tm_now);
282 if (ret < 0) {
283 dev_err(dev, "Error in getting time\n");
284 return -EINVAL;
285 }
286
287 rtc_tm_to_time(alrm_tm, &time_set);
288 rtc_tm_to_time(&tm_now, &time_now);
289 if (time_set <= time_now) {
290 dev_err(dev, "Date to set in the past\n");
291 return -EINVAL;
292 }
293
294 time_gap = time_set - time_now;
295 time_gap_day = time_gap / SEC_IN_DAY;
296 time_gap -= time_gap_day * SEC_IN_DAY;
297 time_gap_hour = time_gap / SEC_IN_HOUR;
298 time_gap -= time_gap_hour * SEC_IN_HOUR;
299 time_gap_min = time_gap / SEC_IN_MIN;
300 time_gap -= time_gap_min * SEC_IN_MIN;
301
302 if (time_gap_day > 255) {
303 dev_err(dev, "Day must be in the range 0 - 255\n");
304 return -EINVAL;
305 }
306
307 sunxi_rtc_setaie(0, chip);
308 writel(0, chip->base + SUNXI_ALRM_DHMS);
309 usleep_range(100, 300);
310
311 alrm = SUNXI_ALRM_SET_SEC_VALUE(time_gap) |
312 SUNXI_ALRM_SET_MIN_VALUE(time_gap_min) |
313 SUNXI_ALRM_SET_HOUR_VALUE(time_gap_hour) |
314 SUNXI_ALRM_SET_DAY_VALUE(time_gap_day);
315 writel(alrm, chip->base + SUNXI_ALRM_DHMS);
316
317 writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
318 writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN);
319
320 sunxi_rtc_setaie(wkalrm->enabled, chip);
321
322 return 0;
323}
324
325static int sunxi_rtc_wait(struct sunxi_rtc_dev *chip, int offset,
326 unsigned int mask, unsigned int ms_timeout)
327{
328 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
329 u32 reg;
330
331 do {
332 reg = readl(chip->base + offset);
333 reg &= mask;
334
335 if (reg == mask)
336 return 0;
337
338 } while (time_before(jiffies, timeout));
339
340 return -ETIMEDOUT;
341}
342
343static int sunxi_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
344{
345 struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
346 u32 date = 0;
347 u32 time = 0;
348 int year;
349
350 /*
351 * the input rtc_tm->tm_year is the offset relative to 1900. We use
352 * the SUNXI_YEAR_OFF macro to rebase it with respect to the min year
353 * allowed by the hardware
354 */
355
356 year = rtc_tm->tm_year + 1900;
357 if (year < chip->data_year->min || year > chip->data_year->max) {
358 dev_err(dev, "rtc only supports year in range %d - %d\n",
359 chip->data_year->min, chip->data_year->max);
360 return -EINVAL;
361 }
362
363 rtc_tm->tm_year -= SUNXI_YEAR_OFF(chip->data_year);
364 rtc_tm->tm_mon += 1;
365
366 date = SUNXI_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
367 SUNXI_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
368 SUNXI_DATE_SET_YEAR_VALUE(rtc_tm->tm_year,
369 chip->data_year->mask);
370
371 if (is_leap_year(year))
372 date |= SUNXI_LEAP_SET_VALUE(1, chip->data_year->leap_shift);
373
374 time = SUNXI_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
375 SUNXI_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
376 SUNXI_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
377
378 writel(0, chip->base + SUNXI_RTC_HMS);
379 writel(0, chip->base + SUNXI_RTC_YMD);
380
381 writel(time, chip->base + SUNXI_RTC_HMS);
382
383 /*
384 * After writing the RTC HH-MM-SS register, the
385 * SUNXI_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
386 * be cleared until the real writing operation is finished
387 */
388
389 if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
390 SUNXI_LOSC_CTRL_RTC_HMS_ACC, 50)) {
391 dev_err(dev, "Failed to set rtc time.\n");
392 return -1;
393 }
394
395 writel(date, chip->base + SUNXI_RTC_YMD);
396
397 /*
398 * After writing the RTC YY-MM-DD register, the
399 * SUNXI_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
400 * be cleared until the real writing operation is finished
401 */
402
403 if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
404 SUNXI_LOSC_CTRL_RTC_YMD_ACC, 50)) {
405 dev_err(dev, "Failed to set rtc time.\n");
406 return -1;
407 }
408
409 return 0;
410}
411
412static int sunxi_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
413{
414 struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
415
416 if (!enabled)
417 sunxi_rtc_setaie(enabled, chip);
418
419 return 0;
420}
421
422static const struct rtc_class_ops sunxi_rtc_ops = {
423 .read_time = sunxi_rtc_gettime,
424 .set_time = sunxi_rtc_settime,
425 .read_alarm = sunxi_rtc_getalarm,
426 .set_alarm = sunxi_rtc_setalarm,
427 .alarm_irq_enable = sunxi_rtc_alarm_irq_enable
428};
429
430static const struct of_device_id sunxi_rtc_dt_ids[] = {
431 { .compatible = "allwinner,sun4i-rtc", .data = &data_year_param[0] },
432 { .compatible = "allwinner,sun7i-a20-rtc", .data = &data_year_param[1] },
433 { /* sentinel */ },
434};
435MODULE_DEVICE_TABLE(of, sunxi_rtc_dt_ids);
436
437static int sunxi_rtc_probe(struct platform_device *pdev)
438{
439 struct sunxi_rtc_dev *chip;
440 struct resource *res;
441 const struct of_device_id *of_id;
442 int ret;
443
444 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
445 if (!chip)
446 return -ENOMEM;
447
448 platform_set_drvdata(pdev, chip);
449 chip->dev = &pdev->dev;
450
451 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
452 chip->base = devm_ioremap_resource(&pdev->dev, res);
453 if (IS_ERR(chip->base))
454 return PTR_ERR(chip->base);
455
456 chip->irq = platform_get_irq(pdev, 0);
457 if (chip->irq < 0) {
458 dev_err(&pdev->dev, "No IRQ resource\n");
459 return chip->irq;
460 }
461 ret = devm_request_irq(&pdev->dev, chip->irq, sunxi_rtc_alarmirq,
462 0, dev_name(&pdev->dev), chip);
463 if (ret) {
464 dev_err(&pdev->dev, "Could not request IRQ\n");
465 return ret;
466 }
467
468 of_id = of_match_device(sunxi_rtc_dt_ids, &pdev->dev);
469 if (!of_id) {
470 dev_err(&pdev->dev, "Unable to setup RTC data\n");
471 return -ENODEV;
472 }
473 chip->data_year = (struct sunxi_rtc_data_year *) of_id->data;
474
475 /* clear the alarm count value */
476 writel(0, chip->base + SUNXI_ALRM_DHMS);
477
478 /* disable alarm, not generate irq pending */
479 writel(0, chip->base + SUNXI_ALRM_EN);
480
481 /* disable alarm week/cnt irq, unset to cpu */
482 writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
483
484 /* clear alarm week/cnt irq pending */
485 writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, chip->base +
486 SUNXI_ALRM_IRQ_STA);
487
488 chip->rtc = rtc_device_register("rtc-sunxi", &pdev->dev,
489 &sunxi_rtc_ops, THIS_MODULE);
490 if (IS_ERR(chip->rtc)) {
491 dev_err(&pdev->dev, "unable to register device\n");
492 return PTR_ERR(chip->rtc);
493 }
494
495 dev_info(&pdev->dev, "RTC enabled\n");
496
497 return 0;
498}
499
500static int sunxi_rtc_remove(struct platform_device *pdev)
501{
502 struct sunxi_rtc_dev *chip = platform_get_drvdata(pdev);
503
504 rtc_device_unregister(chip->rtc);
505
506 return 0;
507}
508
509static struct platform_driver sunxi_rtc_driver = {
510 .probe = sunxi_rtc_probe,
511 .remove = sunxi_rtc_remove,
512 .driver = {
513 .name = "sunxi-rtc",
514 .owner = THIS_MODULE,
515 .of_match_table = sunxi_rtc_dt_ids,
516 },
517};
518
519module_platform_driver(sunxi_rtc_driver);
520
521MODULE_DESCRIPTION("sunxi RTC driver");
522MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
523MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 441ada489874..a3815eaed421 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1034,7 +1034,7 @@ config SERIAL_MSM_CONSOLE
1034 1034
1035config SERIAL_MSM_HS 1035config SERIAL_MSM_HS
1036 tristate "MSM UART High Speed: Serial Driver" 1036 tristate "MSM UART High Speed: Serial Driver"
1037 depends on ARCH_MSM 1037 depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
1038 select SERIAL_CORE 1038 select SERIAL_CORE
1039 help 1039 help
1040 If you have a machine based on MSM family of SoCs, you 1040 If you have a machine based on MSM family of SoCs, you
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index e4bf0e435af6..be33d2b0613b 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -39,6 +39,7 @@
39#include <linux/module.h> 39#include <linux/module.h>
40#include <linux/mm.h> 40#include <linux/mm.h>
41#include <linux/notifier.h> 41#include <linux/notifier.h>
42#include <linux/of.h>
42#include <linux/platform_device.h> 43#include <linux/platform_device.h>
43#include <linux/pm_runtime.h> 44#include <linux/pm_runtime.h>
44#include <linux/scatterlist.h> 45#include <linux/scatterlist.h>
@@ -58,6 +59,23 @@
58 59
59#include "sh-sci.h" 60#include "sh-sci.h"
60 61
62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
61struct sci_port { 79struct sci_port {
62 struct uart_port port; 80 struct uart_port port;
63 81
@@ -1757,17 +1775,6 @@ static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1757 if (s->sampling_rate) 1775 if (s->sampling_rate)
1758 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1; 1776 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1759 1777
1760 switch (s->cfg->scbrr_algo_id) {
1761 case SCBRR_ALGO_1:
1762 return freq / (16 * bps);
1763 case SCBRR_ALGO_2:
1764 return DIV_ROUND_CLOSEST(freq, 32 * bps) - 1;
1765 case SCBRR_ALGO_3:
1766 return freq / (8 * bps);
1767 case SCBRR_ALGO_4:
1768 return DIV_ROUND_CLOSEST(freq, 16 * bps) - 1;
1769 }
1770
1771 /* Warn, but use a safe default */ 1778 /* Warn, but use a safe default */
1772 WARN_ON(1); 1779 WARN_ON(1);
1773 1780
@@ -2105,36 +2112,27 @@ static int sci_init_single(struct platform_device *dev,
2105 port->iotype = UPIO_MEM; 2112 port->iotype = UPIO_MEM;
2106 port->line = index; 2113 port->line = index;
2107 2114
2108 if (dev->num_resources) { 2115 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2109 /* Device has resources, use them. */ 2116 if (res == NULL)
2110 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2117 return -ENOMEM;
2111 if (res == NULL)
2112 return -ENOMEM;
2113 2118
2114 port->mapbase = res->start; 2119 port->mapbase = res->start;
2115 2120
2116 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) 2121 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2117 sci_port->irqs[i] = platform_get_irq(dev, i); 2122 sci_port->irqs[i] = platform_get_irq(dev, i);
2118 2123
2119 /* The SCI generates several interrupts. They can be muxed 2124 /* The SCI generates several interrupts. They can be muxed together or
2120 * together or connected to different interrupt lines. In the 2125 * connected to different interrupt lines. In the muxed case only one
2121 * muxed case only one interrupt resource is specified. In the 2126 * interrupt resource is specified. In the non-muxed case three or four
2122 * non-muxed case three or four interrupt resources are 2127 * interrupt resources are specified, as the BRI interrupt is optional.
2123 * specified, as the BRI interrupt is optional. 2128 */
2124 */ 2129 if (sci_port->irqs[0] < 0)
2125 if (sci_port->irqs[0] < 0) 2130 return -ENXIO;
2126 return -ENXIO;
2127 2131
2128 if (sci_port->irqs[1] < 0) { 2132 if (sci_port->irqs[1] < 0) {
2129 sci_port->irqs[1] = sci_port->irqs[0]; 2133 sci_port->irqs[1] = sci_port->irqs[0];
2130 sci_port->irqs[2] = sci_port->irqs[0]; 2134 sci_port->irqs[2] = sci_port->irqs[0];
2131 sci_port->irqs[3] = sci_port->irqs[0]; 2135 sci_port->irqs[3] = sci_port->irqs[0];
2132 }
2133 } else {
2134 /* No resources, use old-style platform data. */
2135 port->mapbase = p->mapbase;
2136 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2137 sci_port->irqs[i] = p->irqs[i] ? p->irqs[i] : -ENXIO;
2138 } 2136 }
2139 2137
2140 if (p->regtype == SCIx_PROBE_REGTYPE) { 2138 if (p->regtype == SCIx_PROBE_REGTYPE) {
@@ -2176,17 +2174,12 @@ static int sci_init_single(struct platform_device *dev,
2176 break; 2174 break;
2177 } 2175 }
2178 2176
2179 /* Set the sampling rate if the baud rate calculation algorithm isn't 2177 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2180 * specified. 2178 * match the SoC datasheet, this should be investigated. Let platform
2179 * data override the sampling rate for now.
2181 */ 2180 */
2182 if (p->scbrr_algo_id == SCBRR_ALGO_NONE) { 2181 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2183 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that 2182 : sampling_rate;
2184 * doesn't match the SoC datasheet, this should be investigated.
2185 * Let platform data override the sampling rate for now.
2186 */
2187 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2188 : sampling_rate;
2189 }
2190 2183
2191 if (!early) { 2184 if (!early) {
2192 sci_port->iclk = clk_get(&dev->dev, "sci_ick"); 2185 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
@@ -2423,6 +2416,83 @@ static int sci_remove(struct platform_device *dev)
2423 return 0; 2416 return 0;
2424} 2417}
2425 2418
2419struct sci_port_info {
2420 unsigned int type;
2421 unsigned int regtype;
2422};
2423
2424static const struct of_device_id of_sci_match[] = {
2425 {
2426 .compatible = "renesas,scif",
2427 .data = (void *)&(const struct sci_port_info) {
2428 .type = PORT_SCIF,
2429 .regtype = SCIx_SH4_SCIF_REGTYPE,
2430 },
2431 }, {
2432 .compatible = "renesas,scifa",
2433 .data = (void *)&(const struct sci_port_info) {
2434 .type = PORT_SCIFA,
2435 .regtype = SCIx_SCIFA_REGTYPE,
2436 },
2437 }, {
2438 .compatible = "renesas,scifb",
2439 .data = (void *)&(const struct sci_port_info) {
2440 .type = PORT_SCIFB,
2441 .regtype = SCIx_SCIFB_REGTYPE,
2442 },
2443 }, {
2444 .compatible = "renesas,hscif",
2445 .data = (void *)&(const struct sci_port_info) {
2446 .type = PORT_HSCIF,
2447 .regtype = SCIx_HSCIF_REGTYPE,
2448 },
2449 }, {
2450 /* Terminator */
2451 },
2452};
2453MODULE_DEVICE_TABLE(of, of_sci_match);
2454
2455static struct plat_sci_port *
2456sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2457{
2458 struct device_node *np = pdev->dev.of_node;
2459 const struct of_device_id *match;
2460 const struct sci_port_info *info;
2461 struct plat_sci_port *p;
2462 int id;
2463
2464 if (!IS_ENABLED(CONFIG_OF) || !np)
2465 return NULL;
2466
2467 match = of_match_node(of_sci_match, pdev->dev.of_node);
2468 if (!match)
2469 return NULL;
2470
2471 info = match->data;
2472
2473 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2474 if (!p) {
2475 dev_err(&pdev->dev, "failed to allocate DT config data\n");
2476 return NULL;
2477 }
2478
2479 /* Get the line number for the aliases node. */
2480 id = of_alias_get_id(np, "serial");
2481 if (id < 0) {
2482 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2483 return NULL;
2484 }
2485
2486 *dev_id = id;
2487
2488 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2489 p->type = info->type;
2490 p->regtype = info->regtype;
2491 p->scscr = SCSCR_RE | SCSCR_TE;
2492
2493 return p;
2494}
2495
2426static int sci_probe_single(struct platform_device *dev, 2496static int sci_probe_single(struct platform_device *dev,
2427 unsigned int index, 2497 unsigned int index,
2428 struct plat_sci_port *p, 2498 struct plat_sci_port *p,
@@ -2455,8 +2525,9 @@ static int sci_probe_single(struct platform_device *dev,
2455 2525
2456static int sci_probe(struct platform_device *dev) 2526static int sci_probe(struct platform_device *dev)
2457{ 2527{
2458 struct plat_sci_port *p = dev_get_platdata(&dev->dev); 2528 struct plat_sci_port *p;
2459 struct sci_port *sp = &sci_ports[dev->id]; 2529 struct sci_port *sp;
2530 unsigned int dev_id;
2460 int ret; 2531 int ret;
2461 2532
2462 /* 2533 /*
@@ -2467,9 +2538,24 @@ static int sci_probe(struct platform_device *dev)
2467 if (is_early_platform_device(dev)) 2538 if (is_early_platform_device(dev))
2468 return sci_probe_earlyprintk(dev); 2539 return sci_probe_earlyprintk(dev);
2469 2540
2541 if (dev->dev.of_node) {
2542 p = sci_parse_dt(dev, &dev_id);
2543 if (p == NULL)
2544 return -EINVAL;
2545 } else {
2546 p = dev->dev.platform_data;
2547 if (p == NULL) {
2548 dev_err(&dev->dev, "no platform data supplied\n");
2549 return -EINVAL;
2550 }
2551
2552 dev_id = dev->id;
2553 }
2554
2555 sp = &sci_ports[dev_id];
2470 platform_set_drvdata(dev, sp); 2556 platform_set_drvdata(dev, sp);
2471 2557
2472 ret = sci_probe_single(dev, dev->id, p, sp); 2558 ret = sci_probe_single(dev, dev_id, p, sp);
2473 if (ret) 2559 if (ret)
2474 return ret; 2560 return ret;
2475 2561
@@ -2521,6 +2607,7 @@ static struct platform_driver sci_driver = {
2521 .name = "sh-sci", 2607 .name = "sh-sci",
2522 .owner = THIS_MODULE, 2608 .owner = THIS_MODULE,
2523 .pm = &sci_dev_pm_ops, 2609 .pm = &sci_dev_pm_ops,
2610 .of_match_table = of_match_ptr(of_sci_match),
2524 }, 2611 },
2525}; 2612};
2526 2613
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
index c6c325e4d80d..110b4b9ebeaa 100644
--- a/drivers/usb/host/r8a66597-hcd.c
+++ b/drivers/usb/host/r8a66597-hcd.c
@@ -94,7 +94,7 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
94 int i = 0; 94 int i = 0;
95 95
96 if (r8a66597->pdata->on_chip) { 96 if (r8a66597->pdata->on_chip) {
97 clk_enable(r8a66597->clk); 97 clk_prepare_enable(r8a66597->clk);
98 do { 98 do {
99 r8a66597_write(r8a66597, SCKE, SYSCFG0); 99 r8a66597_write(r8a66597, SCKE, SYSCFG0);
100 tmp = r8a66597_read(r8a66597, SYSCFG0); 100 tmp = r8a66597_read(r8a66597, SYSCFG0);
@@ -138,7 +138,7 @@ static void r8a66597_clock_disable(struct r8a66597 *r8a66597)
138 udelay(1); 138 udelay(1);
139 139
140 if (r8a66597->pdata->on_chip) { 140 if (r8a66597->pdata->on_chip) {
141 clk_disable(r8a66597->clk); 141 clk_disable_unprepare(r8a66597->clk);
142 } else { 142 } else {
143 r8a66597_bclr(r8a66597, PLLC, SYSCFG0); 143 r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
144 r8a66597_bclr(r8a66597, XCKE, SYSCFG0); 144 r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index 37752832b770..8546c8dccd51 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -40,8 +40,6 @@
40#include <linux/usb/msm_hsusb_hw.h> 40#include <linux/usb/msm_hsusb_hw.h>
41#include <linux/regulator/consumer.h> 41#include <linux/regulator/consumer.h>
42 42
43#include <mach/clk.h>
44
45#define MSM_USB_BASE (motg->regs) 43#define MSM_USB_BASE (motg->regs)
46#define DRIVER_NAME "msm_otg" 44#define DRIVER_NAME "msm_otg"
47 45
@@ -308,33 +306,30 @@ static void ulpi_init(struct msm_otg *motg)
308 306
309static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert) 307static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
310{ 308{
311 int ret; 309 int ret = 0;
310
311 if (!motg->pdata->link_clk_reset)
312 return ret;
313
314 ret = motg->pdata->link_clk_reset(motg->clk, assert);
315 if (ret)
316 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
317 assert ? "assert" : "deassert");
312 318
313 if (assert) {
314 ret = clk_reset(motg->clk, CLK_RESET_ASSERT);
315 if (ret)
316 dev_err(motg->phy.dev, "usb hs_clk assert failed\n");
317 } else {
318 ret = clk_reset(motg->clk, CLK_RESET_DEASSERT);
319 if (ret)
320 dev_err(motg->phy.dev, "usb hs_clk deassert failed\n");
321 }
322 return ret; 319 return ret;
323} 320}
324 321
325static int msm_otg_phy_clk_reset(struct msm_otg *motg) 322static int msm_otg_phy_clk_reset(struct msm_otg *motg)
326{ 323{
327 int ret; 324 int ret = 0;
328 325
329 ret = clk_reset(motg->phy_reset_clk, CLK_RESET_ASSERT); 326 if (!motg->pdata->phy_clk_reset)
330 if (ret) {
331 dev_err(motg->phy.dev, "usb phy clk assert failed\n");
332 return ret; 327 return ret;
333 } 328
334 usleep_range(10000, 12000); 329 ret = motg->pdata->phy_clk_reset(motg->phy_reset_clk);
335 ret = clk_reset(motg->phy_reset_clk, CLK_RESET_DEASSERT);
336 if (ret) 330 if (ret)
337 dev_err(motg->phy.dev, "usb phy clk deassert failed\n"); 331 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
332
338 return ret; 333 return ret;
339} 334}
340 335
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index dd625cca1ae5..12591f6596ef 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -247,7 +247,7 @@ MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);
247 247
248static struct platform_driver platform_wdt_driver = { 248static struct platform_driver platform_wdt_driver = {
249 .driver = { 249 .driver = {
250 .name = "watchdog", 250 .name = "davinci-wdt",
251 .owner = THIS_MODULE, 251 .owner = THIS_MODULE,
252 .of_match_table = davinci_wdt_of_match, 252 .of_match_table = davinci_wdt_of_match,
253 }, 253 },
@@ -267,4 +267,4 @@ MODULE_PARM_DESC(heartbeat,
267 __MODULE_STRING(DEFAULT_HEARTBEAT)); 267 __MODULE_STRING(DEFAULT_HEARTBEAT));
268 268
269MODULE_LICENSE("GPL"); 269MODULE_LICENSE("GPL");
270MODULE_ALIAS("platform:watchdog"); 270MODULE_ALIAS("platform:davinci-wdt");
diff --git a/include/linux/platform_data/gpio-davinci.h b/include/linux/platform_data/gpio-davinci.h
index 6efd20264585..fbe2f7535741 100644
--- a/include/linux/platform_data/gpio-davinci.h
+++ b/include/linux/platform_data/gpio-davinci.h
@@ -28,13 +28,12 @@ enum davinci_gpio_type {
28struct davinci_gpio_platform_data { 28struct davinci_gpio_platform_data {
29 u32 ngpio; 29 u32 ngpio;
30 u32 gpio_unbanked; 30 u32 gpio_unbanked;
31 u32 intc_irq_num;
32}; 31};
33 32
34 33
35struct davinci_gpio_controller { 34struct davinci_gpio_controller {
36 struct gpio_chip chip; 35 struct gpio_chip chip;
37 int irq_base; 36 struct irq_domain *irq_domain;
38 /* Serialize access to GPIO registers */ 37 /* Serialize access to GPIO registers */
39 spinlock_t lock; 38 spinlock_t lock;
40 void __iomem *regs; 39 void __iomem *regs;
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index af414e1895a5..22b3640c9424 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -10,15 +10,6 @@
10 10
11#define SCIx_NOT_SUPPORTED (-1) 11#define SCIx_NOT_SUPPORTED (-1)
12 12
13enum {
14 SCBRR_ALGO_NONE, /* Compute sampling rate in the driver */
15 SCBRR_ALGO_1, /* clk / (16 * bps) */
16 SCBRR_ALGO_2, /* DIV_ROUND_CLOSEST(clk, 32 * bps) - 1 */
17 SCBRR_ALGO_3, /* clk / (8 * bps) */
18 SCBRR_ALGO_4, /* DIV_ROUND_CLOSEST(clk, 16 * bps) - 1 */
19 SCBRR_ALGO_6, /* HSCIF variable sample rate algorithm */
20};
21
22#define SCSCR_TIE (1 << 7) 13#define SCSCR_TIE (1 << 7)
23#define SCSCR_RIE (1 << 6) 14#define SCSCR_RIE (1 << 6)
24#define SCSCR_TE (1 << 5) 15#define SCSCR_TE (1 << 5)
@@ -59,17 +50,6 @@ enum {
59/* HSSRR HSCIF */ 50/* HSSRR HSCIF */
60#define HSCIF_SRE 0x8000 51#define HSCIF_SRE 0x8000
61 52
62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73enum { 53enum {
74 SCIx_PROBE_REGTYPE, 54 SCIx_PROBE_REGTYPE,
75 55
@@ -88,19 +68,6 @@ enum {
88 SCIx_NR_REGTYPES, 68 SCIx_NR_REGTYPES,
89}; 69};
90 70
91#define SCIx_IRQ_MUXED(irq) \
92{ \
93 [SCIx_ERI_IRQ] = (irq), \
94 [SCIx_RXI_IRQ] = (irq), \
95 [SCIx_TXI_IRQ] = (irq), \
96 [SCIx_BRI_IRQ] = (irq), \
97}
98
99#define SCIx_IRQ_IS_MUXED(port) \
100 ((port)->irqs[SCIx_ERI_IRQ] == \
101 (port)->irqs[SCIx_RXI_IRQ]) || \
102 ((port)->irqs[SCIx_ERI_IRQ] && \
103 ((port)->irqs[SCIx_RXI_IRQ] < 0))
104/* 71/*
105 * SCI register subset common for all port types. 72 * SCI register subset common for all port types.
106 * Not all registers will exist on all parts. 73 * Not all registers will exist on all parts.
@@ -129,14 +96,11 @@ struct plat_sci_port_ops {
129 * Platform device specific platform_data struct 96 * Platform device specific platform_data struct
130 */ 97 */
131struct plat_sci_port { 98struct plat_sci_port {
132 unsigned long mapbase; /* resource base */
133 unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
134 unsigned int type; /* SCI / SCIF / IRDA / HSCIF */ 99 unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
135 upf_t flags; /* UPF_* flags */ 100 upf_t flags; /* UPF_* flags */
136 unsigned long capabilities; /* Port features/capabilities */ 101 unsigned long capabilities; /* Port features/capabilities */
137 102
138 unsigned int sampling_rate; 103 unsigned int sampling_rate;
139 unsigned int scbrr_algo_id; /* SCBRR calculation algo */
140 unsigned int scscr; /* SCSCR initialization */ 104 unsigned int scscr; /* SCSCR initialization */
141 105
142 /* 106 /*
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 22a396c13f3a..32754835a39b 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -20,6 +20,7 @@
20 20
21#include <linux/types.h> 21#include <linux/types.h>
22#include <linux/usb/otg.h> 22#include <linux/usb/otg.h>
23#include <linux/clk.h>
23 24
24/** 25/**
25 * Supported USB modes 26 * Supported USB modes
@@ -135,6 +136,8 @@ struct msm_otg_platform_data {
135 enum msm_usb_phy_type phy_type; 136 enum msm_usb_phy_type phy_type;
136 void (*setup_gpio)(enum usb_otg_state state); 137 void (*setup_gpio)(enum usb_otg_state state);
137 char *pclk_src_name; 138 char *pclk_src_name;
139 int (*link_clk_reset)(struct clk *link_clk, bool assert);
140 int (*phy_clk_reset)(struct clk *phy_clk);
138}; 141};
139 142
140/** 143/**
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 17:05:59 -0500