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authorVille Syrjälä <ville.syrjala@linux.intel.com>2013-12-05 08:51:34 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-12-17 07:17:54 -0500
commit0ba22e26fe47b2a216e5438292aeeb8e015e9d64 (patch)
treee5d6286924e5b91f21181a431949c4ac63cd11c5
parentfacd619b8869b308e02104a200abf6f9d7cddcab (diff)
drm/i915: Don't merge LP1+ watermarks on ILK/SNB/IVB when multiple pipes are enabled
Multi-pipe LP1+ watermarks are a HSW+ feature, so let's not do it on earlier generations. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c43cf138c871..a65d8816c1e6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2690,11 +2690,17 @@ static void ilk_merge_wm_level(struct drm_device *dev,
2690 * Merge all low power watermarks for all active pipes. 2690 * Merge all low power watermarks for all active pipes.
2691 */ 2691 */
2692static void ilk_wm_merge(struct drm_device *dev, 2692static void ilk_wm_merge(struct drm_device *dev,
2693 const struct intel_wm_config *config,
2693 const struct hsw_wm_maximums *max, 2694 const struct hsw_wm_maximums *max,
2694 struct intel_pipe_wm *merged) 2695 struct intel_pipe_wm *merged)
2695{ 2696{
2696 int level, max_level = ilk_wm_max_level(dev); 2697 int level, max_level = ilk_wm_max_level(dev);
2697 2698
2699 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2700 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2701 config->num_pipes_active > 1)
2702 return;
2703
2698 merged->fbc_wm_enabled = true; 2704 merged->fbc_wm_enabled = true;
2699 2705
2700 /* merge each WM1+ level */ 2706 /* merge each WM1+ level */
@@ -3000,13 +3006,13 @@ static void haswell_update_wm(struct drm_crtc *crtc)
3000 intel_crtc->wm.active = pipe_wm; 3006 intel_crtc->wm.active = pipe_wm;
3001 3007
3002 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); 3008 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3003 ilk_wm_merge(dev, &max, &lp_wm_1_2); 3009 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3004 3010
3005 /* 5/6 split only in single pipe config on IVB+ */ 3011 /* 5/6 split only in single pipe config on IVB+ */
3006 if (INTEL_INFO(dev)->gen >= 7 && 3012 if (INTEL_INFO(dev)->gen >= 7 &&
3007 config.num_pipes_active == 1 && config.sprites_enabled) { 3013 config.num_pipes_active == 1 && config.sprites_enabled) {
3008 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); 3014 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3009 ilk_wm_merge(dev, &max, &lp_wm_5_6); 3015 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3010 3016
3011 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); 3017 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3012 } else { 3018 } else {