Merge branch 'clk-msm8996' into clk-next

* clk-msm8996:
  clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver
  clk: qcom: Add gfx3d ping-pong PLL frequency switching
  clk: qcom: Add MSM8996 Global Clock Control (GCC) driver
  clk: qcom: Add Alpha PLL support
  clk: divider: Cap table divider values to 'width' member

13 files changed, 7790 insertions, 4 deletions

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 152dfaab2575..72f82f444091 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -13,6 +13,7 @@ Required properties :
                         "qcom,gcc-msm8974"
                         "qcom,gcc-msm8974pro"
                         "qcom,gcc-msm8974pro-ac"
+                        "qcom,gcc-msm8996"
 
 - reg : shall contain base register location and length
 - #clock-cells : shall contain 1
diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
index 34e7614d5074..8b0f7841af8d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
@@ -9,6 +9,7 @@ Required properties :
                         "qcom,mmcc-msm8660"
                         "qcom,mmcc-msm8960"
                         "qcom,mmcc-msm8974"
+                        "qcom,mmcc-msm8996"
 
 - reg : shall contain base register location and length
 - #clock-cells : shall contain 1
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 3ace102a2a0a..ded3ff4b91b9 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -32,13 +32,14 @@
 
 #define div_mask(width) ((1 << (width)) - 1)
 
-static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
+static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
+                                      u8 width)
 {
-        unsigned int maxdiv = 0;
+        unsigned int maxdiv = 0, mask = div_mask(width);
         const struct clk_div_table *clkt;
 
         for (clkt = table; clkt->div; clkt++)
-                if (clkt->div > maxdiv)
+                if (clkt->div > maxdiv && clkt->val <= mask)
                         maxdiv = clkt->div;
         return maxdiv;
 }
@@ -62,7 +63,7 @@ static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
         if (flags & CLK_DIVIDER_POWER_OF_TWO)
                 return 1 << div_mask(width);
         if (table)
-                return _get_table_maxdiv(table);
+                return _get_table_maxdiv(table, width);
         return div_mask(width) + 1;
 }
 
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ee4c83aab4f4..b552eceec2be 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -106,3 +106,20 @@ config MSM_MMCC_8974
           Support for the multimedia clock controller on msm8974 devices.
           Say Y if you want to support multimedia devices such as display,
           graphics, video encode/decode, camera, etc.
+
+config MSM_GCC_8996
+        tristate "MSM8996 Global Clock Controller"
+        depends on COMMON_CLK_QCOM
+        help
+          Support for the global clock controller on msm8996 devices.
+          Say Y if you want to use peripheral devices such as UART, SPI,
+          i2c, USB, UFS, SD/eMMC, PCIe, etc.
+
+config MSM_MMCC_8996
+        tristate "MSM8996 Multimedia Clock Controller"
+        select MSM_GCC_8996
+        depends on COMMON_CLK_QCOM
+        help
+          Support for the multimedia clock controller on msm8996 devices.
+          Say Y if you want to support multimedia devices such as display,
+          graphics, video encode/decode, camera, etc.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index fe6252349e55..dc4280b85db1 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
 
 clk-qcom-y += common.o
 clk-qcom-y += clk-regmap.o
+clk-qcom-y += clk-alpha-pll.o
 clk-qcom-y += clk-pll.o
 clk-qcom-y += clk-rcg.o
 clk-qcom-y += clk-rcg2.o
@@ -20,5 +21,7 @@ obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
 obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
 obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
 obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
+obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
+obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
new file mode 100644
index 000000000000..e6a03eaf7a93
--- /dev/null
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -0,0 +1,355 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/export.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/delay.h>
+
+#include "clk-alpha-pll.h"
+
+#define PLL_MODE                0x00
+# define PLL_OUTCTRL            BIT(0)
+# define PLL_BYPASSNL           BIT(1)
+# define PLL_RESET_N            BIT(2)
+# define PLL_LOCK_COUNT_SHIFT   8
+# define PLL_LOCK_COUNT_MASK    0x3f
+# define PLL_BIAS_COUNT_SHIFT   14
+# define PLL_BIAS_COUNT_MASK    0x3f
+# define PLL_VOTE_FSM_ENA       BIT(20)
+# define PLL_VOTE_FSM_RESET     BIT(21)
+# define PLL_ACTIVE_FLAG        BIT(30)
+# define PLL_LOCK_DET           BIT(31)
+
+#define PLL_L_VAL               0x04
+#define PLL_ALPHA_VAL           0x08
+#define PLL_ALPHA_VAL_U         0x0c
+
+#define PLL_USER_CTL            0x10
+# define PLL_POST_DIV_SHIFT     8
+# define PLL_POST_DIV_MASK      0xf
+# define PLL_ALPHA_EN           BIT(24)
+# define PLL_VCO_SHIFT          20
+# define PLL_VCO_MASK           0x3
+
+#define PLL_USER_CTL_U          0x14
+
+#define PLL_CONFIG_CTL          0x18
+#define PLL_TEST_CTL            0x1c
+#define PLL_TEST_CTL_U          0x20
+#define PLL_STATUS              0x24
+
+/*
+ * Even though 40 bits are present, use only 32 for ease of calculation.
+ */
+#define ALPHA_REG_BITWIDTH      40
+#define ALPHA_BITWIDTH          32
+
+#define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
+                                           struct clk_alpha_pll, clkr)
+
+#define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
+                                           struct clk_alpha_pll_postdiv, clkr)
+
+static int wait_for_pll(struct clk_alpha_pll *pll)
+{
+        u32 val, mask, off;
+        int count;
+        int ret;
+        const char *name = clk_hw_get_name(&pll->clkr.hw);
+
+        off = pll->offset;
+        ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+        if (ret)
+                return ret;
+
+        if (val & PLL_VOTE_FSM_ENA)
+                mask = PLL_ACTIVE_FLAG;
+        else
+                mask = PLL_LOCK_DET;
+
+        /* Wait for pll to enable. */
+        for (count = 100; count > 0; count--) {
+                ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+                if (ret)
+                        return ret;
+                if ((val & mask) == mask)
+                        return 0;
+
+                udelay(1);
+        }
+
+        WARN(1, "%s didn't enable after voting for it!\n", name);
+        return -ETIMEDOUT;
+}
+
+static int clk_alpha_pll_enable(struct clk_hw *hw)
+{
+        int ret;
+        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+        u32 val, mask, off;
+
+        off = pll->offset;
+
+        mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
+        ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+        if (ret)
+                return ret;
+
+        /* If in FSM mode, just vote for it */
+        if (val & PLL_VOTE_FSM_ENA) {
+                ret = clk_enable_regmap(hw);
+                if (ret)
+                        return ret;
+                return wait_for_pll(pll);
+        }
+
+        /* Skip if already enabled */
+        if ((val & mask) == mask)
+                return 0;
+
+        ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+                                 PLL_BYPASSNL, PLL_BYPASSNL);
+        if (ret)
+                return ret;
+
+        /*
+         * H/W requires a 5us delay between disabling the bypass and
+         * de-asserting the reset.
+         */
+        mb();
+        udelay(5);
+
+        ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+                                 PLL_RESET_N, PLL_RESET_N);
+        if (ret)
+                return ret;
+
+        ret = wait_for_pll(pll);
+        if (ret)
+                return ret;
+
+        ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+                                 PLL_OUTCTRL, PLL_OUTCTRL);
+
+        /* Ensure that the write above goes through before returning. */
+        mb();
+        return ret;
+}
+
+static void clk_alpha_pll_disable(struct clk_hw *hw)
+{
+        int ret;
+        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+        u32 val, mask, off;
+
+        off = pll->offset;
+
+        ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+        if (ret)
+                return;
+
+        /* If in FSM mode, just unvote it */
+        if (val & PLL_VOTE_FSM_ENA) {
+                clk_disable_regmap(hw);
+                return;
+        }
+
+        mask = PLL_OUTCTRL;
+        regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
+
+        /* Delay of 2 output clock ticks required until output is disabled */
+        mb();
+        udelay(1);
+
+        mask = PLL_RESET_N | PLL_BYPASSNL;
+        regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
+}
+
+static unsigned long alpha_pll_calc_rate(u64 prate, u32 l, u32 a)
+{
+        return (prate * l) + ((prate * a) >> ALPHA_BITWIDTH);
+}
+
+static unsigned long
+alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a)
+{
+        u64 remainder;
+        u64 quotient;
+
+        quotient = rate;
+        remainder = do_div(quotient, prate);
+        *l = quotient;
+
+        if (!remainder) {
+                *a = 0;
+                return rate;
+        }
+
+        /* Upper ALPHA_BITWIDTH bits of Alpha */
+        quotient = remainder << ALPHA_BITWIDTH;
+        remainder = do_div(quotient, prate);
+
+        if (remainder)
+                quotient++;
+
+        *a = quotient;
+        return alpha_pll_calc_rate(prate, *l, *a);
+}
+
+static const struct pll_vco *
+alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
+{
+        const struct pll_vco *v = pll->vco_table;
+        const struct pll_vco *end = v + pll->num_vco;
+
+        for (; v < end; v++)
+                if (rate >= v->min_freq && rate <= v->max_freq)
+                        return v;
+
+        return NULL;
+}
+
+static unsigned long
+clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+        u32 l, low, high, ctl;
+        u64 a = 0, prate = parent_rate;
+        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+        u32 off = pll->offset;
+
+        regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l);
+
+        regmap_read(pll->clkr.regmap, off + PLL_USER_CTL, &ctl);
+        if (ctl & PLL_ALPHA_EN) {
+                regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL, &low);
+                regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, &high);
+                a = (u64)high << 32 | low;
+                a >>= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
+        }
+
+        return alpha_pll_calc_rate(prate, l, a);
+}
+
+static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+                                  unsigned long prate)
+{
+        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+        const struct pll_vco *vco;
+        u32 l, off = pll->offset;
+        u64 a;
+
+        rate = alpha_pll_round_rate(rate, prate, &l, &a);
+        vco = alpha_pll_find_vco(pll, rate);
+        if (!vco) {
+                pr_err("alpha pll not in a valid vco range\n");
+                return -EINVAL;
+        }
+
+        a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
+
+        regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l);
+        regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL, a);
+        regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a >> 32);
+
+        regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL,
+                           PLL_VCO_MASK << PLL_VCO_SHIFT,
+                           vco->val << PLL_VCO_SHIFT);
+
+        regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL, PLL_ALPHA_EN,
+                           PLL_ALPHA_EN);
+
+        return 0;
+}
+
+static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+                                     unsigned long *prate)
+{
+        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+        u32 l;
+        u64 a;
+        unsigned long min_freq, max_freq;
+
+        rate = alpha_pll_round_rate(rate, *prate, &l, &a);
+        if (alpha_pll_find_vco(pll, rate))
+                return rate;
+
+        min_freq = pll->vco_table[0].min_freq;
+        max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
+
+        return clamp(rate, min_freq, max_freq);
+}
+
+const struct clk_ops clk_alpha_pll_ops = {
+        .enable = clk_alpha_pll_enable,
+        .disable = clk_alpha_pll_disable,
+        .recalc_rate = clk_alpha_pll_recalc_rate,
+        .round_rate = clk_alpha_pll_round_rate,
+        .set_rate = clk_alpha_pll_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
+
+static unsigned long
+clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+        struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+        u32 ctl;
+
+        regmap_read(pll->clkr.regmap, pll->offset + PLL_USER_CTL, &ctl);
+
+        ctl >>= PLL_POST_DIV_SHIFT;
+        ctl &= PLL_POST_DIV_MASK;
+
+        return parent_rate >> fls(ctl);
+}
+
+static const struct clk_div_table clk_alpha_div_table[] = {
+        { 0x0, 1 },
+        { 0x1, 2 },
+        { 0x3, 4 },
+        { 0x7, 8 },
+        { 0xf, 16 },
+        { }
+};
+
+static long
+clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
+                                 unsigned long *prate)
+{
+        struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+
+        return divider_round_rate(hw, rate, prate, clk_alpha_div_table,
+                                  pll->width, CLK_DIVIDER_POWER_OF_TWO);
+}
+
+static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
+                                          unsigned long parent_rate)
+{
+        struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+        int div;
+
+        /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
+        div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
+
+        return regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_USER_CTL,
+                                  PLL_POST_DIV_MASK << PLL_POST_DIV_SHIFT,
+                                  div << PLL_POST_DIV_SHIFT);
+}
+
+const struct clk_ops clk_alpha_pll_postdiv_ops = {
+        .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
+        .round_rate = clk_alpha_pll_postdiv_round_rate,
+        .set_rate = clk_alpha_pll_postdiv_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
new file mode 100644
index 000000000000..90ce2016e1a0
--- /dev/null
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_CLK_ALPHA_PLL_H__
+#define __QCOM_CLK_ALPHA_PLL_H__
+
+#include <linux/clk-provider.h>
+#include "clk-regmap.h"
+
+struct pll_vco {
+        unsigned long min_freq;
+        unsigned long max_freq;
+        u32 val;
+};
+
+/**
+ * struct clk_alpha_pll - phase locked loop (PLL)
+ * @offset: base address of registers
+ * @vco_table: array of VCO settings
+ * @clkr: regmap clock handle
+ */
+struct clk_alpha_pll {
+        u32 offset;
+
+        const struct pll_vco *vco_table;
+        size_t num_vco;
+
+        struct clk_regmap clkr;
+};
+
+/**
+ * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
+ * @offset: base address of registers
+ * @width: width of post-divider
+ * @clkr: regmap clock handle
+ */
+struct clk_alpha_pll_postdiv {
+        u32 offset;
+        u8 width;
+
+        struct clk_regmap clkr;
+};
+
+extern const struct clk_ops clk_alpha_pll_ops;
+extern const struct clk_ops clk_alpha_pll_postdiv_ops;
+
+#endif
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 4b1e94bdf29e..b904c335cda4 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -178,5 +178,6 @@ extern const struct clk_ops clk_edp_pixel_ops;
 extern const struct clk_ops clk_byte_ops;
 extern const struct clk_ops clk_byte2_ops;
 extern const struct clk_ops clk_pixel_ops;
+extern const struct clk_ops clk_gfx3d_ops;
 
 #endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index b544bb302f79..a071bba8018c 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -723,3 +723,90 @@ const struct clk_ops clk_pixel_ops = {
         .determine_rate = clk_pixel_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_pixel_ops);
+
+static int clk_gfx3d_determine_rate(struct clk_hw *hw,
+                                    struct clk_rate_request *req)
+{
+        struct clk_rate_request parent_req = { };
+        struct clk_hw *p2, *p8, *p9, *xo;
+        unsigned long p9_rate;
+        int ret;
+
+        xo = clk_hw_get_parent_by_index(hw, 0);
+        if (req->rate == clk_hw_get_rate(xo)) {
+                req->best_parent_hw = xo;
+                return 0;
+        }
+
+        p9 = clk_hw_get_parent_by_index(hw, 2);
+        p2 = clk_hw_get_parent_by_index(hw, 3);
+        p8 = clk_hw_get_parent_by_index(hw, 4);
+
+        /* PLL9 is a fixed rate PLL */
+        p9_rate = clk_hw_get_rate(p9);
+
+        parent_req.rate = req->rate = min(req->rate, p9_rate);
+        if (req->rate == p9_rate) {
+                req->rate = req->best_parent_rate = p9_rate;
+                req->best_parent_hw = p9;
+                return 0;
+        }
+
+        if (req->best_parent_hw == p9) {
+                /* Are we going back to a previously used rate? */
+                if (clk_hw_get_rate(p8) == req->rate)
+                        req->best_parent_hw = p8;
+                else
+                        req->best_parent_hw = p2;
+        } else if (req->best_parent_hw == p8) {
+                req->best_parent_hw = p2;
+        } else {
+                req->best_parent_hw = p8;
+        }
+
+        ret = __clk_determine_rate(req->best_parent_hw, &parent_req);
+        if (ret)
+                return ret;
+
+        req->rate = req->best_parent_rate = parent_req.rate;
+
+        return 0;
+}
+
+static int clk_gfx3d_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate, u8 index)
+{
+        struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+        u32 cfg;
+        int ret;
+
+        /* Just mux it, we don't use the division or m/n hardware */
+        cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
+        ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
+        if (ret)
+                return ret;
+
+        return update_config(rcg);
+}
+
+static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate,
+                              unsigned long parent_rate)
+{
+        /*
+         * We should never get here; clk_gfx3d_determine_rate() should always
+         * make us use a different parent than what we're currently using, so
+         * clk_gfx3d_set_rate_and_parent() should always be called.
+         */
+        return 0;
+}
+
+const struct clk_ops clk_gfx3d_ops = {
+        .is_enabled = clk_rcg2_is_enabled,
+        .get_parent = clk_rcg2_get_parent,
+        .set_parent = clk_rcg2_set_parent,
+        .recalc_rate = clk_rcg2_recalc_rate,
+        .set_rate = clk_gfx3d_set_rate,
+        .set_rate_and_parent = clk_gfx3d_set_rate_and_parent,
+        .determine_rate = clk_gfx3d_determine_rate,
+};
+EXPORT_SYMBOL_GPL(clk_gfx3d_ops);
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
new file mode 100644
index 000000000000..16d7c323db49
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -0,0 +1,3422 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/qcom,gcc-msm8996.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-alpha-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+        P_XO,
+        P_GPLL0,
+        P_GPLL2,
+        P_GPLL3,
+        P_GPLL1,
+        P_GPLL2_EARLY,
+        P_GPLL0_EARLY_DIV,
+        P_SLEEP_CLK,
+        P_GPLL4,
+        P_AUD_REF_CLK,
+        P_GPLL1_EARLY_DIV
+};
+
+static const struct parent_map gcc_sleep_clk_map[] = {
+        { P_SLEEP_CLK, 5 }
+};
+
+static const char * const gcc_sleep_clk[] = {
+        "sleep_clk"
+};
+
+static const struct parent_map gcc_xo_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 }
+};
+
+static const char * const gcc_xo_gpll0[] = {
+        "xo",
+        "gpll0"
+};
+
+static const struct parent_map gcc_xo_sleep_clk_map[] = {
+        { P_XO, 0 },
+        { P_SLEEP_CLK, 5 }
+};
+
+static const char * const gcc_xo_sleep_clk[] = {
+        "xo",
+        "sleep_clk"
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_GPLL0_EARLY_DIV, 6 }
+};
+
+static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
+        "xo",
+        "gpll0",
+        "gpll0_early_div"
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_GPLL4, 5 }
+};
+
+static const char * const gcc_xo_gpll0_gpll4[] = {
+        "xo",
+        "gpll0",
+        "gpll4"
+};
+
+static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_AUD_REF_CLK, 2 }
+};
+
+static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
+        "xo",
+        "gpll0",
+        "aud_ref_clk"
+};
+
+static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_SLEEP_CLK, 5 },
+        { P_GPLL0_EARLY_DIV, 6 }
+};
+
+static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
+        "xo",
+        "gpll0",
+        "sleep_clk",
+        "gpll0_early_div"
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_GPLL4, 5 },
+        { P_GPLL0_EARLY_DIV, 6 }
+};
+
+static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
+        "xo",
+        "gpll0",
+        "gpll4",
+        "gpll0_early_div"
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_GPLL2, 2 },
+        { P_GPLL3, 3 },
+        { P_GPLL0_EARLY_DIV, 6 }
+};
+
+static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = {
+        "xo",
+        "gpll0",
+        "gpll2",
+        "gpll3",
+        "gpll0_early_div"
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_GPLL1_EARLY_DIV, 3 },
+        { P_GPLL1, 4 },
+        { P_GPLL4, 5 },
+        { P_GPLL0_EARLY_DIV, 6 }
+};
+
+static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
+        "xo",
+        "gpll0",
+        "gpll1_early_div",
+        "gpll1",
+        "gpll4",
+        "gpll0_early_div"
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_GPLL2, 2 },
+        { P_GPLL3, 3 },
+        { P_GPLL1, 4 },
+        { P_GPLL2_EARLY, 5 },
+        { P_GPLL0_EARLY_DIV, 6 }
+};
+
+static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
+        "xo",
+        "gpll0",
+        "gpll2",
+        "gpll3",
+        "gpll1",
+        "gpll2_early",
+        "gpll0_early_div"
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 1 },
+        { P_GPLL2, 2 },
+        { P_GPLL3, 3 },
+        { P_GPLL1, 4 },
+        { P_GPLL4, 5 },
+        { P_GPLL0_EARLY_DIV, 6 }
+};
+
+static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = {
+        "xo",
+        "gpll0",
+        "gpll2",
+        "gpll3",
+        "gpll1",
+        "gpll4",
+        "gpll0_early_div"
+};
+
+static struct clk_fixed_factor xo = {
+        .mult = 1,
+        .div = 1,
+        .hw.init = &(struct clk_init_data){
+                .name = "xo",
+                .parent_names = (const char *[]){ "xo_board" },
+                .num_parents = 1,
+                .ops = &clk_fixed_factor_ops,
+        },
+};
+
+static struct clk_alpha_pll gpll0_early = {
+        .offset = 0x00000,
+        .clkr = {
+                .enable_reg = 0x52000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpll0_early",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_alpha_pll_ops,
+                },
+        },
+};
+
+static struct clk_fixed_factor gpll0_early_div = {
+        .mult = 1,
+        .div = 2,
+        .hw.init = &(struct clk_init_data){
+                .name = "gpll0_early_div",
+                .parent_names = (const char *[]){ "gpll0_early" },
+                .num_parents = 1,
+                .ops = &clk_fixed_factor_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll0 = {
+        .offset = 0x00000,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll0",
+                .parent_names = (const char *[]){ "gpll0_early" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll gpll4_early = {
+        .offset = 0x77000,
+        .clkr = {
+                .enable_reg = 0x52000,
+                .enable_mask = BIT(4),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpll4_early",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_alpha_pll_ops,
+                },
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll4 = {
+        .offset = 0x77000,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll4",
+                .parent_names = (const char *[]){ "gpll4_early" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_system_noc_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+        F(100000000, P_GPLL0, 6, 0, 0),
+        F(150000000, P_GPLL0, 4, 0, 0),
+        F(200000000, P_GPLL0, 3, 0, 0),
+        F(240000000, P_GPLL0, 2.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 system_noc_clk_src = {
+        .cmd_rcgr = 0x0401c,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
+        .freq_tbl = ftbl_system_noc_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "system_noc_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_config_noc_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(37500000, P_GPLL0, 16, 0, 0),
+        F(75000000, P_GPLL0, 8, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 config_noc_clk_src = {
+        .cmd_rcgr = 0x0500c,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_config_noc_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "config_noc_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(37500000, P_GPLL0, 16, 0, 0),
+        F(50000000, P_GPLL0, 12, 0, 0),
+        F(75000000, P_GPLL0, 8, 0, 0),
+        F(100000000, P_GPLL0, 6, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 periph_noc_clk_src = {
+        .cmd_rcgr = 0x06014,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_periph_noc_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "periph_noc_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(120000000, P_GPLL0, 5, 0, 0),
+        F(150000000, P_GPLL0, 4, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 usb30_master_clk_src = {
+        .cmd_rcgr = 0x0f014,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
+        .freq_tbl = ftbl_usb30_master_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "usb30_master_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll0_early_div,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 usb30_mock_utmi_clk_src = {
+        .cmd_rcgr = 0x0f028,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
+        .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "usb30_mock_utmi_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll0_early_div,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
+        F(1200000, P_XO, 16, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 usb3_phy_aux_clk_src = {
+        .cmd_rcgr = 0x5000c,
+        .hid_width = 5,
+        .parent_map = gcc_xo_sleep_clk_map,
+        .freq_tbl = ftbl_usb3_phy_aux_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "usb3_phy_aux_clk_src",
+                .parent_names = gcc_xo_sleep_clk,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
+        F(120000000, P_GPLL0, 5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 usb20_master_clk_src = {
+        .cmd_rcgr = 0x12010,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
+        .freq_tbl = ftbl_usb20_master_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "usb20_master_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll0_early_div,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 usb20_mock_utmi_clk_src = {
+        .cmd_rcgr = 0x12024,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
+        .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "usb20_mock_utmi_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll0_early_div,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
+        F(144000, P_XO, 16, 3, 25),
+        F(400000, P_XO, 12, 1, 4),
+        F(20000000, P_GPLL0, 15, 1, 2),
+        F(25000000, P_GPLL0, 12, 1, 2),
+        F(50000000, P_GPLL0, 12, 0, 0),
+        F(96000000, P_GPLL4, 4, 0, 0),
+        F(192000000, P_GPLL4, 2, 0, 0),
+        F(384000000, P_GPLL4, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 sdcc1_apps_clk_src = {
+        .cmd_rcgr = 0x13010,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
+        .freq_tbl = ftbl_sdcc1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "sdcc1_apps_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 sdcc1_ice_core_clk_src = {
+        .cmd_rcgr = 0x13024,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "sdcc1_ice_core_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
+        F(144000, P_XO, 16, 3, 25),
+        F(400000, P_XO, 12, 1, 4),
+        F(20000000, P_GPLL0, 15, 1, 2),
+        F(25000000, P_GPLL0, 12, 1, 2),
+        F(50000000, P_GPLL0, 12, 0, 0),
+        F(100000000, P_GPLL0, 6, 0, 0),
+        F(200000000, P_GPLL0, 3, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 sdcc2_apps_clk_src = {
+        .cmd_rcgr = 0x14010,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll4_map,
+        .freq_tbl = ftbl_sdcc2_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "sdcc2_apps_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll4,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 sdcc3_apps_clk_src = {
+        .cmd_rcgr = 0x15010,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll4_map,
+        .freq_tbl = ftbl_sdcc2_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "sdcc3_apps_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll4,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
+        F(144000, P_XO, 16, 3, 25),
+        F(400000, P_XO, 12, 1, 4),
+        F(20000000, P_GPLL0, 15, 1, 2),
+        F(25000000, P_GPLL0, 12, 1, 2),
+        F(50000000, P_GPLL0, 12, 0, 0),
+        F(100000000, P_GPLL0, 6, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 sdcc4_apps_clk_src = {
+        .cmd_rcgr = 0x16010,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_sdcc4_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "sdcc4_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
+        F(960000, P_XO, 10, 1, 2),
+        F(4800000, P_XO, 4, 0, 0),
+        F(9600000, P_XO, 2, 0, 0),
+        F(15000000, P_GPLL0, 10, 1, 4),
+        F(19200000, P_XO, 1, 0, 0),
+        F(25000000, P_GPLL0, 12, 1, 2),
+        F(50000000, P_GPLL0, 12, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+        .cmd_rcgr = 0x1900c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup1_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(50000000, P_GPLL0, 12, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x19020,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup1_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
+        F(3686400, P_GPLL0, 1, 96, 15625),
+        F(7372800, P_GPLL0, 1, 192, 15625),
+        F(14745600, P_GPLL0, 1, 384, 15625),
+        F(16000000, P_GPLL0, 5, 2, 15),
+        F(19200000, P_XO, 1, 0, 0),
+        F(24000000, P_GPLL0, 5, 1, 5),
+        F(32000000, P_GPLL0, 1, 4, 75),
+        F(40000000, P_GPLL0, 15, 0, 0),
+        F(46400000, P_GPLL0, 1, 29, 375),
+        F(48000000, P_GPLL0, 12.5, 0, 0),
+        F(51200000, P_GPLL0, 1, 32, 375),
+        F(56000000, P_GPLL0, 1, 7, 75),
+        F(58982400, P_GPLL0, 1, 1536, 15625),
+        F(60000000, P_GPLL0, 10, 0, 0),
+        F(63157895, P_GPLL0, 9.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+        .cmd_rcgr = 0x1a00c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_uart1_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+        .cmd_rcgr = 0x1b00c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup2_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x1b020,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup2_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+        .cmd_rcgr = 0x1c00c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_uart2_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+        .cmd_rcgr = 0x1d00c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup3_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x1d020,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup3_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
+        .cmd_rcgr = 0x1e00c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_uart3_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
+        .cmd_rcgr = 0x1f00c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup4_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x1f020,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup4_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
+        .cmd_rcgr = 0x2000c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_uart4_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
+        .cmd_rcgr = 0x2100c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup5_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x21020,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup5_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
+        .cmd_rcgr = 0x2200c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_uart5_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
+        .cmd_rcgr = 0x2300c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup6_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x23020,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup6_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
+        .cmd_rcgr = 0x2400c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_uart6_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
+        .cmd_rcgr = 0x2600c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup1_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x26020,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup1_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
+        .cmd_rcgr = 0x2700c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_uart1_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
+        .cmd_rcgr = 0x2800c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup2_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x28020,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup2_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
+        .cmd_rcgr = 0x2900c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_uart2_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
+        .cmd_rcgr = 0x2a00c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup3_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x2a020,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup3_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
+        .cmd_rcgr = 0x2b00c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_uart3_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
+        .cmd_rcgr = 0x2c00c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup4_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x2c020,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup4_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
+        .cmd_rcgr = 0x2d00c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_uart4_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
+        .cmd_rcgr = 0x2e00c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup5_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x2e020,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup5_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
+        .cmd_rcgr = 0x2f00c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_uart5_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
+        .cmd_rcgr = 0x3000c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup6_spi_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x30020,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup6_i2c_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
+        .cmd_rcgr = 0x3100c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_uart6_apps_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_pdm2_clk_src[] = {
+        F(60000000, P_GPLL0, 10, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 pdm2_clk_src = {
+        .cmd_rcgr = 0x33010,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_pdm2_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "pdm2_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
+        F(105495, P_XO, 1, 1, 182),
+        { }
+};
+
+static struct clk_rcg2 tsif_ref_clk_src = {
+        .cmd_rcgr = 0x36010,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_aud_ref_clk_map,
+        .freq_tbl = ftbl_tsif_ref_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "tsif_ref_clk_src",
+                .parent_names = gcc_xo_gpll0_aud_ref_clk,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_sleep_clk_src = {
+        .cmd_rcgr = 0x43014,
+        .hid_width = 5,
+        .parent_map = gcc_sleep_clk_map,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_sleep_clk_src",
+                .parent_names = gcc_sleep_clk,
+                .num_parents = 1,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 hmss_rbcpr_clk_src = {
+        .cmd_rcgr = 0x48040,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "hmss_rbcpr_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 hmss_gpll0_clk_src = {
+        .cmd_rcgr = 0x48058,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "hmss_gpll0_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gp1_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(100000000, P_GPLL0, 6, 0, 0),
+        F(200000000, P_GPLL0, 3, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gp1_clk_src = {
+        .cmd_rcgr = 0x64004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
+        .freq_tbl = ftbl_gp1_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gp1_clk_src",
+                .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gp2_clk_src = {
+        .cmd_rcgr = 0x65004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
+        .freq_tbl = ftbl_gp1_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gp2_clk_src",
+                .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gp3_clk_src = {
+        .cmd_rcgr = 0x66004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
+        .freq_tbl = ftbl_gp1_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gp3_clk_src",
+                .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
+        F(1010526, P_XO, 1, 1, 19),
+        { }
+};
+
+static struct clk_rcg2 pcie_aux_clk_src = {
+        .cmd_rcgr = 0x6c000,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_xo_sleep_clk_map,
+        .freq_tbl = ftbl_pcie_aux_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "pcie_aux_clk_src",
+                .parent_names = gcc_xo_sleep_clk,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
+        F(100000000, P_GPLL0, 6, 0, 0),
+        F(200000000, P_GPLL0, 3, 0, 0),
+        F(240000000, P_GPLL0, 2.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 ufs_axi_clk_src = {
+        .cmd_rcgr = 0x75024,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .freq_tbl = ftbl_ufs_axi_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "ufs_axi_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 ufs_ice_core_clk_src = {
+        .cmd_rcgr = 0x76014,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_map,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "ufs_ice_core_clk_src",
+                .parent_names = gcc_xo_gpll0,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 qspi_ser_clk_src = {
+        .cmd_rcgr = 0x8b00c,
+        .hid_width = 5,
+        .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "qspi_ser_clk_src",
+                .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
+                .num_parents = 6,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
+        .halt_reg = 0x0f03c,
+        .clkr = {
+                .enable_reg = 0x0f03c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sys_noc_usb3_axi_clk",
+                        .parent_names = (const char *[]){ "usb30_master_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
+        .halt_reg = 0x75038,
+        .clkr = {
+                .enable_reg = 0x75038,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sys_noc_ufs_axi_clk",
+                        .parent_names = (const char *[]){ "ufs_axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
+        .halt_reg = 0x6010,
+        .clkr = {
+                .enable_reg = 0x6010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_periph_noc_usb20_ahb_clk",
+                        .parent_names = (const char *[]){ "usb20_master_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
+        .halt_reg = 0x9008,
+        .clkr = {
+                .enable_reg = 0x9008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mmss_noc_cfg_ahb_clk",
+                        .parent_names = (const char *[]){ "config_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mmss_bimc_gfx_clk = {
+        .halt_reg = 0x9010,
+        .clkr = {
+                .enable_reg = 0x9010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mmss_bimc_gfx_clk",
+                        .flags = CLK_SET_RATE_PARENT | CLK_IS_ROOT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_master_clk = {
+        .halt_reg = 0x0f008,
+        .clkr = {
+                .enable_reg = 0x0f008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_master_clk",
+                        .parent_names = (const char *[]){ "usb30_master_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_sleep_clk = {
+        .halt_reg = 0x0f00c,
+        .clkr = {
+                .enable_reg = 0x0f00c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_sleep_clk",
+                        .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_mock_utmi_clk = {
+        .halt_reg = 0x0f010,
+        .clkr = {
+                .enable_reg = 0x0f010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_mock_utmi_clk",
+                        .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_phy_aux_clk = {
+        .halt_reg = 0x50000,
+        .clkr = {
+                .enable_reg = 0x50000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_phy_aux_clk",
+                        .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_phy_pipe_clk = {
+        .halt_reg = 0x50004,
+        .clkr = {
+                .enable_reg = 0x50004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_phy_pipe_clk",
+                        .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb20_master_clk = {
+        .halt_reg = 0x12004,
+        .clkr = {
+                .enable_reg = 0x12004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb20_master_clk",
+                        .parent_names = (const char *[]){ "usb20_master_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb20_sleep_clk = {
+        .halt_reg = 0x12008,
+        .clkr = {
+                .enable_reg = 0x12008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb20_sleep_clk",
+                        .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb20_mock_utmi_clk = {
+        .halt_reg = 0x1200c,
+        .clkr = {
+                .enable_reg = 0x1200c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb20_mock_utmi_clk",
+                        .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
+        .halt_reg = 0x6a004,
+        .clkr = {
+                .enable_reg = 0x6a004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb_phy_cfg_ahb2phy_clk",
+                        .parent_names = (const char *[]){ "periph_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+        .halt_reg = 0x13004,
+        .clkr = {
+                .enable_reg = 0x13004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc1_apps_clk",
+                        .parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+        .halt_reg = 0x13008,
+        .clkr = {
+                .enable_reg = 0x13008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc1_ahb_clk",
+                        .parent_names = (const char *[]){ "periph_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc1_ice_core_clk = {
+        .halt_reg = 0x13038,
+        .clkr = {
+                .enable_reg = 0x13038,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc1_ice_core_clk",
+                        .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+        .halt_reg = 0x14004,
+        .clkr = {
+                .enable_reg = 0x14004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc2_apps_clk",
+                        .parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc2_ahb_clk = {
+        .halt_reg = 0x14008,
+        .clkr = {
+                .enable_reg = 0x14008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc2_ahb_clk",
+                        .parent_names = (const char *[]){ "periph_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc3_apps_clk = {
+        .halt_reg = 0x15004,
+        .clkr = {
+                .enable_reg = 0x15004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc3_apps_clk",
+                        .parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc3_ahb_clk = {
+        .halt_reg = 0x15008,
+        .clkr = {
+                .enable_reg = 0x15008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc3_ahb_clk",
+                        .parent_names = (const char *[]){ "periph_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc4_apps_clk = {
+        .halt_reg = 0x16004,
+        .clkr = {
+                .enable_reg = 0x16004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc4_apps_clk",
+                        .parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc4_ahb_clk = {
+        .halt_reg = 0x16008,
+        .clkr = {
+                .enable_reg = 0x16008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc4_ahb_clk",
+                        .parent_names = (const char *[]){ "periph_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+        .halt_reg = 0x17004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(17),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_ahb_clk",
+                        .parent_names = (const char *[]){ "periph_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_sleep_clk = {
+        .halt_reg = 0x17008,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(16),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_sleep_clk",
+                        .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+        .halt_reg = 0x19004,
+        .clkr = {
+                .enable_reg = 0x19004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup1_spi_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+        .halt_reg = 0x19008,
+        .clkr = {
+                .enable_reg = 0x19008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup1_i2c_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+        .halt_reg = 0x1a004,
+        .clkr = {
+                .enable_reg = 0x1a004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_uart1_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+        .halt_reg = 0x1b004,
+        .clkr = {
+                .enable_reg = 0x1b004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup2_spi_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+        .halt_reg = 0x1b008,
+        .clkr = {
+                .enable_reg = 0x1b008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup2_i2c_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+        .halt_reg = 0x1c004,
+        .clkr = {
+                .enable_reg = 0x1c004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_uart2_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+        .halt_reg = 0x1d004,
+        .clkr = {
+                .enable_reg = 0x1d004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup3_spi_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+        .halt_reg = 0x1d008,
+        .clkr = {
+                .enable_reg = 0x1d008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup3_i2c_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_uart3_apps_clk = {
+        .halt_reg = 0x1e004,
+        .clkr = {
+                .enable_reg = 0x1e004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_uart3_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
+        .halt_reg = 0x1f004,
+        .clkr = {
+                .enable_reg = 0x1f004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup4_spi_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
+        .halt_reg = 0x1f008,
+        .clkr = {
+                .enable_reg = 0x1f008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup4_i2c_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_uart4_apps_clk = {
+        .halt_reg = 0x20004,
+        .clkr = {
+                .enable_reg = 0x20004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_uart4_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
+        .halt_reg = 0x21004,
+        .clkr = {
+                .enable_reg = 0x21004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup5_spi_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
+        .halt_reg = 0x21008,
+        .clkr = {
+                .enable_reg = 0x21008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup5_i2c_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_uart5_apps_clk = {
+        .halt_reg = 0x22004,
+        .clkr = {
+                .enable_reg = 0x22004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_uart5_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
+        .halt_reg = 0x23004,
+        .clkr = {
+                .enable_reg = 0x23004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup6_spi_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
+        .halt_reg = 0x23008,
+        .clkr = {
+                .enable_reg = 0x23008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup6_i2c_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_uart6_apps_clk = {
+        .halt_reg = 0x24004,
+        .clkr = {
+                .enable_reg = 0x24004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_uart6_apps_clk",
+                        .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_ahb_clk = {
+        .halt_reg = 0x25004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(15),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_ahb_clk",
+                        .parent_names = (const char *[]){ "periph_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_sleep_clk = {
+        .halt_reg = 0x25008,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(14),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_sleep_clk",
+                        .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
+        .halt_reg = 0x26004,
+        .clkr = {
+                .enable_reg = 0x26004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup1_spi_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
+        .halt_reg = 0x26008,
+        .clkr = {
+                .enable_reg = 0x26008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup1_i2c_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_uart1_apps_clk = {
+        .halt_reg = 0x27004,
+        .clkr = {
+                .enable_reg = 0x27004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_uart1_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
+        .halt_reg = 0x28004,
+        .clkr = {
+                .enable_reg = 0x28004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup2_spi_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
+        .halt_reg = 0x28008,
+        .clkr = {
+                .enable_reg = 0x28008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup2_i2c_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_uart2_apps_clk = {
+        .halt_reg = 0x29004,
+        .clkr = {
+                .enable_reg = 0x29004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_uart2_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
+        .halt_reg = 0x2a004,
+        .clkr = {
+                .enable_reg = 0x2a004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup3_spi_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
+        .halt_reg = 0x2a008,
+        .clkr = {
+                .enable_reg = 0x2a008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup3_i2c_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_uart3_apps_clk = {
+        .halt_reg = 0x2b004,
+        .clkr = {
+                .enable_reg = 0x2b004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_uart3_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
+        .halt_reg = 0x2c004,
+        .clkr = {
+                .enable_reg = 0x2c004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup4_spi_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
+        .halt_reg = 0x2c008,
+        .clkr = {
+                .enable_reg = 0x2c008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup4_i2c_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_uart4_apps_clk = {
+        .halt_reg = 0x2d004,
+        .clkr = {
+                .enable_reg = 0x2d004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_uart4_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
+        .halt_reg = 0x2e004,
+        .clkr = {
+                .enable_reg = 0x2e004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup5_spi_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
+        .halt_reg = 0x2e008,
+        .clkr = {
+                .enable_reg = 0x2e008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup5_i2c_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_uart5_apps_clk = {
+        .halt_reg = 0x2f004,
+        .clkr = {
+                .enable_reg = 0x2f004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_uart5_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
+        .halt_reg = 0x30004,
+        .clkr = {
+                .enable_reg = 0x30004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup6_spi_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
+        .halt_reg = 0x30008,
+        .clkr = {
+                .enable_reg = 0x30008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup6_i2c_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_uart6_apps_clk = {
+        .halt_reg = 0x31004,
+        .clkr = {
+                .enable_reg = 0x31004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_uart6_apps_clk",
+                        .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pdm_ahb_clk = {
+        .halt_reg = 0x33004,
+        .clkr = {
+                .enable_reg = 0x33004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pdm_ahb_clk",
+                        .parent_names = (const char *[]){ "periph_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+        .halt_reg = 0x3300c,
+        .clkr = {
+                .enable_reg = 0x3300c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pdm2_clk",
+                        .parent_names = (const char *[]){ "pdm2_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+        .halt_reg = 0x34004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(13),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_prng_ahb_clk",
+                        .parent_names = (const char *[]){ "config_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_tsif_ahb_clk = {
+        .halt_reg = 0x36004,
+        .clkr = {
+                .enable_reg = 0x36004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_tsif_ahb_clk",
+                        .parent_names = (const char *[]){ "periph_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_tsif_ref_clk = {
+        .halt_reg = 0x36008,
+        .clkr = {
+                .enable_reg = 0x36008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_tsif_ref_clk",
+                        .parent_names = (const char *[]){ "tsif_ref_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_tsif_inactivity_timers_clk = {
+        .halt_reg = 0x3600c,
+        .clkr = {
+                .enable_reg = 0x3600c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_tsif_inactivity_timers_clk",
+                        .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_boot_rom_ahb_clk = {
+        .halt_reg = 0x38004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(10),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_boot_rom_ahb_clk",
+                        .parent_names = (const char *[]){ "config_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_bimc_gfx_clk = {
+        .halt_reg = 0x46018,
+        .clkr = {
+                .enable_reg = 0x46018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_bimc_gfx_clk",
+                        .flags = CLK_SET_RATE_PARENT | CLK_IS_ROOT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_hmss_rbcpr_clk = {
+        .halt_reg = 0x4800c,
+        .clkr = {
+                .enable_reg = 0x4800c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_hmss_rbcpr_clk",
+                        .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+        .halt_reg = 0x64000,
+        .clkr = {
+                .enable_reg = 0x64000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gp1_clk",
+                        .parent_names = (const char *[]){ "gp1_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+        .halt_reg = 0x65000,
+        .clkr = {
+                .enable_reg = 0x65000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gp2_clk",
+                        .parent_names = (const char *[]){ "gp2_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+        .halt_reg = 0x66000,
+        .clkr = {
+                .enable_reg = 0x66000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gp3_clk",
+                        .parent_names = (const char *[]){ "gp3_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_slv_axi_clk = {
+        .halt_reg = 0x6b008,
+        .clkr = {
+                .enable_reg = 0x6b008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_slv_axi_clk",
+                        .parent_names = (const char *[]){ "system_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
+        .halt_reg = 0x6b00c,
+        .clkr = {
+                .enable_reg = 0x6b00c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_mstr_axi_clk",
+                        .parent_names = (const char *[]){ "system_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
+        .halt_reg = 0x6b010,
+        .clkr = {
+                .enable_reg = 0x6b010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_cfg_ahb_clk",
+                        .parent_names = (const char *[]){ "config_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_aux_clk = {
+        .halt_reg = 0x6b014,
+        .clkr = {
+                .enable_reg = 0x6b014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_aux_clk",
+                        .parent_names = (const char *[]){ "pcie_aux_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_pipe_clk = {
+        .halt_reg = 0x6b018,
+        .clkr = {
+                .enable_reg = 0x6b018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_pipe_clk",
+                        .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_slv_axi_clk = {
+        .halt_reg = 0x6d008,
+        .clkr = {
+                .enable_reg = 0x6d008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_slv_axi_clk",
+                        .parent_names = (const char *[]){ "system_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
+        .halt_reg = 0x6d00c,
+        .clkr = {
+                .enable_reg = 0x6d00c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_mstr_axi_clk",
+                        .parent_names = (const char *[]){ "system_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
+        .halt_reg = 0x6d010,
+        .clkr = {
+                .enable_reg = 0x6d010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_cfg_ahb_clk",
+                        .parent_names = (const char *[]){ "config_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_aux_clk = {
+        .halt_reg = 0x6d014,
+        .clkr = {
+                .enable_reg = 0x6d014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_aux_clk",
+                        .parent_names = (const char *[]){ "pcie_aux_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_pipe_clk = {
+        .halt_reg = 0x6d018,
+        .clkr = {
+                .enable_reg = 0x6d018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_pipe_clk",
+                        .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_2_slv_axi_clk = {
+        .halt_reg = 0x6e008,
+        .clkr = {
+                .enable_reg = 0x6e008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_2_slv_axi_clk",
+                        .parent_names = (const char *[]){ "system_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
+        .halt_reg = 0x6e00c,
+        .clkr = {
+                .enable_reg = 0x6e00c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_2_mstr_axi_clk",
+                        .parent_names = (const char *[]){ "system_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
+        .halt_reg = 0x6e010,
+        .clkr = {
+                .enable_reg = 0x6e010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_2_cfg_ahb_clk",
+                        .parent_names = (const char *[]){ "config_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_2_aux_clk = {
+        .halt_reg = 0x6e014,
+        .clkr = {
+                .enable_reg = 0x6e014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_2_aux_clk",
+                        .parent_names = (const char *[]){ "pcie_aux_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_2_pipe_clk = {
+        .halt_reg = 0x6e108,
+        .clkr = {
+                .enable_reg = 0x6e108,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_2_pipe_clk",
+                        .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
+        .halt_reg = 0x6f004,
+        .clkr = {
+                .enable_reg = 0x6f004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_phy_cfg_ahb_clk",
+                        .parent_names = (const char *[]){ "config_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_phy_aux_clk = {
+        .halt_reg = 0x6f008,
+        .clkr = {
+                .enable_reg = 0x6f008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_phy_aux_clk",
+                        .parent_names = (const char *[]){ "pcie_aux_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_axi_clk = {
+        .halt_reg = 0x75008,
+        .clkr = {
+                .enable_reg = 0x75008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_axi_clk",
+                        .parent_names = (const char *[]){ "ufs_axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_ahb_clk = {
+        .halt_reg = 0x7500c,
+        .clkr = {
+                .enable_reg = 0x7500c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_ahb_clk",
+                        .parent_names = (const char *[]){ "config_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
+        .mult = 1,
+        .div = 16,
+        .hw.init = &(struct clk_init_data){
+                .name = "ufs_tx_cfg_clk_src",
+                .parent_names = (const char *[]){ "ufs_axi_clk_src" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_fixed_factor_ops,
+        },
+};
+
+static struct clk_branch gcc_ufs_tx_cfg_clk = {
+        .halt_reg = 0x75010,
+        .clkr = {
+                .enable_reg = 0x75010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_tx_cfg_clk",
+                        .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
+        .mult = 1,
+        .div = 16,
+        .hw.init = &(struct clk_init_data){
+                .name = "ufs_rx_cfg_clk_src",
+                .parent_names = (const char *[]){ "ufs_axi_clk_src" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_fixed_factor_ops,
+        },
+};
+
+static struct clk_branch gcc_ufs_rx_cfg_clk = {
+        .halt_reg = 0x75014,
+        .clkr = {
+                .enable_reg = 0x75014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_rx_cfg_clk",
+                        .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
+        .halt_reg = 0x75018,
+        .clkr = {
+                .enable_reg = 0x75018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_tx_symbol_0_clk",
+                        .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
+        .halt_reg = 0x7501c,
+        .clkr = {
+                .enable_reg = 0x7501c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_rx_symbol_0_clk",
+                        .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
+        .halt_reg = 0x75020,
+        .clkr = {
+                .enable_reg = 0x75020,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_rx_symbol_1_clk",
+                        .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
+        .mult = 1,
+        .div = 2,
+        .hw.init = &(struct clk_init_data){
+                .name = "ufs_ice_core_postdiv_clk_src",
+                .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_fixed_factor_ops,
+        },
+};
+
+static struct clk_branch gcc_ufs_unipro_core_clk = {
+        .halt_reg = 0x7600c,
+        .clkr = {
+                .enable_reg = 0x7600c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_unipro_core_clk",
+                        .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_ice_core_clk = {
+        .halt_reg = 0x76010,
+        .clkr = {
+                .enable_reg = 0x76010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_ice_core_clk",
+                        .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_sys_clk_core_clk = {
+        .halt_check = BRANCH_HALT_DELAY,
+        .clkr = {
+                .enable_reg = 0x76030,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_sys_clk_core_clk",
+                        .ops = &clk_branch2_ops,
+                        .flags = CLK_IS_ROOT,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
+        .halt_check = BRANCH_HALT_DELAY,
+        .clkr = {
+                .enable_reg = 0x76034,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_tx_symbol_clk_core_clk",
+                        .ops = &clk_branch2_ops,
+                        .flags = CLK_IS_ROOT,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre0_snoc_axi_clk = {
+        .halt_reg = 0x81008,
+        .clkr = {
+                .enable_reg = 0x81008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre0_snoc_axi_clk",
+                        .parent_names = (const char *[]){ "system_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
+        .halt_reg = 0x8100c,
+        .clkr = {
+                .enable_reg = 0x8100c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre0_cnoc_ahb_clk",
+                        .parent_names = (const char *[]){ "config_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_smmu_aggre0_axi_clk = {
+        .halt_reg = 0x81014,
+        .clkr = {
+                .enable_reg = 0x81014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_smmu_aggre0_axi_clk",
+                        .parent_names = (const char *[]){ "system_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
+        .halt_reg = 0x81018,
+        .clkr = {
+                .enable_reg = 0x81018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_smmu_aggre0_ahb_clk",
+                        .parent_names = (const char *[]){ "config_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
+        .halt_reg = 0x82014,
+        .clkr = {
+                .enable_reg = 0x82014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre1_pnoc_ahb_clk",
+                        .parent_names = (const char *[]){ "periph_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre2_ufs_axi_clk = {
+        .halt_reg = 0x83014,
+        .clkr = {
+                .enable_reg = 0x83014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre2_ufs_axi_clk",
+                        .parent_names = (const char *[]){ "ufs_axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre2_usb3_axi_clk = {
+        .halt_reg = 0x83018,
+        .clkr = {
+                .enable_reg = 0x83018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre2_usb3_axi_clk",
+                        .parent_names = (const char *[]){ "usb30_master_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qspi_ahb_clk = {
+        .halt_reg = 0x8b004,
+        .clkr = {
+                .enable_reg = 0x8b004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qspi_ahb_clk",
+                        .parent_names = (const char *[]){ "periph_noc_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qspi_ser_clk = {
+        .halt_reg = 0x8b008,
+        .clkr = {
+                .enable_reg = 0x8b008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qspi_ser_clk",
+                        .parent_names = (const char *[]){ "qspi_ser_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_clkref_clk = {
+        .halt_reg = 0x8800C,
+        .clkr = {
+                .enable_reg = 0x8800C,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_clkref_clk",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_hdmi_clkref_clk = {
+        .halt_reg = 0x88000,
+        .clkr = {
+                .enable_reg = 0x88000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_hdmi_clkref_clk",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_clkref_clk = {
+        .halt_reg = 0x88008,
+        .clkr = {
+                .enable_reg = 0x88008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_clkref_clk",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_clkref_clk = {
+        .halt_reg = 0x88010,
+        .clkr = {
+                .enable_reg = 0x88010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_clkref_clk",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_rx2_usb2_clkref_clk = {
+        .halt_reg = 0x88014,
+        .clkr = {
+                .enable_reg = 0x88014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_rx2_usb2_clkref_clk",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_rx1_usb2_clkref_clk = {
+        .halt_reg = 0x88018,
+        .clkr = {
+                .enable_reg = 0x88018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_rx1_usb2_clkref_clk",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_hw *gcc_msm8996_hws[] = {
+        &xo.hw,
+        &gpll0_early_div.hw,
+        &ufs_tx_cfg_clk_src.hw,
+        &ufs_rx_cfg_clk_src.hw,
+        &ufs_ice_core_postdiv_clk_src.hw,
+};
+
+static struct clk_regmap *gcc_msm8996_clocks[] = {
+        [GPLL0_EARLY] = &gpll0_early.clkr,
+        [GPLL0] = &gpll0.clkr,
+        [GPLL4_EARLY] = &gpll4_early.clkr,
+        [GPLL4] = &gpll4.clkr,
+        [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
+        [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
+        [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
+        [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
+        [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
+        [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
+        [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
+        [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
+        [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
+        [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
+        [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
+        [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
+        [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
+        [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+        [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+        [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+        [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+        [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+        [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+        [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+        [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+        [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
+        [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
+        [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
+        [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
+        [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
+        [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
+        [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
+        [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
+        [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
+        [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
+        [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
+        [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
+        [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
+        [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
+        [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
+        [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
+        [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
+        [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
+        [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
+        [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
+        [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
+        [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
+        [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
+        [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
+        [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
+        [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
+        [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
+        [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
+        [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
+        [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
+        [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
+        [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
+        [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
+        [GP1_CLK_SRC] = &gp1_clk_src.clkr,
+        [GP2_CLK_SRC] = &gp2_clk_src.clkr,
+        [GP3_CLK_SRC] = &gp3_clk_src.clkr,
+        [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
+        [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
+        [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
+        [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
+        [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
+        [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
+        [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
+        [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
+        [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
+        [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
+        [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
+        [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
+        [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
+        [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
+        [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
+        [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
+        [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
+        [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
+        [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+        [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+        [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
+        [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+        [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+        [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
+        [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
+        [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
+        [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
+        [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+        [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
+        [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+        [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+        [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+        [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+        [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+        [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
+        [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
+        [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
+        [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
+        [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
+        [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
+        [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
+        [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
+        [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
+        [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
+        [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
+        [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
+        [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
+        [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
+        [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
+        [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
+        [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
+        [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
+        [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
+        [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
+        [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
+        [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
+        [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
+        [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
+        [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
+        [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
+        [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
+        [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+        [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+        [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+        [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
+        [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
+        [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
+        [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+        [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
+        [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
+        [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+        [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+        [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+        [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
+        [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
+        [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
+        [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
+        [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
+        [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
+        [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
+        [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
+        [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
+        [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
+        [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
+        [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
+        [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
+        [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
+        [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
+        [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
+        [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
+        [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
+        [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
+        [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
+        [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
+        [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
+        [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
+        [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
+        [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
+        [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
+        [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
+        [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
+        [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
+        [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
+        [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
+        [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
+        [GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
+        [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
+        [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
+        [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
+        [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
+        [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
+        [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
+        [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
+        [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
+        [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
+        [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
+};
+
+static const struct qcom_reset_map gcc_msm8996_resets[] = {
+        [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
+        [GCC_CONFIG_NOC_BCR] = { 0x5000 },
+        [GCC_PERIPH_NOC_BCR] = { 0x6000 },
+        [GCC_IMEM_BCR] = { 0x8000 },
+        [GCC_MMSS_BCR] = { 0x9000 },
+        [GCC_PIMEM_BCR] = { 0x0a000 },
+        [GCC_QDSS_BCR] = { 0x0c000 },
+        [GCC_USB_30_BCR] = { 0x0f000 },
+        [GCC_USB_20_BCR] = { 0x12000 },
+        [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
+        [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
+        [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
+        [GCC_SDCC1_BCR] = { 0x13000 },
+        [GCC_SDCC2_BCR] = { 0x14000 },
+        [GCC_SDCC3_BCR] = { 0x15000 },
+        [GCC_SDCC4_BCR] = { 0x16000 },
+        [GCC_BLSP1_BCR] = { 0x17000 },
+        [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
+        [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
+        [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
+        [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
+        [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
+        [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
+        [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
+        [GCC_BLSP1_UART4_BCR] = { 0x20000 },
+        [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
+        [GCC_BLSP1_UART5_BCR] = { 0x22000 },
+        [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
+        [GCC_BLSP1_UART6_BCR] = { 0x24000 },
+        [GCC_BLSP2_BCR] = { 0x25000 },
+        [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
+        [GCC_BLSP2_UART1_BCR] = { 0x27000 },
+        [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
+        [GCC_BLSP2_UART2_BCR] = { 0x29000 },
+        [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
+        [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
+        [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
+        [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
+        [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
+        [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
+        [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
+        [GCC_BLSP2_UART6_BCR] = { 0x31000 },
+        [GCC_PDM_BCR] = { 0x33000 },
+        [GCC_PRNG_BCR] = { 0x34000 },
+        [GCC_TSIF_BCR] = { 0x36000 },
+        [GCC_TCSR_BCR] = { 0x37000 },
+        [GCC_BOOT_ROM_BCR] = { 0x38000 },
+        [GCC_MSG_RAM_BCR] = { 0x39000 },
+        [GCC_TLMM_BCR] = { 0x3a000 },
+        [GCC_MPM_BCR] = { 0x3b000 },
+        [GCC_SEC_CTRL_BCR] = { 0x3d000 },
+        [GCC_SPMI_BCR] = { 0x3f000 },
+        [GCC_SPDM_BCR] = { 0x40000 },
+        [GCC_CE1_BCR] = { 0x41000 },
+        [GCC_BIMC_BCR] = { 0x44000 },
+        [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
+        [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
+        [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
+        [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
+        [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
+        [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
+        [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
+        [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
+        [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
+        [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
+        [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
+        [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
+        [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
+        [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
+        [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
+        [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
+        [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
+        [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
+        [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
+        [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
+        [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
+        [GCC_APB2JTAG_BCR] = { 0x4c000 },
+        [GCC_RBCPR_CX_BCR] = { 0x4e000 },
+        [GCC_RBCPR_MX_BCR] = { 0x4f000 },
+        [GCC_PCIE_0_BCR] = { 0x6b000 },
+        [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
+        [GCC_PCIE_1_BCR] = { 0x6d000 },
+        [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
+        [GCC_PCIE_2_BCR] = { 0x6e000 },
+        [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
+        [GCC_PCIE_PHY_BCR] = { 0x6f000 },
+        [GCC_DCD_BCR] = { 0x70000 },
+        [GCC_OBT_ODT_BCR] = { 0x73000 },
+        [GCC_UFS_BCR] = { 0x75000 },
+        [GCC_SSC_BCR] = { 0x63000 },
+        [GCC_VS_BCR] = { 0x7a000 },
+        [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
+        [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
+        [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
+        [GCC_DCC_BCR] = { 0x84000 },
+        [GCC_IPA_BCR] = { 0x89000 },
+        [GCC_QSPI_BCR] = { 0x8b000 },
+        [GCC_SKL_BCR] = { 0x8c000 },
+        [GCC_MSMPU_BCR] = { 0x8d000 },
+        [GCC_MSS_Q6_BCR] = { 0x8e000 },
+        [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
+};
+
+static const struct regmap_config gcc_msm8996_regmap_config = {
+        .reg_bits       = 32,
+        .reg_stride     = 4,
+        .val_bits       = 32,
+        .max_register   = 0x8f010,
+        .fast_io        = true,
+};
+
+static const struct qcom_cc_desc gcc_msm8996_desc = {
+        .config = &gcc_msm8996_regmap_config,
+        .clks = gcc_msm8996_clocks,
+        .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
+        .resets = gcc_msm8996_resets,
+        .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
+};
+
+static const struct of_device_id gcc_msm8996_match_table[] = {
+        { .compatible = "qcom,gcc-msm8996" },
+        { }
+};
+MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
+
+static int gcc_msm8996_probe(struct platform_device *pdev)
+{
+        struct clk *clk;
+        struct device *dev = &pdev->dev;
+        int i;
+        struct regmap *regmap;
+
+        regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
+        if (IS_ERR(regmap))
+                return PTR_ERR(regmap);
+
+        /*
+         * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
+         * turned off by hardware during certain apps low power modes.
+         */
+        regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
+
+        for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) {
+                clk = devm_clk_register(dev, gcc_msm8996_hws[i]);
+                if (IS_ERR(clk))
+                        return PTR_ERR(clk);
+        }
+
+        return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
+}
+
+static struct platform_driver gcc_msm8996_driver = {
+        .probe          = gcc_msm8996_probe,
+        .driver         = {
+                .name   = "gcc-msm8996",
+                .of_match_table = gcc_msm8996_match_table,
+        },
+};
+
+static int __init gcc_msm8996_init(void)
+{
+        return platform_driver_register(&gcc_msm8996_driver);
+}
+core_initcall(gcc_msm8996_init);
+
+static void __exit gcc_msm8996_exit(void)
+{
+        platform_driver_unregister(&gcc_msm8996_driver);
+}
+module_exit(gcc_msm8996_exit);
+
+MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:gcc-msm8996");
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
new file mode 100644
index 000000000000..064f3eaa39d0
--- /dev/null
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -0,0 +1,3217 @@
+/*x
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/clk.h>
+
+#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-alpha-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+        P_XO,
+        P_MMPLL0,
+        P_GPLL0,
+        P_GPLL0_DIV,
+        P_MMPLL1,
+        P_MMPLL9,
+        P_MMPLL2,
+        P_MMPLL8,
+        P_MMPLL3,
+        P_DSI0PLL,
+        P_DSI1PLL,
+        P_MMPLL5,
+        P_HDMIPLL,
+        P_DSI0PLL_BYTE,
+        P_DSI1PLL_BYTE,
+        P_MMPLL4,
+};
+
+static const struct parent_map mmss_xo_hdmi_map[] = {
+        { P_XO, 0 },
+        { P_HDMIPLL, 1 }
+};
+
+static const char * const mmss_xo_hdmi[] = {
+        "xo",
+        "hdmipll"
+};
+
+static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
+        { P_XO, 0 },
+        { P_DSI0PLL, 1 },
+        { P_DSI1PLL, 2 }
+};
+
+static const char * const mmss_xo_dsi0pll_dsi1pll[] = {
+        "xo",
+        "dsi0pll",
+        "dsi1pll"
+};
+
+static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
+        { P_XO, 0 },
+        { P_GPLL0, 5 },
+        { P_GPLL0_DIV, 6 }
+};
+
+static const char * const mmss_xo_gpll0_gpll0_div[] = {
+        "xo",
+        "gpll0",
+        "gpll0_div"
+};
+
+static const struct parent_map mmss_xo_dsibyte_map[] = {
+        { P_XO, 0 },
+        { P_DSI0PLL_BYTE, 1 },
+        { P_DSI1PLL_BYTE, 2 }
+};
+
+static const char * const mmss_xo_dsibyte[] = {
+        "xo",
+        "dsi0pllbyte",
+        "dsi1pllbyte"
+};
+
+static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_GPLL0, 5 },
+        { P_GPLL0_DIV, 6 }
+};
+
+static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = {
+        "xo",
+        "mmpll0",
+        "gpll0",
+        "gpll0_div"
+};
+
+static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL1, 2 },
+        { P_GPLL0, 5 },
+        { P_GPLL0_DIV, 6 }
+};
+
+static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
+        "xo",
+        "mmpll0",
+        "mmpll1",
+        "gpll0",
+        "gpll0_div"
+};
+
+static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL3, 3 },
+        { P_GPLL0, 5 },
+        { P_GPLL0_DIV, 6 }
+};
+
+static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = {
+        "xo",
+        "mmpll0",
+        "mmpll3",
+        "gpll0",
+        "gpll0_div"
+};
+
+static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL5, 2 },
+        { P_GPLL0, 5 },
+        { P_GPLL0_DIV, 6 }
+};
+
+static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
+        "xo",
+        "mmpll0",
+        "mmpll5",
+        "gpll0",
+        "gpll0_div"
+};
+
+static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL4, 3 },
+        { P_GPLL0, 5 },
+        { P_GPLL0_DIV, 6 }
+};
+
+static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = {
+        "xo",
+        "mmpll0",
+        "mmpll4",
+        "gpll0",
+        "gpll0_div"
+};
+
+static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL9, 2 },
+        { P_MMPLL2, 3 },
+        { P_MMPLL8, 4 },
+        { P_GPLL0, 5 }
+};
+
+static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = {
+        "xo",
+        "mmpll0",
+        "mmpll9",
+        "mmpll2",
+        "mmpll8",
+        "gpll0"
+};
+
+static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL9, 2 },
+        { P_MMPLL2, 3 },
+        { P_MMPLL8, 4 },
+        { P_GPLL0, 5 },
+        { P_GPLL0_DIV, 6 }
+};
+
+static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = {
+        "xo",
+        "mmpll0",
+        "mmpll9",
+        "mmpll2",
+        "mmpll8",
+        "gpll0",
+        "gpll0_div"
+};
+
+static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = {
+        { P_XO, 0 },
+        { P_MMPLL0, 1 },
+        { P_MMPLL1, 2 },
+        { P_MMPLL4, 3 },
+        { P_MMPLL3, 4 },
+        { P_GPLL0, 5 },
+        { P_GPLL0_DIV, 6 }
+};
+
+static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = {
+        "xo",
+        "mmpll0",
+        "mmpll1",
+        "mmpll4",
+        "mmpll3",
+        "gpll0",
+        "gpll0_div"
+};
+
+static struct clk_fixed_factor gpll0_div = {
+        .mult = 1,
+        .div = 2,
+        .hw.init = &(struct clk_init_data){
+                .name = "gpll0_div",
+                .parent_names = (const char *[]){ "gpll0" },
+                .num_parents = 1,
+                .ops = &clk_fixed_factor_ops,
+        },
+};
+
+static struct pll_vco mmpll_p_vco[] = {
+        { 250000000, 500000000, 3 },
+        { 500000000, 1000000000, 2 },
+        { 1000000000, 1500000000, 1 },
+        { 1500000000, 2000000000, 0 },
+};
+
+static struct pll_vco mmpll_gfx_vco[] = {
+        { 400000000, 1000000000, 2 },
+        { 1000000000, 1500000000, 1 },
+        { 1500000000, 2000000000, 0 },
+};
+
+static struct pll_vco mmpll_t_vco[] = {
+        { 500000000, 1500000000, 0 },
+};
+
+static struct clk_alpha_pll mmpll0_early = {
+        .offset = 0x0,
+        .vco_table = mmpll_p_vco,
+        .num_vco = ARRAY_SIZE(mmpll_p_vco),
+        .clkr = {
+                .enable_reg = 0x100,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmpll0_early",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_alpha_pll_ops,
+                },
+        },
+};
+
+static struct clk_alpha_pll_postdiv mmpll0 = {
+        .offset = 0x0,
+        .width = 4,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll0",
+                .parent_names = (const char *[]){ "mmpll0_early" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_alpha_pll mmpll1_early = {
+        .offset = 0x30,
+        .vco_table = mmpll_p_vco,
+        .num_vco = ARRAY_SIZE(mmpll_p_vco),
+        .clkr = {
+                .enable_reg = 0x100,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmpll1_early",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_alpha_pll_ops,
+                }
+        },
+};
+
+static struct clk_alpha_pll_postdiv mmpll1 = {
+        .offset = 0x30,
+        .width = 4,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll1",
+                .parent_names = (const char *[]){ "mmpll1_early" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_alpha_pll mmpll2_early = {
+        .offset = 0x4100,
+        .vco_table = mmpll_gfx_vco,
+        .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll2_early",
+                .parent_names = (const char *[]){ "xo" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv mmpll2 = {
+        .offset = 0x4100,
+        .width = 4,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll2",
+                .parent_names = (const char *[]){ "mmpll2_early" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_alpha_pll mmpll3_early = {
+        .offset = 0x60,
+        .vco_table = mmpll_p_vco,
+        .num_vco = ARRAY_SIZE(mmpll_p_vco),
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll3_early",
+                .parent_names = (const char *[]){ "xo" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv mmpll3 = {
+        .offset = 0x60,
+        .width = 4,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll3",
+                .parent_names = (const char *[]){ "mmpll3_early" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_alpha_pll mmpll4_early = {
+        .offset = 0x90,
+        .vco_table = mmpll_t_vco,
+        .num_vco = ARRAY_SIZE(mmpll_t_vco),
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll4_early",
+                .parent_names = (const char *[]){ "xo" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv mmpll4 = {
+        .offset = 0x90,
+        .width = 2,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll4",
+                .parent_names = (const char *[]){ "mmpll4_early" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_alpha_pll mmpll5_early = {
+        .offset = 0xc0,
+        .vco_table = mmpll_p_vco,
+        .num_vco = ARRAY_SIZE(mmpll_p_vco),
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll5_early",
+                .parent_names = (const char *[]){ "xo" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv mmpll5 = {
+        .offset = 0xc0,
+        .width = 4,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll5",
+                .parent_names = (const char *[]){ "mmpll5_early" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_alpha_pll mmpll8_early = {
+        .offset = 0x4130,
+        .vco_table = mmpll_gfx_vco,
+        .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll8_early",
+                .parent_names = (const char *[]){ "xo" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv mmpll8 = {
+        .offset = 0x4130,
+        .width = 4,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll8",
+                .parent_names = (const char *[]){ "mmpll8_early" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_alpha_pll mmpll9_early = {
+        .offset = 0x4200,
+        .vco_table = mmpll_t_vco,
+        .num_vco = ARRAY_SIZE(mmpll_t_vco),
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll9_early",
+                .parent_names = (const char *[]){ "xo" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv mmpll9 = {
+        .offset = 0x4200,
+        .width = 2,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mmpll9",
+                .parent_names = (const char *[]){ "mmpll9_early" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static const struct freq_tbl ftbl_ahb_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
+        F(80000000, P_MMPLL0, 10, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 ahb_clk_src = {
+        .cmd_rcgr = 0x5000,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_ahb_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "ahb_clk_src",
+                .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_axi_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(75000000, P_GPLL0_DIV, 4, 0, 0),
+        F(100000000, P_GPLL0, 6, 0, 0),
+        F(171430000, P_GPLL0, 3.5, 0, 0),
+        F(200000000, P_GPLL0, 3, 0, 0),
+        F(320000000, P_MMPLL0, 2.5, 0, 0),
+        F(400000000, P_MMPLL0, 2, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 axi_clk_src = {
+        .cmd_rcgr = 0x5040,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_axi_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "axi_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 maxi_clk_src = {
+        .cmd_rcgr = 0x5090,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_axi_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "maxi_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gfx3d_clk_src = {
+        .cmd_rcgr = 0x4000,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gfx3d_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
+                .num_parents = 6,
+                .ops = &clk_gfx3d_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 rbbmtimer_clk_src = {
+        .cmd_rcgr = 0x4090,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_rbbmtimer_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "rbbmtimer_clk_src",
+                .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 isense_clk_src = {
+        .cmd_rcgr = 0x4010,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "isense_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(50000000, P_GPLL0, 12, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 rbcpr_clk_src = {
+        .cmd_rcgr = 0x4060,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_rbcpr_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "rbcpr_clk_src",
+                .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_video_core_clk_src[] = {
+        F(75000000, P_GPLL0_DIV, 4, 0, 0),
+        F(150000000, P_GPLL0, 4, 0, 0),
+        F(346666667, P_MMPLL3, 3, 0, 0),
+        F(520000000, P_MMPLL3, 2, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 video_core_clk_src = {
+        .cmd_rcgr = 0x1000,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_video_core_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "video_core_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 video_subcore0_clk_src = {
+        .cmd_rcgr = 0x1060,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_video_core_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "video_subcore0_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 video_subcore1_clk_src = {
+        .cmd_rcgr = 0x1080,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_video_core_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "video_subcore1_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 pclk0_clk_src = {
+        .cmd_rcgr = 0x2000,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "pclk0_clk_src",
+                .parent_names = mmss_xo_dsi0pll_dsi1pll,
+                .num_parents = 3,
+                .ops = &clk_pixel_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_rcg2 pclk1_clk_src = {
+        .cmd_rcgr = 0x2020,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "pclk1_clk_src",
+                .parent_names = mmss_xo_dsi0pll_dsi1pll,
+                .num_parents = 3,
+                .ops = &clk_pixel_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static const struct freq_tbl ftbl_mdp_clk_src[] = {
+        F(85714286, P_GPLL0, 7, 0, 0),
+        F(100000000, P_GPLL0, 6, 0, 0),
+        F(150000000, P_GPLL0, 4, 0, 0),
+        F(171428571, P_GPLL0, 3.5, 0, 0),
+        F(200000000, P_GPLL0, 3, 0, 0),
+        F(275000000, P_MMPLL5, 3, 0, 0),
+        F(300000000, P_GPLL0, 2, 0, 0),
+        F(330000000, P_MMPLL5, 2.5, 0, 0),
+        F(412500000, P_MMPLL5, 2, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 mdp_clk_src = {
+        .cmd_rcgr = 0x2040,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_mdp_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mdp_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct freq_tbl extpclk_freq_tbl[] = {
+        { .src = P_HDMIPLL },
+        { }
+};
+
+static struct clk_rcg2 extpclk_clk_src = {
+        .cmd_rcgr = 0x2060,
+        .hid_width = 5,
+        .parent_map = mmss_xo_hdmi_map,
+        .freq_tbl = extpclk_freq_tbl,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "extpclk_clk_src",
+                .parent_names = mmss_xo_hdmi,
+                .num_parents = 2,
+                .ops = &clk_byte_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct freq_tbl ftbl_mdss_vsync_clk[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 vsync_clk_src = {
+        .cmd_rcgr = 0x2080,
+        .hid_width = 5,
+        .parent_map = mmss_xo_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_mdss_vsync_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "vsync_clk_src",
+                .parent_names = mmss_xo_gpll0_gpll0_div,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 hdmi_clk_src = {
+        .cmd_rcgr = 0x2100,
+        .hid_width = 5,
+        .parent_map = mmss_xo_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_mdss_hdmi_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "hdmi_clk_src",
+                .parent_names = mmss_xo_gpll0_gpll0_div,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 byte0_clk_src = {
+        .cmd_rcgr = 0x2120,
+        .hid_width = 5,
+        .parent_map = mmss_xo_dsibyte_map,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "byte0_clk_src",
+                .parent_names = mmss_xo_dsibyte,
+                .num_parents = 3,
+                .ops = &clk_byte2_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_rcg2 byte1_clk_src = {
+        .cmd_rcgr = 0x2140,
+        .hid_width = 5,
+        .parent_map = mmss_xo_dsibyte_map,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "byte1_clk_src",
+                .parent_names = mmss_xo_dsibyte,
+                .num_parents = 3,
+                .ops = &clk_byte2_ops,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 esc0_clk_src = {
+        .cmd_rcgr = 0x2160,
+        .hid_width = 5,
+        .parent_map = mmss_xo_dsibyte_map,
+        .freq_tbl = ftbl_mdss_esc0_1_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "esc0_clk_src",
+                .parent_names = mmss_xo_dsibyte,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 esc1_clk_src = {
+        .cmd_rcgr = 0x2180,
+        .hid_width = 5,
+        .parent_map = mmss_xo_dsibyte_map,
+        .freq_tbl = ftbl_mdss_esc0_1_clk,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "esc1_clk_src",
+                .parent_names = mmss_xo_dsibyte,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
+        F(10000, P_XO, 16, 1, 120),
+        F(24000, P_XO, 16, 1, 50),
+        F(6000000, P_GPLL0_DIV, 10, 1, 5),
+        F(12000000, P_GPLL0_DIV, 1, 1, 25),
+        F(13000000, P_GPLL0_DIV, 2, 13, 150),
+        F(24000000, P_GPLL0_DIV, 1, 2, 25),
+        { }
+};
+
+static struct clk_rcg2 camss_gp0_clk_src = {
+        .cmd_rcgr = 0x3420,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_camss_gp0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "camss_gp0_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 camss_gp1_clk_src = {
+        .cmd_rcgr = 0x3450,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_camss_gp0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "camss_gp1_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_mclk0_clk_src[] = {
+        F(4800000, P_XO, 4, 0, 0),
+        F(6000000, P_GPLL0_DIV, 10, 1, 5),
+        F(8000000, P_GPLL0_DIV, 1, 2, 75),
+        F(9600000, P_XO, 2, 0, 0),
+        F(16666667, P_GPLL0_DIV, 2, 1, 9),
+        F(19200000, P_XO, 1, 0, 0),
+        F(24000000, P_GPLL0_DIV, 1, 2, 25),
+        F(33333333, P_GPLL0_DIV, 1, 1, 9),
+        F(48000000, P_GPLL0, 1, 2, 25),
+        F(66666667, P_GPLL0, 1, 1, 9),
+        { }
+};
+
+static struct clk_rcg2 mclk0_clk_src = {
+        .cmd_rcgr = 0x3360,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_mclk0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mclk0_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 mclk1_clk_src = {
+        .cmd_rcgr = 0x3390,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_mclk0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mclk1_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 mclk2_clk_src = {
+        .cmd_rcgr = 0x33c0,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_mclk0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mclk2_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 mclk3_clk_src = {
+        .cmd_rcgr = 0x33f0,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_mclk0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "mclk3_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_cci_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(37500000, P_GPLL0, 16, 0, 0),
+        F(50000000, P_GPLL0, 12, 0, 0),
+        F(100000000, P_GPLL0, 6, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 cci_clk_src = {
+        .cmd_rcgr = 0x3300,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_cci_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "cci_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
+        F(100000000, P_GPLL0_DIV, 3, 0, 0),
+        F(200000000, P_GPLL0, 3, 0, 0),
+        F(266666667, P_MMPLL0, 3, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 csi0phytimer_clk_src = {
+        .cmd_rcgr = 0x3000,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_csi0phytimer_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "csi0phytimer_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 csi1phytimer_clk_src = {
+        .cmd_rcgr = 0x3030,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_csi0phytimer_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "csi1phytimer_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 csi2phytimer_clk_src = {
+        .cmd_rcgr = 0x3060,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_csi0phytimer_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "csi2phytimer_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = {
+        F(100000000, P_GPLL0_DIV, 3, 0, 0),
+        F(200000000, P_GPLL0, 3, 0, 0),
+        F(320000000, P_MMPLL4, 3, 0, 0),
+        F(384000000, P_MMPLL4, 2.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 csiphy0_3p_clk_src = {
+        .cmd_rcgr = 0x3240,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_csiphy0_3p_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "csiphy0_3p_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 csiphy1_3p_clk_src = {
+        .cmd_rcgr = 0x3260,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_csiphy0_3p_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "csiphy1_3p_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 csiphy2_3p_clk_src = {
+        .cmd_rcgr = 0x3280,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_csiphy0_3p_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "csiphy2_3p_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
+        F(75000000, P_GPLL0_DIV, 4, 0, 0),
+        F(150000000, P_GPLL0, 4, 0, 0),
+        F(228571429, P_MMPLL0, 3.5, 0, 0),
+        F(266666667, P_MMPLL0, 3, 0, 0),
+        F(320000000, P_MMPLL0, 2.5, 0, 0),
+        F(480000000, P_MMPLL4, 2, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 jpeg0_clk_src = {
+        .cmd_rcgr = 0x3500,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_jpeg0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "jpeg0_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
+        F(75000000, P_GPLL0_DIV, 4, 0, 0),
+        F(150000000, P_GPLL0, 4, 0, 0),
+        F(228571429, P_MMPLL0, 3.5, 0, 0),
+        F(266666667, P_MMPLL0, 3, 0, 0),
+        F(320000000, P_MMPLL0, 2.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 jpeg2_clk_src = {
+        .cmd_rcgr = 0x3540,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_jpeg2_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "jpeg2_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 jpeg_dma_clk_src = {
+        .cmd_rcgr = 0x3560,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_jpeg0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "jpeg_dma_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_vfe0_clk_src[] = {
+        F(75000000, P_GPLL0_DIV, 4, 0, 0),
+        F(100000000, P_GPLL0_DIV, 3, 0, 0),
+        F(300000000, P_GPLL0, 2, 0, 0),
+        F(320000000, P_MMPLL0, 2.5, 0, 0),
+        F(480000000, P_MMPLL4, 2, 0, 0),
+        F(600000000, P_GPLL0, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 vfe0_clk_src = {
+        .cmd_rcgr = 0x3600,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_vfe0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "vfe0_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 vfe1_clk_src = {
+        .cmd_rcgr = 0x3620,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_vfe0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "vfe1_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_cpp_clk_src[] = {
+        F(100000000, P_GPLL0_DIV, 3, 0, 0),
+        F(200000000, P_GPLL0, 3, 0, 0),
+        F(320000000, P_MMPLL0, 2.5, 0, 0),
+        F(480000000, P_MMPLL4, 2, 0, 0),
+        F(640000000, P_MMPLL4, 1.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 cpp_clk_src = {
+        .cmd_rcgr = 0x3640,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_cpp_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "cpp_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_csi0_clk_src[] = {
+        F(100000000, P_GPLL0_DIV, 3, 0, 0),
+        F(200000000, P_GPLL0, 3, 0, 0),
+        F(266666667, P_MMPLL0, 3, 0, 0),
+        F(480000000, P_MMPLL4, 2, 0, 0),
+        F(600000000, P_GPLL0, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 csi0_clk_src = {
+        .cmd_rcgr = 0x3090,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_csi0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "csi0_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 csi1_clk_src = {
+        .cmd_rcgr = 0x3100,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_csi0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "csi1_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 csi2_clk_src = {
+        .cmd_rcgr = 0x3160,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_csi0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "csi2_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 csi3_clk_src = {
+        .cmd_rcgr = 0x31c0,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_csi0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "csi3_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
+                .num_parents = 7,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_fd_core_clk_src[] = {
+        F(100000000, P_GPLL0_DIV, 3, 0, 0),
+        F(200000000, P_GPLL0, 3, 0, 0),
+        F(400000000, P_MMPLL0, 2, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 fd_core_clk_src = {
+        .cmd_rcgr = 0x3b00,
+        .hid_width = 5,
+        .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
+        .freq_tbl = ftbl_fd_core_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "fd_core_clk_src",
+                .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_branch mmss_mmagic_ahb_clk = {
+        .halt_reg = 0x5024,
+        .clkr = {
+                .enable_reg = 0x5024,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmss_mmagic_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mmss_mmagic_cfg_ahb_clk = {
+        .halt_reg = 0x5054,
+        .clkr = {
+                .enable_reg = 0x5054,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmss_mmagic_cfg_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mmss_misc_ahb_clk = {
+        .halt_reg = 0x5018,
+        .clkr = {
+                .enable_reg = 0x5018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmss_misc_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mmss_misc_cxo_clk = {
+        .halt_reg = 0x5014,
+        .clkr = {
+                .enable_reg = 0x5014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmss_misc_cxo_clk",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mmss_mmagic_axi_clk = {
+        .halt_reg = 0x506c,
+        .clkr = {
+                .enable_reg = 0x506c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmss_mmagic_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mmss_mmagic_maxi_clk = {
+        .halt_reg = 0x5074,
+        .clkr = {
+                .enable_reg = 0x5074,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmss_mmagic_maxi_clk",
+                        .parent_names = (const char *[]){ "maxi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mmagic_camss_axi_clk = {
+        .halt_reg = 0x3c44,
+        .clkr = {
+                .enable_reg = 0x3c44,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmagic_camss_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = {
+        .halt_reg = 0x3c48,
+        .clkr = {
+                .enable_reg = 0x3c48,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmagic_camss_noc_cfg_ahb_clk",
+                        .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch smmu_vfe_ahb_clk = {
+        .halt_reg = 0x3c04,
+        .clkr = {
+                .enable_reg = 0x3c04,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "smmu_vfe_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch smmu_vfe_axi_clk = {
+        .halt_reg = 0x3c08,
+        .clkr = {
+                .enable_reg = 0x3c08,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "smmu_vfe_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch smmu_cpp_ahb_clk = {
+        .halt_reg = 0x3c14,
+        .clkr = {
+                .enable_reg = 0x3c14,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "smmu_cpp_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch smmu_cpp_axi_clk = {
+        .halt_reg = 0x3c18,
+        .clkr = {
+                .enable_reg = 0x3c18,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "smmu_cpp_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch smmu_jpeg_ahb_clk = {
+        .halt_reg = 0x3c24,
+        .clkr = {
+                .enable_reg = 0x3c24,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "smmu_jpeg_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch smmu_jpeg_axi_clk = {
+        .halt_reg = 0x3c28,
+        .clkr = {
+                .enable_reg = 0x3c28,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "smmu_jpeg_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mmagic_mdss_axi_clk = {
+        .halt_reg = 0x2474,
+        .clkr = {
+                .enable_reg = 0x2474,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmagic_mdss_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = {
+        .halt_reg = 0x2478,
+        .clkr = {
+                .enable_reg = 0x2478,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmagic_mdss_noc_cfg_ahb_clk",
+                        .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch smmu_rot_ahb_clk = {
+        .halt_reg = 0x2444,
+        .clkr = {
+                .enable_reg = 0x2444,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "smmu_rot_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch smmu_rot_axi_clk = {
+        .halt_reg = 0x2448,
+        .clkr = {
+                .enable_reg = 0x2448,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "smmu_rot_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch smmu_mdp_ahb_clk = {
+        .halt_reg = 0x2454,
+        .clkr = {
+                .enable_reg = 0x2454,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "smmu_mdp_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch smmu_mdp_axi_clk = {
+        .halt_reg = 0x2458,
+        .clkr = {
+                .enable_reg = 0x2458,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "smmu_mdp_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mmagic_video_axi_clk = {
+        .halt_reg = 0x1194,
+        .clkr = {
+                .enable_reg = 0x1194,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmagic_video_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mmagic_video_noc_cfg_ahb_clk = {
+        .halt_reg = 0x1198,
+        .clkr = {
+                .enable_reg = 0x1198,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmagic_video_noc_cfg_ahb_clk",
+                        .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch smmu_video_ahb_clk = {
+        .halt_reg = 0x1174,
+        .clkr = {
+                .enable_reg = 0x1174,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "smmu_video_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch smmu_video_axi_clk = {
+        .halt_reg = 0x1178,
+        .clkr = {
+                .enable_reg = 0x1178,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "smmu_video_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mmagic_bimc_axi_clk = {
+        .halt_reg = 0x5294,
+        .clkr = {
+                .enable_reg = 0x5294,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmagic_bimc_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = {
+        .halt_reg = 0x5298,
+        .clkr = {
+                .enable_reg = 0x5298,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmagic_bimc_noc_cfg_ahb_clk",
+                        .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gpu_gx_gfx3d_clk = {
+        .halt_reg = 0x4028,
+        .clkr = {
+                .enable_reg = 0x4028,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpu_gx_gfx3d_clk",
+                        .parent_names = (const char *[]){ "gfx3d_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gpu_gx_rbbmtimer_clk = {
+        .halt_reg = 0x40b0,
+        .clkr = {
+                .enable_reg = 0x40b0,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpu_gx_rbbmtimer_clk",
+                        .parent_names = (const char *[]){ "rbbmtimer_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gpu_ahb_clk = {
+        .halt_reg = 0x403c,
+        .clkr = {
+                .enable_reg = 0x403c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpu_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gpu_aon_isense_clk = {
+        .halt_reg = 0x4044,
+        .clkr = {
+                .enable_reg = 0x4044,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpu_aon_isense_clk",
+                        .parent_names = (const char *[]){ "isense_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch vmem_maxi_clk = {
+        .halt_reg = 0x1204,
+        .clkr = {
+                .enable_reg = 0x1204,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "vmem_maxi_clk",
+                        .parent_names = (const char *[]){ "maxi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch vmem_ahb_clk = {
+        .halt_reg = 0x1208,
+        .clkr = {
+                .enable_reg = 0x1208,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "vmem_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mmss_rbcpr_clk = {
+        .halt_reg = 0x4084,
+        .clkr = {
+                .enable_reg = 0x4084,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmss_rbcpr_clk",
+                        .parent_names = (const char *[]){ "rbcpr_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mmss_rbcpr_ahb_clk = {
+        .halt_reg = 0x4088,
+        .clkr = {
+                .enable_reg = 0x4088,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mmss_rbcpr_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_core_clk = {
+        .halt_reg = 0x1028,
+        .clkr = {
+                .enable_reg = 0x1028,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_core_clk",
+                        .parent_names = (const char *[]){ "video_core_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_axi_clk = {
+        .halt_reg = 0x1034,
+        .clkr = {
+                .enable_reg = 0x1034,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_maxi_clk = {
+        .halt_reg = 0x1038,
+        .clkr = {
+                .enable_reg = 0x1038,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_maxi_clk",
+                        .parent_names = (const char *[]){ "maxi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_ahb_clk = {
+        .halt_reg = 0x1030,
+        .clkr = {
+                .enable_reg = 0x1030,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_subcore0_clk = {
+        .halt_reg = 0x1048,
+        .clkr = {
+                .enable_reg = 0x1048,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_subcore0_clk",
+                        .parent_names = (const char *[]){ "video_subcore0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_subcore1_clk = {
+        .halt_reg = 0x104c,
+        .clkr = {
+                .enable_reg = 0x104c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_subcore1_clk",
+                        .parent_names = (const char *[]){ "video_subcore1_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mdss_ahb_clk = {
+        .halt_reg = 0x2308,
+        .clkr = {
+                .enable_reg = 0x2308,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mdss_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mdss_hdmi_ahb_clk = {
+        .halt_reg = 0x230c,
+        .clkr = {
+                .enable_reg = 0x230c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mdss_hdmi_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mdss_axi_clk = {
+        .halt_reg = 0x2310,
+        .clkr = {
+                .enable_reg = 0x2310,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mdss_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mdss_pclk0_clk = {
+        .halt_reg = 0x2314,
+        .clkr = {
+                .enable_reg = 0x2314,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mdss_pclk0_clk",
+                        .parent_names = (const char *[]){ "pclk0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mdss_pclk1_clk = {
+        .halt_reg = 0x2318,
+        .clkr = {
+                .enable_reg = 0x2318,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mdss_pclk1_clk",
+                        .parent_names = (const char *[]){ "pclk1_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mdss_mdp_clk = {
+        .halt_reg = 0x231c,
+        .clkr = {
+                .enable_reg = 0x231c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mdss_mdp_clk",
+                        .parent_names = (const char *[]){ "mdp_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mdss_extpclk_clk = {
+        .halt_reg = 0x2324,
+        .clkr = {
+                .enable_reg = 0x2324,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mdss_extpclk_clk",
+                        .parent_names = (const char *[]){ "extpclk_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mdss_vsync_clk = {
+        .halt_reg = 0x2328,
+        .clkr = {
+                .enable_reg = 0x2328,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mdss_vsync_clk",
+                        .parent_names = (const char *[]){ "vsync_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mdss_hdmi_clk = {
+        .halt_reg = 0x2338,
+        .clkr = {
+                .enable_reg = 0x2338,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mdss_hdmi_clk",
+                        .parent_names = (const char *[]){ "hdmi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mdss_byte0_clk = {
+        .halt_reg = 0x233c,
+        .clkr = {
+                .enable_reg = 0x233c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mdss_byte0_clk",
+                        .parent_names = (const char *[]){ "byte0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mdss_byte1_clk = {
+        .halt_reg = 0x2340,
+        .clkr = {
+                .enable_reg = 0x2340,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mdss_byte1_clk",
+                        .parent_names = (const char *[]){ "byte1_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mdss_esc0_clk = {
+        .halt_reg = 0x2344,
+        .clkr = {
+                .enable_reg = 0x2344,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mdss_esc0_clk",
+                        .parent_names = (const char *[]){ "esc0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch mdss_esc1_clk = {
+        .halt_reg = 0x2348,
+        .clkr = {
+                .enable_reg = 0x2348,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "mdss_esc1_clk",
+                        .parent_names = (const char *[]){ "esc1_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_top_ahb_clk = {
+        .halt_reg = 0x3484,
+        .clkr = {
+                .enable_reg = 0x3484,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_top_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_ahb_clk = {
+        .halt_reg = 0x348c,
+        .clkr = {
+                .enable_reg = 0x348c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_micro_ahb_clk = {
+        .halt_reg = 0x3494,
+        .clkr = {
+                .enable_reg = 0x3494,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_micro_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_gp0_clk = {
+        .halt_reg = 0x3444,
+        .clkr = {
+                .enable_reg = 0x3444,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_gp0_clk",
+                        .parent_names = (const char *[]){ "camss_gp0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_gp1_clk = {
+        .halt_reg = 0x3474,
+        .clkr = {
+                .enable_reg = 0x3474,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_gp1_clk",
+                        .parent_names = (const char *[]){ "camss_gp1_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_mclk0_clk = {
+        .halt_reg = 0x3384,
+        .clkr = {
+                .enable_reg = 0x3384,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_mclk0_clk",
+                        .parent_names = (const char *[]){ "mclk0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_mclk1_clk = {
+        .halt_reg = 0x33b4,
+        .clkr = {
+                .enable_reg = 0x33b4,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_mclk1_clk",
+                        .parent_names = (const char *[]){ "mclk1_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_mclk2_clk = {
+        .halt_reg = 0x33e4,
+        .clkr = {
+                .enable_reg = 0x33e4,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_mclk2_clk",
+                        .parent_names = (const char *[]){ "mclk2_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_mclk3_clk = {
+        .halt_reg = 0x3414,
+        .clkr = {
+                .enable_reg = 0x3414,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_mclk3_clk",
+                        .parent_names = (const char *[]){ "mclk3_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_cci_clk = {
+        .halt_reg = 0x3344,
+        .clkr = {
+                .enable_reg = 0x3344,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_cci_clk",
+                        .parent_names = (const char *[]){ "cci_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_cci_ahb_clk = {
+        .halt_reg = 0x3348,
+        .clkr = {
+                .enable_reg = 0x3348,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_cci_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi0phytimer_clk = {
+        .halt_reg = 0x3024,
+        .clkr = {
+                .enable_reg = 0x3024,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi0phytimer_clk",
+                        .parent_names = (const char *[]){ "csi0phytimer_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi1phytimer_clk = {
+        .halt_reg = 0x3054,
+        .clkr = {
+                .enable_reg = 0x3054,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi1phytimer_clk",
+                        .parent_names = (const char *[]){ "csi1phytimer_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi2phytimer_clk = {
+        .halt_reg = 0x3084,
+        .clkr = {
+                .enable_reg = 0x3084,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi2phytimer_clk",
+                        .parent_names = (const char *[]){ "csi2phytimer_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csiphy0_3p_clk = {
+        .halt_reg = 0x3234,
+        .clkr = {
+                .enable_reg = 0x3234,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csiphy0_3p_clk",
+                        .parent_names = (const char *[]){ "csiphy0_3p_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csiphy1_3p_clk = {
+        .halt_reg = 0x3254,
+        .clkr = {
+                .enable_reg = 0x3254,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csiphy1_3p_clk",
+                        .parent_names = (const char *[]){ "csiphy1_3p_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csiphy2_3p_clk = {
+        .halt_reg = 0x3274,
+        .clkr = {
+                .enable_reg = 0x3274,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csiphy2_3p_clk",
+                        .parent_names = (const char *[]){ "csiphy2_3p_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_jpeg0_clk = {
+        .halt_reg = 0x35a8,
+        .clkr = {
+                .enable_reg = 0x35a8,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_jpeg0_clk",
+                        .parent_names = (const char *[]){ "jpeg0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_jpeg2_clk = {
+        .halt_reg = 0x35b0,
+        .clkr = {
+                .enable_reg = 0x35b0,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_jpeg2_clk",
+                        .parent_names = (const char *[]){ "jpeg2_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_jpeg_dma_clk = {
+        .halt_reg = 0x35c0,
+        .clkr = {
+                .enable_reg = 0x35c0,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_jpeg_dma_clk",
+                        .parent_names = (const char *[]){ "jpeg_dma_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_jpeg_ahb_clk = {
+        .halt_reg = 0x35b4,
+        .clkr = {
+                .enable_reg = 0x35b4,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_jpeg_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_jpeg_axi_clk = {
+        .halt_reg = 0x35b8,
+        .clkr = {
+                .enable_reg = 0x35b8,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_jpeg_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_vfe_ahb_clk = {
+        .halt_reg = 0x36b8,
+        .clkr = {
+                .enable_reg = 0x36b8,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_vfe_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_vfe_axi_clk = {
+        .halt_reg = 0x36bc,
+        .clkr = {
+                .enable_reg = 0x36bc,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_vfe_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_vfe0_clk = {
+        .halt_reg = 0x36a8,
+        .clkr = {
+                .enable_reg = 0x36a8,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_vfe0_clk",
+                        .parent_names = (const char *[]){ "vfe0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_vfe0_stream_clk = {
+        .halt_reg = 0x3720,
+        .clkr = {
+                .enable_reg = 0x3720,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_vfe0_stream_clk",
+                        .parent_names = (const char *[]){ "vfe0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_vfe0_ahb_clk = {
+        .halt_reg = 0x3668,
+        .clkr = {
+                .enable_reg = 0x3668,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_vfe0_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_vfe1_clk = {
+        .halt_reg = 0x36ac,
+        .clkr = {
+                .enable_reg = 0x36ac,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_vfe1_clk",
+                        .parent_names = (const char *[]){ "vfe1_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_vfe1_stream_clk = {
+        .halt_reg = 0x3724,
+        .clkr = {
+                .enable_reg = 0x3724,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_vfe1_stream_clk",
+                        .parent_names = (const char *[]){ "vfe1_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_vfe1_ahb_clk = {
+        .halt_reg = 0x3678,
+        .clkr = {
+                .enable_reg = 0x3678,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_vfe1_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi_vfe0_clk = {
+        .halt_reg = 0x3704,
+        .clkr = {
+                .enable_reg = 0x3704,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi_vfe0_clk",
+                        .parent_names = (const char *[]){ "vfe0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi_vfe1_clk = {
+        .halt_reg = 0x3714,
+        .clkr = {
+                .enable_reg = 0x3714,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi_vfe1_clk",
+                        .parent_names = (const char *[]){ "vfe1_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_cpp_vbif_ahb_clk = {
+        .halt_reg = 0x36c8,
+        .clkr = {
+                .enable_reg = 0x36c8,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_cpp_vbif_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_cpp_axi_clk = {
+        .halt_reg = 0x36c4,
+        .clkr = {
+                .enable_reg = 0x36c4,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_cpp_axi_clk",
+                        .parent_names = (const char *[]){ "axi_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_cpp_clk = {
+        .halt_reg = 0x36b0,
+        .clkr = {
+                .enable_reg = 0x36b0,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_cpp_clk",
+                        .parent_names = (const char *[]){ "cpp_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_cpp_ahb_clk = {
+        .halt_reg = 0x36b4,
+        .clkr = {
+                .enable_reg = 0x36b4,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_cpp_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi0_clk = {
+        .halt_reg = 0x30b4,
+        .clkr = {
+                .enable_reg = 0x30b4,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi0_clk",
+                        .parent_names = (const char *[]){ "csi0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi0_ahb_clk = {
+        .halt_reg = 0x30bc,
+        .clkr = {
+                .enable_reg = 0x30bc,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi0_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi0phy_clk = {
+        .halt_reg = 0x30c4,
+        .clkr = {
+                .enable_reg = 0x30c4,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi0phy_clk",
+                        .parent_names = (const char *[]){ "csi0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi0rdi_clk = {
+        .halt_reg = 0x30d4,
+        .clkr = {
+                .enable_reg = 0x30d4,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi0rdi_clk",
+                        .parent_names = (const char *[]){ "csi0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi0pix_clk = {
+        .halt_reg = 0x30e4,
+        .clkr = {
+                .enable_reg = 0x30e4,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi0pix_clk",
+                        .parent_names = (const char *[]){ "csi0_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi1_clk = {
+        .halt_reg = 0x3124,
+        .clkr = {
+                .enable_reg = 0x3124,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi1_clk",
+                        .parent_names = (const char *[]){ "csi1_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi1_ahb_clk = {
+        .halt_reg = 0x3128,
+        .clkr = {
+                .enable_reg = 0x3128,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi1_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi1phy_clk = {
+        .halt_reg = 0x3134,
+        .clkr = {
+                .enable_reg = 0x3134,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi1phy_clk",
+                        .parent_names = (const char *[]){ "csi1_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi1rdi_clk = {
+        .halt_reg = 0x3144,
+        .clkr = {
+                .enable_reg = 0x3144,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi1rdi_clk",
+                        .parent_names = (const char *[]){ "csi1_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi1pix_clk = {
+        .halt_reg = 0x3154,
+        .clkr = {
+                .enable_reg = 0x3154,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi1pix_clk",
+                        .parent_names = (const char *[]){ "csi1_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi2_clk = {
+        .halt_reg = 0x3184,
+        .clkr = {
+                .enable_reg = 0x3184,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi2_clk",
+                        .parent_names = (const char *[]){ "csi2_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi2_ahb_clk = {
+        .halt_reg = 0x3188,
+        .clkr = {
+                .enable_reg = 0x3188,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi2_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi2phy_clk = {
+        .halt_reg = 0x3194,
+        .clkr = {
+                .enable_reg = 0x3194,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi2phy_clk",
+                        .parent_names = (const char *[]){ "csi2_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi2rdi_clk = {
+        .halt_reg = 0x31a4,
+        .clkr = {
+                .enable_reg = 0x31a4,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi2rdi_clk",
+                        .parent_names = (const char *[]){ "csi2_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi2pix_clk = {
+        .halt_reg = 0x31b4,
+        .clkr = {
+                .enable_reg = 0x31b4,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi2pix_clk",
+                        .parent_names = (const char *[]){ "csi2_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi3_clk = {
+        .halt_reg = 0x31e4,
+        .clkr = {
+                .enable_reg = 0x31e4,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi3_clk",
+                        .parent_names = (const char *[]){ "csi3_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi3_ahb_clk = {
+        .halt_reg = 0x31e8,
+        .clkr = {
+                .enable_reg = 0x31e8,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi3_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi3phy_clk = {
+        .halt_reg = 0x31f4,
+        .clkr = {
+                .enable_reg = 0x31f4,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi3phy_clk",
+                        .parent_names = (const char *[]){ "csi3_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi3rdi_clk = {
+        .halt_reg = 0x3204,
+        .clkr = {
+                .enable_reg = 0x3204,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi3rdi_clk",
+                        .parent_names = (const char *[]){ "csi3_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_csi3pix_clk = {
+        .halt_reg = 0x3214,
+        .clkr = {
+                .enable_reg = 0x3214,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_csi3pix_clk",
+                        .parent_names = (const char *[]){ "csi3_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch camss_ispif_ahb_clk = {
+        .halt_reg = 0x3224,
+        .clkr = {
+                .enable_reg = 0x3224,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "camss_ispif_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch fd_core_clk = {
+        .halt_reg = 0x3b68,
+        .clkr = {
+                .enable_reg = 0x3b68,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "fd_core_clk",
+                        .parent_names = (const char *[]){ "fd_core_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch fd_core_uar_clk = {
+        .halt_reg = 0x3b6c,
+        .clkr = {
+                .enable_reg = 0x3b6c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "fd_core_uar_clk",
+                        .parent_names = (const char *[]){ "fd_core_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch fd_ahb_clk = {
+        .halt_reg = 0x3ba74,
+        .clkr = {
+                .enable_reg = 0x3ba74,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "fd_ahb_clk",
+                        .parent_names = (const char *[]){ "ahb_clk_src" },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_hw *mmcc_msm8996_hws[] = {
+        &gpll0_div.hw,
+};
+
+static struct clk_regmap *mmcc_msm8996_clocks[] = {
+        [MMPLL0_EARLY] = &mmpll0_early.clkr,
+        [MMPLL0_PLL] = &mmpll0.clkr,
+        [MMPLL1_EARLY] = &mmpll1_early.clkr,
+        [MMPLL1_PLL] = &mmpll1.clkr,
+        [MMPLL2_EARLY] = &mmpll2_early.clkr,
+        [MMPLL2_PLL] = &mmpll2.clkr,
+        [MMPLL3_EARLY] = &mmpll3_early.clkr,
+        [MMPLL3_PLL] = &mmpll3.clkr,
+        [MMPLL4_EARLY] = &mmpll4_early.clkr,
+        [MMPLL4_PLL] = &mmpll4.clkr,
+        [MMPLL5_EARLY] = &mmpll5_early.clkr,
+        [MMPLL5_PLL] = &mmpll5.clkr,
+        [MMPLL8_EARLY] = &mmpll8_early.clkr,
+        [MMPLL8_PLL] = &mmpll8.clkr,
+        [MMPLL9_EARLY] = &mmpll9_early.clkr,
+        [MMPLL9_PLL] = &mmpll9.clkr,
+        [AHB_CLK_SRC] = &ahb_clk_src.clkr,
+        [AXI_CLK_SRC] = &axi_clk_src.clkr,
+        [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
+        [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
+        [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
+        [ISENSE_CLK_SRC] = &isense_clk_src.clkr,
+        [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
+        [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
+        [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
+        [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
+        [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
+        [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
+        [MDP_CLK_SRC] = &mdp_clk_src.clkr,
+        [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
+        [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
+        [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
+        [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
+        [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
+        [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
+        [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
+        [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
+        [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
+        [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
+        [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
+        [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
+        [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
+        [CCI_CLK_SRC] = &cci_clk_src.clkr,
+        [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
+        [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
+        [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
+        [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr,
+        [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr,
+        [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr,
+        [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
+        [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
+        [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
+        [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
+        [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
+        [CPP_CLK_SRC] = &cpp_clk_src.clkr,
+        [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
+        [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
+        [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
+        [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
+        [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
+        [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr,
+        [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr,
+        [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
+        [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr,
+        [MMSS_MMAGIC_AXI_CLK] = &mmss_mmagic_axi_clk.clkr,
+        [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr,
+        [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr,
+        [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr,
+        [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr,
+        [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr,
+        [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr,
+        [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr,
+        [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr,
+        [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr,
+        [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr,
+        [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr,
+        [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr,
+        [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr,
+        [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr,
+        [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr,
+        [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr,
+        [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr,
+        [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr,
+        [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr,
+        [MMAGIC_BIMC_AXI_CLK] = &mmagic_bimc_axi_clk.clkr,
+        [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr,
+        [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr,
+        [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr,
+        [GPU_AHB_CLK] = &gpu_ahb_clk.clkr,
+        [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr,
+        [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
+        [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
+        [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
+        [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
+        [VIDEO_CORE_CLK] = &video_core_clk.clkr,
+        [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
+        [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
+        [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
+        [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
+        [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
+        [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
+        [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
+        [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
+        [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
+        [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
+        [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
+        [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
+        [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
+        [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
+        [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
+        [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
+        [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
+        [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
+        [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
+        [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
+        [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
+        [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
+        [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
+        [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
+        [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
+        [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
+        [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
+        [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
+        [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
+        [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
+        [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
+        [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
+        [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr,
+        [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr,
+        [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr,
+        [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
+        [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr,
+        [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
+        [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
+        [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
+        [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr,
+        [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr,
+        [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
+        [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
+        [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
+        [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
+        [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
+        [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
+        [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
+        [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
+        [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
+        [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
+        [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
+        [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
+        [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
+        [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
+        [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
+        [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
+        [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
+        [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
+        [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
+        [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
+        [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
+        [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
+        [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
+        [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
+        [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
+        [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
+        [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
+        [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
+        [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
+        [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
+        [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
+        [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
+        [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
+        [FD_CORE_CLK] = &fd_core_clk.clkr,
+        [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
+        [FD_AHB_CLK] = &fd_ahb_clk.clkr,
+};
+
+static const struct qcom_reset_map mmcc_msm8996_resets[] = {
+        [MMAGICAHB_BCR] = { 0x5020 },
+        [MMAGIC_CFG_BCR] = { 0x5050 },
+        [MISC_BCR] = { 0x5010 },
+        [BTO_BCR] = { 0x5030 },
+        [MMAGICAXI_BCR] = { 0x5060 },
+        [MMAGICMAXI_BCR] = { 0x5070 },
+        [DSA_BCR] = { 0x50a0 },
+        [MMAGIC_CAMSS_BCR] = { 0x3c40 },
+        [THROTTLE_CAMSS_BCR] = { 0x3c30 },
+        [SMMU_VFE_BCR] = { 0x3c00 },
+        [SMMU_CPP_BCR] = { 0x3c10 },
+        [SMMU_JPEG_BCR] = { 0x3c20 },
+        [MMAGIC_MDSS_BCR] = { 0x2470 },
+        [THROTTLE_MDSS_BCR] = { 0x2460 },
+        [SMMU_ROT_BCR] = { 0x2440 },
+        [SMMU_MDP_BCR] = { 0x2450 },
+        [MMAGIC_VIDEO_BCR] = { 0x1190 },
+        [THROTTLE_VIDEO_BCR] = { 0x1180 },
+        [SMMU_VIDEO_BCR] = { 0x1170 },
+        [MMAGIC_BIMC_BCR] = { 0x5290 },
+        [GPU_GX_BCR] = { 0x4020 },
+        [GPU_BCR] = { 0x4030 },
+        [GPU_AON_BCR] = { 0x4040 },
+        [VMEM_BCR] = { 0x1200 },
+        [MMSS_RBCPR_BCR] = { 0x4080 },
+        [VIDEO_BCR] = { 0x1020 },
+        [MDSS_BCR] = { 0x2300 },
+        [CAMSS_TOP_BCR] = { 0x3480 },
+        [CAMSS_AHB_BCR] = { 0x3488 },
+        [CAMSS_MICRO_BCR] = { 0x3490 },
+        [CAMSS_CCI_BCR] = { 0x3340 },
+        [CAMSS_PHY0_BCR] = { 0x3020 },
+        [CAMSS_PHY1_BCR] = { 0x3050 },
+        [CAMSS_PHY2_BCR] = { 0x3080 },
+        [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
+        [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
+        [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
+        [CAMSS_JPEG_BCR] = { 0x35a0 },
+        [CAMSS_VFE_BCR] = { 0x36a0 },
+        [CAMSS_VFE0_BCR] = { 0x3660 },
+        [CAMSS_VFE1_BCR] = { 0x3670 },
+        [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
+        [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
+        [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
+        [CAMSS_CPP_BCR] = { 0x36d0 },
+        [CAMSS_CSI0_BCR] = { 0x30b0 },
+        [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
+        [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
+        [CAMSS_CSI1_BCR] = { 0x3120 },
+        [CAMSS_CSI1RDI_BCR] = { 0x3140 },
+        [CAMSS_CSI1PIX_BCR] = { 0x3150 },
+        [CAMSS_CSI2_BCR] = { 0x3180 },
+        [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
+        [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
+        [CAMSS_CSI3_BCR] = { 0x31e0 },
+        [CAMSS_CSI3RDI_BCR] = { 0x3200 },
+        [CAMSS_CSI3PIX_BCR] = { 0x3210 },
+        [CAMSS_ISPIF_BCR] = { 0x3220 },
+        [FD_BCR] = { 0x3b60 },
+        [MMSS_SPDM_RM_BCR] = { 0x300 },
+};
+
+static const struct regmap_config mmcc_msm8996_regmap_config = {
+        .reg_bits       = 32,
+        .reg_stride     = 4,
+        .val_bits       = 32,
+        .max_register   = 0xb008,
+        .fast_io        = true,
+};
+
+static const struct qcom_cc_desc mmcc_msm8996_desc = {
+        .config = &mmcc_msm8996_regmap_config,
+        .clks = mmcc_msm8996_clocks,
+        .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks),
+        .resets = mmcc_msm8996_resets,
+        .num_resets = ARRAY_SIZE(mmcc_msm8996_resets),
+};
+
+static const struct of_device_id mmcc_msm8996_match_table[] = {
+        { .compatible = "qcom,mmcc-msm8996" },
+        { }
+};
+MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table);
+
+static int mmcc_msm8996_probe(struct platform_device *pdev)
+{
+        struct clk *clk;
+        struct device *dev = &pdev->dev;
+        int i;
+        struct regmap *regmap;
+
+        regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc);
+        if (IS_ERR(regmap))
+                return PTR_ERR(regmap);
+
+        /* Disable the AHB DCD */
+        regmap_update_bits(regmap, 0x50d8, BIT(31), 0);
+        /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */
+        regmap_update_bits(regmap, 0x5054, BIT(15), 0);
+
+        for (i = 0; i < ARRAY_SIZE(mmcc_msm8996_hws); i++) {
+                clk = devm_clk_register(dev, mmcc_msm8996_hws[i]);
+                if (IS_ERR(clk))
+                        return PTR_ERR(clk);
+        }
+
+        return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap);
+}
+
+static struct platform_driver mmcc_msm8996_driver = {
+        .probe          = mmcc_msm8996_probe,
+        .driver         = {
+                .name   = "mmcc-msm8996",
+                .of_match_table = mmcc_msm8996_match_table,
+        },
+};
+module_platform_driver(mmcc_msm8996_driver);
+
+MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:mmcc-msm8996");
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h
new file mode 100644
index 000000000000..888e75ce8fec
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -0,0 +1,339 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8996_H
+
+#define GPLL0_EARLY                                             0
+#define GPLL0                                                   1
+#define GPLL1_EARLY                                             2
+#define GPLL1                                                   3
+#define GPLL2_EARLY                                             4
+#define GPLL2                                                   5
+#define GPLL3_EARLY                                             6
+#define GPLL3                                                   7
+#define GPLL4_EARLY                                             8
+#define GPLL4                                                   9
+#define SYSTEM_NOC_CLK_SRC                                      10
+#define CONFIG_NOC_CLK_SRC                                      11
+#define PERIPH_NOC_CLK_SRC                                      12
+#define MMSS_BIMC_GFX_CLK_SRC                                   13
+#define USB30_MASTER_CLK_SRC                                    14
+#define USB30_MOCK_UTMI_CLK_SRC                                 15
+#define USB3_PHY_AUX_CLK_SRC                                    16
+#define USB20_MASTER_CLK_SRC                                    17
+#define USB20_MOCK_UTMI_CLK_SRC                                 18
+#define SDCC1_APPS_CLK_SRC                                      19
+#define SDCC1_ICE_CORE_CLK_SRC                                  20
+#define SDCC2_APPS_CLK_SRC                                      21
+#define SDCC3_APPS_CLK_SRC                                      22
+#define SDCC4_APPS_CLK_SRC                                      23
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC                             24
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC                             25
+#define BLSP1_UART1_APPS_CLK_SRC                                26
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC                             27
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC                             28
+#define BLSP1_UART2_APPS_CLK_SRC                                29
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC                             30
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC                             31
+#define BLSP1_UART3_APPS_CLK_SRC                                32
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC                             33
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC                             34
+#define BLSP1_UART4_APPS_CLK_SRC                                35
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC                             36
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC                             37
+#define BLSP1_UART5_APPS_CLK_SRC                                38
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC                             39
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC                             40
+#define BLSP1_UART6_APPS_CLK_SRC                                41
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC                             42
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC                             43
+#define BLSP2_UART1_APPS_CLK_SRC                                44
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC                             45
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC                             46
+#define BLSP2_UART2_APPS_CLK_SRC                                47
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC                             48
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC                             49
+#define BLSP2_UART3_APPS_CLK_SRC                                50
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC                             51
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC                             52
+#define BLSP2_UART4_APPS_CLK_SRC                                53
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC                             54
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC                             55
+#define BLSP2_UART5_APPS_CLK_SRC                                56
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC                             57
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC                             58
+#define BLSP2_UART6_APPS_CLK_SRC                                59
+#define PDM2_CLK_SRC                                            60
+#define TSIF_REF_CLK_SRC                                        61
+#define CE1_CLK_SRC                                             62
+#define GCC_SLEEP_CLK_SRC                                       63
+#define BIMC_CLK_SRC                                            64
+#define HMSS_AHB_CLK_SRC                                        65
+#define BIMC_HMSS_AXI_CLK_SRC                                   66
+#define HMSS_RBCPR_CLK_SRC                                      67
+#define HMSS_GPLL0_CLK_SRC                                      68
+#define GP1_CLK_SRC                                             69
+#define GP2_CLK_SRC                                             70
+#define GP3_CLK_SRC                                             71
+#define PCIE_AUX_CLK_SRC                                        72
+#define UFS_AXI_CLK_SRC                                         73
+#define UFS_ICE_CORE_CLK_SRC                                    74
+#define QSPI_SER_CLK_SRC                                        75
+#define GCC_SYS_NOC_AXI_CLK                                     76
+#define GCC_SYS_NOC_HMSS_AHB_CLK                                77
+#define GCC_SNOC_CNOC_AHB_CLK                                   78
+#define GCC_SNOC_PNOC_AHB_CLK                                   79
+#define GCC_SYS_NOC_AT_CLK                                      80
+#define GCC_SYS_NOC_USB3_AXI_CLK                                81
+#define GCC_SYS_NOC_UFS_AXI_CLK                                 82
+#define GCC_CFG_NOC_AHB_CLK                                     83
+#define GCC_PERIPH_NOC_AHB_CLK                                  84
+#define GCC_PERIPH_NOC_USB20_AHB_CLK                            85
+#define GCC_TIC_CLK                                             86
+#define GCC_IMEM_AXI_CLK                                        87
+#define GCC_MMSS_SYS_NOC_AXI_CLK                                88
+#define GCC_MMSS_NOC_CFG_AHB_CLK                                89
+#define GCC_MMSS_BIMC_GFX_CLK                                   90
+#define GCC_USB30_MASTER_CLK                                    91
+#define GCC_USB30_SLEEP_CLK                                     92
+#define GCC_USB30_MOCK_UTMI_CLK                                 93
+#define GCC_USB3_PHY_AUX_CLK                                    94
+#define GCC_USB3_PHY_PIPE_CLK                                   95
+#define GCC_USB20_MASTER_CLK                                    96
+#define GCC_USB20_SLEEP_CLK                                     97
+#define GCC_USB20_MOCK_UTMI_CLK                                 98
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK                             99
+#define GCC_SDCC1_APPS_CLK                                      100
+#define GCC_SDCC1_AHB_CLK                                       101
+#define GCC_SDCC1_ICE_CORE_CLK                                  102
+#define GCC_SDCC2_APPS_CLK                                      103
+#define GCC_SDCC2_AHB_CLK                                       104
+#define GCC_SDCC3_APPS_CLK                                      105
+#define GCC_SDCC3_AHB_CLK                                       106
+#define GCC_SDCC4_APPS_CLK                                      107
+#define GCC_SDCC4_AHB_CLK                                       108
+#define GCC_BLSP1_AHB_CLK                                       109
+#define GCC_BLSP1_SLEEP_CLK                                     110
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK                             111
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK                             112
+#define GCC_BLSP1_UART1_APPS_CLK                                113
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK                             114
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK                             115
+#define GCC_BLSP1_UART2_APPS_CLK                                116
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK                             117
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK                             118
+#define GCC_BLSP1_UART3_APPS_CLK                                119
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK                             120
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK                             121
+#define GCC_BLSP1_UART4_APPS_CLK                                122
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK                             123
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK                             124
+#define GCC_BLSP1_UART5_APPS_CLK                                125
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK                             126
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK                             127
+#define GCC_BLSP1_UART6_APPS_CLK                                128
+#define GCC_BLSP2_AHB_CLK                                       129
+#define GCC_BLSP2_SLEEP_CLK                                     130
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK                             131
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK                             132
+#define GCC_BLSP2_UART1_APPS_CLK                                133
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK                             134
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK                             135
+#define GCC_BLSP2_UART2_APPS_CLK                                136
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK                             137
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK                             138
+#define GCC_BLSP2_UART3_APPS_CLK                                139
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK                             140
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK                             141
+#define GCC_BLSP2_UART4_APPS_CLK                                142
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK                             143
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK                             144
+#define GCC_BLSP2_UART5_APPS_CLK                                145
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK                             146
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK                             147
+#define GCC_BLSP2_UART6_APPS_CLK                                148
+#define GCC_PDM_AHB_CLK                                         149
+#define GCC_PDM_XO4_CLK                                         150
+#define GCC_PDM2_CLK                                            151
+#define GCC_PRNG_AHB_CLK                                        152
+#define GCC_TSIF_AHB_CLK                                        153
+#define GCC_TSIF_REF_CLK                                        154
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK                          155
+#define GCC_TCSR_AHB_CLK                                        156
+#define GCC_BOOT_ROM_AHB_CLK                                    157
+#define GCC_MSG_RAM_AHB_CLK                                     158
+#define GCC_TLMM_AHB_CLK                                        159
+#define GCC_TLMM_CLK                                            160
+#define GCC_MPM_AHB_CLK                                         161
+#define GCC_SPMI_SER_CLK                                        162
+#define GCC_SPMI_CNOC_AHB_CLK                                   163
+#define GCC_CE1_CLK                                             164
+#define GCC_CE1_AXI_CLK                                         165
+#define GCC_CE1_AHB_CLK                                         166
+#define GCC_BIMC_HMSS_AXI_CLK                                   167
+#define GCC_BIMC_GFX_CLK                                        168
+#define GCC_HMSS_AHB_CLK                                        169
+#define GCC_HMSS_SLV_AXI_CLK                                    170
+#define GCC_HMSS_MSTR_AXI_CLK                                   171
+#define GCC_HMSS_RBCPR_CLK                                      172
+#define GCC_GP1_CLK                                             173
+#define GCC_GP2_CLK                                             174
+#define GCC_GP3_CLK                                             175
+#define GCC_PCIE_0_SLV_AXI_CLK                                  176
+#define GCC_PCIE_0_MSTR_AXI_CLK                                 177
+#define GCC_PCIE_0_CFG_AHB_CLK                                  178
+#define GCC_PCIE_0_AUX_CLK                                      179
+#define GCC_PCIE_0_PIPE_CLK                                     180
+#define GCC_PCIE_1_SLV_AXI_CLK                                  181
+#define GCC_PCIE_1_MSTR_AXI_CLK                                 182
+#define GCC_PCIE_1_CFG_AHB_CLK                                  183
+#define GCC_PCIE_1_AUX_CLK                                      184
+#define GCC_PCIE_1_PIPE_CLK                                     185
+#define GCC_PCIE_2_SLV_AXI_CLK                                  186
+#define GCC_PCIE_2_MSTR_AXI_CLK                                 187
+#define GCC_PCIE_2_CFG_AHB_CLK                                  188
+#define GCC_PCIE_2_AUX_CLK                                      189
+#define GCC_PCIE_2_PIPE_CLK                                     190
+#define GCC_PCIE_PHY_CFG_AHB_CLK                                191
+#define GCC_PCIE_PHY_AUX_CLK                                    192
+#define GCC_UFS_AXI_CLK                                         193
+#define GCC_UFS_AHB_CLK                                         194
+#define GCC_UFS_TX_CFG_CLK                                      195
+#define GCC_UFS_RX_CFG_CLK                                      196
+#define GCC_UFS_TX_SYMBOL_0_CLK                                 197
+#define GCC_UFS_RX_SYMBOL_0_CLK                                 198
+#define GCC_UFS_RX_SYMBOL_1_CLK                                 199
+#define GCC_UFS_UNIPRO_CORE_CLK                                 200
+#define GCC_UFS_ICE_CORE_CLK                                    201
+#define GCC_UFS_SYS_CLK_CORE_CLK                                202
+#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK                          203
+#define GCC_AGGRE0_SNOC_AXI_CLK                                 204
+#define GCC_AGGRE0_CNOC_AHB_CLK                                 205
+#define GCC_SMMU_AGGRE0_AXI_CLK                                 206
+#define GCC_SMMU_AGGRE0_AHB_CLK                                 207
+#define GCC_AGGRE1_PNOC_AHB_CLK                                 208
+#define GCC_AGGRE2_UFS_AXI_CLK                                  209
+#define GCC_AGGRE2_USB3_AXI_CLK                                 210
+#define GCC_QSPI_AHB_CLK                                        211
+#define GCC_QSPI_SER_CLK                                        212
+#define GCC_USB3_CLKREF_CLK                                     213
+#define GCC_HDMI_CLKREF_CLK                                     214
+#define GCC_UFS_CLKREF_CLK                                      215
+#define GCC_PCIE_CLKREF_CLK                                     216
+#define GCC_RX2_USB2_CLKREF_CLK                                 217
+#define GCC_RX1_USB2_CLKREF_CLK                                 218
+
+#define GCC_SYSTEM_NOC_BCR                                      0
+#define GCC_CONFIG_NOC_BCR                                      1
+#define GCC_PERIPH_NOC_BCR                                      2
+#define GCC_IMEM_BCR                                            3
+#define GCC_MMSS_BCR                                            4
+#define GCC_PIMEM_BCR                                           5
+#define GCC_QDSS_BCR                                            6
+#define GCC_USB_30_BCR                                          7
+#define GCC_USB_20_BCR                                          8
+#define GCC_QUSB2PHY_PRIM_BCR                                   9
+#define GCC_QUSB2PHY_SEC_BCR                                    10
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR                             11
+#define GCC_SDCC1_BCR                                           12
+#define GCC_SDCC2_BCR                                           13
+#define GCC_SDCC3_BCR                                           14
+#define GCC_SDCC4_BCR                                           15
+#define GCC_BLSP1_BCR                                           16
+#define GCC_BLSP1_QUP1_BCR                                      17
+#define GCC_BLSP1_UART1_BCR                                     18
+#define GCC_BLSP1_QUP2_BCR                                      19
+#define GCC_BLSP1_UART2_BCR                                     20
+#define GCC_BLSP1_QUP3_BCR                                      21
+#define GCC_BLSP1_UART3_BCR                                     22
+#define GCC_BLSP1_QUP4_BCR                                      23
+#define GCC_BLSP1_UART4_BCR                                     24
+#define GCC_BLSP1_QUP5_BCR                                      25
+#define GCC_BLSP1_UART5_BCR                                     26
+#define GCC_BLSP1_QUP6_BCR                                      27
+#define GCC_BLSP1_UART6_BCR                                     28
+#define GCC_BLSP2_BCR                                           29
+#define GCC_BLSP2_QUP1_BCR                                      30
+#define GCC_BLSP2_UART1_BCR                                     31
+#define GCC_BLSP2_QUP2_BCR                                      32
+#define GCC_BLSP2_UART2_BCR                                     33
+#define GCC_BLSP2_QUP3_BCR                                      34
+#define GCC_BLSP2_UART3_BCR                                     35
+#define GCC_BLSP2_QUP4_BCR                                      36
+#define GCC_BLSP2_UART4_BCR                                     37
+#define GCC_BLSP2_QUP5_BCR                                      38
+#define GCC_BLSP2_UART5_BCR                                     39
+#define GCC_BLSP2_QUP6_BCR                                      40
+#define GCC_BLSP2_UART6_BCR                                     41
+#define GCC_PDM_BCR                                             42
+#define GCC_PRNG_BCR                                            43
+#define GCC_TSIF_BCR                                            44
+#define GCC_TCSR_BCR                                            45
+#define GCC_BOOT_ROM_BCR                                        46
+#define GCC_MSG_RAM_BCR                                         47
+#define GCC_TLMM_BCR                                            48
+#define GCC_MPM_BCR                                             49
+#define GCC_SEC_CTRL_BCR                                        50
+#define GCC_SPMI_BCR                                            51
+#define GCC_SPDM_BCR                                            52
+#define GCC_CE1_BCR                                             53
+#define GCC_BIMC_BCR                                            54
+#define GCC_SNOC_BUS_TIMEOUT0_BCR                               55
+#define GCC_SNOC_BUS_TIMEOUT2_BCR                               56
+#define GCC_SNOC_BUS_TIMEOUT1_BCR                               57
+#define GCC_SNOC_BUS_TIMEOUT3_BCR                               58
+#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR                         59
+#define GCC_PNOC_BUS_TIMEOUT0_BCR                               60
+#define GCC_PNOC_BUS_TIMEOUT1_BCR                               61
+#define GCC_PNOC_BUS_TIMEOUT2_BCR                               62
+#define GCC_PNOC_BUS_TIMEOUT3_BCR                               63
+#define GCC_PNOC_BUS_TIMEOUT4_BCR                               64
+#define GCC_CNOC_BUS_TIMEOUT0_BCR                               65
+#define GCC_CNOC_BUS_TIMEOUT1_BCR                               66
+#define GCC_CNOC_BUS_TIMEOUT2_BCR                               67
+#define GCC_CNOC_BUS_TIMEOUT3_BCR                               68
+#define GCC_CNOC_BUS_TIMEOUT4_BCR                               69
+#define GCC_CNOC_BUS_TIMEOUT5_BCR                               70
+#define GCC_CNOC_BUS_TIMEOUT6_BCR                               71
+#define GCC_CNOC_BUS_TIMEOUT7_BCR                               72
+#define GCC_CNOC_BUS_TIMEOUT8_BCR                               73
+#define GCC_CNOC_BUS_TIMEOUT9_BCR                               74
+#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR                         75
+#define GCC_APB2JTAG_BCR                                        76
+#define GCC_RBCPR_CX_BCR                                        77
+#define GCC_RBCPR_MX_BCR                                        78
+#define GCC_PCIE_0_BCR                                          79
+#define GCC_PCIE_0_PHY_BCR                                      80
+#define GCC_PCIE_1_BCR                                          81
+#define GCC_PCIE_1_PHY_BCR                                      82
+#define GCC_PCIE_2_BCR                                          83
+#define GCC_PCIE_2_PHY_BCR                                      84
+#define GCC_PCIE_PHY_BCR                                        85
+#define GCC_DCD_BCR                                             86
+#define GCC_OBT_ODT_BCR                                         87
+#define GCC_UFS_BCR                                             88
+#define GCC_SSC_BCR                                             89
+#define GCC_VS_BCR                                              90
+#define GCC_AGGRE0_NOC_BCR                                      91
+#define GCC_AGGRE1_NOC_BCR                                      92
+#define GCC_AGGRE2_NOC_BCR                                      93
+#define GCC_DCC_BCR                                             94
+#define GCC_IPA_BCR                                             95
+#define GCC_QSPI_BCR                                            96
+#define GCC_SKL_BCR                                             97
+#define GCC_MSMPU_BCR                                           98
+#define GCC_MSS_Q6_BCR                                          99
+#define GCC_QREFS_VBG_CAL_BCR                                   100
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h
new file mode 100644
index 000000000000..9b81ca65fcec
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8996.h
@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H
+#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H
+
+#define MMPLL0_EARLY                                    0
+#define MMPLL0_PLL                                      1
+#define MMPLL1_EARLY                                    2
+#define MMPLL1_PLL                                      3
+#define MMPLL2_EARLY                                    4
+#define MMPLL2_PLL                                      5
+#define MMPLL3_EARLY                                    6
+#define MMPLL3_PLL                                      7
+#define MMPLL4_EARLY                                    8
+#define MMPLL4_PLL                                      9
+#define MMPLL5_EARLY                                    10
+#define MMPLL5_PLL                                      11
+#define MMPLL8_EARLY                                    12
+#define MMPLL8_PLL                                      13
+#define MMPLL9_EARLY                                    14
+#define MMPLL9_PLL                                      15
+#define AHB_CLK_SRC                                     16
+#define AXI_CLK_SRC                                     17
+#define MAXI_CLK_SRC                                    18
+#define DSA_CORE_CLK_SRC                                19
+#define GFX3D_CLK_SRC                                   20
+#define RBBMTIMER_CLK_SRC                               21
+#define ISENSE_CLK_SRC                                  22
+#define RBCPR_CLK_SRC                                   23
+#define VIDEO_CORE_CLK_SRC                              24
+#define VIDEO_SUBCORE0_CLK_SRC                          25
+#define VIDEO_SUBCORE1_CLK_SRC                          26
+#define PCLK0_CLK_SRC                                   27
+#define PCLK1_CLK_SRC                                   28
+#define MDP_CLK_SRC                                     29
+#define EXTPCLK_CLK_SRC                                 30
+#define VSYNC_CLK_SRC                                   31
+#define HDMI_CLK_SRC                                    32
+#define BYTE0_CLK_SRC                                   33
+#define BYTE1_CLK_SRC                                   34
+#define ESC0_CLK_SRC                                    35
+#define ESC1_CLK_SRC                                    36
+#define CAMSS_GP0_CLK_SRC                               37
+#define CAMSS_GP1_CLK_SRC                               38
+#define MCLK0_CLK_SRC                                   39
+#define MCLK1_CLK_SRC                                   40
+#define MCLK2_CLK_SRC                                   41
+#define MCLK3_CLK_SRC                                   42
+#define CCI_CLK_SRC                                     43
+#define CSI0PHYTIMER_CLK_SRC                            44
+#define CSI1PHYTIMER_CLK_SRC                            45
+#define CSI2PHYTIMER_CLK_SRC                            46
+#define CSIPHY0_3P_CLK_SRC                              47
+#define CSIPHY1_3P_CLK_SRC                              48
+#define CSIPHY2_3P_CLK_SRC                              49
+#define JPEG0_CLK_SRC                                   50
+#define JPEG2_CLK_SRC                                   51
+#define JPEG_DMA_CLK_SRC                                52
+#define VFE0_CLK_SRC                                    53
+#define VFE1_CLK_SRC                                    54
+#define CPP_CLK_SRC                                     55
+#define CSI0_CLK_SRC                                    56
+#define CSI1_CLK_SRC                                    57
+#define CSI2_CLK_SRC                                    58
+#define CSI3_CLK_SRC                                    59
+#define FD_CORE_CLK_SRC                                 60
+#define MMSS_CXO_CLK                                    61
+#define MMSS_SLEEPCLK_CLK                               62
+#define MMSS_MMAGIC_AHB_CLK                             63
+#define MMSS_MMAGIC_CFG_AHB_CLK                         64
+#define MMSS_MISC_AHB_CLK                               65
+#define MMSS_MISC_CXO_CLK                               66
+#define MMSS_BTO_AHB_CLK                                67
+#define MMSS_MMAGIC_AXI_CLK                             68
+#define MMSS_S0_AXI_CLK                                 69
+#define MMSS_MMAGIC_MAXI_CLK                            70
+#define DSA_CORE_CLK                                    71
+#define DSA_NOC_CFG_AHB_CLK                             72
+#define MMAGIC_CAMSS_AXI_CLK                            73
+#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK                    74
+#define THROTTLE_CAMSS_CXO_CLK                          75
+#define THROTTLE_CAMSS_AHB_CLK                          76
+#define THROTTLE_CAMSS_AXI_CLK                          77
+#define SMMU_VFE_AHB_CLK                                78
+#define SMMU_VFE_AXI_CLK                                79
+#define SMMU_CPP_AHB_CLK                                80
+#define SMMU_CPP_AXI_CLK                                81
+#define SMMU_JPEG_AHB_CLK                               82
+#define SMMU_JPEG_AXI_CLK                               83
+#define MMAGIC_MDSS_AXI_CLK                             84
+#define MMAGIC_MDSS_NOC_CFG_AHB_CLK                     85
+#define THROTTLE_MDSS_CXO_CLK                           86
+#define THROTTLE_MDSS_AHB_CLK                           87
+#define THROTTLE_MDSS_AXI_CLK                           88
+#define SMMU_ROT_AHB_CLK                                89
+#define SMMU_ROT_AXI_CLK                                90
+#define SMMU_MDP_AHB_CLK                                91
+#define SMMU_MDP_AXI_CLK                                92
+#define MMAGIC_VIDEO_AXI_CLK                            93
+#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK                    94
+#define THROTTLE_VIDEO_CXO_CLK                          95
+#define THROTTLE_VIDEO_AHB_CLK                          96
+#define THROTTLE_VIDEO_AXI_CLK                          97
+#define SMMU_VIDEO_AHB_CLK                              98
+#define SMMU_VIDEO_AXI_CLK                              99
+#define MMAGIC_BIMC_AXI_CLK                             100
+#define MMAGIC_BIMC_NOC_CFG_AHB_CLK                     101
+#define GPU_GX_GFX3D_CLK                                102
+#define GPU_GX_RBBMTIMER_CLK                            103
+#define GPU_AHB_CLK                                     104
+#define GPU_AON_ISENSE_CLK                              105
+#define VMEM_MAXI_CLK                                   106
+#define VMEM_AHB_CLK                                    107
+#define MMSS_RBCPR_CLK                                  108
+#define MMSS_RBCPR_AHB_CLK                              109
+#define VIDEO_CORE_CLK                                  110
+#define VIDEO_AXI_CLK                                   111
+#define VIDEO_MAXI_CLK                                  112
+#define VIDEO_AHB_CLK                                   113
+#define VIDEO_SUBCORE0_CLK                              114
+#define VIDEO_SUBCORE1_CLK                              115
+#define MDSS_AHB_CLK                                    116
+#define MDSS_HDMI_AHB_CLK                               117
+#define MDSS_AXI_CLK                                    118
+#define MDSS_PCLK0_CLK                                  119
+#define MDSS_PCLK1_CLK                                  120
+#define MDSS_MDP_CLK                                    121
+#define MDSS_EXTPCLK_CLK                                122
+#define MDSS_VSYNC_CLK                                  123
+#define MDSS_HDMI_CLK                                   124
+#define MDSS_BYTE0_CLK                                  125
+#define MDSS_BYTE1_CLK                                  126
+#define MDSS_ESC0_CLK                                   127
+#define MDSS_ESC1_CLK                                   128
+#define CAMSS_TOP_AHB_CLK                               129
+#define CAMSS_AHB_CLK                                   130
+#define CAMSS_MICRO_AHB_CLK                             131
+#define CAMSS_GP0_CLK                                   132
+#define CAMSS_GP1_CLK                                   133
+#define CAMSS_MCLK0_CLK                                 134
+#define CAMSS_MCLK1_CLK                                 135
+#define CAMSS_MCLK2_CLK                                 136
+#define CAMSS_MCLK3_CLK                                 137
+#define CAMSS_CCI_CLK                                   138
+#define CAMSS_CCI_AHB_CLK                               139
+#define CAMSS_CSI0PHYTIMER_CLK                          140
+#define CAMSS_CSI1PHYTIMER_CLK                          141
+#define CAMSS_CSI2PHYTIMER_CLK                          142
+#define CAMSS_CSIPHY0_3P_CLK                            143
+#define CAMSS_CSIPHY1_3P_CLK                            144
+#define CAMSS_CSIPHY2_3P_CLK                            145
+#define CAMSS_JPEG0_CLK                                 146
+#define CAMSS_JPEG2_CLK                                 147
+#define CAMSS_JPEG_DMA_CLK                              148
+#define CAMSS_JPEG_AHB_CLK                              149
+#define CAMSS_JPEG_AXI_CLK                              150
+#define CAMSS_VFE_AHB_CLK                               151
+#define CAMSS_VFE_AXI_CLK                               152
+#define CAMSS_VFE0_CLK                                  153
+#define CAMSS_VFE0_STREAM_CLK                           154
+#define CAMSS_VFE0_AHB_CLK                              155
+#define CAMSS_VFE1_CLK                                  156
+#define CAMSS_VFE1_STREAM_CLK                           157
+#define CAMSS_VFE1_AHB_CLK                              158
+#define CAMSS_CSI_VFE0_CLK                              159
+#define CAMSS_CSI_VFE1_CLK                              160
+#define CAMSS_CPP_VBIF_AHB_CLK                          161
+#define CAMSS_CPP_AXI_CLK                               162
+#define CAMSS_CPP_CLK                                   163
+#define CAMSS_CPP_AHB_CLK                               164
+#define CAMSS_CSI0_CLK                                  165
+#define CAMSS_CSI0_AHB_CLK                              166
+#define CAMSS_CSI0PHY_CLK                               167
+#define CAMSS_CSI0RDI_CLK                               168
+#define CAMSS_CSI0PIX_CLK                               169
+#define CAMSS_CSI1_CLK                                  170
+#define CAMSS_CSI1_AHB_CLK                              171
+#define CAMSS_CSI1PHY_CLK                               172
+#define CAMSS_CSI1RDI_CLK                               173
+#define CAMSS_CSI1PIX_CLK                               174
+#define CAMSS_CSI2_CLK                                  175
+#define CAMSS_CSI2_AHB_CLK                              176
+#define CAMSS_CSI2PHY_CLK                               177
+#define CAMSS_CSI2RDI_CLK                               178
+#define CAMSS_CSI2PIX_CLK                               179
+#define CAMSS_CSI3_CLK                                  180
+#define CAMSS_CSI3_AHB_CLK                              181
+#define CAMSS_CSI3PHY_CLK                               182
+#define CAMSS_CSI3RDI_CLK                               183
+#define CAMSS_CSI3PIX_CLK                               184
+#define CAMSS_ISPIF_AHB_CLK                             185
+#define FD_CORE_CLK                                     186
+#define FD_CORE_UAR_CLK                                 187
+#define FD_AHB_CLK                                      188
+#define MMSS_SPDM_CSI0_CLK                              189
+#define MMSS_SPDM_JPEG_DMA_CLK                          190
+#define MMSS_SPDM_CPP_CLK                               191
+#define MMSS_SPDM_PCLK0_CLK                             192
+#define MMSS_SPDM_AHB_CLK                               193
+#define MMSS_SPDM_GFX3D_CLK                             194
+#define MMSS_SPDM_PCLK1_CLK                             195
+#define MMSS_SPDM_JPEG2_CLK                             196
+#define MMSS_SPDM_DEBUG_CLK                             197
+#define MMSS_SPDM_VFE1_CLK                              198
+#define MMSS_SPDM_VFE0_CLK                              199
+#define MMSS_SPDM_VIDEO_CORE_CLK                        200
+#define MMSS_SPDM_AXI_CLK                               201
+#define MMSS_SPDM_MDP_CLK                               202
+#define MMSS_SPDM_JPEG0_CLK                             203
+#define MMSS_SPDM_RM_AXI_CLK                            204
+#define MMSS_SPDM_RM_MAXI_CLK                           205
+
+#define MMAGICAHB_BCR                                   0
+#define MMAGIC_CFG_BCR                                  1
+#define MISC_BCR                                        2
+#define BTO_BCR                                         3
+#define MMAGICAXI_BCR                                   4
+#define MMAGICMAXI_BCR                                  5
+#define DSA_BCR                                         6
+#define MMAGIC_CAMSS_BCR                                7
+#define THROTTLE_CAMSS_BCR                              8
+#define SMMU_VFE_BCR                                    9
+#define SMMU_CPP_BCR                                    10
+#define SMMU_JPEG_BCR                                   11
+#define MMAGIC_MDSS_BCR                                 12
+#define THROTTLE_MDSS_BCR                               13
+#define SMMU_ROT_BCR                                    14
+#define SMMU_MDP_BCR                                    15
+#define MMAGIC_VIDEO_BCR                                16
+#define THROTTLE_VIDEO_BCR                              17
+#define SMMU_VIDEO_BCR                                  18
+#define MMAGIC_BIMC_BCR                                 19
+#define GPU_GX_BCR                                      20
+#define GPU_BCR                                         21
+#define GPU_AON_BCR                                     22
+#define VMEM_BCR                                        23
+#define MMSS_RBCPR_BCR                                  24
+#define VIDEO_BCR                                       25
+#define MDSS_BCR                                        26
+#define CAMSS_TOP_BCR                                   27
+#define CAMSS_AHB_BCR                                   28
+#define CAMSS_MICRO_BCR                                 29
+#define CAMSS_CCI_BCR                                   30
+#define CAMSS_PHY0_BCR                                  31
+#define CAMSS_PHY1_BCR                                  32
+#define CAMSS_PHY2_BCR                                  33
+#define CAMSS_CSIPHY0_3P_BCR                            34
+#define CAMSS_CSIPHY1_3P_BCR                            35
+#define CAMSS_CSIPHY2_3P_BCR                            36
+#define CAMSS_JPEG_BCR                                  37
+#define CAMSS_VFE_BCR                                   38
+#define CAMSS_VFE0_BCR                                  39
+#define CAMSS_VFE1_BCR                                  40
+#define CAMSS_CSI_VFE0_BCR                              41
+#define CAMSS_CSI_VFE1_BCR                              42
+#define CAMSS_CPP_TOP_BCR                               43
+#define CAMSS_CPP_BCR                                   44
+#define CAMSS_CSI0_BCR                                  45
+#define CAMSS_CSI0RDI_BCR                               46
+#define CAMSS_CSI0PIX_BCR                               47
+#define CAMSS_CSI1_BCR                                  48
+#define CAMSS_CSI1RDI_BCR                               49
+#define CAMSS_CSI1PIX_BCR                               50
+#define CAMSS_CSI2_BCR                                  51
+#define CAMSS_CSI2RDI_BCR                               52
+#define CAMSS_CSI2PIX_BCR                               53
+#define CAMSS_CSI3_BCR                                  54
+#define CAMSS_CSI3RDI_BCR                               55
+#define CAMSS_CSI3PIX_BCR                               56
+#define CAMSS_ISPIF_BCR                                 57
+#define FD_BCR                                          58
+#define MMSS_SPDM_RM_BCR                                59
+
+#endif