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authorDavid S. Miller <davem@davemloft.net>2018-05-15 16:41:16 -0400
committerDavid S. Miller <davem@davemloft.net>2018-05-15 16:41:16 -0400
commit0b7d9978406fba914160342be2ed8af0608bc3ec (patch)
treedc048e4d360e37f0197414dc6fe62b2fc77fa0f8
parent961423f9fcbcfebee5b7a5d6cc0f1069835f25c0 (diff)
parent0ce60edd78d3efa8570362846ea76ce1beb3c2b8 (diff)
Merge branch 'Microsemi-Ocelot-Ethernet-switch-support'
Alexandre Belloni says: ==================== Microsemi Ocelot Ethernet switch support This series adds initial support for the Microsemi Ethernet switch present on Ocelot SoCs. This only has bridging (and STP) support for now and it uses the switchdev framework. Coming features are VLAN filtering, link aggregation, IGMP snooping. The switch can also be connected to an external CPU using PCIe. Also, support for integration on other SoCs will be submitted. The ocelot dts changes are here for reference and should probably go through the MIPS tree once the bindings are accepted. Changes in v3: - Collected Reviewed-by * Switchdev driver: - Fixed two issues reported by kbuild - Modified ethtool statistics to support different layoiut on different chips and take care of counter overflow Changes in v2: - Dropped Microsemi Ocelot PHY support * MIIM driver: - Documented interrupts bindings - Moved the driver to drivers/net/phy/ - Removed unused mutex - Removed MDIO bus scanning * Switchdev driver: - Changed compatible to mscc,vsc7514-switch - Removed unused header inclusion - Factorized MAC table selection in ocelot_mact_select() - Disable the port in ocelot_port_stop() - Fixed the smatch endianness warnings - int to unsinged int where necessary - Removed VID handling for the FDB it has been reworked anyway and will be submitted with VLAN support - Fixed up unused cases in ocelot_port_attr_set() - Added a loop to register all the IO register spaces - the ports are now in an ethernet-ports node I've tried switching to NAPI but this is not working well, mainly because the only way to disable interrupts is to actually mask them in the interrupt controller (it is not possible to tell the switch to stop generating interrupts). ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/net/mscc-miim.txt26
-rw-r--r--Documentation/devicetree/bindings/net/mscc-ocelot.txt82
-rw-r--r--MAINTAINERS6
-rw-r--r--drivers/net/ethernet/Kconfig1
-rw-r--r--drivers/net/ethernet/Makefile1
-rw-r--r--drivers/net/ethernet/mscc/Kconfig30
-rw-r--r--drivers/net/ethernet/mscc/Makefile5
-rw-r--r--drivers/net/ethernet/mscc/ocelot.c1333
-rw-r--r--drivers/net/ethernet/mscc/ocelot.h572
-rw-r--r--drivers/net/ethernet/mscc/ocelot_ana.h625
-rw-r--r--drivers/net/ethernet/mscc/ocelot_board.c316
-rw-r--r--drivers/net/ethernet/mscc/ocelot_dev.h275
-rw-r--r--drivers/net/ethernet/mscc/ocelot_dev_gmii.h154
-rw-r--r--drivers/net/ethernet/mscc/ocelot_hsio.h785
-rw-r--r--drivers/net/ethernet/mscc/ocelot_io.c116
-rw-r--r--drivers/net/ethernet/mscc/ocelot_qs.h78
-rw-r--r--drivers/net/ethernet/mscc/ocelot_qsys.h270
-rw-r--r--drivers/net/ethernet/mscc/ocelot_regs.c497
-rw-r--r--drivers/net/ethernet/mscc/ocelot_rew.h81
-rw-r--r--drivers/net/ethernet/mscc/ocelot_sys.h144
-rw-r--r--drivers/net/phy/Kconfig7
-rw-r--r--drivers/net/phy/Makefile1
-rw-r--r--drivers/net/phy/mdio-mscc-miim.c197
23 files changed, 5602 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/net/mscc-miim.txt b/Documentation/devicetree/bindings/net/mscc-miim.txt
new file mode 100644
index 000000000000..7104679cf59d
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mscc-miim.txt
@@ -0,0 +1,26 @@
1Microsemi MII Management Controller (MIIM) / MDIO
2=================================================
3
4Properties:
5- compatible: must be "mscc,ocelot-miim"
6- reg: The base address of the MDIO bus controller register bank. Optionally, a
7 second register bank can be defined if there is an associated reset register
8 for internal PHYs
9- #address-cells: Must be <1>.
10- #size-cells: Must be <0>. MDIO addresses have no size component.
11- interrupts: interrupt specifier (refer to the interrupt binding)
12
13Typically an MDIO bus might have several children.
14
15Example:
16 mdio@107009c {
17 #address-cells = <1>;
18 #size-cells = <0>;
19 compatible = "mscc,ocelot-miim";
20 reg = <0x107009c 0x36>, <0x10700f0 0x8>;
21 interrupts = <14>;
22
23 phy0: ethernet-phy@0 {
24 reg = <0>;
25 };
26 };
diff --git a/Documentation/devicetree/bindings/net/mscc-ocelot.txt b/Documentation/devicetree/bindings/net/mscc-ocelot.txt
new file mode 100644
index 000000000000..0a84711abece
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mscc-ocelot.txt
@@ -0,0 +1,82 @@
1Microsemi Ocelot network Switch
2===============================
3
4The Microsemi Ocelot network switch can be found on Microsemi SoCs (VSC7513,
5VSC7514)
6
7Required properties:
8- compatible: Should be "mscc,vsc7514-switch"
9- reg: Must contain an (offset, length) pair of the register set for each
10 entry in reg-names.
11- reg-names: Must include the following entries:
12 - "sys"
13 - "rew"
14 - "qs"
15 - "hsio"
16 - "qsys"
17 - "ana"
18 - "portX" with X from 0 to the number of last port index available on that
19 switch
20- interrupts: Should contain the switch interrupts for frame extraction and
21 frame injection
22- interrupt-names: should contain the interrupt names: "xtr", "inj"
23- ethernet-ports: A container for child nodes representing switch ports.
24
25The ethernet-ports container has the following properties
26
27Required properties:
28
29- #address-cells: Must be 1
30- #size-cells: Must be 0
31
32Each port node must have the following mandatory properties:
33- reg: Describes the port address in the switch
34
35Port nodes may also contain the following optional standardised
36properties, described in binding documents:
37
38- phy-handle: Phandle to a PHY on an MDIO bus. See
39 Documentation/devicetree/bindings/net/ethernet.txt for details.
40
41Example:
42
43 switch@1010000 {
44 compatible = "mscc,vsc7514-switch";
45 reg = <0x1010000 0x10000>,
46 <0x1030000 0x10000>,
47 <0x1080000 0x100>,
48 <0x10d0000 0x10000>,
49 <0x11e0000 0x100>,
50 <0x11f0000 0x100>,
51 <0x1200000 0x100>,
52 <0x1210000 0x100>,
53 <0x1220000 0x100>,
54 <0x1230000 0x100>,
55 <0x1240000 0x100>,
56 <0x1250000 0x100>,
57 <0x1260000 0x100>,
58 <0x1270000 0x100>,
59 <0x1280000 0x100>,
60 <0x1800000 0x80000>,
61 <0x1880000 0x10000>;
62 reg-names = "sys", "rew", "qs", "hsio", "port0",
63 "port1", "port2", "port3", "port4", "port5",
64 "port6", "port7", "port8", "port9", "port10",
65 "qsys", "ana";
66 interrupts = <21 22>;
67 interrupt-names = "xtr", "inj";
68
69 ethernet-ports {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 port0: port@0 {
74 reg = <0>;
75 phy-handle = <&phy0>;
76 };
77 port1: port@1 {
78 reg = <1>;
79 phy-handle = <&phy1>;
80 };
81 };
82 };
diff --git a/MAINTAINERS b/MAINTAINERS
index c6989d04afef..658880464b9d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9279,6 +9279,12 @@ F: include/linux/cciss*.h
9279F: include/uapi/linux/cciss*.h 9279F: include/uapi/linux/cciss*.h
9280F: Documentation/scsi/smartpqi.txt 9280F: Documentation/scsi/smartpqi.txt
9281 9281
9282MICROSEMI ETHERNET SWITCH DRIVER
9283M: Alexandre Belloni <alexandre.belloni@bootlin.com>
9284L: netdev@vger.kernel.org
9285S: Supported
9286F: drivers/net/ethernet/mscc/
9287
9282MICROSOFT SURFACE PRO 3 BUTTON DRIVER 9288MICROSOFT SURFACE PRO 3 BUTTON DRIVER
9283M: Chen Yu <yu.c.chen@intel.com> 9289M: Chen Yu <yu.c.chen@intel.com>
9284L: platform-driver-x86@vger.kernel.org 9290L: platform-driver-x86@vger.kernel.org
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index 603a5704dab8..54d71e1c48d5 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -114,6 +114,7 @@ source "drivers/net/ethernet/mediatek/Kconfig"
114source "drivers/net/ethernet/mellanox/Kconfig" 114source "drivers/net/ethernet/mellanox/Kconfig"
115source "drivers/net/ethernet/micrel/Kconfig" 115source "drivers/net/ethernet/micrel/Kconfig"
116source "drivers/net/ethernet/microchip/Kconfig" 116source "drivers/net/ethernet/microchip/Kconfig"
117source "drivers/net/ethernet/mscc/Kconfig"
117source "drivers/net/ethernet/moxa/Kconfig" 118source "drivers/net/ethernet/moxa/Kconfig"
118source "drivers/net/ethernet/myricom/Kconfig" 119source "drivers/net/ethernet/myricom/Kconfig"
119 120
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index 2bfd2eea50bf..8fbfe9ce2fa5 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_NET_VENDOR_MEDIATEK) += mediatek/
55obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ 55obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
56obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/ 56obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/
57obj-$(CONFIG_NET_VENDOR_MICROCHIP) += microchip/ 57obj-$(CONFIG_NET_VENDOR_MICROCHIP) += microchip/
58obj-$(CONFIG_NET_VENDOR_MICROSEMI) += mscc/
58obj-$(CONFIG_NET_VENDOR_MOXART) += moxa/ 59obj-$(CONFIG_NET_VENDOR_MOXART) += moxa/
59obj-$(CONFIG_NET_VENDOR_MYRI) += myricom/ 60obj-$(CONFIG_NET_VENDOR_MYRI) += myricom/
60obj-$(CONFIG_FEALNX) += fealnx.o 61obj-$(CONFIG_FEALNX) += fealnx.o
diff --git a/drivers/net/ethernet/mscc/Kconfig b/drivers/net/ethernet/mscc/Kconfig
new file mode 100644
index 000000000000..36c84625d54e
--- /dev/null
+++ b/drivers/net/ethernet/mscc/Kconfig
@@ -0,0 +1,30 @@
1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2config NET_VENDOR_MICROSEMI
3 bool "Microsemi devices"
4 default y
5 help
6 If you have a network (Ethernet) card belonging to this class, say Y.
7
8 Note that the answer to this question doesn't directly affect the
9 kernel: saying N will just cause the configurator to skip all
10 the questions about Microsemi devices.
11
12if NET_VENDOR_MICROSEMI
13
14config MSCC_OCELOT_SWITCH
15 tristate "Ocelot switch driver"
16 depends on NET_SWITCHDEV
17 depends on HAS_IOMEM
18 select PHYLIB
19 select REGMAP_MMIO
20 help
21 This driver supports the Ocelot network switch device.
22
23config MSCC_OCELOT_SWITCH_OCELOT
24 tristate "Ocelot switch driver on Ocelot"
25 depends on MSCC_OCELOT_SWITCH
26 help
27 This driver supports the Ocelot network switch device as present on
28 the Ocelot SoCs.
29
30endif # NET_VENDOR_MICROSEMI
diff --git a/drivers/net/ethernet/mscc/Makefile b/drivers/net/ethernet/mscc/Makefile
new file mode 100644
index 000000000000..cb52a3b128ae
--- /dev/null
+++ b/drivers/net/ethernet/mscc/Makefile
@@ -0,0 +1,5 @@
1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2obj-$(CONFIG_MSCC_OCELOT_SWITCH) += mscc_ocelot_common.o
3mscc_ocelot_common-y := ocelot.o ocelot_io.o
4mscc_ocelot_common-y += ocelot_regs.o
5obj-$(CONFIG_MSCC_OCELOT_SWITCH_OCELOT) += ocelot_board.o
diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c
new file mode 100644
index 000000000000..c8c74aa548d9
--- /dev/null
+++ b/drivers/net/ethernet/mscc/ocelot.c
@@ -0,0 +1,1333 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <linux/etherdevice.h>
8#include <linux/ethtool.h>
9#include <linux/if_bridge.h>
10#include <linux/if_ether.h>
11#include <linux/if_vlan.h>
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/netdevice.h>
16#include <linux/phy.h>
17#include <linux/skbuff.h>
18#include <net/arp.h>
19#include <net/netevent.h>
20#include <net/rtnetlink.h>
21#include <net/switchdev.h>
22
23#include "ocelot.h"
24
25/* MAC table entry types.
26 * ENTRYTYPE_NORMAL is subject to aging.
27 * ENTRYTYPE_LOCKED is not subject to aging.
28 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
29 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
30 */
31enum macaccess_entry_type {
32 ENTRYTYPE_NORMAL = 0,
33 ENTRYTYPE_LOCKED,
34 ENTRYTYPE_MACv4,
35 ENTRYTYPE_MACv6,
36};
37
38struct ocelot_mact_entry {
39 u8 mac[ETH_ALEN];
40 u16 vid;
41 enum macaccess_entry_type type;
42};
43
44static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
45{
46 unsigned int val, timeout = 10;
47
48 /* Wait for the issued mac table command to be completed, or timeout.
49 * When the command read from ANA_TABLES_MACACCESS is
50 * MACACCESS_CMD_IDLE, the issued command completed successfully.
51 */
52 do {
53 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
54 val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M;
55 } while (val != MACACCESS_CMD_IDLE && timeout--);
56
57 if (!timeout)
58 return -ETIMEDOUT;
59
60 return 0;
61}
62
63static void ocelot_mact_select(struct ocelot *ocelot,
64 const unsigned char mac[ETH_ALEN],
65 unsigned int vid)
66{
67 u32 macl = 0, mach = 0;
68
69 /* Set the MAC address to handle and the vlan associated in a format
70 * understood by the hardware.
71 */
72 mach |= vid << 16;
73 mach |= mac[0] << 8;
74 mach |= mac[1] << 0;
75 macl |= mac[2] << 24;
76 macl |= mac[3] << 16;
77 macl |= mac[4] << 8;
78 macl |= mac[5] << 0;
79
80 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
81 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
82
83}
84
85static int ocelot_mact_learn(struct ocelot *ocelot, int port,
86 const unsigned char mac[ETH_ALEN],
87 unsigned int vid,
88 enum macaccess_entry_type type)
89{
90 ocelot_mact_select(ocelot, mac, vid);
91
92 /* Issue a write command */
93 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
94 ANA_TABLES_MACACCESS_DEST_IDX(port) |
95 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
96 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
97 ANA_TABLES_MACACCESS);
98
99 return ocelot_mact_wait_for_completion(ocelot);
100}
101
102static int ocelot_mact_forget(struct ocelot *ocelot,
103 const unsigned char mac[ETH_ALEN],
104 unsigned int vid)
105{
106 ocelot_mact_select(ocelot, mac, vid);
107
108 /* Issue a forget command */
109 ocelot_write(ocelot,
110 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
111 ANA_TABLES_MACACCESS);
112
113 return ocelot_mact_wait_for_completion(ocelot);
114}
115
116static void ocelot_mact_init(struct ocelot *ocelot)
117{
118 /* Configure the learning mode entries attributes:
119 * - Do not copy the frame to the CPU extraction queues.
120 * - Use the vlan and mac_cpoy for dmac lookup.
121 */
122 ocelot_rmw(ocelot, 0,
123 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
124 | ANA_AGENCTRL_LEARN_FWD_KILL
125 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
126 ANA_AGENCTRL);
127
128 /* Clear the MAC table */
129 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
130}
131
132static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
133{
134 unsigned int val, timeout = 10;
135
136 /* Wait for the issued mac table command to be completed, or timeout.
137 * When the command read from ANA_TABLES_MACACCESS is
138 * MACACCESS_CMD_IDLE, the issued command completed successfully.
139 */
140 do {
141 val = ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
142 val &= ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M;
143 } while (val != ANA_TABLES_VLANACCESS_CMD_IDLE && timeout--);
144
145 if (!timeout)
146 return -ETIMEDOUT;
147
148 return 0;
149}
150
151static void ocelot_vlan_init(struct ocelot *ocelot)
152{
153 /* Clear VLAN table, by default all ports are members of all VLANs */
154 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
155 ANA_TABLES_VLANACCESS);
156 ocelot_vlant_wait_for_completion(ocelot);
157}
158
159/* Watermark encode
160 * Bit 8: Unit; 0:1, 1:16
161 * Bit 7-0: Value to be multiplied with unit
162 */
163static u16 ocelot_wm_enc(u16 value)
164{
165 if (value >= BIT(8))
166 return BIT(8) | (value / 16);
167
168 return value;
169}
170
171static void ocelot_port_adjust_link(struct net_device *dev)
172{
173 struct ocelot_port *port = netdev_priv(dev);
174 struct ocelot *ocelot = port->ocelot;
175 u8 p = port->chip_port;
176 int speed, atop_wm, mode = 0;
177
178 switch (dev->phydev->speed) {
179 case SPEED_10:
180 speed = OCELOT_SPEED_10;
181 break;
182 case SPEED_100:
183 speed = OCELOT_SPEED_100;
184 break;
185 case SPEED_1000:
186 speed = OCELOT_SPEED_1000;
187 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
188 break;
189 case SPEED_2500:
190 speed = OCELOT_SPEED_2500;
191 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
192 break;
193 default:
194 netdev_err(dev, "Unsupported PHY speed: %d\n",
195 dev->phydev->speed);
196 return;
197 }
198
199 phy_print_status(dev->phydev);
200
201 if (!dev->phydev->link)
202 return;
203
204 /* Only full duplex supported for now */
205 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA |
206 mode, DEV_MAC_MODE_CFG);
207
208 /* Set MAC IFG Gaps
209 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
210 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
211 */
212 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG);
213
214 /* Load seed (0) and set MAC HDX late collision */
215 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
216 DEV_MAC_HDX_CFG_SEED_LOAD,
217 DEV_MAC_HDX_CFG);
218 mdelay(1);
219 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
220 DEV_MAC_HDX_CFG);
221
222 /* Disable HDX fast control */
223 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC);
224
225 /* SGMII only for now */
226 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG);
227 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
228
229 /* Enable PCS */
230 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
231
232 /* No aneg on SGMII */
233 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG);
234
235 /* No loopback */
236 ocelot_port_writel(port, 0, PCS1G_LB_CFG);
237
238 /* Set Max Length and maximum tags allowed */
239 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG);
240 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
241 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
242 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
243 DEV_MAC_TAGS_CFG);
244
245 /* Enable MAC module */
246 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA |
247 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
248
249 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
250 * reset */
251 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed),
252 DEV_CLOCK_CFG);
253
254 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
255 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
256 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG);
257
258 /* No PFC */
259 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
260 ANA_PFC_PFC_CFG, p);
261
262 /* Set Pause WM hysteresis
263 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
264 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
265 */
266 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
267 SYS_PAUSE_CFG_PAUSE_STOP(101) |
268 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p);
269
270 /* Core: Enable port for frame transfer */
271 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
272 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
273 QSYS_SWITCH_PORT_MODE_PORT_ENA,
274 QSYS_SWITCH_PORT_MODE, p);
275
276 /* Flow control */
277 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
278 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
279 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
280 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
281 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
282 SYS_MAC_FC_CFG, p);
283 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p);
284
285 /* Tail dropping watermark */
286 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
287 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
288 SYS_ATOP, p);
289 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
290}
291
292static int ocelot_port_open(struct net_device *dev)
293{
294 struct ocelot_port *port = netdev_priv(dev);
295 struct ocelot *ocelot = port->ocelot;
296 int err;
297
298 /* Enable receiving frames on the port, and activate auto-learning of
299 * MAC addresses.
300 */
301 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
302 ANA_PORT_PORT_CFG_RECV_ENA |
303 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port),
304 ANA_PORT_PORT_CFG, port->chip_port);
305
306 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link,
307 PHY_INTERFACE_MODE_NA);
308 if (err) {
309 netdev_err(dev, "Could not attach to PHY\n");
310 return err;
311 }
312
313 dev->phydev = port->phy;
314
315 phy_attached_info(port->phy);
316 phy_start(port->phy);
317 return 0;
318}
319
320static int ocelot_port_stop(struct net_device *dev)
321{
322 struct ocelot_port *port = netdev_priv(dev);
323
324 phy_disconnect(port->phy);
325
326 dev->phydev = NULL;
327
328 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG);
329 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA,
330 QSYS_SWITCH_PORT_MODE, port->chip_port);
331 return 0;
332}
333
334/* Generate the IFH for frame injection
335 *
336 * The IFH is a 128bit-value
337 * bit 127: bypass the analyzer processing
338 * bit 56-67: destination mask
339 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
340 * bit 20-27: cpu extraction queue mask
341 * bit 16: tag type 0: C-tag, 1: S-tag
342 * bit 0-11: VID
343 */
344static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info)
345{
346 ifh[0] = IFH_INJ_BYPASS;
347 ifh[1] = (0xff00 & info->port) >> 8;
348 ifh[2] = (0xff & info->port) << 24;
349 ifh[3] = IFH_INJ_POP_CNT_DISABLE | (info->cpuq << 20) |
350 (info->tag_type << 16) | info->vid;
351
352 return 0;
353}
354
355static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev)
356{
357 struct ocelot_port *port = netdev_priv(dev);
358 struct ocelot *ocelot = port->ocelot;
359 u32 val, ifh[IFH_LEN];
360 struct frame_info info = {};
361 u8 grp = 0; /* Send everything on CPU group 0 */
362 unsigned int i, count, last;
363
364 val = ocelot_read(ocelot, QS_INJ_STATUS);
365 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) ||
366 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))))
367 return NETDEV_TX_BUSY;
368
369 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
370 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
371
372 info.port = BIT(port->chip_port);
373 info.cpuq = 0xff;
374 ocelot_gen_ifh(ifh, &info);
375
376 for (i = 0; i < IFH_LEN; i++)
377 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp);
378
379 count = (skb->len + 3) / 4;
380 last = skb->len % 4;
381 for (i = 0; i < count; i++) {
382 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
383 }
384
385 /* Add padding */
386 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
387 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
388 i++;
389 }
390
391 /* Indicate EOF and valid bytes in last word */
392 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
393 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
394 QS_INJ_CTRL_EOF,
395 QS_INJ_CTRL, grp);
396
397 /* Add dummy CRC */
398 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
399 skb_tx_timestamp(skb);
400
401 dev->stats.tx_packets++;
402 dev->stats.tx_bytes += skb->len;
403 dev_kfree_skb_any(skb);
404
405 return NETDEV_TX_OK;
406}
407
408static void ocelot_mact_mc_reset(struct ocelot_port *port)
409{
410 struct ocelot *ocelot = port->ocelot;
411 struct netdev_hw_addr *ha, *n;
412
413 /* Free and forget all the MAC addresses stored in the port private mc
414 * list. These are mc addresses that were previously added by calling
415 * ocelot_mact_mc_add().
416 */
417 list_for_each_entry_safe(ha, n, &port->mc, list) {
418 ocelot_mact_forget(ocelot, ha->addr, port->pvid);
419 list_del(&ha->list);
420 kfree(ha);
421 }
422}
423
424static int ocelot_mact_mc_add(struct ocelot_port *port,
425 struct netdev_hw_addr *hw_addr)
426{
427 struct ocelot *ocelot = port->ocelot;
428 struct netdev_hw_addr *ha = kzalloc(sizeof(*ha), GFP_KERNEL);
429
430 if (!ha)
431 return -ENOMEM;
432
433 memcpy(ha, hw_addr, sizeof(*ha));
434 list_add_tail(&ha->list, &port->mc);
435
436 ocelot_mact_learn(ocelot, PGID_CPU, ha->addr, port->pvid,
437 ENTRYTYPE_LOCKED);
438
439 return 0;
440}
441
442static void ocelot_set_rx_mode(struct net_device *dev)
443{
444 struct ocelot_port *port = netdev_priv(dev);
445 struct ocelot *ocelot = port->ocelot;
446 struct netdev_hw_addr *ha;
447 int i;
448 u32 val;
449
450 /* This doesn't handle promiscuous mode because the bridge core is
451 * setting IFF_PROMISC on all slave interfaces and all frames would be
452 * forwarded to the CPU port.
453 */
454 val = GENMASK(ocelot->num_phys_ports - 1, 0);
455 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++)
456 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
457
458 /* Handle the device multicast addresses. First remove all the
459 * previously installed addresses and then add the latest ones to the
460 * mac table.
461 */
462 ocelot_mact_mc_reset(port);
463 netdev_for_each_mc_addr(ha, dev)
464 ocelot_mact_mc_add(port, ha);
465}
466
467static int ocelot_port_get_phys_port_name(struct net_device *dev,
468 char *buf, size_t len)
469{
470 struct ocelot_port *port = netdev_priv(dev);
471 int ret;
472
473 ret = snprintf(buf, len, "p%d", port->chip_port);
474 if (ret >= len)
475 return -EINVAL;
476
477 return 0;
478}
479
480static int ocelot_port_set_mac_address(struct net_device *dev, void *p)
481{
482 struct ocelot_port *port = netdev_priv(dev);
483 struct ocelot *ocelot = port->ocelot;
484 const struct sockaddr *addr = p;
485
486 /* Learn the new net device MAC address in the mac table. */
487 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid,
488 ENTRYTYPE_LOCKED);
489 /* Then forget the previous one. */
490 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid);
491
492 ether_addr_copy(dev->dev_addr, addr->sa_data);
493 return 0;
494}
495
496static void ocelot_get_stats64(struct net_device *dev,
497 struct rtnl_link_stats64 *stats)
498{
499 struct ocelot_port *port = netdev_priv(dev);
500 struct ocelot *ocelot = port->ocelot;
501
502 /* Configure the port to read the stats from */
503 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port),
504 SYS_STAT_CFG);
505
506 /* Get Rx stats */
507 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS);
508 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) +
509 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) +
510 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) +
511 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) +
512 ocelot_read(ocelot, SYS_COUNT_RX_64) +
513 ocelot_read(ocelot, SYS_COUNT_RX_65_127) +
514 ocelot_read(ocelot, SYS_COUNT_RX_128_255) +
515 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) +
516 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) +
517 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX);
518 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST);
519 stats->rx_dropped = dev->stats.rx_dropped;
520
521 /* Get Tx stats */
522 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS);
523 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) +
524 ocelot_read(ocelot, SYS_COUNT_TX_65_127) +
525 ocelot_read(ocelot, SYS_COUNT_TX_128_511) +
526 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) +
527 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) +
528 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX);
529 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) +
530 ocelot_read(ocelot, SYS_COUNT_TX_AGING);
531 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION);
532}
533
534static int ocelot_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
535 struct net_device *dev, const unsigned char *addr,
536 u16 vid, u16 flags)
537{
538 struct ocelot_port *port = netdev_priv(dev);
539 struct ocelot *ocelot = port->ocelot;
540
541 return ocelot_mact_learn(ocelot, port->chip_port, addr, vid,
542 ENTRYTYPE_NORMAL);
543}
544
545static int ocelot_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
546 struct net_device *dev,
547 const unsigned char *addr, u16 vid)
548{
549 struct ocelot_port *port = netdev_priv(dev);
550 struct ocelot *ocelot = port->ocelot;
551
552 return ocelot_mact_forget(ocelot, addr, vid);
553}
554
555struct ocelot_dump_ctx {
556 struct net_device *dev;
557 struct sk_buff *skb;
558 struct netlink_callback *cb;
559 int idx;
560};
561
562static int ocelot_fdb_do_dump(struct ocelot_mact_entry *entry,
563 struct ocelot_dump_ctx *dump)
564{
565 u32 portid = NETLINK_CB(dump->cb->skb).portid;
566 u32 seq = dump->cb->nlh->nlmsg_seq;
567 struct nlmsghdr *nlh;
568 struct ndmsg *ndm;
569
570 if (dump->idx < dump->cb->args[2])
571 goto skip;
572
573 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
574 sizeof(*ndm), NLM_F_MULTI);
575 if (!nlh)
576 return -EMSGSIZE;
577
578 ndm = nlmsg_data(nlh);
579 ndm->ndm_family = AF_BRIDGE;
580 ndm->ndm_pad1 = 0;
581 ndm->ndm_pad2 = 0;
582 ndm->ndm_flags = NTF_SELF;
583 ndm->ndm_type = 0;
584 ndm->ndm_ifindex = dump->dev->ifindex;
585 ndm->ndm_state = NUD_REACHABLE;
586
587 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, entry->mac))
588 goto nla_put_failure;
589
590 if (entry->vid && nla_put_u16(dump->skb, NDA_VLAN, entry->vid))
591 goto nla_put_failure;
592
593 nlmsg_end(dump->skb, nlh);
594
595skip:
596 dump->idx++;
597 return 0;
598
599nla_put_failure:
600 nlmsg_cancel(dump->skb, nlh);
601 return -EMSGSIZE;
602}
603
604static inline int ocelot_mact_read(struct ocelot_port *port, int row, int col,
605 struct ocelot_mact_entry *entry)
606{
607 struct ocelot *ocelot = port->ocelot;
608 char mac[ETH_ALEN];
609 u32 val, dst, macl, mach;
610
611 /* Set row and column to read from */
612 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
613 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
614
615 /* Issue a read command */
616 ocelot_write(ocelot,
617 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
618 ANA_TABLES_MACACCESS);
619
620 if (ocelot_mact_wait_for_completion(ocelot))
621 return -ETIMEDOUT;
622
623 /* Read the entry flags */
624 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
625 if (!(val & ANA_TABLES_MACACCESS_VALID))
626 return -EINVAL;
627
628 /* If the entry read has another port configured as its destination,
629 * do not report it.
630 */
631 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
632 if (dst != port->chip_port)
633 return -EINVAL;
634
635 /* Get the entry's MAC address and VLAN id */
636 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
637 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
638
639 mac[0] = (mach >> 8) & 0xff;
640 mac[1] = (mach >> 0) & 0xff;
641 mac[2] = (macl >> 24) & 0xff;
642 mac[3] = (macl >> 16) & 0xff;
643 mac[4] = (macl >> 8) & 0xff;
644 mac[5] = (macl >> 0) & 0xff;
645
646 entry->vid = (mach >> 16) & 0xfff;
647 ether_addr_copy(entry->mac, mac);
648
649 return 0;
650}
651
652static int ocelot_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb,
653 struct net_device *dev,
654 struct net_device *filter_dev, int *idx)
655{
656 struct ocelot_port *port = netdev_priv(dev);
657 int i, j, ret = 0;
658 struct ocelot_dump_ctx dump = {
659 .dev = dev,
660 .skb = skb,
661 .cb = cb,
662 .idx = *idx,
663 };
664
665 struct ocelot_mact_entry entry;
666
667 /* Loop through all the mac tables entries. There are 1024 rows of 4
668 * entries.
669 */
670 for (i = 0; i < 1024; i++) {
671 for (j = 0; j < 4; j++) {
672 ret = ocelot_mact_read(port, i, j, &entry);
673 /* If the entry is invalid (wrong port, invalid...),
674 * skip it.
675 */
676 if (ret == -EINVAL)
677 continue;
678 else if (ret)
679 goto end;
680
681 ret = ocelot_fdb_do_dump(&entry, &dump);
682 if (ret)
683 goto end;
684 }
685 }
686
687end:
688 *idx = dump.idx;
689 return ret;
690}
691
692static const struct net_device_ops ocelot_port_netdev_ops = {
693 .ndo_open = ocelot_port_open,
694 .ndo_stop = ocelot_port_stop,
695 .ndo_start_xmit = ocelot_port_xmit,
696 .ndo_set_rx_mode = ocelot_set_rx_mode,
697 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name,
698 .ndo_set_mac_address = ocelot_port_set_mac_address,
699 .ndo_get_stats64 = ocelot_get_stats64,
700 .ndo_fdb_add = ocelot_fdb_add,
701 .ndo_fdb_del = ocelot_fdb_del,
702 .ndo_fdb_dump = ocelot_fdb_dump,
703};
704
705static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data)
706{
707 struct ocelot_port *port = netdev_priv(netdev);
708 struct ocelot *ocelot = port->ocelot;
709 int i;
710
711 if (sset != ETH_SS_STATS)
712 return;
713
714 for (i = 0; i < ocelot->num_stats; i++)
715 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
716 ETH_GSTRING_LEN);
717}
718
719static void ocelot_check_stats(struct work_struct *work)
720{
721 struct delayed_work *del_work = to_delayed_work(work);
722 struct ocelot *ocelot = container_of(del_work, struct ocelot, stats_work);
723 int i, j;
724
725 mutex_lock(&ocelot->stats_lock);
726
727 for (i = 0; i < ocelot->num_phys_ports; i++) {
728 /* Configure the port to read the stats from */
729 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG);
730
731 for (j = 0; j < ocelot->num_stats; j++) {
732 u32 val;
733 unsigned int idx = i * ocelot->num_stats + j;
734
735 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS,
736 ocelot->stats_layout[j].offset);
737
738 if (val < (ocelot->stats[idx] & U32_MAX))
739 ocelot->stats[idx] += (u64)1 << 32;
740
741 ocelot->stats[idx] = (ocelot->stats[idx] &
742 ~(u64)U32_MAX) + val;
743 }
744 }
745
746 cancel_delayed_work(&ocelot->stats_work);
747 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
748 OCELOT_STATS_CHECK_DELAY);
749
750 mutex_unlock(&ocelot->stats_lock);
751}
752
753static void ocelot_get_ethtool_stats(struct net_device *dev,
754 struct ethtool_stats *stats, u64 *data)
755{
756 struct ocelot_port *port = netdev_priv(dev);
757 struct ocelot *ocelot = port->ocelot;
758 int i;
759
760 /* check and update now */
761 ocelot_check_stats(&ocelot->stats_work.work);
762
763 /* Copy all counters */
764 for (i = 0; i < ocelot->num_stats; i++)
765 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i];
766}
767
768static int ocelot_get_sset_count(struct net_device *dev, int sset)
769{
770 struct ocelot_port *port = netdev_priv(dev);
771 struct ocelot *ocelot = port->ocelot;
772
773 if (sset != ETH_SS_STATS)
774 return -EOPNOTSUPP;
775 return ocelot->num_stats;
776}
777
778static const struct ethtool_ops ocelot_ethtool_ops = {
779 .get_strings = ocelot_get_strings,
780 .get_ethtool_stats = ocelot_get_ethtool_stats,
781 .get_sset_count = ocelot_get_sset_count,
782};
783
784static int ocelot_port_attr_get(struct net_device *dev,
785 struct switchdev_attr *attr)
786{
787 struct ocelot_port *ocelot_port = netdev_priv(dev);
788 struct ocelot *ocelot = ocelot_port->ocelot;
789
790 switch (attr->id) {
791 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
792 attr->u.ppid.id_len = sizeof(ocelot->base_mac);
793 memcpy(&attr->u.ppid.id, &ocelot->base_mac,
794 attr->u.ppid.id_len);
795 break;
796 default:
797 return -EOPNOTSUPP;
798 }
799
800 return 0;
801}
802
803static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port,
804 struct switchdev_trans *trans,
805 u8 state)
806{
807 struct ocelot *ocelot = ocelot_port->ocelot;
808 u32 port_cfg;
809 int port, i;
810
811 if (switchdev_trans_ph_prepare(trans))
812 return 0;
813
814 if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask))
815 return 0;
816
817 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG,
818 ocelot_port->chip_port);
819
820 switch (state) {
821 case BR_STATE_FORWARDING:
822 ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port);
823 /* Fallthrough */
824 case BR_STATE_LEARNING:
825 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
826 break;
827
828 default:
829 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
830 ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port);
831 break;
832 }
833
834 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG,
835 ocelot_port->chip_port);
836
837 /* Apply FWD mask. The loop is needed to add/remove the current port as
838 * a source for the other ports.
839 */
840 for (port = 0; port < ocelot->num_phys_ports; port++) {
841 if (ocelot->bridge_fwd_mask & BIT(port)) {
842 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port);
843
844 for (i = 0; i < ocelot->num_phys_ports; i++) {
845 unsigned long bond_mask = ocelot->lags[i];
846
847 if (!bond_mask)
848 continue;
849
850 if (bond_mask & BIT(port)) {
851 mask &= ~bond_mask;
852 break;
853 }
854 }
855
856 ocelot_write_rix(ocelot,
857 BIT(ocelot->num_phys_ports) | mask,
858 ANA_PGID_PGID, PGID_SRC + port);
859 } else {
860 /* Only the CPU port, this is compatible with link
861 * aggregation.
862 */
863 ocelot_write_rix(ocelot,
864 BIT(ocelot->num_phys_ports),
865 ANA_PGID_PGID, PGID_SRC + port);
866 }
867 }
868
869 return 0;
870}
871
872static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port,
873 unsigned long ageing_clock_t)
874{
875 struct ocelot *ocelot = ocelot_port->ocelot;
876 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t);
877 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000;
878
879 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2),
880 ANA_AUTOAGE);
881}
882
883static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc)
884{
885 struct ocelot *ocelot = port->ocelot;
886 u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG,
887 port->chip_port);
888
889 if (mc)
890 val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
891 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
892 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA;
893 else
894 val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
895 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
896 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA);
897
898 ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port);
899}
900
901static int ocelot_port_attr_set(struct net_device *dev,
902 const struct switchdev_attr *attr,
903 struct switchdev_trans *trans)
904{
905 struct ocelot_port *ocelot_port = netdev_priv(dev);
906 int err = 0;
907
908 switch (attr->id) {
909 case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
910 ocelot_port_attr_stp_state_set(ocelot_port, trans,
911 attr->u.stp_state);
912 break;
913 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
914 ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time);
915 break;
916 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED:
917 ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled);
918 break;
919 default:
920 err = -EOPNOTSUPP;
921 break;
922 }
923
924 return err;
925}
926
927static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
928 const unsigned char *addr,
929 u16 vid)
930{
931 struct ocelot_multicast *mc;
932
933 list_for_each_entry(mc, &ocelot->multicast, list) {
934 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
935 return mc;
936 }
937
938 return NULL;
939}
940
941static int ocelot_port_obj_add_mdb(struct net_device *dev,
942 const struct switchdev_obj_port_mdb *mdb,
943 struct switchdev_trans *trans)
944{
945 struct ocelot_port *port = netdev_priv(dev);
946 struct ocelot *ocelot = port->ocelot;
947 struct ocelot_multicast *mc;
948 unsigned char addr[ETH_ALEN];
949 u16 vid = mdb->vid;
950 bool new = false;
951
952 if (!vid)
953 vid = 1;
954
955 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
956 if (!mc) {
957 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
958 if (!mc)
959 return -ENOMEM;
960
961 memcpy(mc->addr, mdb->addr, ETH_ALEN);
962 mc->vid = vid;
963
964 list_add_tail(&mc->list, &ocelot->multicast);
965 new = true;
966 }
967
968 memcpy(addr, mc->addr, ETH_ALEN);
969 addr[0] = 0;
970
971 if (!new) {
972 addr[2] = mc->ports << 0;
973 addr[1] = mc->ports << 8;
974 ocelot_mact_forget(ocelot, addr, vid);
975 }
976
977 mc->ports |= BIT(port->chip_port);
978 addr[2] = mc->ports << 0;
979 addr[1] = mc->ports << 8;
980
981 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
982}
983
984static int ocelot_port_obj_del_mdb(struct net_device *dev,
985 const struct switchdev_obj_port_mdb *mdb)
986{
987 struct ocelot_port *port = netdev_priv(dev);
988 struct ocelot *ocelot = port->ocelot;
989 struct ocelot_multicast *mc;
990 unsigned char addr[ETH_ALEN];
991 u16 vid = mdb->vid;
992
993 if (!vid)
994 vid = 1;
995
996 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
997 if (!mc)
998 return -ENOENT;
999
1000 memcpy(addr, mc->addr, ETH_ALEN);
1001 addr[2] = mc->ports << 0;
1002 addr[1] = mc->ports << 8;
1003 addr[0] = 0;
1004 ocelot_mact_forget(ocelot, addr, vid);
1005
1006 mc->ports &= ~BIT(port->chip_port);
1007 if (!mc->ports) {
1008 list_del(&mc->list);
1009 devm_kfree(ocelot->dev, mc);
1010 return 0;
1011 }
1012
1013 addr[2] = mc->ports << 0;
1014 addr[1] = mc->ports << 8;
1015
1016 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1017}
1018
1019static int ocelot_port_obj_add(struct net_device *dev,
1020 const struct switchdev_obj *obj,
1021 struct switchdev_trans *trans)
1022{
1023 int ret = 0;
1024
1025 switch (obj->id) {
1026 case SWITCHDEV_OBJ_ID_PORT_MDB:
1027 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj),
1028 trans);
1029 break;
1030 default:
1031 return -EOPNOTSUPP;
1032 }
1033
1034 return ret;
1035}
1036
1037static int ocelot_port_obj_del(struct net_device *dev,
1038 const struct switchdev_obj *obj)
1039{
1040 int ret = 0;
1041
1042 switch (obj->id) {
1043 case SWITCHDEV_OBJ_ID_PORT_MDB:
1044 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj));
1045 break;
1046 default:
1047 return -EOPNOTSUPP;
1048 }
1049
1050 return ret;
1051}
1052
1053static const struct switchdev_ops ocelot_port_switchdev_ops = {
1054 .switchdev_port_attr_get = ocelot_port_attr_get,
1055 .switchdev_port_attr_set = ocelot_port_attr_set,
1056 .switchdev_port_obj_add = ocelot_port_obj_add,
1057 .switchdev_port_obj_del = ocelot_port_obj_del,
1058};
1059
1060static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port,
1061 struct net_device *bridge)
1062{
1063 struct ocelot *ocelot = ocelot_port->ocelot;
1064
1065 if (!ocelot->bridge_mask) {
1066 ocelot->hw_bridge_dev = bridge;
1067 } else {
1068 if (ocelot->hw_bridge_dev != bridge)
1069 /* This is adding the port to a second bridge, this is
1070 * unsupported */
1071 return -ENODEV;
1072 }
1073
1074 ocelot->bridge_mask |= BIT(ocelot_port->chip_port);
1075
1076 return 0;
1077}
1078
1079static void ocelot_port_bridge_leave(struct ocelot_port *ocelot_port,
1080 struct net_device *bridge)
1081{
1082 struct ocelot *ocelot = ocelot_port->ocelot;
1083
1084 ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port);
1085
1086 if (!ocelot->bridge_mask)
1087 ocelot->hw_bridge_dev = NULL;
1088}
1089
1090/* Checks if the net_device instance given to us originate from our driver. */
1091static bool ocelot_netdevice_dev_check(const struct net_device *dev)
1092{
1093 return dev->netdev_ops == &ocelot_port_netdev_ops;
1094}
1095
1096static int ocelot_netdevice_port_event(struct net_device *dev,
1097 unsigned long event,
1098 struct netdev_notifier_changeupper_info *info)
1099{
1100 struct ocelot_port *ocelot_port = netdev_priv(dev);
1101 int err = 0;
1102
1103 if (!ocelot_netdevice_dev_check(dev))
1104 return 0;
1105
1106 switch (event) {
1107 case NETDEV_CHANGEUPPER:
1108 if (netif_is_bridge_master(info->upper_dev)) {
1109 if (info->linking)
1110 err = ocelot_port_bridge_join(ocelot_port,
1111 info->upper_dev);
1112 else
1113 ocelot_port_bridge_leave(ocelot_port,
1114 info->upper_dev);
1115 }
1116 break;
1117 default:
1118 break;
1119 }
1120
1121 return err;
1122}
1123
1124static int ocelot_netdevice_event(struct notifier_block *unused,
1125 unsigned long event, void *ptr)
1126{
1127 struct netdev_notifier_changeupper_info *info = ptr;
1128 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
1129 int ret;
1130
1131 if (netif_is_lag_master(dev)) {
1132 struct net_device *slave;
1133 struct list_head *iter;
1134
1135 netdev_for_each_lower_dev(dev, slave, iter) {
1136 ret = ocelot_netdevice_port_event(slave, event, info);
1137 if (ret)
1138 goto notify;
1139 }
1140 } else {
1141 ret = ocelot_netdevice_port_event(dev, event, info);
1142 }
1143
1144notify:
1145 return notifier_from_errno(ret);
1146}
1147
1148struct notifier_block ocelot_netdevice_nb __read_mostly = {
1149 .notifier_call = ocelot_netdevice_event,
1150};
1151EXPORT_SYMBOL(ocelot_netdevice_nb);
1152
1153int ocelot_probe_port(struct ocelot *ocelot, u8 port,
1154 void __iomem *regs,
1155 struct phy_device *phy)
1156{
1157 struct ocelot_port *ocelot_port;
1158 struct net_device *dev;
1159 int err;
1160
1161 dev = alloc_etherdev(sizeof(struct ocelot_port));
1162 if (!dev)
1163 return -ENOMEM;
1164 SET_NETDEV_DEV(dev, ocelot->dev);
1165 ocelot_port = netdev_priv(dev);
1166 ocelot_port->dev = dev;
1167 ocelot_port->ocelot = ocelot;
1168 ocelot_port->regs = regs;
1169 ocelot_port->chip_port = port;
1170 ocelot_port->phy = phy;
1171 INIT_LIST_HEAD(&ocelot_port->mc);
1172 ocelot->ports[port] = ocelot_port;
1173
1174 dev->netdev_ops = &ocelot_port_netdev_ops;
1175 dev->ethtool_ops = &ocelot_ethtool_ops;
1176 dev->switchdev_ops = &ocelot_port_switchdev_ops;
1177
1178 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN);
1179 dev->dev_addr[ETH_ALEN - 1] += port;
1180 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid,
1181 ENTRYTYPE_LOCKED);
1182
1183 err = register_netdev(dev);
1184 if (err) {
1185 dev_err(ocelot->dev, "register_netdev failed\n");
1186 goto err_register_netdev;
1187 }
1188
1189 return 0;
1190
1191err_register_netdev:
1192 free_netdev(dev);
1193 return err;
1194}
1195EXPORT_SYMBOL(ocelot_probe_port);
1196
1197int ocelot_init(struct ocelot *ocelot)
1198{
1199 u32 port;
1200 int i, cpu = ocelot->num_phys_ports;
1201 char queue_name[32];
1202
1203 ocelot->stats = devm_kcalloc(ocelot->dev,
1204 ocelot->num_phys_ports * ocelot->num_stats,
1205 sizeof(u64), GFP_KERNEL);
1206 if (!ocelot->stats)
1207 return -ENOMEM;
1208
1209 mutex_init(&ocelot->stats_lock);
1210 snprintf(queue_name, sizeof(queue_name), "%s-stats",
1211 dev_name(ocelot->dev));
1212 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
1213 if (!ocelot->stats_queue)
1214 return -ENOMEM;
1215
1216 ocelot_mact_init(ocelot);
1217 ocelot_vlan_init(ocelot);
1218
1219 for (port = 0; port < ocelot->num_phys_ports; port++) {
1220 /* Clear all counters (5 groups) */
1221 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
1222 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
1223 SYS_STAT_CFG);
1224 }
1225
1226 /* Only use S-Tag */
1227 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
1228
1229 /* Aggregation mode */
1230 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
1231 ANA_AGGR_CFG_AC_DMAC_ENA |
1232 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
1233 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG);
1234
1235 /* Set MAC age time to default value. The entry is aged after
1236 * 2*AGE_PERIOD
1237 */
1238 ocelot_write(ocelot,
1239 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
1240 ANA_AUTOAGE);
1241
1242 /* Disable learning for frames discarded by VLAN ingress filtering */
1243 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
1244
1245 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
1246 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
1247 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
1248
1249 /* Setup flooding PGIDs */
1250 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
1251 ANA_FLOODING_FLD_BROADCAST(PGID_MC) |
1252 ANA_FLOODING_FLD_UNICAST(PGID_UC),
1253 ANA_FLOODING, 0);
1254 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
1255 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
1256 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
1257 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
1258 ANA_FLOODING_IPMC);
1259
1260 for (port = 0; port < ocelot->num_phys_ports; port++) {
1261 /* Transmit the frame to the local port. */
1262 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1263 /* Do not forward BPDU frames to the front ports. */
1264 ocelot_write_gix(ocelot,
1265 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
1266 ANA_PORT_CPU_FWD_BPDU_CFG,
1267 port);
1268 /* Ensure bridging is disabled */
1269 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
1270 }
1271
1272 /* Configure and enable the CPU port. */
1273 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
1274 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
1275 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
1276 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
1277 ANA_PORT_PORT_CFG, cpu);
1278
1279 /* Allow broadcast MAC frames. */
1280 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) {
1281 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
1282
1283 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
1284 }
1285 ocelot_write_rix(ocelot,
1286 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
1287 ANA_PGID_PGID, PGID_MC);
1288 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
1289 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
1290
1291 /* CPU port Injection/Extraction configuration */
1292 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
1293 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
1294 QSYS_SWITCH_PORT_MODE_PORT_ENA,
1295 QSYS_SWITCH_PORT_MODE, cpu);
1296 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) |
1297 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu);
1298 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
1299 * registers endianness.
1300 */
1301 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
1302 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
1303 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
1304 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
1305 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
1306 ANA_CPUQ_CFG_CPUQ_LRN(2) |
1307 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
1308 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
1309 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
1310 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
1311 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
1312 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
1313 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
1314 for (i = 0; i < 16; i++)
1315 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
1316 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
1317 ANA_CPUQ_8021_CFG, i);
1318
1319 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats);
1320 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1321 OCELOT_STATS_CHECK_DELAY);
1322 return 0;
1323}
1324EXPORT_SYMBOL(ocelot_init);
1325
1326void ocelot_deinit(struct ocelot *ocelot)
1327{
1328 destroy_workqueue(ocelot->stats_queue);
1329 mutex_destroy(&ocelot->stats_lock);
1330}
1331EXPORT_SYMBOL(ocelot_deinit);
1332
1333MODULE_LICENSE("Dual MIT/GPL");
diff --git a/drivers/net/ethernet/mscc/ocelot.h b/drivers/net/ethernet/mscc/ocelot.h
new file mode 100644
index 000000000000..097bd12a10d4
--- /dev/null
+++ b/drivers/net/ethernet/mscc/ocelot.h
@@ -0,0 +1,572 @@
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_H_
9#define _MSCC_OCELOT_H_
10
11#include <linux/bitops.h>
12#include <linux/etherdevice.h>
13#include <linux/if_vlan.h>
14#include <linux/platform_device.h>
15#include <linux/regmap.h>
16
17#include "ocelot_ana.h"
18#include "ocelot_dev.h"
19#include "ocelot_hsio.h"
20#include "ocelot_qsys.h"
21#include "ocelot_rew.h"
22#include "ocelot_sys.h"
23#include "ocelot_qs.h"
24
25#define PGID_AGGR 64
26#define PGID_SRC 80
27
28/* Reserved PGIDs */
29#define PGID_CPU (PGID_AGGR - 5)
30#define PGID_UC (PGID_AGGR - 4)
31#define PGID_MC (PGID_AGGR - 3)
32#define PGID_MCIPV4 (PGID_AGGR - 2)
33#define PGID_MCIPV6 (PGID_AGGR - 1)
34
35#define OCELOT_BUFFER_CELL_SZ 60
36
37#define OCELOT_STATS_CHECK_DELAY (2 * HZ)
38
39#define IFH_LEN 4
40
41struct frame_info {
42 u32 len;
43 u16 port;
44 u16 vid;
45 u8 cpuq;
46 u8 tag_type;
47};
48
49#define IFH_INJ_BYPASS BIT(31)
50#define IFH_INJ_POP_CNT_DISABLE (3 << 28)
51
52#define IFH_TAG_TYPE_C 0
53#define IFH_TAG_TYPE_S 1
54
55#define OCELOT_SPEED_2500 0
56#define OCELOT_SPEED_1000 1
57#define OCELOT_SPEED_100 2
58#define OCELOT_SPEED_10 3
59
60#define TARGET_OFFSET 24
61#define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
62#define REG(reg, offset) [reg & REG_MASK] = offset
63
64enum ocelot_target {
65 ANA = 1,
66 QS,
67 QSYS,
68 REW,
69 SYS,
70 HSIO,
71 TARGET_MAX,
72};
73
74enum ocelot_reg {
75 ANA_ADVLEARN = ANA << TARGET_OFFSET,
76 ANA_VLANMASK,
77 ANA_PORT_B_DOMAIN,
78 ANA_ANAGEFIL,
79 ANA_ANEVENTS,
80 ANA_STORMLIMIT_BURST,
81 ANA_STORMLIMIT_CFG,
82 ANA_ISOLATED_PORTS,
83 ANA_COMMUNITY_PORTS,
84 ANA_AUTOAGE,
85 ANA_MACTOPTIONS,
86 ANA_LEARNDISC,
87 ANA_AGENCTRL,
88 ANA_MIRRORPORTS,
89 ANA_EMIRRORPORTS,
90 ANA_FLOODING,
91 ANA_FLOODING_IPMC,
92 ANA_SFLOW_CFG,
93 ANA_PORT_MODE,
94 ANA_CUT_THRU_CFG,
95 ANA_PGID_PGID,
96 ANA_TABLES_ANMOVED,
97 ANA_TABLES_MACHDATA,
98 ANA_TABLES_MACLDATA,
99 ANA_TABLES_STREAMDATA,
100 ANA_TABLES_MACACCESS,
101 ANA_TABLES_MACTINDX,
102 ANA_TABLES_VLANACCESS,
103 ANA_TABLES_VLANTIDX,
104 ANA_TABLES_ISDXACCESS,
105 ANA_TABLES_ISDXTIDX,
106 ANA_TABLES_ENTRYLIM,
107 ANA_TABLES_PTP_ID_HIGH,
108 ANA_TABLES_PTP_ID_LOW,
109 ANA_TABLES_STREAMACCESS,
110 ANA_TABLES_STREAMTIDX,
111 ANA_TABLES_SEQ_HISTORY,
112 ANA_TABLES_SEQ_MASK,
113 ANA_TABLES_SFID_MASK,
114 ANA_TABLES_SFIDACCESS,
115 ANA_TABLES_SFIDTIDX,
116 ANA_MSTI_STATE,
117 ANA_OAM_UPM_LM_CNT,
118 ANA_SG_ACCESS_CTRL,
119 ANA_SG_CONFIG_REG_1,
120 ANA_SG_CONFIG_REG_2,
121 ANA_SG_CONFIG_REG_3,
122 ANA_SG_CONFIG_REG_4,
123 ANA_SG_CONFIG_REG_5,
124 ANA_SG_GCL_GS_CONFIG,
125 ANA_SG_GCL_TI_CONFIG,
126 ANA_SG_STATUS_REG_1,
127 ANA_SG_STATUS_REG_2,
128 ANA_SG_STATUS_REG_3,
129 ANA_PORT_VLAN_CFG,
130 ANA_PORT_DROP_CFG,
131 ANA_PORT_QOS_CFG,
132 ANA_PORT_VCAP_CFG,
133 ANA_PORT_VCAP_S1_KEY_CFG,
134 ANA_PORT_VCAP_S2_CFG,
135 ANA_PORT_PCP_DEI_MAP,
136 ANA_PORT_CPU_FWD_CFG,
137 ANA_PORT_CPU_FWD_BPDU_CFG,
138 ANA_PORT_CPU_FWD_GARP_CFG,
139 ANA_PORT_CPU_FWD_CCM_CFG,
140 ANA_PORT_PORT_CFG,
141 ANA_PORT_POL_CFG,
142 ANA_PORT_PTP_CFG,
143 ANA_PORT_PTP_DLY1_CFG,
144 ANA_PORT_PTP_DLY2_CFG,
145 ANA_PORT_SFID_CFG,
146 ANA_PFC_PFC_CFG,
147 ANA_PFC_PFC_TIMER,
148 ANA_IPT_OAM_MEP_CFG,
149 ANA_IPT_IPT,
150 ANA_PPT_PPT,
151 ANA_FID_MAP_FID_MAP,
152 ANA_AGGR_CFG,
153 ANA_CPUQ_CFG,
154 ANA_CPUQ_CFG2,
155 ANA_CPUQ_8021_CFG,
156 ANA_DSCP_CFG,
157 ANA_DSCP_REWR_CFG,
158 ANA_VCAP_RNG_TYPE_CFG,
159 ANA_VCAP_RNG_VAL_CFG,
160 ANA_VRAP_CFG,
161 ANA_VRAP_HDR_DATA,
162 ANA_VRAP_HDR_MASK,
163 ANA_DISCARD_CFG,
164 ANA_FID_CFG,
165 ANA_POL_PIR_CFG,
166 ANA_POL_CIR_CFG,
167 ANA_POL_MODE_CFG,
168 ANA_POL_PIR_STATE,
169 ANA_POL_CIR_STATE,
170 ANA_POL_STATE,
171 ANA_POL_FLOWC,
172 ANA_POL_HYST,
173 ANA_POL_MISC_CFG,
174 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
175 QS_XTR_RD,
176 QS_XTR_FRM_PRUNING,
177 QS_XTR_FLUSH,
178 QS_XTR_DATA_PRESENT,
179 QS_XTR_CFG,
180 QS_INJ_GRP_CFG,
181 QS_INJ_WR,
182 QS_INJ_CTRL,
183 QS_INJ_STATUS,
184 QS_INJ_ERR,
185 QS_INH_DBG,
186 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
187 QSYS_SWITCH_PORT_MODE,
188 QSYS_STAT_CNT_CFG,
189 QSYS_EEE_CFG,
190 QSYS_EEE_THRES,
191 QSYS_IGR_NO_SHARING,
192 QSYS_EGR_NO_SHARING,
193 QSYS_SW_STATUS,
194 QSYS_EXT_CPU_CFG,
195 QSYS_PAD_CFG,
196 QSYS_CPU_GROUP_MAP,
197 QSYS_QMAP,
198 QSYS_ISDX_SGRP,
199 QSYS_TIMED_FRAME_ENTRY,
200 QSYS_TFRM_MISC,
201 QSYS_TFRM_PORT_DLY,
202 QSYS_TFRM_TIMER_CFG_1,
203 QSYS_TFRM_TIMER_CFG_2,
204 QSYS_TFRM_TIMER_CFG_3,
205 QSYS_TFRM_TIMER_CFG_4,
206 QSYS_TFRM_TIMER_CFG_5,
207 QSYS_TFRM_TIMER_CFG_6,
208 QSYS_TFRM_TIMER_CFG_7,
209 QSYS_TFRM_TIMER_CFG_8,
210 QSYS_RED_PROFILE,
211 QSYS_RES_QOS_MODE,
212 QSYS_RES_CFG,
213 QSYS_RES_STAT,
214 QSYS_EGR_DROP_MODE,
215 QSYS_EQ_CTRL,
216 QSYS_EVENTS_CORE,
217 QSYS_QMAXSDU_CFG_0,
218 QSYS_QMAXSDU_CFG_1,
219 QSYS_QMAXSDU_CFG_2,
220 QSYS_QMAXSDU_CFG_3,
221 QSYS_QMAXSDU_CFG_4,
222 QSYS_QMAXSDU_CFG_5,
223 QSYS_QMAXSDU_CFG_6,
224 QSYS_QMAXSDU_CFG_7,
225 QSYS_PREEMPTION_CFG,
226 QSYS_CIR_CFG,
227 QSYS_EIR_CFG,
228 QSYS_SE_CFG,
229 QSYS_SE_DWRR_CFG,
230 QSYS_SE_CONNECT,
231 QSYS_SE_DLB_SENSE,
232 QSYS_CIR_STATE,
233 QSYS_EIR_STATE,
234 QSYS_SE_STATE,
235 QSYS_HSCH_MISC_CFG,
236 QSYS_TAG_CONFIG,
237 QSYS_TAS_PARAM_CFG_CTRL,
238 QSYS_PORT_MAX_SDU,
239 QSYS_PARAM_CFG_REG_1,
240 QSYS_PARAM_CFG_REG_2,
241 QSYS_PARAM_CFG_REG_3,
242 QSYS_PARAM_CFG_REG_4,
243 QSYS_PARAM_CFG_REG_5,
244 QSYS_GCL_CFG_REG_1,
245 QSYS_GCL_CFG_REG_2,
246 QSYS_PARAM_STATUS_REG_1,
247 QSYS_PARAM_STATUS_REG_2,
248 QSYS_PARAM_STATUS_REG_3,
249 QSYS_PARAM_STATUS_REG_4,
250 QSYS_PARAM_STATUS_REG_5,
251 QSYS_PARAM_STATUS_REG_6,
252 QSYS_PARAM_STATUS_REG_7,
253 QSYS_PARAM_STATUS_REG_8,
254 QSYS_PARAM_STATUS_REG_9,
255 QSYS_GCL_STATUS_REG_1,
256 QSYS_GCL_STATUS_REG_2,
257 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
258 REW_TAG_CFG,
259 REW_PORT_CFG,
260 REW_DSCP_CFG,
261 REW_PCP_DEI_QOS_MAP_CFG,
262 REW_PTP_CFG,
263 REW_PTP_DLY1_CFG,
264 REW_RED_TAG_CFG,
265 REW_DSCP_REMAP_DP1_CFG,
266 REW_DSCP_REMAP_CFG,
267 REW_STAT_CFG,
268 REW_REW_STICKY,
269 REW_PPT,
270 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
271 SYS_COUNT_RX_UNICAST,
272 SYS_COUNT_RX_MULTICAST,
273 SYS_COUNT_RX_BROADCAST,
274 SYS_COUNT_RX_SHORTS,
275 SYS_COUNT_RX_FRAGMENTS,
276 SYS_COUNT_RX_JABBERS,
277 SYS_COUNT_RX_CRC_ALIGN_ERRS,
278 SYS_COUNT_RX_SYM_ERRS,
279 SYS_COUNT_RX_64,
280 SYS_COUNT_RX_65_127,
281 SYS_COUNT_RX_128_255,
282 SYS_COUNT_RX_256_1023,
283 SYS_COUNT_RX_1024_1526,
284 SYS_COUNT_RX_1527_MAX,
285 SYS_COUNT_RX_PAUSE,
286 SYS_COUNT_RX_CONTROL,
287 SYS_COUNT_RX_LONGS,
288 SYS_COUNT_RX_CLASSIFIED_DROPS,
289 SYS_COUNT_TX_OCTETS,
290 SYS_COUNT_TX_UNICAST,
291 SYS_COUNT_TX_MULTICAST,
292 SYS_COUNT_TX_BROADCAST,
293 SYS_COUNT_TX_COLLISION,
294 SYS_COUNT_TX_DROPS,
295 SYS_COUNT_TX_PAUSE,
296 SYS_COUNT_TX_64,
297 SYS_COUNT_TX_65_127,
298 SYS_COUNT_TX_128_511,
299 SYS_COUNT_TX_512_1023,
300 SYS_COUNT_TX_1024_1526,
301 SYS_COUNT_TX_1527_MAX,
302 SYS_COUNT_TX_AGING,
303 SYS_RESET_CFG,
304 SYS_SR_ETYPE_CFG,
305 SYS_VLAN_ETYPE_CFG,
306 SYS_PORT_MODE,
307 SYS_FRONT_PORT_MODE,
308 SYS_FRM_AGING,
309 SYS_STAT_CFG,
310 SYS_SW_STATUS,
311 SYS_MISC_CFG,
312 SYS_REW_MAC_HIGH_CFG,
313 SYS_REW_MAC_LOW_CFG,
314 SYS_TIMESTAMP_OFFSET,
315 SYS_CMID,
316 SYS_PAUSE_CFG,
317 SYS_PAUSE_TOT_CFG,
318 SYS_ATOP,
319 SYS_ATOP_TOT_CFG,
320 SYS_MAC_FC_CFG,
321 SYS_MMGT,
322 SYS_MMGT_FAST,
323 SYS_EVENTS_DIF,
324 SYS_EVENTS_CORE,
325 SYS_CNT,
326 SYS_PTP_STATUS,
327 SYS_PTP_TXSTAMP,
328 SYS_PTP_NXT,
329 SYS_PTP_CFG,
330 SYS_RAM_INIT,
331 SYS_CM_ADDR,
332 SYS_CM_DATA_WR,
333 SYS_CM_DATA_RD,
334 SYS_CM_OP,
335 SYS_CM_DATA,
336 HSIO_PLL5G_CFG0 = HSIO << TARGET_OFFSET,
337 HSIO_PLL5G_CFG1,
338 HSIO_PLL5G_CFG2,
339 HSIO_PLL5G_CFG3,
340 HSIO_PLL5G_CFG4,
341 HSIO_PLL5G_CFG5,
342 HSIO_PLL5G_CFG6,
343 HSIO_PLL5G_STATUS0,
344 HSIO_PLL5G_STATUS1,
345 HSIO_PLL5G_BIST_CFG0,
346 HSIO_PLL5G_BIST_CFG1,
347 HSIO_PLL5G_BIST_CFG2,
348 HSIO_PLL5G_BIST_STAT0,
349 HSIO_PLL5G_BIST_STAT1,
350 HSIO_RCOMP_CFG0,
351 HSIO_RCOMP_STATUS,
352 HSIO_SYNC_ETH_CFG,
353 HSIO_SYNC_ETH_PLL_CFG,
354 HSIO_S1G_DES_CFG,
355 HSIO_S1G_IB_CFG,
356 HSIO_S1G_OB_CFG,
357 HSIO_S1G_SER_CFG,
358 HSIO_S1G_COMMON_CFG,
359 HSIO_S1G_PLL_CFG,
360 HSIO_S1G_PLL_STATUS,
361 HSIO_S1G_DFT_CFG0,
362 HSIO_S1G_DFT_CFG1,
363 HSIO_S1G_DFT_CFG2,
364 HSIO_S1G_TP_CFG,
365 HSIO_S1G_RC_PLL_BIST_CFG,
366 HSIO_S1G_MISC_CFG,
367 HSIO_S1G_DFT_STATUS,
368 HSIO_S1G_MISC_STATUS,
369 HSIO_MCB_S1G_ADDR_CFG,
370 HSIO_S6G_DIG_CFG,
371 HSIO_S6G_DFT_CFG0,
372 HSIO_S6G_DFT_CFG1,
373 HSIO_S6G_DFT_CFG2,
374 HSIO_S6G_TP_CFG0,
375 HSIO_S6G_TP_CFG1,
376 HSIO_S6G_RC_PLL_BIST_CFG,
377 HSIO_S6G_MISC_CFG,
378 HSIO_S6G_OB_ANEG_CFG,
379 HSIO_S6G_DFT_STATUS,
380 HSIO_S6G_ERR_CNT,
381 HSIO_S6G_MISC_STATUS,
382 HSIO_S6G_DES_CFG,
383 HSIO_S6G_IB_CFG,
384 HSIO_S6G_IB_CFG1,
385 HSIO_S6G_IB_CFG2,
386 HSIO_S6G_IB_CFG3,
387 HSIO_S6G_IB_CFG4,
388 HSIO_S6G_IB_CFG5,
389 HSIO_S6G_OB_CFG,
390 HSIO_S6G_OB_CFG1,
391 HSIO_S6G_SER_CFG,
392 HSIO_S6G_COMMON_CFG,
393 HSIO_S6G_PLL_CFG,
394 HSIO_S6G_ACJTAG_CFG,
395 HSIO_S6G_GP_CFG,
396 HSIO_S6G_IB_STATUS0,
397 HSIO_S6G_IB_STATUS1,
398 HSIO_S6G_ACJTAG_STATUS,
399 HSIO_S6G_PLL_STATUS,
400 HSIO_S6G_REVID,
401 HSIO_MCB_S6G_ADDR_CFG,
402 HSIO_HW_CFG,
403 HSIO_HW_QSGMII_CFG,
404 HSIO_HW_QSGMII_STAT,
405 HSIO_CLK_CFG,
406 HSIO_TEMP_SENSOR_CTRL,
407 HSIO_TEMP_SENSOR_CFG,
408 HSIO_TEMP_SENSOR_STAT,
409};
410
411enum ocelot_regfield {
412 ANA_ADVLEARN_VLAN_CHK,
413 ANA_ADVLEARN_LEARN_MIRROR,
414 ANA_ANEVENTS_FLOOD_DISCARD,
415 ANA_ANEVENTS_MSTI_DROP,
416 ANA_ANEVENTS_ACLKILL,
417 ANA_ANEVENTS_ACLUSED,
418 ANA_ANEVENTS_AUTOAGE,
419 ANA_ANEVENTS_VS2TTL1,
420 ANA_ANEVENTS_STORM_DROP,
421 ANA_ANEVENTS_LEARN_DROP,
422 ANA_ANEVENTS_AGED_ENTRY,
423 ANA_ANEVENTS_CPU_LEARN_FAILED,
424 ANA_ANEVENTS_AUTO_LEARN_FAILED,
425 ANA_ANEVENTS_LEARN_REMOVE,
426 ANA_ANEVENTS_AUTO_LEARNED,
427 ANA_ANEVENTS_AUTO_MOVED,
428 ANA_ANEVENTS_DROPPED,
429 ANA_ANEVENTS_CLASSIFIED_DROP,
430 ANA_ANEVENTS_CLASSIFIED_COPY,
431 ANA_ANEVENTS_VLAN_DISCARD,
432 ANA_ANEVENTS_FWD_DISCARD,
433 ANA_ANEVENTS_MULTICAST_FLOOD,
434 ANA_ANEVENTS_UNICAST_FLOOD,
435 ANA_ANEVENTS_DEST_KNOWN,
436 ANA_ANEVENTS_BUCKET3_MATCH,
437 ANA_ANEVENTS_BUCKET2_MATCH,
438 ANA_ANEVENTS_BUCKET1_MATCH,
439 ANA_ANEVENTS_BUCKET0_MATCH,
440 ANA_ANEVENTS_CPU_OPERATION,
441 ANA_ANEVENTS_DMAC_LOOKUP,
442 ANA_ANEVENTS_SMAC_LOOKUP,
443 ANA_ANEVENTS_SEQ_GEN_ERR_0,
444 ANA_ANEVENTS_SEQ_GEN_ERR_1,
445 ANA_TABLES_MACACCESS_B_DOM,
446 ANA_TABLES_MACTINDX_BUCKET,
447 ANA_TABLES_MACTINDX_M_INDEX,
448 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
449 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
450 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
451 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
452 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
453 SYS_RESET_CFG_CORE_ENA,
454 SYS_RESET_CFG_MEM_ENA,
455 SYS_RESET_CFG_MEM_INIT,
456 REGFIELD_MAX
457};
458
459struct ocelot_multicast {
460 struct list_head list;
461 unsigned char addr[ETH_ALEN];
462 u16 vid;
463 u16 ports;
464};
465
466struct ocelot_port;
467
468struct ocelot_stat_layout {
469 u32 offset;
470 char name[ETH_GSTRING_LEN];
471};
472
473struct ocelot {
474 struct device *dev;
475
476 struct regmap *targets[TARGET_MAX];
477 struct regmap_field *regfields[REGFIELD_MAX];
478 const u32 *const *map;
479 const struct ocelot_stat_layout *stats_layout;
480 unsigned int num_stats;
481
482 u8 base_mac[ETH_ALEN];
483
484 struct net_device *hw_bridge_dev;
485 u16 bridge_mask;
486 u16 bridge_fwd_mask;
487
488 struct workqueue_struct *ocelot_owq;
489
490 int shared_queue_sz;
491
492 u8 num_phys_ports;
493 u8 num_cpu_ports;
494 struct ocelot_port **ports;
495
496 u16 lags[16];
497
498 /* Keep track of the vlan port masks */
499 u32 vlan_mask[VLAN_N_VID];
500
501 struct list_head multicast;
502
503 /* Workqueue to check statistics for overflow with its lock */
504 struct mutex stats_lock;
505 u64 *stats;
506 struct delayed_work stats_work;
507 struct workqueue_struct *stats_queue;
508};
509
510struct ocelot_port {
511 struct net_device *dev;
512 struct ocelot *ocelot;
513 struct phy_device *phy;
514 void __iomem *regs;
515 u8 chip_port;
516 /* Keep a track of the mc addresses added to the mac table, so that they
517 * can be removed when needed.
518 */
519 struct list_head mc;
520
521 /* Ingress default VLAN (pvid) */
522 u16 pvid;
523
524 /* Egress default VLAN (vid) */
525 u16 vid;
526
527 u8 vlan_aware;
528
529 u64 *stats;
530};
531
532u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
533#define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
534#define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
535#define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
536#define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
537
538void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
539#define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
540#define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
541#define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
542#define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
543
544void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 mask,
545 u32 offset);
546#define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
547#define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
548#define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
549#define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
550
551u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
552void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
553
554int ocelot_regfields_init(struct ocelot *ocelot,
555 const struct reg_field *const regfields);
556struct regmap *ocelot_io_platform_init(struct ocelot *ocelot,
557 struct platform_device *pdev,
558 const char *name);
559
560#define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
561#define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
562
563int ocelot_init(struct ocelot *ocelot);
564void ocelot_deinit(struct ocelot *ocelot);
565int ocelot_chip_init(struct ocelot *ocelot);
566int ocelot_probe_port(struct ocelot *ocelot, u8 port,
567 void __iomem *regs,
568 struct phy_device *phy);
569
570extern struct notifier_block ocelot_netdevice_nb;
571
572#endif
diff --git a/drivers/net/ethernet/mscc/ocelot_ana.h b/drivers/net/ethernet/mscc/ocelot_ana.h
new file mode 100644
index 000000000000..841c6ec22b64
--- /dev/null
+++ b/drivers/net/ethernet/mscc/ocelot_ana.h
@@ -0,0 +1,625 @@
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_ANA_H_
9#define _MSCC_OCELOT_ANA_H_
10
11#define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12#define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13#define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14#define ANA_ANAGEFIL_PID_EN BIT(19)
15#define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))
16#define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
17#define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)
18#define ANA_ANAGEFIL_VID_EN BIT(13)
19#define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
20#define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
21
22#define ANA_STORMLIMIT_CFG_RSZ 0x4
23
24#define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))
25#define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
26#define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)
27#define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
28#define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0))
29#define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0)
30
31#define ANA_AUTOAGE_AGE_FAST BIT(21)
32#define ANA_AUTOAGE_AGE_PERIOD(x) (((x) << 1) & GENMASK(20, 1))
33#define ANA_AUTOAGE_AGE_PERIOD_M GENMASK(20, 1)
34#define ANA_AUTOAGE_AGE_PERIOD_X(x) (((x) & GENMASK(20, 1)) >> 1)
35#define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
36
37#define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
38#define ANA_MACTOPTIONS_SHADOW BIT(0)
39
40#define ANA_AGENCTRL_FID_MASK(x) (((x) << 12) & GENMASK(23, 12))
41#define ANA_AGENCTRL_FID_MASK_M GENMASK(23, 12)
42#define ANA_AGENCTRL_FID_MASK_X(x) (((x) & GENMASK(23, 12)) >> 12)
43#define ANA_AGENCTRL_IGNORE_DMAC_FLAGS BIT(11)
44#define ANA_AGENCTRL_IGNORE_SMAC_FLAGS BIT(10)
45#define ANA_AGENCTRL_FLOOD_SPECIAL BIT(9)
46#define ANA_AGENCTRL_FLOOD_IGNORE_VLAN BIT(8)
47#define ANA_AGENCTRL_MIRROR_CPU BIT(7)
48#define ANA_AGENCTRL_LEARN_CPU_COPY BIT(6)
49#define ANA_AGENCTRL_LEARN_FWD_KILL BIT(5)
50#define ANA_AGENCTRL_LEARN_IGNORE_VLAN BIT(4)
51#define ANA_AGENCTRL_CPU_CPU_KILL_ENA BIT(3)
52#define ANA_AGENCTRL_GREEN_COUNT_MODE BIT(2)
53#define ANA_AGENCTRL_YELLOW_COUNT_MODE BIT(1)
54#define ANA_AGENCTRL_RED_COUNT_MODE BIT(0)
55
56#define ANA_FLOODING_RSZ 0x4
57
58#define ANA_FLOODING_FLD_UNICAST(x) (((x) << 12) & GENMASK(17, 12))
59#define ANA_FLOODING_FLD_UNICAST_M GENMASK(17, 12)
60#define ANA_FLOODING_FLD_UNICAST_X(x) (((x) & GENMASK(17, 12)) >> 12)
61#define ANA_FLOODING_FLD_BROADCAST(x) (((x) << 6) & GENMASK(11, 6))
62#define ANA_FLOODING_FLD_BROADCAST_M GENMASK(11, 6)
63#define ANA_FLOODING_FLD_BROADCAST_X(x) (((x) & GENMASK(11, 6)) >> 6)
64#define ANA_FLOODING_FLD_MULTICAST(x) ((x) & GENMASK(5, 0))
65#define ANA_FLOODING_FLD_MULTICAST_M GENMASK(5, 0)
66
67#define ANA_FLOODING_IPMC_FLD_MC4_CTRL(x) (((x) << 18) & GENMASK(23, 18))
68#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_M GENMASK(23, 18)
69#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_X(x) (((x) & GENMASK(23, 18)) >> 18)
70#define ANA_FLOODING_IPMC_FLD_MC4_DATA(x) (((x) << 12) & GENMASK(17, 12))
71#define ANA_FLOODING_IPMC_FLD_MC4_DATA_M GENMASK(17, 12)
72#define ANA_FLOODING_IPMC_FLD_MC4_DATA_X(x) (((x) & GENMASK(17, 12)) >> 12)
73#define ANA_FLOODING_IPMC_FLD_MC6_CTRL(x) (((x) << 6) & GENMASK(11, 6))
74#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M GENMASK(11, 6)
75#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_X(x) (((x) & GENMASK(11, 6)) >> 6)
76#define ANA_FLOODING_IPMC_FLD_MC6_DATA(x) ((x) & GENMASK(5, 0))
77#define ANA_FLOODING_IPMC_FLD_MC6_DATA_M GENMASK(5, 0)
78
79#define ANA_SFLOW_CFG_RSZ 0x4
80
81#define ANA_SFLOW_CFG_SF_RATE(x) (((x) << 2) & GENMASK(13, 2))
82#define ANA_SFLOW_CFG_SF_RATE_M GENMASK(13, 2)
83#define ANA_SFLOW_CFG_SF_RATE_X(x) (((x) & GENMASK(13, 2)) >> 2)
84#define ANA_SFLOW_CFG_SF_SAMPLE_RX BIT(1)
85#define ANA_SFLOW_CFG_SF_SAMPLE_TX BIT(0)
86
87#define ANA_PORT_MODE_RSZ 0x4
88
89#define ANA_PORT_MODE_REDTAG_PARSE_CFG BIT(3)
90#define ANA_PORT_MODE_VLAN_PARSE_CFG(x) (((x) << 1) & GENMASK(2, 1))
91#define ANA_PORT_MODE_VLAN_PARSE_CFG_M GENMASK(2, 1)
92#define ANA_PORT_MODE_VLAN_PARSE_CFG_X(x) (((x) & GENMASK(2, 1)) >> 1)
93#define ANA_PORT_MODE_L3_PARSE_CFG BIT(0)
94
95#define ANA_CUT_THRU_CFG_RSZ 0x4
96
97#define ANA_PGID_PGID_RSZ 0x4
98
99#define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0))
100#define ANA_PGID_PGID_PGID_M GENMASK(11, 0)
101#define ANA_PGID_PGID_CPUQ_DST_PGID(x) (((x) << 27) & GENMASK(29, 27))
102#define ANA_PGID_PGID_CPUQ_DST_PGID_M GENMASK(29, 27)
103#define ANA_PGID_PGID_CPUQ_DST_PGID_X(x) (((x) & GENMASK(29, 27)) >> 27)
104
105#define ANA_TABLES_MACHDATA_VID(x) (((x) << 16) & GENMASK(28, 16))
106#define ANA_TABLES_MACHDATA_VID_M GENMASK(28, 16)
107#define ANA_TABLES_MACHDATA_VID_X(x) (((x) & GENMASK(28, 16)) >> 16)
108#define ANA_TABLES_MACHDATA_MACHDATA(x) ((x) & GENMASK(15, 0))
109#define ANA_TABLES_MACHDATA_MACHDATA_M GENMASK(15, 0)
110
111#define ANA_TABLES_STREAMDATA_SSID_VALID BIT(16)
112#define ANA_TABLES_STREAMDATA_SSID(x) (((x) << 9) & GENMASK(15, 9))
113#define ANA_TABLES_STREAMDATA_SSID_M GENMASK(15, 9)
114#define ANA_TABLES_STREAMDATA_SSID_X(x) (((x) & GENMASK(15, 9)) >> 9)
115#define ANA_TABLES_STREAMDATA_SFID_VALID BIT(8)
116#define ANA_TABLES_STREAMDATA_SFID(x) ((x) & GENMASK(7, 0))
117#define ANA_TABLES_STREAMDATA_SFID_M GENMASK(7, 0)
118
119#define ANA_TABLES_MACACCESS_MAC_CPU_COPY BIT(15)
120#define ANA_TABLES_MACACCESS_SRC_KILL BIT(14)
121#define ANA_TABLES_MACACCESS_IGNORE_VLAN BIT(13)
122#define ANA_TABLES_MACACCESS_AGED_FLAG BIT(12)
123#define ANA_TABLES_MACACCESS_VALID BIT(11)
124#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) (((x) << 9) & GENMASK(10, 9))
125#define ANA_TABLES_MACACCESS_ENTRYTYPE_M GENMASK(10, 9)
126#define ANA_TABLES_MACACCESS_ENTRYTYPE_X(x) (((x) & GENMASK(10, 9)) >> 9)
127#define ANA_TABLES_MACACCESS_DEST_IDX(x) (((x) << 3) & GENMASK(8, 3))
128#define ANA_TABLES_MACACCESS_DEST_IDX_M GENMASK(8, 3)
129#define ANA_TABLES_MACACCESS_DEST_IDX_X(x) (((x) & GENMASK(8, 3)) >> 3)
130#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) ((x) & GENMASK(2, 0))
131#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)
132#define MACACCESS_CMD_IDLE 0
133#define MACACCESS_CMD_LEARN 1
134#define MACACCESS_CMD_FORGET 2
135#define MACACCESS_CMD_AGE 3
136#define MACACCESS_CMD_GET_NEXT 4
137#define MACACCESS_CMD_INIT 5
138#define MACACCESS_CMD_READ 6
139#define MACACCESS_CMD_WRITE 7
140
141#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(x) (((x) << 2) & GENMASK(13, 2))
142#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_M GENMASK(13, 2)
143#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_X(x) (((x) & GENMASK(13, 2)) >> 2)
144#define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD(x) ((x) & GENMASK(1, 0))
145#define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M GENMASK(1, 0)
146#define ANA_TABLES_VLANACCESS_CMD_IDLE 0x0
147#define ANA_TABLES_VLANACCESS_CMD_WRITE 0x2
148#define ANA_TABLES_VLANACCESS_CMD_INIT 0x3
149
150#define ANA_TABLES_VLANTIDX_VLAN_SEC_FWD_ENA BIT(17)
151#define ANA_TABLES_VLANTIDX_VLAN_FLOOD_DIS BIT(16)
152#define ANA_TABLES_VLANTIDX_VLAN_PRIV_VLAN BIT(15)
153#define ANA_TABLES_VLANTIDX_VLAN_LEARN_DISABLED BIT(14)
154#define ANA_TABLES_VLANTIDX_VLAN_MIRROR BIT(13)
155#define ANA_TABLES_VLANTIDX_VLAN_SRC_CHK BIT(12)
156#define ANA_TABLES_VLANTIDX_V_INDEX(x) ((x) & GENMASK(11, 0))
157#define ANA_TABLES_VLANTIDX_V_INDEX_M GENMASK(11, 0)
158
159#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK(x) (((x) << 2) & GENMASK(8, 2))
160#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_M GENMASK(8, 2)
161#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_X(x) (((x) & GENMASK(8, 2)) >> 2)
162#define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD(x) ((x) & GENMASK(1, 0))
163#define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD_M GENMASK(1, 0)
164
165#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI(x) (((x) << 21) & GENMASK(28, 21))
166#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_M GENMASK(28, 21)
167#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_X(x) (((x) & GENMASK(28, 21)) >> 21)
168#define ANA_TABLES_ISDXTIDX_ISDX_MSTI(x) (((x) << 15) & GENMASK(20, 15))
169#define ANA_TABLES_ISDXTIDX_ISDX_MSTI_M GENMASK(20, 15)
170#define ANA_TABLES_ISDXTIDX_ISDX_MSTI_X(x) (((x) & GENMASK(20, 15)) >> 15)
171#define ANA_TABLES_ISDXTIDX_ISDX_ES0_KEY_ENA BIT(14)
172#define ANA_TABLES_ISDXTIDX_ISDX_FORCE_ENA BIT(10)
173#define ANA_TABLES_ISDXTIDX_ISDX_INDEX(x) ((x) & GENMASK(7, 0))
174#define ANA_TABLES_ISDXTIDX_ISDX_INDEX_M GENMASK(7, 0)
175
176#define ANA_TABLES_ENTRYLIM_RSZ 0x4
177
178#define ANA_TABLES_ENTRYLIM_ENTRYLIM(x) (((x) << 14) & GENMASK(17, 14))
179#define ANA_TABLES_ENTRYLIM_ENTRYLIM_M GENMASK(17, 14)
180#define ANA_TABLES_ENTRYLIM_ENTRYLIM_X(x) (((x) & GENMASK(17, 14)) >> 14)
181#define ANA_TABLES_ENTRYLIM_ENTRYSTAT(x) ((x) & GENMASK(13, 0))
182#define ANA_TABLES_ENTRYLIM_ENTRYSTAT_M GENMASK(13, 0)
183
184#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM(x) (((x) << 4) & GENMASK(31, 4))
185#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_M GENMASK(31, 4)
186#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_X(x) (((x) & GENMASK(31, 4)) >> 4)
187#define ANA_TABLES_STREAMACCESS_SEQ_GEN_REC_ENA BIT(3)
188#define ANA_TABLES_STREAMACCESS_GEN_REC_TYPE BIT(2)
189#define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD(x) ((x) & GENMASK(1, 0))
190#define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD_M GENMASK(1, 0)
191
192#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS(x) (((x) << 30) & GENMASK(31, 30))
193#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_M GENMASK(31, 30)
194#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_X(x) (((x) & GENMASK(31, 30)) >> 30)
195#define ANA_TABLES_STREAMTIDX_S_INDEX(x) (((x) << 16) & GENMASK(22, 16))
196#define ANA_TABLES_STREAMTIDX_S_INDEX_M GENMASK(22, 16)
197#define ANA_TABLES_STREAMTIDX_S_INDEX_X(x) (((x) & GENMASK(22, 16)) >> 16)
198#define ANA_TABLES_STREAMTIDX_FORCE_SF_BEHAVIOUR BIT(14)
199#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN(x) (((x) << 8) & GENMASK(13, 8))
200#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_M GENMASK(13, 8)
201#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_X(x) (((x) & GENMASK(13, 8)) >> 8)
202#define ANA_TABLES_STREAMTIDX_RESET_ON_ROGUE BIT(7)
203#define ANA_TABLES_STREAMTIDX_REDTAG_POP BIT(6)
204#define ANA_TABLES_STREAMTIDX_STREAM_SPLIT BIT(5)
205#define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2(x) ((x) & GENMASK(4, 0))
206#define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2_M GENMASK(4, 0)
207
208#define ANA_TABLES_SEQ_MASK_SPLIT_MASK(x) (((x) << 16) & GENMASK(22, 16))
209#define ANA_TABLES_SEQ_MASK_SPLIT_MASK_M GENMASK(22, 16)
210#define ANA_TABLES_SEQ_MASK_SPLIT_MASK_X(x) (((x) & GENMASK(22, 16)) >> 16)
211#define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK(x) ((x) & GENMASK(6, 0))
212#define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK_M GENMASK(6, 0)
213
214#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK(x) (((x) << 1) & GENMASK(7, 1))
215#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_M GENMASK(7, 1)
216#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_X(x) (((x) & GENMASK(7, 1)) >> 1)
217#define ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA BIT(0)
218
219#define ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA BIT(22)
220#define ANA_TABLES_SFIDACCESS_IGR_PRIO(x) (((x) << 19) & GENMASK(21, 19))
221#define ANA_TABLES_SFIDACCESS_IGR_PRIO_M GENMASK(21, 19)
222#define ANA_TABLES_SFIDACCESS_IGR_PRIO_X(x) (((x) & GENMASK(21, 19)) >> 19)
223#define ANA_TABLES_SFIDACCESS_FORCE_BLOCK BIT(18)
224#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(x) (((x) << 2) & GENMASK(17, 2))
225#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_M GENMASK(17, 2)
226#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_X(x) (((x) & GENMASK(17, 2)) >> 2)
227#define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(x) ((x) & GENMASK(1, 0))
228#define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M GENMASK(1, 0)
229
230#define ANA_TABLES_SFIDTIDX_SGID_VALID BIT(26)
231#define ANA_TABLES_SFIDTIDX_SGID(x) (((x) << 18) & GENMASK(25, 18))
232#define ANA_TABLES_SFIDTIDX_SGID_M GENMASK(25, 18)
233#define ANA_TABLES_SFIDTIDX_SGID_X(x) (((x) & GENMASK(25, 18)) >> 18)
234#define ANA_TABLES_SFIDTIDX_POL_ENA BIT(17)
235#define ANA_TABLES_SFIDTIDX_POL_IDX(x) (((x) << 8) & GENMASK(16, 8))
236#define ANA_TABLES_SFIDTIDX_POL_IDX_M GENMASK(16, 8)
237#define ANA_TABLES_SFIDTIDX_POL_IDX_X(x) (((x) & GENMASK(16, 8)) >> 8)
238#define ANA_TABLES_SFIDTIDX_SFID_INDEX(x) ((x) & GENMASK(7, 0))
239#define ANA_TABLES_SFIDTIDX_SFID_INDEX_M GENMASK(7, 0)
240
241#define ANA_MSTI_STATE_RSZ 0x4
242
243#define ANA_OAM_UPM_LM_CNT_RSZ 0x4
244
245#define ANA_SG_ACCESS_CTRL_SGID(x) ((x) & GENMASK(7, 0))
246#define ANA_SG_ACCESS_CTRL_SGID_M GENMASK(7, 0)
247#define ANA_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28)
248
249#define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
250#define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
251#define ANA_SG_CONFIG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(18, 16))
252#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M GENMASK(18, 16)
253#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(18, 16)) >> 16)
254#define ANA_SG_CONFIG_REG_3_GATE_ENABLE BIT(20)
255#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 24) & GENMASK(27, 24))
256#define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(27, 24)
257#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(27, 24)) >> 24)
258#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(28)
259
260#define ANA_SG_GCL_GS_CONFIG_RSZ 0x4
261
262#define ANA_SG_GCL_GS_CONFIG_IPS(x) ((x) & GENMASK(3, 0))
263#define ANA_SG_GCL_GS_CONFIG_IPS_M GENMASK(3, 0)
264#define ANA_SG_GCL_GS_CONFIG_GATE_STATE BIT(4)
265
266#define ANA_SG_GCL_TI_CONFIG_RSZ 0x4
267
268#define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
269#define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0)
270#define ANA_SG_STATUS_REG_3_GATE_STATE BIT(16)
271#define ANA_SG_STATUS_REG_3_IPS(x) (((x) << 20) & GENMASK(23, 20))
272#define ANA_SG_STATUS_REG_3_IPS_M GENMASK(23, 20)
273#define ANA_SG_STATUS_REG_3_IPS_X(x) (((x) & GENMASK(23, 20)) >> 20)
274#define ANA_SG_STATUS_REG_3_CONFIG_PENDING BIT(24)
275
276#define ANA_PORT_VLAN_CFG_GSZ 0x100
277
278#define ANA_PORT_VLAN_CFG_VLAN_VID_AS_ISDX BIT(21)
279#define ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA BIT(20)
280#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT(x) (((x) << 18) & GENMASK(19, 18))
281#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M GENMASK(19, 18)
282#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_X(x) (((x) & GENMASK(19, 18)) >> 18)
283#define ANA_PORT_VLAN_CFG_VLAN_INNER_TAG_ENA BIT(17)
284#define ANA_PORT_VLAN_CFG_VLAN_TAG_TYPE BIT(16)
285#define ANA_PORT_VLAN_CFG_VLAN_DEI BIT(15)
286#define ANA_PORT_VLAN_CFG_VLAN_PCP(x) (((x) << 12) & GENMASK(14, 12))
287#define ANA_PORT_VLAN_CFG_VLAN_PCP_M GENMASK(14, 12)
288#define ANA_PORT_VLAN_CFG_VLAN_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12)
289#define ANA_PORT_VLAN_CFG_VLAN_VID(x) ((x) & GENMASK(11, 0))
290#define ANA_PORT_VLAN_CFG_VLAN_VID_M GENMASK(11, 0)
291
292#define ANA_PORT_DROP_CFG_GSZ 0x100
293
294#define ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA BIT(6)
295#define ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA BIT(5)
296#define ANA_PORT_DROP_CFG_DROP_C_TAGGED_ENA BIT(4)
297#define ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3)
298#define ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2)
299#define ANA_PORT_DROP_CFG_DROP_NULL_MAC_ENA BIT(1)
300#define ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA BIT(0)
301
302#define ANA_PORT_QOS_CFG_GSZ 0x100
303
304#define ANA_PORT_QOS_CFG_DP_DEFAULT_VAL BIT(8)
305#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(x) (((x) << 5) & GENMASK(7, 5))
306#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M GENMASK(7, 5)
307#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(x) (((x) & GENMASK(7, 5)) >> 5)
308#define ANA_PORT_QOS_CFG_QOS_DSCP_ENA BIT(4)
309#define ANA_PORT_QOS_CFG_QOS_PCP_ENA BIT(3)
310#define ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA BIT(2)
311#define ANA_PORT_QOS_CFG_DSCP_REWR_CFG(x) ((x) & GENMASK(1, 0))
312#define ANA_PORT_QOS_CFG_DSCP_REWR_CFG_M GENMASK(1, 0)
313
314#define ANA_PORT_VCAP_CFG_GSZ 0x100
315
316#define ANA_PORT_VCAP_CFG_S1_ENA BIT(14)
317#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA(x) (((x) << 11) & GENMASK(13, 11))
318#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_M GENMASK(13, 11)
319#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_X(x) (((x) & GENMASK(13, 11)) >> 11)
320#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA(x) (((x) << 8) & GENMASK(10, 8))
321#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_M GENMASK(10, 8)
322#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_X(x) (((x) & GENMASK(10, 8)) >> 8)
323#define ANA_PORT_VCAP_CFG_PAG_VAL(x) ((x) & GENMASK(7, 0))
324#define ANA_PORT_VCAP_CFG_PAG_VAL_M GENMASK(7, 0)
325
326#define ANA_PORT_VCAP_S1_KEY_CFG_GSZ 0x100
327#define ANA_PORT_VCAP_S1_KEY_CFG_RSZ 0x4
328
329#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG(x) (((x) << 4) & GENMASK(6, 4))
330#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_M GENMASK(6, 4)
331#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_X(x) (((x) & GENMASK(6, 4)) >> 4)
332#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG(x) (((x) << 2) & GENMASK(3, 2))
333#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_M GENMASK(3, 2)
334#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2)
335#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG(x) ((x) & GENMASK(1, 0))
336#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG_M GENMASK(1, 0)
337
338#define ANA_PORT_VCAP_S2_CFG_GSZ 0x100
339
340#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA(x) (((x) << 17) & GENMASK(18, 17))
341#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_M GENMASK(18, 17)
342#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_X(x) (((x) & GENMASK(18, 17)) >> 17)
343#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA(x) (((x) << 15) & GENMASK(16, 15))
344#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_M GENMASK(16, 15)
345#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_X(x) (((x) & GENMASK(16, 15)) >> 15)
346#define ANA_PORT_VCAP_S2_CFG_S2_ENA BIT(14)
347#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(x) (((x) << 12) & GENMASK(13, 12))
348#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_M GENMASK(13, 12)
349#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_X(x) (((x) & GENMASK(13, 12)) >> 12)
350#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(x) (((x) << 10) & GENMASK(11, 10))
351#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_M GENMASK(11, 10)
352#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_X(x) (((x) & GENMASK(11, 10)) >> 10)
353#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(x) (((x) << 8) & GENMASK(9, 8))
354#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_M GENMASK(9, 8)
355#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_X(x) (((x) & GENMASK(9, 8)) >> 8)
356#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(x) (((x) << 6) & GENMASK(7, 6))
357#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_M GENMASK(7, 6)
358#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_X(x) (((x) & GENMASK(7, 6)) >> 6)
359#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(x) (((x) << 2) & GENMASK(5, 2))
360#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_M GENMASK(5, 2)
361#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_X(x) (((x) & GENMASK(5, 2)) >> 2)
362#define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(x) ((x) & GENMASK(1, 0))
363#define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS_M GENMASK(1, 0)
364
365#define ANA_PORT_PCP_DEI_MAP_GSZ 0x100
366#define ANA_PORT_PCP_DEI_MAP_RSZ 0x4
367
368#define ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL BIT(3)
369#define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(x) ((x) & GENMASK(2, 0))
370#define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M GENMASK(2, 0)
371
372#define ANA_PORT_CPU_FWD_CFG_GSZ 0x100
373
374#define ANA_PORT_CPU_FWD_CFG_CPU_VRAP_REDIR_ENA BIT(7)
375#define ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA BIT(6)
376#define ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA BIT(5)
377#define ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA BIT(4)
378#define ANA_PORT_CPU_FWD_CFG_CPU_SRC_COPY_ENA BIT(3)
379#define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_DROP_ENA BIT(2)
380#define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_REDIR_ENA BIT(1)
381#define ANA_PORT_CPU_FWD_CFG_CPU_OAM_ENA BIT(0)
382
383#define ANA_PORT_CPU_FWD_BPDU_CFG_GSZ 0x100
384
385#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
386#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_M GENMASK(31, 16)
387#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
388#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(x) ((x) & GENMASK(15, 0))
389#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA_M GENMASK(15, 0)
390
391#define ANA_PORT_CPU_FWD_GARP_CFG_GSZ 0x100
392
393#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
394#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_M GENMASK(31, 16)
395#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
396#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA(x) ((x) & GENMASK(15, 0))
397#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA_M GENMASK(15, 0)
398
399#define ANA_PORT_CPU_FWD_CCM_CFG_GSZ 0x100
400
401#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
402#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_M GENMASK(31, 16)
403#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
404#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA(x) ((x) & GENMASK(15, 0))
405#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA_M GENMASK(15, 0)
406
407#define ANA_PORT_PORT_CFG_GSZ 0x100
408
409#define ANA_PORT_PORT_CFG_SRC_MIRROR_ENA BIT(15)
410#define ANA_PORT_PORT_CFG_LIMIT_DROP BIT(14)
411#define ANA_PORT_PORT_CFG_LIMIT_CPU BIT(13)
412#define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_DROP BIT(12)
413#define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_CPU BIT(11)
414#define ANA_PORT_PORT_CFG_LEARNDROP BIT(10)
415#define ANA_PORT_PORT_CFG_LEARNCPU BIT(9)
416#define ANA_PORT_PORT_CFG_LEARNAUTO BIT(8)
417#define ANA_PORT_PORT_CFG_LEARN_ENA BIT(7)
418#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
419#define ANA_PORT_PORT_CFG_PORTID_VAL(x) (((x) << 2) & GENMASK(5, 2))
420#define ANA_PORT_PORT_CFG_PORTID_VAL_M GENMASK(5, 2)
421#define ANA_PORT_PORT_CFG_PORTID_VAL_X(x) (((x) & GENMASK(5, 2)) >> 2)
422#define ANA_PORT_PORT_CFG_USE_B_DOM_TBL BIT(1)
423#define ANA_PORT_PORT_CFG_LSR_MODE BIT(0)
424
425#define ANA_PORT_POL_CFG_GSZ 0x100
426
427#define ANA_PORT_POL_CFG_POL_CPU_REDIR_8021 BIT(19)
428#define ANA_PORT_POL_CFG_POL_CPU_REDIR_IP BIT(18)
429#define ANA_PORT_POL_CFG_PORT_POL_ENA BIT(17)
430#define ANA_PORT_POL_CFG_QUEUE_POL_ENA(x) (((x) << 9) & GENMASK(16, 9))
431#define ANA_PORT_POL_CFG_QUEUE_POL_ENA_M GENMASK(16, 9)
432#define ANA_PORT_POL_CFG_QUEUE_POL_ENA_X(x) (((x) & GENMASK(16, 9)) >> 9)
433#define ANA_PORT_POL_CFG_POL_ORDER(x) ((x) & GENMASK(8, 0))
434#define ANA_PORT_POL_CFG_POL_ORDER_M GENMASK(8, 0)
435
436#define ANA_PORT_PTP_CFG_GSZ 0x100
437
438#define ANA_PORT_PTP_CFG_PTP_BACKPLANE_MODE BIT(0)
439
440#define ANA_PORT_PTP_DLY1_CFG_GSZ 0x100
441
442#define ANA_PORT_PTP_DLY2_CFG_GSZ 0x100
443
444#define ANA_PORT_SFID_CFG_GSZ 0x100
445#define ANA_PORT_SFID_CFG_RSZ 0x4
446
447#define ANA_PORT_SFID_CFG_SFID_VALID BIT(8)
448#define ANA_PORT_SFID_CFG_SFID(x) ((x) & GENMASK(7, 0))
449#define ANA_PORT_SFID_CFG_SFID_M GENMASK(7, 0)
450
451#define ANA_PFC_PFC_CFG_GSZ 0x40
452
453#define ANA_PFC_PFC_CFG_RX_PFC_ENA(x) (((x) << 2) & GENMASK(9, 2))
454#define ANA_PFC_PFC_CFG_RX_PFC_ENA_M GENMASK(9, 2)
455#define ANA_PFC_PFC_CFG_RX_PFC_ENA_X(x) (((x) & GENMASK(9, 2)) >> 2)
456#define ANA_PFC_PFC_CFG_FC_LINK_SPEED(x) ((x) & GENMASK(1, 0))
457#define ANA_PFC_PFC_CFG_FC_LINK_SPEED_M GENMASK(1, 0)
458
459#define ANA_PFC_PFC_TIMER_GSZ 0x40
460#define ANA_PFC_PFC_TIMER_RSZ 0x4
461
462#define ANA_IPT_OAM_MEP_CFG_GSZ 0x8
463
464#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P(x) (((x) << 6) & GENMASK(10, 6))
465#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_M GENMASK(10, 6)
466#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_X(x) (((x) & GENMASK(10, 6)) >> 6)
467#define ANA_IPT_OAM_MEP_CFG_MEP_IDX(x) (((x) << 1) & GENMASK(5, 1))
468#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_M GENMASK(5, 1)
469#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_X(x) (((x) & GENMASK(5, 1)) >> 1)
470#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_ENA BIT(0)
471
472#define ANA_IPT_IPT_GSZ 0x8
473
474#define ANA_IPT_IPT_IPT_CFG(x) (((x) << 15) & GENMASK(16, 15))
475#define ANA_IPT_IPT_IPT_CFG_M GENMASK(16, 15)
476#define ANA_IPT_IPT_IPT_CFG_X(x) (((x) & GENMASK(16, 15)) >> 15)
477#define ANA_IPT_IPT_ISDX_P(x) (((x) << 7) & GENMASK(14, 7))
478#define ANA_IPT_IPT_ISDX_P_M GENMASK(14, 7)
479#define ANA_IPT_IPT_ISDX_P_X(x) (((x) & GENMASK(14, 7)) >> 7)
480#define ANA_IPT_IPT_PPT_IDX(x) ((x) & GENMASK(6, 0))
481#define ANA_IPT_IPT_PPT_IDX_M GENMASK(6, 0)
482
483#define ANA_PPT_PPT_RSZ 0x4
484
485#define ANA_FID_MAP_FID_MAP_RSZ 0x4
486
487#define ANA_FID_MAP_FID_MAP_FID_C_VAL(x) (((x) << 6) & GENMASK(11, 6))
488#define ANA_FID_MAP_FID_MAP_FID_C_VAL_M GENMASK(11, 6)
489#define ANA_FID_MAP_FID_MAP_FID_C_VAL_X(x) (((x) & GENMASK(11, 6)) >> 6)
490#define ANA_FID_MAP_FID_MAP_FID_B_VAL(x) ((x) & GENMASK(5, 0))
491#define ANA_FID_MAP_FID_MAP_FID_B_VAL_M GENMASK(5, 0)
492
493#define ANA_AGGR_CFG_AC_RND_ENA BIT(7)
494#define ANA_AGGR_CFG_AC_DMAC_ENA BIT(6)
495#define ANA_AGGR_CFG_AC_SMAC_ENA BIT(5)
496#define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(4)
497#define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(3)
498#define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(2)
499#define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(1)
500#define ANA_AGGR_CFG_AC_ISDX_ENA BIT(0)
501
502#define ANA_CPUQ_CFG_CPUQ_MLD(x) (((x) << 27) & GENMASK(29, 27))
503#define ANA_CPUQ_CFG_CPUQ_MLD_M GENMASK(29, 27)
504#define ANA_CPUQ_CFG_CPUQ_MLD_X(x) (((x) & GENMASK(29, 27)) >> 27)
505#define ANA_CPUQ_CFG_CPUQ_IGMP(x) (((x) << 24) & GENMASK(26, 24))
506#define ANA_CPUQ_CFG_CPUQ_IGMP_M GENMASK(26, 24)
507#define ANA_CPUQ_CFG_CPUQ_IGMP_X(x) (((x) & GENMASK(26, 24)) >> 24)
508#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(x) (((x) << 21) & GENMASK(23, 21))
509#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_M GENMASK(23, 21)
510#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_X(x) (((x) & GENMASK(23, 21)) >> 21)
511#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(x) (((x) << 18) & GENMASK(20, 18))
512#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_M GENMASK(20, 18)
513#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_X(x) (((x) & GENMASK(20, 18)) >> 18)
514#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(x) (((x) << 15) & GENMASK(17, 15))
515#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_M GENMASK(17, 15)
516#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_X(x) (((x) & GENMASK(17, 15)) >> 15)
517#define ANA_CPUQ_CFG_CPUQ_SRC_COPY(x) (((x) << 12) & GENMASK(14, 12))
518#define ANA_CPUQ_CFG_CPUQ_SRC_COPY_M GENMASK(14, 12)
519#define ANA_CPUQ_CFG_CPUQ_SRC_COPY_X(x) (((x) & GENMASK(14, 12)) >> 12)
520#define ANA_CPUQ_CFG_CPUQ_MAC_COPY(x) (((x) << 9) & GENMASK(11, 9))
521#define ANA_CPUQ_CFG_CPUQ_MAC_COPY_M GENMASK(11, 9)
522#define ANA_CPUQ_CFG_CPUQ_MAC_COPY_X(x) (((x) & GENMASK(11, 9)) >> 9)
523#define ANA_CPUQ_CFG_CPUQ_LRN(x) (((x) << 6) & GENMASK(8, 6))
524#define ANA_CPUQ_CFG_CPUQ_LRN_M GENMASK(8, 6)
525#define ANA_CPUQ_CFG_CPUQ_LRN_X(x) (((x) & GENMASK(8, 6)) >> 6)
526#define ANA_CPUQ_CFG_CPUQ_MIRROR(x) (((x) << 3) & GENMASK(5, 3))
527#define ANA_CPUQ_CFG_CPUQ_MIRROR_M GENMASK(5, 3)
528#define ANA_CPUQ_CFG_CPUQ_MIRROR_X(x) (((x) & GENMASK(5, 3)) >> 3)
529#define ANA_CPUQ_CFG_CPUQ_SFLOW(x) ((x) & GENMASK(2, 0))
530#define ANA_CPUQ_CFG_CPUQ_SFLOW_M GENMASK(2, 0)
531
532#define ANA_CPUQ_8021_CFG_RSZ 0x4
533
534#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(x) (((x) << 6) & GENMASK(8, 6))
535#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_M GENMASK(8, 6)
536#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_X(x) (((x) & GENMASK(8, 6)) >> 6)
537#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(x) (((x) << 3) & GENMASK(5, 3))
538#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_M GENMASK(5, 3)
539#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_X(x) (((x) & GENMASK(5, 3)) >> 3)
540#define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL(x) ((x) & GENMASK(2, 0))
541#define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL_M GENMASK(2, 0)
542
543#define ANA_DSCP_CFG_RSZ 0x4
544
545#define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11)
546#define ANA_DSCP_CFG_QOS_DSCP_VAL(x) (((x) << 8) & GENMASK(10, 8))
547#define ANA_DSCP_CFG_QOS_DSCP_VAL_M GENMASK(10, 8)
548#define ANA_DSCP_CFG_QOS_DSCP_VAL_X(x) (((x) & GENMASK(10, 8)) >> 8)
549#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL(x) (((x) << 2) & GENMASK(7, 2))
550#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_M GENMASK(7, 2)
551#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(x) (((x) & GENMASK(7, 2)) >> 2)
552#define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1)
553#define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0)
554
555#define ANA_DSCP_REWR_CFG_RSZ 0x4
556
557#define ANA_VCAP_RNG_TYPE_CFG_RSZ 0x4
558
559#define ANA_VCAP_RNG_VAL_CFG_RSZ 0x4
560
561#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL(x) (((x) << 16) & GENMASK(31, 16))
562#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_M GENMASK(31, 16)
563#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_X(x) (((x) & GENMASK(31, 16)) >> 16)
564#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL(x) ((x) & GENMASK(15, 0))
565#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL_M GENMASK(15, 0)
566
567#define ANA_VRAP_CFG_VRAP_VLAN_AWARE_ENA BIT(12)
568#define ANA_VRAP_CFG_VRAP_VID(x) ((x) & GENMASK(11, 0))
569#define ANA_VRAP_CFG_VRAP_VID_M GENMASK(11, 0)
570
571#define ANA_DISCARD_CFG_DROP_TAGGING_ISDX0 BIT(3)
572#define ANA_DISCARD_CFG_DROP_CTRLPROT_ISDX0 BIT(2)
573#define ANA_DISCARD_CFG_DROP_TAGGING_S2_ENA BIT(1)
574#define ANA_DISCARD_CFG_DROP_CTRLPROT_S2_ENA BIT(0)
575
576#define ANA_FID_CFG_VID_MC_ENA BIT(0)
577
578#define ANA_POL_PIR_CFG_GSZ 0x20
579
580#define ANA_POL_PIR_CFG_PIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
581#define ANA_POL_PIR_CFG_PIR_RATE_M GENMASK(20, 6)
582#define ANA_POL_PIR_CFG_PIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
583#define ANA_POL_PIR_CFG_PIR_BURST(x) ((x) & GENMASK(5, 0))
584#define ANA_POL_PIR_CFG_PIR_BURST_M GENMASK(5, 0)
585
586#define ANA_POL_CIR_CFG_GSZ 0x20
587
588#define ANA_POL_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
589#define ANA_POL_CIR_CFG_CIR_RATE_M GENMASK(20, 6)
590#define ANA_POL_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
591#define ANA_POL_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0))
592#define ANA_POL_CIR_CFG_CIR_BURST_M GENMASK(5, 0)
593
594#define ANA_POL_MODE_CFG_GSZ 0x20
595
596#define ANA_POL_MODE_CFG_IPG_SIZE(x) (((x) << 5) & GENMASK(9, 5))
597#define ANA_POL_MODE_CFG_IPG_SIZE_M GENMASK(9, 5)
598#define ANA_POL_MODE_CFG_IPG_SIZE_X(x) (((x) & GENMASK(9, 5)) >> 5)
599#define ANA_POL_MODE_CFG_FRM_MODE(x) (((x) << 3) & GENMASK(4, 3))
600#define ANA_POL_MODE_CFG_FRM_MODE_M GENMASK(4, 3)
601#define ANA_POL_MODE_CFG_FRM_MODE_X(x) (((x) & GENMASK(4, 3)) >> 3)
602#define ANA_POL_MODE_CFG_DLB_COUPLED BIT(2)
603#define ANA_POL_MODE_CFG_CIR_ENA BIT(1)
604#define ANA_POL_MODE_CFG_OVERSHOOT_ENA BIT(0)
605
606#define ANA_POL_PIR_STATE_GSZ 0x20
607
608#define ANA_POL_CIR_STATE_GSZ 0x20
609
610#define ANA_POL_STATE_GSZ 0x20
611
612#define ANA_POL_FLOWC_RSZ 0x4
613
614#define ANA_POL_FLOWC_POL_FLOWC BIT(0)
615
616#define ANA_POL_HYST_POL_FC_HYST(x) (((x) << 4) & GENMASK(9, 4))
617#define ANA_POL_HYST_POL_FC_HYST_M GENMASK(9, 4)
618#define ANA_POL_HYST_POL_FC_HYST_X(x) (((x) & GENMASK(9, 4)) >> 4)
619#define ANA_POL_HYST_POL_STOP_HYST(x) ((x) & GENMASK(3, 0))
620#define ANA_POL_HYST_POL_STOP_HYST_M GENMASK(3, 0)
621
622#define ANA_POL_MISC_CFG_POL_CLOSE_ALL BIT(1)
623#define ANA_POL_MISC_CFG_POL_LEAK_DIS BIT(0)
624
625#endif
diff --git a/drivers/net/ethernet/mscc/ocelot_board.c b/drivers/net/ethernet/mscc/ocelot_board.c
new file mode 100644
index 000000000000..18df7d934e81
--- /dev/null
+++ b/drivers/net/ethernet/mscc/ocelot_board.c
@@ -0,0 +1,316 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <linux/interrupt.h>
8#include <linux/module.h>
9#include <linux/netdevice.h>
10#include <linux/of_mdio.h>
11#include <linux/of_platform.h>
12#include <linux/skbuff.h>
13
14#include "ocelot.h"
15
16static int ocelot_parse_ifh(u32 *ifh, struct frame_info *info)
17{
18 int i;
19 u8 llen, wlen;
20
21 /* The IFH is in network order, switch to CPU order */
22 for (i = 0; i < IFH_LEN; i++)
23 ifh[i] = ntohl((__force __be32)ifh[i]);
24
25 wlen = (ifh[1] >> 7) & 0xff;
26 llen = (ifh[1] >> 15) & 0x3f;
27 info->len = OCELOT_BUFFER_CELL_SZ * wlen + llen - 80;
28
29 info->port = (ifh[2] & GENMASK(14, 11)) >> 11;
30
31 info->cpuq = (ifh[3] & GENMASK(27, 20)) >> 20;
32 info->tag_type = (ifh[3] & GENMASK(16, 16)) >> 16;
33 info->vid = ifh[3] & GENMASK(11, 0);
34
35 return 0;
36}
37
38static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
39 u32 *rval)
40{
41 u32 val;
42 u32 bytes_valid;
43
44 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
45 if (val == XTR_NOT_READY) {
46 if (ifh)
47 return -EIO;
48
49 do {
50 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
51 } while (val == XTR_NOT_READY);
52 }
53
54 switch (val) {
55 case XTR_ABORT:
56 return -EIO;
57 case XTR_EOF_0:
58 case XTR_EOF_1:
59 case XTR_EOF_2:
60 case XTR_EOF_3:
61 case XTR_PRUNED:
62 bytes_valid = XTR_VALID_BYTES(val);
63 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
64 if (val == XTR_ESCAPE)
65 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
66 else
67 *rval = val;
68
69 return bytes_valid;
70 case XTR_ESCAPE:
71 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
72
73 return 4;
74 default:
75 *rval = val;
76
77 return 4;
78 }
79}
80
81static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg)
82{
83 struct ocelot *ocelot = arg;
84 int i = 0, grp = 0;
85 int err = 0;
86
87 if (!(ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)))
88 return IRQ_NONE;
89
90 do {
91 struct sk_buff *skb;
92 struct net_device *dev;
93 u32 *buf;
94 int sz, len;
95 u32 ifh[4];
96 u32 val;
97 struct frame_info info;
98
99 for (i = 0; i < IFH_LEN; i++) {
100 err = ocelot_rx_frame_word(ocelot, grp, true, &ifh[i]);
101 if (err != 4)
102 break;
103 }
104
105 if (err != 4)
106 break;
107
108 ocelot_parse_ifh(ifh, &info);
109
110 dev = ocelot->ports[info.port]->dev;
111
112 skb = netdev_alloc_skb(dev, info.len);
113
114 if (unlikely(!skb)) {
115 netdev_err(dev, "Unable to allocate sk_buff\n");
116 err = -ENOMEM;
117 break;
118 }
119 buf = (u32 *)skb_put(skb, info.len);
120
121 len = 0;
122 do {
123 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
124 *buf++ = val;
125 len += sz;
126 } while ((sz == 4) && (len < info.len));
127
128 if (sz < 0) {
129 err = sz;
130 break;
131 }
132
133 /* Everything we see on an interface that is in the HW bridge
134 * has already been forwarded.
135 */
136 if (ocelot->bridge_mask & BIT(info.port))
137 skb->offload_fwd_mark = 1;
138
139 skb->protocol = eth_type_trans(skb, dev);
140 netif_rx(skb);
141 dev->stats.rx_bytes += len;
142 dev->stats.rx_packets++;
143 } while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp));
144
145 if (err)
146 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
147 ocelot_read_rix(ocelot, QS_XTR_RD, grp);
148
149 return IRQ_HANDLED;
150}
151
152static const struct of_device_id mscc_ocelot_match[] = {
153 { .compatible = "mscc,vsc7514-switch" },
154 { }
155};
156MODULE_DEVICE_TABLE(of, mscc_ocelot_match);
157
158static int mscc_ocelot_probe(struct platform_device *pdev)
159{
160 int err, irq;
161 unsigned int i;
162 struct device_node *np = pdev->dev.of_node;
163 struct device_node *ports, *portnp;
164 struct ocelot *ocelot;
165 u32 val;
166
167 struct {
168 enum ocelot_target id;
169 char *name;
170 } res[] = {
171 { SYS, "sys" },
172 { REW, "rew" },
173 { QSYS, "qsys" },
174 { ANA, "ana" },
175 { QS, "qs" },
176 { HSIO, "hsio" },
177 };
178
179 if (!np && !pdev->dev.platform_data)
180 return -ENODEV;
181
182 ocelot = devm_kzalloc(&pdev->dev, sizeof(*ocelot), GFP_KERNEL);
183 if (!ocelot)
184 return -ENOMEM;
185
186 platform_set_drvdata(pdev, ocelot);
187 ocelot->dev = &pdev->dev;
188
189 for (i = 0; i < ARRAY_SIZE(res); i++) {
190 struct regmap *target;
191
192 target = ocelot_io_platform_init(ocelot, pdev, res[i].name);
193 if (IS_ERR(target))
194 return PTR_ERR(target);
195
196 ocelot->targets[res[i].id] = target;
197 }
198
199 err = ocelot_chip_init(ocelot);
200 if (err)
201 return err;
202
203 irq = platform_get_irq_byname(pdev, "xtr");
204 if (irq < 0)
205 return -ENODEV;
206
207 err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
208 ocelot_xtr_irq_handler, IRQF_ONESHOT,
209 "frame extraction", ocelot);
210 if (err)
211 return err;
212
213 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
214 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
215
216 do {
217 msleep(1);
218 regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
219 &val);
220 } while (val);
221
222 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
223 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
224
225 ocelot->num_cpu_ports = 1; /* 1 port on the switch, two groups */
226
227 ports = of_get_child_by_name(np, "ethernet-ports");
228 if (!ports) {
229 dev_err(&pdev->dev, "no ethernet-ports child node found\n");
230 return -ENODEV;
231 }
232
233 ocelot->num_phys_ports = of_get_child_count(ports);
234
235 ocelot->ports = devm_kcalloc(&pdev->dev, ocelot->num_phys_ports,
236 sizeof(struct ocelot_port *), GFP_KERNEL);
237
238 INIT_LIST_HEAD(&ocelot->multicast);
239 ocelot_init(ocelot);
240
241 ocelot_rmw(ocelot, HSIO_HW_CFG_DEV1G_4_MODE |
242 HSIO_HW_CFG_DEV1G_6_MODE |
243 HSIO_HW_CFG_DEV1G_9_MODE,
244 HSIO_HW_CFG_DEV1G_4_MODE |
245 HSIO_HW_CFG_DEV1G_6_MODE |
246 HSIO_HW_CFG_DEV1G_9_MODE,
247 HSIO_HW_CFG);
248
249 for_each_available_child_of_node(ports, portnp) {
250 struct device_node *phy_node;
251 struct phy_device *phy;
252 struct resource *res;
253 void __iomem *regs;
254 char res_name[8];
255 u32 port;
256
257 if (of_property_read_u32(portnp, "reg", &port))
258 continue;
259
260 snprintf(res_name, sizeof(res_name), "port%d", port);
261
262 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
263 res_name);
264 regs = devm_ioremap_resource(&pdev->dev, res);
265 if (IS_ERR(regs))
266 continue;
267
268 phy_node = of_parse_phandle(portnp, "phy-handle", 0);
269 if (!phy_node)
270 continue;
271
272 phy = of_phy_find_device(phy_node);
273 if (!phy)
274 continue;
275
276 err = ocelot_probe_port(ocelot, port, regs, phy);
277 if (err) {
278 dev_err(&pdev->dev, "failed to probe ports\n");
279 goto err_probe_ports;
280 }
281 }
282
283 register_netdevice_notifier(&ocelot_netdevice_nb);
284
285 dev_info(&pdev->dev, "Ocelot switch probed\n");
286
287 return 0;
288
289err_probe_ports:
290 return err;
291}
292
293static int mscc_ocelot_remove(struct platform_device *pdev)
294{
295 struct ocelot *ocelot = platform_get_drvdata(pdev);
296
297 ocelot_deinit(ocelot);
298 unregister_netdevice_notifier(&ocelot_netdevice_nb);
299
300 return 0;
301}
302
303static struct platform_driver mscc_ocelot_driver = {
304 .probe = mscc_ocelot_probe,
305 .remove = mscc_ocelot_remove,
306 .driver = {
307 .name = "ocelot-switch",
308 .of_match_table = mscc_ocelot_match,
309 },
310};
311
312module_platform_driver(mscc_ocelot_driver);
313
314MODULE_DESCRIPTION("Microsemi Ocelot switch driver");
315MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
316MODULE_LICENSE("Dual MIT/GPL");
diff --git a/drivers/net/ethernet/mscc/ocelot_dev.h b/drivers/net/ethernet/mscc/ocelot_dev.h
new file mode 100644
index 000000000000..0a50d53bbd3f
--- /dev/null
+++ b/drivers/net/ethernet/mscc/ocelot_dev.h
@@ -0,0 +1,275 @@
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_DEV_H_
9#define _MSCC_OCELOT_DEV_H_
10
11#define DEV_CLOCK_CFG 0x0
12
13#define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
14#define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
15#define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
16#define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
17#define DEV_CLOCK_CFG_PORT_RST BIT(3)
18#define DEV_CLOCK_CFG_PHY_RST BIT(2)
19#define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))
20#define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
21
22#define DEV_PORT_MISC 0x4
23
24#define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
25#define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
26#define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
27#define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
28#define DEV_PORT_MISC_HDX_FAST_DIS BIT(0)
29
30#define DEV_EVENTS 0x8
31
32#define DEV_EEE_CFG 0xc
33
34#define DEV_EEE_CFG_EEE_ENA BIT(22)
35#define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))
36#define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
37#define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)
38#define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
39#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
40#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
41#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))
42#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
43#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) (((x) & GENMASK(7, 1)) >> 1)
44#define DEV_EEE_CFG_PORT_LPI BIT(0)
45
46#define DEV_RX_PATH_DELAY 0x10
47
48#define DEV_TX_PATH_DELAY 0x14
49
50#define DEV_PTP_PREDICT_CFG 0x18
51
52#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x) (((x) << 4) & GENMASK(11, 4))
53#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M GENMASK(11, 4)
54#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x) (((x) & GENMASK(11, 4)) >> 4)
55#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x) ((x) & GENMASK(3, 0))
56#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M GENMASK(3, 0)
57
58#define DEV_MAC_ENA_CFG 0x1c
59
60#define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
61#define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
62
63#define DEV_MAC_MODE_CFG 0x20
64
65#define DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8)
66#define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4)
67#define DEV_MAC_MODE_CFG_FDX_ENA BIT(0)
68
69#define DEV_MAC_MAXLEN_CFG 0x24
70
71#define DEV_MAC_TAGS_CFG 0x28
72
73#define DEV_MAC_TAGS_CFG_TAG_ID(x) (((x) << 16) & GENMASK(31, 16))
74#define DEV_MAC_TAGS_CFG_TAG_ID_M GENMASK(31, 16)
75#define DEV_MAC_TAGS_CFG_TAG_ID_X(x) (((x) & GENMASK(31, 16)) >> 16)
76#define DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(2)
77#define DEV_MAC_TAGS_CFG_PB_ENA BIT(1)
78#define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0)
79
80#define DEV_MAC_ADV_CHK_CFG 0x2c
81
82#define DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0)
83
84#define DEV_MAC_IFG_CFG 0x30
85
86#define DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17)
87#define DEV_MAC_IFG_CFG_REDUCED_TX_IFG BIT(16)
88#define DEV_MAC_IFG_CFG_TX_IFG(x) (((x) << 8) & GENMASK(12, 8))
89#define DEV_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8)
90#define DEV_MAC_IFG_CFG_TX_IFG_X(x) (((x) & GENMASK(12, 8)) >> 8)
91#define DEV_MAC_IFG_CFG_RX_IFG2(x) (((x) << 4) & GENMASK(7, 4))
92#define DEV_MAC_IFG_CFG_RX_IFG2_M GENMASK(7, 4)
93#define DEV_MAC_IFG_CFG_RX_IFG2_X(x) (((x) & GENMASK(7, 4)) >> 4)
94#define DEV_MAC_IFG_CFG_RX_IFG1(x) ((x) & GENMASK(3, 0))
95#define DEV_MAC_IFG_CFG_RX_IFG1_M GENMASK(3, 0)
96
97#define DEV_MAC_HDX_CFG 0x34
98
99#define DEV_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26)
100#define DEV_MAC_HDX_CFG_OB_ENA BIT(25)
101#define DEV_MAC_HDX_CFG_WEXC_DIS BIT(24)
102#define DEV_MAC_HDX_CFG_SEED(x) (((x) << 16) & GENMASK(23, 16))
103#define DEV_MAC_HDX_CFG_SEED_M GENMASK(23, 16)
104#define DEV_MAC_HDX_CFG_SEED_X(x) (((x) & GENMASK(23, 16)) >> 16)
105#define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12)
106#define DEV_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8)
107#define DEV_MAC_HDX_CFG_LATE_COL_POS(x) ((x) & GENMASK(6, 0))
108#define DEV_MAC_HDX_CFG_LATE_COL_POS_M GENMASK(6, 0)
109
110#define DEV_MAC_DBG_CFG 0x38
111
112#define DEV_MAC_DBG_CFG_TBI_MODE BIT(4)
113#define DEV_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA BIT(0)
114
115#define DEV_MAC_FC_MAC_LOW_CFG 0x3c
116
117#define DEV_MAC_FC_MAC_HIGH_CFG 0x40
118
119#define DEV_MAC_STICKY 0x44
120
121#define DEV_MAC_STICKY_RX_IPG_SHRINK_STICKY BIT(9)
122#define DEV_MAC_STICKY_RX_PREAM_SHRINK_STICKY BIT(8)
123#define DEV_MAC_STICKY_RX_CARRIER_EXT_STICKY BIT(7)
124#define DEV_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY BIT(6)
125#define DEV_MAC_STICKY_RX_JUNK_STICKY BIT(5)
126#define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY BIT(4)
127#define DEV_MAC_STICKY_TX_JAM_STICKY BIT(3)
128#define DEV_MAC_STICKY_TX_FIFO_OFLW_STICKY BIT(2)
129#define DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY BIT(1)
130#define DEV_MAC_STICKY_TX_ABORT_STICKY BIT(0)
131
132#define PCS1G_CFG 0x48
133
134#define PCS1G_CFG_LINK_STATUS_TYPE BIT(4)
135#define PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1)
136#define PCS1G_CFG_PCS_ENA BIT(0)
137
138#define PCS1G_MODE_CFG 0x4c
139
140#define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4)
141#define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
142
143#define PCS1G_SD_CFG 0x50
144
145#define PCS1G_SD_CFG_SD_SEL BIT(8)
146#define PCS1G_SD_CFG_SD_POL BIT(4)
147#define PCS1G_SD_CFG_SD_ENA BIT(0)
148
149#define PCS1G_ANEG_CFG 0x54
150
151#define PCS1G_ANEG_CFG_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16))
152#define PCS1G_ANEG_CFG_ADV_ABILITY_M GENMASK(31, 16)
153#define PCS1G_ANEG_CFG_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16)
154#define PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8)
155#define PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)
156#define PCS1G_ANEG_CFG_ANEG_ENA BIT(0)
157
158#define PCS1G_ANEG_NP_CFG 0x58
159
160#define PCS1G_ANEG_NP_CFG_NP_TX(x) (((x) << 16) & GENMASK(31, 16))
161#define PCS1G_ANEG_NP_CFG_NP_TX_M GENMASK(31, 16)
162#define PCS1G_ANEG_NP_CFG_NP_TX_X(x) (((x) & GENMASK(31, 16)) >> 16)
163#define PCS1G_ANEG_NP_CFG_NP_LOADED_ONE_SHOT BIT(0)
164
165#define PCS1G_LB_CFG 0x5c
166
167#define PCS1G_LB_CFG_RA_ENA BIT(4)
168#define PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1)
169#define PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0)
170
171#define PCS1G_DBG_CFG 0x60
172
173#define PCS1G_DBG_CFG_UDLT BIT(0)
174
175#define PCS1G_CDET_CFG 0x64
176
177#define PCS1G_CDET_CFG_CDET_ENA BIT(0)
178
179#define PCS1G_ANEG_STATUS 0x68
180
181#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16))
182#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M GENMASK(31, 16)
183#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16)
184#define PCS1G_ANEG_STATUS_PR BIT(4)
185#define PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3)
186#define PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0)
187
188#define PCS1G_ANEG_NP_STATUS 0x6c
189
190#define PCS1G_LINK_STATUS 0x70
191
192#define PCS1G_LINK_STATUS_DELAY_VAR(x) (((x) << 12) & GENMASK(15, 12))
193#define PCS1G_LINK_STATUS_DELAY_VAR_M GENMASK(15, 12)
194#define PCS1G_LINK_STATUS_DELAY_VAR_X(x) (((x) & GENMASK(15, 12)) >> 12)
195#define PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8)
196#define PCS1G_LINK_STATUS_LINK_STATUS BIT(4)
197#define PCS1G_LINK_STATUS_SYNC_STATUS BIT(0)
198
199#define PCS1G_LINK_DOWN_CNT 0x74
200
201#define PCS1G_STICKY 0x78
202
203#define PCS1G_STICKY_LINK_DOWN_STICKY BIT(4)
204#define PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0)
205
206#define PCS1G_DEBUG_STATUS 0x7c
207
208#define PCS1G_LPI_CFG 0x80
209
210#define PCS1G_LPI_CFG_QSGMII_MS_SEL BIT(20)
211#define PCS1G_LPI_CFG_RX_LPI_OUT_DIS BIT(17)
212#define PCS1G_LPI_CFG_LPI_TESTMODE BIT(16)
213#define PCS1G_LPI_CFG_LPI_RX_WTIM(x) (((x) << 4) & GENMASK(5, 4))
214#define PCS1G_LPI_CFG_LPI_RX_WTIM_M GENMASK(5, 4)
215#define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x) (((x) & GENMASK(5, 4)) >> 4)
216#define PCS1G_LPI_CFG_TX_ASSERT_LPIDLE BIT(0)
217
218#define PCS1G_LPI_WAKE_ERROR_CNT 0x84
219
220#define PCS1G_LPI_STATUS 0x88
221
222#define PCS1G_LPI_STATUS_RX_LPI_FAIL BIT(16)
223#define PCS1G_LPI_STATUS_RX_LPI_EVENT_STICKY BIT(12)
224#define PCS1G_LPI_STATUS_RX_QUIET BIT(9)
225#define PCS1G_LPI_STATUS_RX_LPI_MODE BIT(8)
226#define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY BIT(4)
227#define PCS1G_LPI_STATUS_TX_QUIET BIT(1)
228#define PCS1G_LPI_STATUS_TX_LPI_MODE BIT(0)
229
230#define PCS1G_TSTPAT_MODE_CFG 0x8c
231
232#define PCS1G_TSTPAT_STATUS 0x90
233
234#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x) (((x) << 8) & GENMASK(15, 8))
235#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M GENMASK(15, 8)
236#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x) (((x) & GENMASK(15, 8)) >> 8)
237#define PCS1G_TSTPAT_STATUS_JTP_ERR BIT(4)
238#define PCS1G_TSTPAT_STATUS_JTP_LOCK BIT(0)
239
240#define DEV_PCS_FX100_CFG 0x94
241
242#define DEV_PCS_FX100_CFG_SD_SEL BIT(26)
243#define DEV_PCS_FX100_CFG_SD_POL BIT(25)
244#define DEV_PCS_FX100_CFG_SD_ENA BIT(24)
245#define DEV_PCS_FX100_CFG_LOOPBACK_ENA BIT(20)
246#define DEV_PCS_FX100_CFG_SWAP_MII_ENA BIT(16)
247#define DEV_PCS_FX100_CFG_RXBITSEL(x) (((x) << 12) & GENMASK(15, 12))
248#define DEV_PCS_FX100_CFG_RXBITSEL_M GENMASK(15, 12)
249#define DEV_PCS_FX100_CFG_RXBITSEL_X(x) (((x) & GENMASK(15, 12)) >> 12)
250#define DEV_PCS_FX100_CFG_SIGDET_CFG(x) (((x) << 9) & GENMASK(10, 9))
251#define DEV_PCS_FX100_CFG_SIGDET_CFG_M GENMASK(10, 9)
252#define DEV_PCS_FX100_CFG_SIGDET_CFG_X(x) (((x) & GENMASK(10, 9)) >> 9)
253#define DEV_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8)
254#define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x) (((x) << 4) & GENMASK(7, 4))
255#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M GENMASK(7, 4)
256#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x) (((x) & GENMASK(7, 4)) >> 4)
257#define DEV_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3)
258#define DEV_PCS_FX100_CFG_FEFCHK_ENA BIT(2)
259#define DEV_PCS_FX100_CFG_FEFGEN_ENA BIT(1)
260#define DEV_PCS_FX100_CFG_PCS_ENA BIT(0)
261
262#define DEV_PCS_FX100_STATUS 0x98
263
264#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x) (((x) << 8) & GENMASK(11, 8))
265#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M GENMASK(11, 8)
266#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x) (((x) & GENMASK(11, 8)) >> 8)
267#define DEV_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7)
268#define DEV_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6)
269#define DEV_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5)
270#define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4)
271#define DEV_PCS_FX100_STATUS_FEF_STATUS BIT(2)
272#define DEV_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1)
273#define DEV_PCS_FX100_STATUS_SYNC_STATUS BIT(0)
274
275#endif
diff --git a/drivers/net/ethernet/mscc/ocelot_dev_gmii.h b/drivers/net/ethernet/mscc/ocelot_dev_gmii.h
new file mode 100644
index 000000000000..6aa40ea223a2
--- /dev/null
+++ b/drivers/net/ethernet/mscc/ocelot_dev_gmii.h
@@ -0,0 +1,154 @@
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_DEV_GMII_H_
9#define _MSCC_OCELOT_DEV_GMII_H_
10
11#define DEV_GMII_PORT_MODE_CLOCK_CFG 0x0
12
13#define DEV_GMII_PORT_MODE_CLOCK_CFG_MAC_TX_RST BIT(5)
14#define DEV_GMII_PORT_MODE_CLOCK_CFG_MAC_RX_RST BIT(4)
15#define DEV_GMII_PORT_MODE_CLOCK_CFG_PORT_RST BIT(3)
16#define DEV_GMII_PORT_MODE_CLOCK_CFG_PHY_RST BIT(2)
17#define DEV_GMII_PORT_MODE_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))
18#define DEV_GMII_PORT_MODE_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
19
20#define DEV_GMII_PORT_MODE_PORT_MISC 0x4
21
22#define DEV_GMII_PORT_MODE_PORT_MISC_MPLS_RX_ENA BIT(5)
23#define DEV_GMII_PORT_MODE_PORT_MISC_FWD_ERROR_ENA BIT(4)
24#define DEV_GMII_PORT_MODE_PORT_MISC_FWD_PAUSE_ENA BIT(3)
25#define DEV_GMII_PORT_MODE_PORT_MISC_FWD_CTRL_ENA BIT(2)
26#define DEV_GMII_PORT_MODE_PORT_MISC_GMII_LOOP_ENA BIT(1)
27#define DEV_GMII_PORT_MODE_PORT_MISC_DEV_LOOP_ENA BIT(0)
28
29#define DEV_GMII_PORT_MODE_EVENTS 0x8
30
31#define DEV_GMII_PORT_MODE_EEE_CFG 0xc
32
33#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_ENA BIT(22)
34#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))
35#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
36#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)
37#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
38#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
39#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
40#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))
41#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
42#define DEV_GMII_PORT_MODE_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) (((x) & GENMASK(7, 1)) >> 1)
43#define DEV_GMII_PORT_MODE_EEE_CFG_PORT_LPI BIT(0)
44
45#define DEV_GMII_PORT_MODE_RX_PATH_DELAY 0x10
46
47#define DEV_GMII_PORT_MODE_TX_PATH_DELAY 0x14
48
49#define DEV_GMII_PORT_MODE_PTP_PREDICT_CFG 0x18
50
51#define DEV_GMII_MAC_CFG_STATUS_MAC_ENA_CFG 0x1c
52
53#define DEV_GMII_MAC_CFG_STATUS_MAC_ENA_CFG_RX_ENA BIT(4)
54#define DEV_GMII_MAC_CFG_STATUS_MAC_ENA_CFG_TX_ENA BIT(0)
55
56#define DEV_GMII_MAC_CFG_STATUS_MAC_MODE_CFG 0x20
57
58#define DEV_GMII_MAC_CFG_STATUS_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8)
59#define DEV_GMII_MAC_CFG_STATUS_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4)
60#define DEV_GMII_MAC_CFG_STATUS_MAC_MODE_CFG_FDX_ENA BIT(0)
61
62#define DEV_GMII_MAC_CFG_STATUS_MAC_MAXLEN_CFG 0x24
63
64#define DEV_GMII_MAC_CFG_STATUS_MAC_TAGS_CFG 0x28
65
66#define DEV_GMII_MAC_CFG_STATUS_MAC_TAGS_CFG_TAG_ID(x) (((x) << 16) & GENMASK(31, 16))
67#define DEV_GMII_MAC_CFG_STATUS_MAC_TAGS_CFG_TAG_ID_M GENMASK(31, 16)
68#define DEV_GMII_MAC_CFG_STATUS_MAC_TAGS_CFG_TAG_ID_X(x) (((x) & GENMASK(31, 16)) >> 16)
69#define DEV_GMII_MAC_CFG_STATUS_MAC_TAGS_CFG_PB_ENA BIT(1)
70#define DEV_GMII_MAC_CFG_STATUS_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0)
71#define DEV_GMII_MAC_CFG_STATUS_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(2)
72
73#define DEV_GMII_MAC_CFG_STATUS_MAC_ADV_CHK_CFG 0x2c
74
75#define DEV_GMII_MAC_CFG_STATUS_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0)
76
77#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG 0x30
78
79#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17)
80#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_REDUCED_TX_IFG BIT(16)
81#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_TX_IFG(x) (((x) << 8) & GENMASK(12, 8))
82#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8)
83#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_TX_IFG_X(x) (((x) & GENMASK(12, 8)) >> 8)
84#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_RX_IFG2(x) (((x) << 4) & GENMASK(7, 4))
85#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_RX_IFG2_M GENMASK(7, 4)
86#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_RX_IFG2_X(x) (((x) & GENMASK(7, 4)) >> 4)
87#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_RX_IFG1(x) ((x) & GENMASK(3, 0))
88#define DEV_GMII_MAC_CFG_STATUS_MAC_IFG_CFG_RX_IFG1_M GENMASK(3, 0)
89
90#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG 0x34
91
92#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26)
93#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_OB_ENA BIT(25)
94#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_WEXC_DIS BIT(24)
95#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_SEED(x) (((x) << 16) & GENMASK(23, 16))
96#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_SEED_M GENMASK(23, 16)
97#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_SEED_X(x) (((x) & GENMASK(23, 16)) >> 16)
98#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_SEED_LOAD BIT(12)
99#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8)
100#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_LATE_COL_POS(x) ((x) & GENMASK(6, 0))
101#define DEV_GMII_MAC_CFG_STATUS_MAC_HDX_CFG_LATE_COL_POS_M GENMASK(6, 0)
102
103#define DEV_GMII_MAC_CFG_STATUS_MAC_DBG_CFG 0x38
104
105#define DEV_GMII_MAC_CFG_STATUS_MAC_DBG_CFG_TBI_MODE BIT(4)
106#define DEV_GMII_MAC_CFG_STATUS_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA BIT(0)
107
108#define DEV_GMII_MAC_CFG_STATUS_MAC_FC_MAC_LOW_CFG 0x3c
109
110#define DEV_GMII_MAC_CFG_STATUS_MAC_FC_MAC_HIGH_CFG 0x40
111
112#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY 0x44
113
114#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_RX_IPG_SHRINK_STICKY BIT(9)
115#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_RX_PREAM_SHRINK_STICKY BIT(8)
116#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_RX_CARRIER_EXT_STICKY BIT(7)
117#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY BIT(6)
118#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_RX_JUNK_STICKY BIT(5)
119#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_TX_RETRANSMIT_STICKY BIT(4)
120#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_TX_JAM_STICKY BIT(3)
121#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_TX_FIFO_OFLW_STICKY BIT(2)
122#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_TX_FRM_LEN_OVR_STICKY BIT(1)
123#define DEV_GMII_MAC_CFG_STATUS_MAC_STICKY_TX_ABORT_STICKY BIT(0)
124
125#define DEV_GMII_MM_CONFIG_ENABLE_CONFIG 0x48
126
127#define DEV_GMII_MM_CONFIG_ENABLE_CONFIG_MM_RX_ENA BIT(0)
128#define DEV_GMII_MM_CONFIG_ENABLE_CONFIG_MM_TX_ENA BIT(4)
129#define DEV_GMII_MM_CONFIG_ENABLE_CONFIG_KEEP_S_AFTER_D BIT(8)
130
131#define DEV_GMII_MM_CONFIG_VERIF_CONFIG 0x4c
132
133#define DEV_GMII_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_DIS BIT(0)
134#define DEV_GMII_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME(x) (((x) << 4) & GENMASK(11, 4))
135#define DEV_GMII_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_M GENMASK(11, 4)
136#define DEV_GMII_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_X(x) (((x) & GENMASK(11, 4)) >> 4)
137#define DEV_GMII_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS(x) (((x) << 12) & GENMASK(13, 12))
138#define DEV_GMII_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_M GENMASK(13, 12)
139#define DEV_GMII_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_X(x) (((x) & GENMASK(13, 12)) >> 12)
140
141#define DEV_GMII_MM_STATISTICS_MM_STATUS 0x50
142
143#define DEV_GMII_MM_STATISTICS_MM_STATUS_PRMPT_ACTIVE_STATUS BIT(0)
144#define DEV_GMII_MM_STATISTICS_MM_STATUS_PRMPT_ACTIVE_STICKY BIT(4)
145#define DEV_GMII_MM_STATISTICS_MM_STATUS_PRMPT_VERIFY_STATE(x) (((x) << 8) & GENMASK(10, 8))
146#define DEV_GMII_MM_STATISTICS_MM_STATUS_PRMPT_VERIFY_STATE_M GENMASK(10, 8)
147#define DEV_GMII_MM_STATISTICS_MM_STATUS_PRMPT_VERIFY_STATE_X(x) (((x) & GENMASK(10, 8)) >> 8)
148#define DEV_GMII_MM_STATISTICS_MM_STATUS_UNEXP_RX_PFRM_STICKY BIT(12)
149#define DEV_GMII_MM_STATISTICS_MM_STATUS_UNEXP_TX_PFRM_STICKY BIT(16)
150#define DEV_GMII_MM_STATISTICS_MM_STATUS_MM_RX_FRAME_STATUS BIT(20)
151#define DEV_GMII_MM_STATISTICS_MM_STATUS_MM_TX_FRAME_STATUS BIT(24)
152#define DEV_GMII_MM_STATISTICS_MM_STATUS_MM_TX_PRMPT_STATUS BIT(28)
153
154#endif
diff --git a/drivers/net/ethernet/mscc/ocelot_hsio.h b/drivers/net/ethernet/mscc/ocelot_hsio.h
new file mode 100644
index 000000000000..d93ddec3931b
--- /dev/null
+++ b/drivers/net/ethernet/mscc/ocelot_hsio.h
@@ -0,0 +1,785 @@
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_HSIO_H_
9#define _MSCC_OCELOT_HSIO_H_
10
11#define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
12#define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
13#define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
14#define HSIO_PLL5G_CFG0_DIV4 BIT(28)
15#define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
16#define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))
17#define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
18#define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)
19#define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))
20#define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
21#define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)
22#define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
23#define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
24#define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
25#define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
26#define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
27#define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
28#define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
29#define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6))
30#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M GENMASK(11, 6)
31#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x) (((x) & GENMASK(11, 6)) >> 6)
32#define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0))
33#define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M GENMASK(5, 0)
34
35#define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
36#define HSIO_PLL5G_CFG1_ROT_SPEED BIT(17)
37#define HSIO_PLL5G_CFG1_ROT_DIR BIT(16)
38#define HSIO_PLL5G_CFG1_READBACK_DATA_SEL BIT(15)
39#define HSIO_PLL5G_CFG1_RC_ENABLE BIT(14)
40#define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6))
41#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M GENMASK(13, 6)
42#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6)
43#define HSIO_PLL5G_CFG1_QUARTER_RATE BIT(5)
44#define HSIO_PLL5G_CFG1_PWD_TX BIT(4)
45#define HSIO_PLL5G_CFG1_PWD_RX BIT(3)
46#define HSIO_PLL5G_CFG1_OUT_OF_RANGE_RECAL_ENA BIT(2)
47#define HSIO_PLL5G_CFG1_HALF_RATE BIT(1)
48#define HSIO_PLL5G_CFG1_FORCE_SET_ENA BIT(0)
49
50#define HSIO_PLL5G_CFG2_ENA_TEST_MODE BIT(30)
51#define HSIO_PLL5G_CFG2_ENA_PFD_IN_FLIP BIT(29)
52#define HSIO_PLL5G_CFG2_ENA_VCO_NREF_TESTOUT BIT(28)
53#define HSIO_PLL5G_CFG2_ENA_FBTESTOUT BIT(27)
54#define HSIO_PLL5G_CFG2_ENA_RCPLL BIT(26)
55#define HSIO_PLL5G_CFG2_ENA_CP2 BIT(25)
56#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS1 BIT(24)
57#define HSIO_PLL5G_CFG2_AMPC_SEL(x) (((x) << 16) & GENMASK(23, 16))
58#define HSIO_PLL5G_CFG2_AMPC_SEL_M GENMASK(23, 16)
59#define HSIO_PLL5G_CFG2_AMPC_SEL_X(x) (((x) & GENMASK(23, 16)) >> 16)
60#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS BIT(15)
61#define HSIO_PLL5G_CFG2_PWD_AMPCTRL_N BIT(14)
62#define HSIO_PLL5G_CFG2_ENA_AMPCTRL BIT(13)
63#define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE BIT(12)
64#define HSIO_PLL5G_CFG2_FRC_FSM_POR BIT(11)
65#define HSIO_PLL5G_CFG2_DISABLE_FSM_POR BIT(10)
66#define HSIO_PLL5G_CFG2_GAIN_TEST(x) (((x) << 5) & GENMASK(9, 5))
67#define HSIO_PLL5G_CFG2_GAIN_TEST_M GENMASK(9, 5)
68#define HSIO_PLL5G_CFG2_GAIN_TEST_X(x) (((x) & GENMASK(9, 5)) >> 5)
69#define HSIO_PLL5G_CFG2_EN_RESET_OVERRUN BIT(4)
70#define HSIO_PLL5G_CFG2_EN_RESET_LIM_DET BIT(3)
71#define HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET BIT(2)
72#define HSIO_PLL5G_CFG2_DISABLE_FSM BIT(1)
73#define HSIO_PLL5G_CFG2_ENA_GAIN_TEST BIT(0)
74
75#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL(x) (((x) << 22) & GENMASK(23, 22))
76#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M GENMASK(23, 22)
77#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X(x) (((x) & GENMASK(23, 22)) >> 22)
78#define HSIO_PLL5G_CFG3_TESTOUT_SEL(x) (((x) << 19) & GENMASK(21, 19))
79#define HSIO_PLL5G_CFG3_TESTOUT_SEL_M GENMASK(21, 19)
80#define HSIO_PLL5G_CFG3_TESTOUT_SEL_X(x) (((x) & GENMASK(21, 19)) >> 19)
81#define HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT BIT(18)
82#define HSIO_PLL5G_CFG3_ENA_TEST_OUT BIT(17)
83#define HSIO_PLL5G_CFG3_SEL_FBDCLK BIT(16)
84#define HSIO_PLL5G_CFG3_SEL_CML_CMOS_PFD BIT(15)
85#define HSIO_PLL5G_CFG3_RST_FB_N BIT(14)
86#define HSIO_PLL5G_CFG3_FORCE_VCO_CONTRH BIT(13)
87#define HSIO_PLL5G_CFG3_FORCE_LO BIT(12)
88#define HSIO_PLL5G_CFG3_FORCE_HI BIT(11)
89#define HSIO_PLL5G_CFG3_FORCE_ENA BIT(10)
90#define HSIO_PLL5G_CFG3_FORCE_CP BIT(9)
91#define HSIO_PLL5G_CFG3_FBDIVSEL_TST_ENA BIT(8)
92#define HSIO_PLL5G_CFG3_FBDIVSEL(x) ((x) & GENMASK(7, 0))
93#define HSIO_PLL5G_CFG3_FBDIVSEL_M GENMASK(7, 0)
94
95#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))
96#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M GENMASK(23, 16)
97#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)
98#define HSIO_PLL5G_CFG4_IB_CTRL(x) ((x) & GENMASK(15, 0))
99#define HSIO_PLL5G_CFG4_IB_CTRL_M GENMASK(15, 0)
100
101#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))
102#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M GENMASK(23, 16)
103#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)
104#define HSIO_PLL5G_CFG5_OB_CTRL(x) ((x) & GENMASK(15, 0))
105#define HSIO_PLL5G_CFG5_OB_CTRL_M GENMASK(15, 0)
106
107#define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC BIT(23)
108#define HSIO_PLL5G_CFG6_REFCLK_SEL(x) (((x) << 20) & GENMASK(22, 20))
109#define HSIO_PLL5G_CFG6_REFCLK_SEL_M GENMASK(22, 20)
110#define HSIO_PLL5G_CFG6_REFCLK_SEL_X(x) (((x) & GENMASK(22, 20)) >> 20)
111#define HSIO_PLL5G_CFG6_REFCLK_SRC BIT(19)
112#define HSIO_PLL5G_CFG6_POR_DEL_SEL(x) (((x) << 16) & GENMASK(17, 16))
113#define HSIO_PLL5G_CFG6_POR_DEL_SEL_M GENMASK(17, 16)
114#define HSIO_PLL5G_CFG6_POR_DEL_SEL_X(x) (((x) & GENMASK(17, 16)) >> 16)
115#define HSIO_PLL5G_CFG6_DIV125REF_SEL(x) (((x) << 8) & GENMASK(15, 8))
116#define HSIO_PLL5G_CFG6_DIV125REF_SEL_M GENMASK(15, 8)
117#define HSIO_PLL5G_CFG6_DIV125REF_SEL_X(x) (((x) & GENMASK(15, 8)) >> 8)
118#define HSIO_PLL5G_CFG6_ENA_REFCLKC2 BIT(7)
119#define HSIO_PLL5G_CFG6_ENA_FBCLKC2 BIT(6)
120#define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x) ((x) & GENMASK(5, 0))
121#define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M GENMASK(5, 0)
122
123#define HSIO_PLL5G_STATUS0_RANGE_LIM BIT(12)
124#define HSIO_PLL5G_STATUS0_OUT_OF_RANGE_ERR BIT(11)
125#define HSIO_PLL5G_STATUS0_CALIBRATION_ERR BIT(10)
126#define HSIO_PLL5G_STATUS0_CALIBRATION_DONE BIT(9)
127#define HSIO_PLL5G_STATUS0_READBACK_DATA(x) (((x) << 1) & GENMASK(8, 1))
128#define HSIO_PLL5G_STATUS0_READBACK_DATA_M GENMASK(8, 1)
129#define HSIO_PLL5G_STATUS0_READBACK_DATA_X(x) (((x) & GENMASK(8, 1)) >> 1)
130#define HSIO_PLL5G_STATUS0_LOCK_STATUS BIT(0)
131
132#define HSIO_PLL5G_STATUS1_SIG_DEL(x) (((x) << 21) & GENMASK(28, 21))
133#define HSIO_PLL5G_STATUS1_SIG_DEL_M GENMASK(28, 21)
134#define HSIO_PLL5G_STATUS1_SIG_DEL_X(x) (((x) & GENMASK(28, 21)) >> 21)
135#define HSIO_PLL5G_STATUS1_GAIN_STAT(x) (((x) << 16) & GENMASK(20, 16))
136#define HSIO_PLL5G_STATUS1_GAIN_STAT_M GENMASK(20, 16)
137#define HSIO_PLL5G_STATUS1_GAIN_STAT_X(x) (((x) & GENMASK(20, 16)) >> 16)
138#define HSIO_PLL5G_STATUS1_FBCNT_DIF(x) (((x) << 4) & GENMASK(13, 4))
139#define HSIO_PLL5G_STATUS1_FBCNT_DIF_M GENMASK(13, 4)
140#define HSIO_PLL5G_STATUS1_FBCNT_DIF_X(x) (((x) & GENMASK(13, 4)) >> 4)
141#define HSIO_PLL5G_STATUS1_FSM_STAT(x) (((x) << 1) & GENMASK(3, 1))
142#define HSIO_PLL5G_STATUS1_FSM_STAT_M GENMASK(3, 1)
143#define HSIO_PLL5G_STATUS1_FSM_STAT_X(x) (((x) & GENMASK(3, 1)) >> 1)
144#define HSIO_PLL5G_STATUS1_FSM_LOCK BIT(0)
145
146#define HSIO_PLL5G_BIST_CFG0_PLLB_START_BIST BIT(31)
147#define HSIO_PLL5G_BIST_CFG0_PLLB_MEAS_MODE BIT(30)
148#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT(x) (((x) << 20) & GENMASK(23, 20))
149#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M GENMASK(23, 20)
150#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X(x) (((x) & GENMASK(23, 20)) >> 20)
151#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT(x) (((x) << 16) & GENMASK(19, 16))
152#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_M GENMASK(19, 16)
153#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_X(x) (((x) & GENMASK(19, 16)) >> 16)
154#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x) ((x) & GENMASK(15, 0))
155#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE_M GENMASK(15, 0)
156
157#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT(x) (((x) << 4) & GENMASK(7, 4))
158#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_M GENMASK(7, 4)
159#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_X(x) (((x) & GENMASK(7, 4)) >> 4)
160#define HSIO_PLL5G_BIST_STAT0_PLLB_BUSY BIT(2)
161#define HSIO_PLL5G_BIST_STAT0_PLLB_DONE_N BIT(1)
162#define HSIO_PLL5G_BIST_STAT0_PLLB_FAIL BIT(0)
163
164#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT(x) (((x) << 16) & GENMASK(31, 16))
165#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_M GENMASK(31, 16)
166#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_X(x) (((x) & GENMASK(31, 16)) >> 16)
167#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF(x) ((x) & GENMASK(15, 0))
168#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF_M GENMASK(15, 0)
169
170#define HSIO_RCOMP_CFG0_PWD_ENA BIT(13)
171#define HSIO_RCOMP_CFG0_RUN_CAL BIT(12)
172#define HSIO_RCOMP_CFG0_SPEED_SEL(x) (((x) << 10) & GENMASK(11, 10))
173#define HSIO_RCOMP_CFG0_SPEED_SEL_M GENMASK(11, 10)
174#define HSIO_RCOMP_CFG0_SPEED_SEL_X(x) (((x) & GENMASK(11, 10)) >> 10)
175#define HSIO_RCOMP_CFG0_MODE_SEL(x) (((x) << 8) & GENMASK(9, 8))
176#define HSIO_RCOMP_CFG0_MODE_SEL_M GENMASK(9, 8)
177#define HSIO_RCOMP_CFG0_MODE_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)
178#define HSIO_RCOMP_CFG0_FORCE_ENA BIT(4)
179#define HSIO_RCOMP_CFG0_RCOMP_VAL(x) ((x) & GENMASK(3, 0))
180#define HSIO_RCOMP_CFG0_RCOMP_VAL_M GENMASK(3, 0)
181
182#define HSIO_RCOMP_STATUS_BUSY BIT(12)
183#define HSIO_RCOMP_STATUS_DELTA_ALERT BIT(7)
184#define HSIO_RCOMP_STATUS_RCOMP(x) ((x) & GENMASK(3, 0))
185#define HSIO_RCOMP_STATUS_RCOMP_M GENMASK(3, 0)
186
187#define HSIO_SYNC_ETH_CFG_RSZ 0x4
188
189#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC(x) (((x) << 4) & GENMASK(7, 4))
190#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_M GENMASK(7, 4)
191#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_X(x) (((x) & GENMASK(7, 4)) >> 4)
192#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV(x) (((x) << 1) & GENMASK(3, 1))
193#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_M GENMASK(3, 1)
194#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_X(x) (((x) & GENMASK(3, 1)) >> 1)
195#define HSIO_SYNC_ETH_CFG_RECO_CLK_ENA BIT(0)
196
197#define HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA BIT(0)
198
199#define HSIO_S1G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13))
200#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13)
201#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)
202#define HSIO_S1G_DES_CFG_DES_CPMD_SEL(x) (((x) << 11) & GENMASK(12, 11))
203#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_M GENMASK(12, 11)
204#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(12, 11)) >> 11)
205#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 8) & GENMASK(10, 8))
206#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_M GENMASK(10, 8)
207#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(10, 8)) >> 8)
208#define HSIO_S1G_DES_CFG_DES_BW_ANA(x) (((x) << 5) & GENMASK(7, 5))
209#define HSIO_S1G_DES_CFG_DES_BW_ANA_M GENMASK(7, 5)
210#define HSIO_S1G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(7, 5)) >> 5)
211#define HSIO_S1G_DES_CFG_DES_SWAP_ANA BIT(4)
212#define HSIO_S1G_DES_CFG_DES_BW_HYST(x) (((x) << 1) & GENMASK(3, 1))
213#define HSIO_S1G_DES_CFG_DES_BW_HYST_M GENMASK(3, 1)
214#define HSIO_S1G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(3, 1)) >> 1)
215#define HSIO_S1G_DES_CFG_DES_SWAP_HYST BIT(0)
216
217#define HSIO_S1G_IB_CFG_IB_FX100_ENA BIT(27)
218#define HSIO_S1G_IB_CFG_ACJTAG_HYST(x) (((x) << 24) & GENMASK(26, 24))
219#define HSIO_S1G_IB_CFG_ACJTAG_HYST_M GENMASK(26, 24)
220#define HSIO_S1G_IB_CFG_ACJTAG_HYST_X(x) (((x) & GENMASK(26, 24)) >> 24)
221#define HSIO_S1G_IB_CFG_IB_DET_LEV(x) (((x) << 19) & GENMASK(21, 19))
222#define HSIO_S1G_IB_CFG_IB_DET_LEV_M GENMASK(21, 19)
223#define HSIO_S1G_IB_CFG_IB_DET_LEV_X(x) (((x) & GENMASK(21, 19)) >> 19)
224#define HSIO_S1G_IB_CFG_IB_HYST_LEV BIT(14)
225#define HSIO_S1G_IB_CFG_IB_ENA_CMV_TERM BIT(13)
226#define HSIO_S1G_IB_CFG_IB_ENA_DC_COUPLING BIT(12)
227#define HSIO_S1G_IB_CFG_IB_ENA_DETLEV BIT(11)
228#define HSIO_S1G_IB_CFG_IB_ENA_HYST BIT(10)
229#define HSIO_S1G_IB_CFG_IB_ENA_OFFSET_COMP BIT(9)
230#define HSIO_S1G_IB_CFG_IB_EQ_GAIN(x) (((x) << 6) & GENMASK(8, 6))
231#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_M GENMASK(8, 6)
232#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_X(x) (((x) & GENMASK(8, 6)) >> 6)
233#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ(x) (((x) << 4) & GENMASK(5, 4))
234#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_M GENMASK(5, 4)
235#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_X(x) (((x) & GENMASK(5, 4)) >> 4)
236#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
237#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL_M GENMASK(3, 0)
238
239#define HSIO_S1G_OB_CFG_OB_SLP(x) (((x) << 17) & GENMASK(18, 17))
240#define HSIO_S1G_OB_CFG_OB_SLP_M GENMASK(18, 17)
241#define HSIO_S1G_OB_CFG_OB_SLP_X(x) (((x) & GENMASK(18, 17)) >> 17)
242#define HSIO_S1G_OB_CFG_OB_AMP_CTRL(x) (((x) << 13) & GENMASK(16, 13))
243#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_M GENMASK(16, 13)
244#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)
245#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL(x) (((x) << 10) & GENMASK(12, 10))
246#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_M GENMASK(12, 10)
247#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10)
248#define HSIO_S1G_OB_CFG_OB_DIS_VCM_CTRL BIT(9)
249#define HSIO_S1G_OB_CFG_OB_EN_MEAS_VREG BIT(8)
250#define HSIO_S1G_OB_CFG_OB_VCM_CTRL(x) (((x) << 4) & GENMASK(7, 4))
251#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_M GENMASK(7, 4)
252#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_X(x) (((x) & GENMASK(7, 4)) >> 4)
253#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
254#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0)
255
256#define HSIO_S1G_SER_CFG_SER_IDLE BIT(9)
257#define HSIO_S1G_SER_CFG_SER_DEEMPH BIT(8)
258#define HSIO_S1G_SER_CFG_SER_CPMD_SEL BIT(7)
259#define HSIO_S1G_SER_CFG_SER_SWAP_CPMD BIT(6)
260#define HSIO_S1G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4))
261#define HSIO_S1G_SER_CFG_SER_ALISEL_M GENMASK(5, 4)
262#define HSIO_S1G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4)
263#define HSIO_S1G_SER_CFG_SER_ENHYS BIT(3)
264#define HSIO_S1G_SER_CFG_SER_BIG_WIN BIT(2)
265#define HSIO_S1G_SER_CFG_SER_EN_WIN BIT(1)
266#define HSIO_S1G_SER_CFG_SER_ENALI BIT(0)
267
268#define HSIO_S1G_COMMON_CFG_SYS_RST BIT(31)
269#define HSIO_S1G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(21)
270#define HSIO_S1G_COMMON_CFG_ENA_LANE BIT(18)
271#define HSIO_S1G_COMMON_CFG_PWD_RX BIT(17)
272#define HSIO_S1G_COMMON_CFG_PWD_TX BIT(16)
273#define HSIO_S1G_COMMON_CFG_LANE_CTRL(x) (((x) << 13) & GENMASK(15, 13))
274#define HSIO_S1G_COMMON_CFG_LANE_CTRL_M GENMASK(15, 13)
275#define HSIO_S1G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(15, 13)) >> 13)
276#define HSIO_S1G_COMMON_CFG_ENA_DIRECT BIT(12)
277#define HSIO_S1G_COMMON_CFG_ENA_ELOOP BIT(11)
278#define HSIO_S1G_COMMON_CFG_ENA_FLOOP BIT(10)
279#define HSIO_S1G_COMMON_CFG_ENA_ILOOP BIT(9)
280#define HSIO_S1G_COMMON_CFG_ENA_PLOOP BIT(8)
281#define HSIO_S1G_COMMON_CFG_HRATE BIT(7)
282#define HSIO_S1G_COMMON_CFG_IF_MODE BIT(0)
283
284#define HSIO_S1G_PLL_CFG_PLL_ENA_FB_DIV2 BIT(22)
285#define HSIO_S1G_PLL_CFG_PLL_ENA_RC_DIV2 BIT(21)
286#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 8) & GENMASK(15, 8))
287#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(15, 8)
288#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(15, 8)) >> 8)
289#define HSIO_S1G_PLL_CFG_PLL_FSM_ENA BIT(7)
290#define HSIO_S1G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(6)
291#define HSIO_S1G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(5)
292#define HSIO_S1G_PLL_CFG_PLL_RB_DATA_SEL BIT(3)
293
294#define HSIO_S1G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(12)
295#define HSIO_S1G_PLL_STATUS_PLL_CAL_ERR BIT(11)
296#define HSIO_S1G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(10)
297#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0))
298#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0)
299
300#define HSIO_S1G_DFT_CFG0_LAZYBIT BIT(31)
301#define HSIO_S1G_DFT_CFG0_INV_DIS BIT(23)
302#define HSIO_S1G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20))
303#define HSIO_S1G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20)
304#define HSIO_S1G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20)
305#define HSIO_S1G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16))
306#define HSIO_S1G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16)
307#define HSIO_S1G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16)
308#define HSIO_S1G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4)
309#define HSIO_S1G_DFT_CFG0_RX_PDSENS_ENA BIT(3)
310#define HSIO_S1G_DFT_CFG0_RX_DFT_ENA BIT(2)
311#define HSIO_S1G_DFT_CFG0_TX_DFT_ENA BIT(0)
312
313#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
314#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8)
315#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
316#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
317#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4)
318#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
319#define HSIO_S1G_DFT_CFG1_TX_JI_ENA BIT(3)
320#define HSIO_S1G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2)
321#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_DIR BIT(1)
322#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
323
324#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
325#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8)
326#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
327#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
328#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4)
329#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
330#define HSIO_S1G_DFT_CFG2_RX_JI_ENA BIT(3)
331#define HSIO_S1G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2)
332#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_DIR BIT(1)
333#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
334
335#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20)
336#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(17, 16))
337#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(17, 16)
338#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(17, 16)) >> 16)
339#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8))
340#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8)
341#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8)
342#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0))
343#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0)
344
345#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11))
346#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11)
347#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11)
348#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10)
349#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9)
350#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8)
351#define HSIO_S1G_MISC_CFG_RX_LPI_MODE_ENA BIT(5)
352#define HSIO_S1G_MISC_CFG_TX_LPI_MODE_ENA BIT(4)
353#define HSIO_S1G_MISC_CFG_RX_DATA_INV_ENA BIT(3)
354#define HSIO_S1G_MISC_CFG_TX_DATA_INV_ENA BIT(2)
355#define HSIO_S1G_MISC_CFG_LANE_RST BIT(0)
356
357#define HSIO_S1G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7)
358#define HSIO_S1G_DFT_STATUS_PLL_BIST_FAILED BIT(6)
359#define HSIO_S1G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5)
360#define HSIO_S1G_DFT_STATUS_BIST_ACTIVE BIT(3)
361#define HSIO_S1G_DFT_STATUS_BIST_NOSYNC BIT(2)
362#define HSIO_S1G_DFT_STATUS_BIST_COMPLETE_N BIT(1)
363#define HSIO_S1G_DFT_STATUS_BIST_ERROR BIT(0)
364
365#define HSIO_S1G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
366
367#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT BIT(31)
368#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT BIT(30)
369#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(x) ((x) & GENMASK(8, 0))
370#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR_M GENMASK(8, 0)
371
372#define HSIO_S6G_DIG_CFG_GP(x) (((x) << 16) & GENMASK(18, 16))
373#define HSIO_S6G_DIG_CFG_GP_M GENMASK(18, 16)
374#define HSIO_S6G_DIG_CFG_GP_X(x) (((x) & GENMASK(18, 16)) >> 16)
375#define HSIO_S6G_DIG_CFG_TX_BIT_DOUBLING_MODE_ENA BIT(7)
376#define HSIO_S6G_DIG_CFG_SIGDET_TESTMODE BIT(6)
377#define HSIO_S6G_DIG_CFG_SIGDET_AST(x) (((x) << 3) & GENMASK(5, 3))
378#define HSIO_S6G_DIG_CFG_SIGDET_AST_M GENMASK(5, 3)
379#define HSIO_S6G_DIG_CFG_SIGDET_AST_X(x) (((x) & GENMASK(5, 3)) >> 3)
380#define HSIO_S6G_DIG_CFG_SIGDET_DST(x) ((x) & GENMASK(2, 0))
381#define HSIO_S6G_DIG_CFG_SIGDET_DST_M GENMASK(2, 0)
382
383#define HSIO_S6G_DFT_CFG0_LAZYBIT BIT(31)
384#define HSIO_S6G_DFT_CFG0_INV_DIS BIT(23)
385#define HSIO_S6G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20))
386#define HSIO_S6G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20)
387#define HSIO_S6G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20)
388#define HSIO_S6G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16))
389#define HSIO_S6G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16)
390#define HSIO_S6G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16)
391#define HSIO_S6G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4)
392#define HSIO_S6G_DFT_CFG0_RX_PDSENS_ENA BIT(3)
393#define HSIO_S6G_DFT_CFG0_RX_DFT_ENA BIT(2)
394#define HSIO_S6G_DFT_CFG0_TX_DFT_ENA BIT(0)
395
396#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
397#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8)
398#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
399#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
400#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4)
401#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
402#define HSIO_S6G_DFT_CFG1_TX_JI_ENA BIT(3)
403#define HSIO_S6G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2)
404#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_DIR BIT(1)
405#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
406
407#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
408#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8)
409#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
410#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
411#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4)
412#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
413#define HSIO_S6G_DFT_CFG2_RX_JI_ENA BIT(3)
414#define HSIO_S6G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2)
415#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_DIR BIT(1)
416#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
417
418#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20)
419#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(19, 16))
420#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(19, 16)
421#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(19, 16)) >> 16)
422#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8))
423#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8)
424#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8)
425#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0))
426#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0)
427
428#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK(x) (((x) << 13) & GENMASK(14, 13))
429#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_M GENMASK(14, 13)
430#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_X(x) (((x) & GENMASK(14, 13)) >> 13)
431#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11))
432#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11)
433#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11)
434#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10)
435#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9)
436#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8)
437#define HSIO_S6G_MISC_CFG_RX_BUS_FLIP_ENA BIT(7)
438#define HSIO_S6G_MISC_CFG_TX_BUS_FLIP_ENA BIT(6)
439#define HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA BIT(5)
440#define HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA BIT(4)
441#define HSIO_S6G_MISC_CFG_RX_DATA_INV_ENA BIT(3)
442#define HSIO_S6G_MISC_CFG_TX_DATA_INV_ENA BIT(2)
443#define HSIO_S6G_MISC_CFG_LANE_RST BIT(0)
444
445#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))
446#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_M GENMASK(28, 23)
447#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)
448#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1(x) (((x) << 18) & GENMASK(22, 18))
449#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_M GENMASK(22, 18)
450#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_X(x) (((x) & GENMASK(22, 18)) >> 18)
451#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC(x) (((x) << 13) & GENMASK(17, 13))
452#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_M GENMASK(17, 13)
453#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_X(x) (((x) & GENMASK(17, 13)) >> 13)
454#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6))
455#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_M GENMASK(8, 6)
456#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6)
457#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV(x) ((x) & GENMASK(5, 0))
458#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV_M GENMASK(5, 0)
459
460#define HSIO_S6G_DFT_STATUS_PRBS_SYNC_STAT BIT(8)
461#define HSIO_S6G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7)
462#define HSIO_S6G_DFT_STATUS_PLL_BIST_FAILED BIT(6)
463#define HSIO_S6G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5)
464#define HSIO_S6G_DFT_STATUS_BIST_ACTIVE BIT(3)
465#define HSIO_S6G_DFT_STATUS_BIST_NOSYNC BIT(2)
466#define HSIO_S6G_DFT_STATUS_BIST_COMPLETE_N BIT(1)
467#define HSIO_S6G_DFT_STATUS_BIST_ERROR BIT(0)
468
469#define HSIO_S6G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
470
471#define HSIO_S6G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13))
472#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13)
473#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)
474#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 10) & GENMASK(12, 10))
475#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_M GENMASK(12, 10)
476#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10)
477#define HSIO_S6G_DES_CFG_DES_CPMD_SEL(x) (((x) << 8) & GENMASK(9, 8))
478#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_M GENMASK(9, 8)
479#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)
480#define HSIO_S6G_DES_CFG_DES_BW_HYST(x) (((x) << 5) & GENMASK(7, 5))
481#define HSIO_S6G_DES_CFG_DES_BW_HYST_M GENMASK(7, 5)
482#define HSIO_S6G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(7, 5)) >> 5)
483#define HSIO_S6G_DES_CFG_DES_SWAP_HYST BIT(4)
484#define HSIO_S6G_DES_CFG_DES_BW_ANA(x) (((x) << 1) & GENMASK(3, 1))
485#define HSIO_S6G_DES_CFG_DES_BW_ANA_M GENMASK(3, 1)
486#define HSIO_S6G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(3, 1)) >> 1)
487#define HSIO_S6G_DES_CFG_DES_SWAP_ANA BIT(0)
488
489#define HSIO_S6G_IB_CFG_IB_SOFSI(x) (((x) << 29) & GENMASK(30, 29))
490#define HSIO_S6G_IB_CFG_IB_SOFSI_M GENMASK(30, 29)
491#define HSIO_S6G_IB_CFG_IB_SOFSI_X(x) (((x) & GENMASK(30, 29)) >> 29)
492#define HSIO_S6G_IB_CFG_IB_VBULK_SEL BIT(28)
493#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ(x) (((x) << 24) & GENMASK(27, 24))
494#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_M GENMASK(27, 24)
495#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_X(x) (((x) & GENMASK(27, 24)) >> 24)
496#define HSIO_S6G_IB_CFG_IB_ICML_ADJ(x) (((x) << 20) & GENMASK(23, 20))
497#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_M GENMASK(23, 20)
498#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_X(x) (((x) & GENMASK(23, 20)) >> 20)
499#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL(x) (((x) << 18) & GENMASK(19, 18))
500#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_M GENMASK(19, 18)
501#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_X(x) (((x) & GENMASK(19, 18)) >> 18)
502#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(x) (((x) << 15) & GENMASK(17, 15))
503#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M GENMASK(17, 15)
504#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_X(x) (((x) & GENMASK(17, 15)) >> 15)
505#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP(x) (((x) << 13) & GENMASK(14, 13))
506#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_M GENMASK(14, 13)
507#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_X(x) (((x) & GENMASK(14, 13)) >> 13)
508#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID(x) (((x) << 11) & GENMASK(12, 11))
509#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_M GENMASK(12, 11)
510#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_X(x) (((x) & GENMASK(12, 11)) >> 11)
511#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP(x) (((x) << 9) & GENMASK(10, 9))
512#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_M GENMASK(10, 9)
513#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_X(x) (((x) & GENMASK(10, 9)) >> 9)
514#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(x) (((x) << 7) & GENMASK(8, 7))
515#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M GENMASK(8, 7)
516#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_X(x) (((x) & GENMASK(8, 7)) >> 7)
517#define HSIO_S6G_IB_CFG_IB_ANA_TEST_ENA BIT(6)
518#define HSIO_S6G_IB_CFG_IB_SIG_DET_ENA BIT(5)
519#define HSIO_S6G_IB_CFG_IB_CONCUR BIT(4)
520#define HSIO_S6G_IB_CFG_IB_CAL_ENA BIT(3)
521#define HSIO_S6G_IB_CFG_IB_SAM_ENA BIT(2)
522#define HSIO_S6G_IB_CFG_IB_EQZ_ENA BIT(1)
523#define HSIO_S6G_IB_CFG_IB_REG_ENA BIT(0)
524
525#define HSIO_S6G_IB_CFG1_IB_TJTAG(x) (((x) << 17) & GENMASK(21, 17))
526#define HSIO_S6G_IB_CFG1_IB_TJTAG_M GENMASK(21, 17)
527#define HSIO_S6G_IB_CFG1_IB_TJTAG_X(x) (((x) & GENMASK(21, 17)) >> 17)
528#define HSIO_S6G_IB_CFG1_IB_TSDET(x) (((x) << 12) & GENMASK(16, 12))
529#define HSIO_S6G_IB_CFG1_IB_TSDET_M GENMASK(16, 12)
530#define HSIO_S6G_IB_CFG1_IB_TSDET_X(x) (((x) & GENMASK(16, 12)) >> 12)
531#define HSIO_S6G_IB_CFG1_IB_SCALY(x) (((x) << 8) & GENMASK(11, 8))
532#define HSIO_S6G_IB_CFG1_IB_SCALY_M GENMASK(11, 8)
533#define HSIO_S6G_IB_CFG1_IB_SCALY_X(x) (((x) & GENMASK(11, 8)) >> 8)
534#define HSIO_S6G_IB_CFG1_IB_FILT_HP BIT(7)
535#define HSIO_S6G_IB_CFG1_IB_FILT_MID BIT(6)
536#define HSIO_S6G_IB_CFG1_IB_FILT_LP BIT(5)
537#define HSIO_S6G_IB_CFG1_IB_FILT_OFFSET BIT(4)
538#define HSIO_S6G_IB_CFG1_IB_FRC_HP BIT(3)
539#define HSIO_S6G_IB_CFG1_IB_FRC_MID BIT(2)
540#define HSIO_S6G_IB_CFG1_IB_FRC_LP BIT(1)
541#define HSIO_S6G_IB_CFG1_IB_FRC_OFFSET BIT(0)
542
543#define HSIO_S6G_IB_CFG2_IB_TINFV(x) (((x) << 27) & GENMASK(29, 27))
544#define HSIO_S6G_IB_CFG2_IB_TINFV_M GENMASK(29, 27)
545#define HSIO_S6G_IB_CFG2_IB_TINFV_X(x) (((x) & GENMASK(29, 27)) >> 27)
546#define HSIO_S6G_IB_CFG2_IB_OINFI(x) (((x) << 22) & GENMASK(26, 22))
547#define HSIO_S6G_IB_CFG2_IB_OINFI_M GENMASK(26, 22)
548#define HSIO_S6G_IB_CFG2_IB_OINFI_X(x) (((x) & GENMASK(26, 22)) >> 22)
549#define HSIO_S6G_IB_CFG2_IB_TAUX(x) (((x) << 19) & GENMASK(21, 19))
550#define HSIO_S6G_IB_CFG2_IB_TAUX_M GENMASK(21, 19)
551#define HSIO_S6G_IB_CFG2_IB_TAUX_X(x) (((x) & GENMASK(21, 19)) >> 19)
552#define HSIO_S6G_IB_CFG2_IB_OINFS(x) (((x) << 16) & GENMASK(18, 16))
553#define HSIO_S6G_IB_CFG2_IB_OINFS_M GENMASK(18, 16)
554#define HSIO_S6G_IB_CFG2_IB_OINFS_X(x) (((x) & GENMASK(18, 16)) >> 16)
555#define HSIO_S6G_IB_CFG2_IB_OCALS(x) (((x) << 10) & GENMASK(15, 10))
556#define HSIO_S6G_IB_CFG2_IB_OCALS_M GENMASK(15, 10)
557#define HSIO_S6G_IB_CFG2_IB_OCALS_X(x) (((x) & GENMASK(15, 10)) >> 10)
558#define HSIO_S6G_IB_CFG2_IB_TCALV(x) (((x) << 5) & GENMASK(9, 5))
559#define HSIO_S6G_IB_CFG2_IB_TCALV_M GENMASK(9, 5)
560#define HSIO_S6G_IB_CFG2_IB_TCALV_X(x) (((x) & GENMASK(9, 5)) >> 5)
561#define HSIO_S6G_IB_CFG2_IB_UMAX(x) (((x) << 3) & GENMASK(4, 3))
562#define HSIO_S6G_IB_CFG2_IB_UMAX_M GENMASK(4, 3)
563#define HSIO_S6G_IB_CFG2_IB_UMAX_X(x) (((x) & GENMASK(4, 3)) >> 3)
564#define HSIO_S6G_IB_CFG2_IB_UREG(x) ((x) & GENMASK(2, 0))
565#define HSIO_S6G_IB_CFG2_IB_UREG_M GENMASK(2, 0)
566
567#define HSIO_S6G_IB_CFG3_IB_INI_HP(x) (((x) << 18) & GENMASK(23, 18))
568#define HSIO_S6G_IB_CFG3_IB_INI_HP_M GENMASK(23, 18)
569#define HSIO_S6G_IB_CFG3_IB_INI_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
570#define HSIO_S6G_IB_CFG3_IB_INI_MID(x) (((x) << 12) & GENMASK(17, 12))
571#define HSIO_S6G_IB_CFG3_IB_INI_MID_M GENMASK(17, 12)
572#define HSIO_S6G_IB_CFG3_IB_INI_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)
573#define HSIO_S6G_IB_CFG3_IB_INI_LP(x) (((x) << 6) & GENMASK(11, 6))
574#define HSIO_S6G_IB_CFG3_IB_INI_LP_M GENMASK(11, 6)
575#define HSIO_S6G_IB_CFG3_IB_INI_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)
576#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET(x) ((x) & GENMASK(5, 0))
577#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M GENMASK(5, 0)
578
579#define HSIO_S6G_IB_CFG4_IB_MAX_HP(x) (((x) << 18) & GENMASK(23, 18))
580#define HSIO_S6G_IB_CFG4_IB_MAX_HP_M GENMASK(23, 18)
581#define HSIO_S6G_IB_CFG4_IB_MAX_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
582#define HSIO_S6G_IB_CFG4_IB_MAX_MID(x) (((x) << 12) & GENMASK(17, 12))
583#define HSIO_S6G_IB_CFG4_IB_MAX_MID_M GENMASK(17, 12)
584#define HSIO_S6G_IB_CFG4_IB_MAX_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)
585#define HSIO_S6G_IB_CFG4_IB_MAX_LP(x) (((x) << 6) & GENMASK(11, 6))
586#define HSIO_S6G_IB_CFG4_IB_MAX_LP_M GENMASK(11, 6)
587#define HSIO_S6G_IB_CFG4_IB_MAX_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)
588#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET(x) ((x) & GENMASK(5, 0))
589#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET_M GENMASK(5, 0)
590
591#define HSIO_S6G_IB_CFG5_IB_MIN_HP(x) (((x) << 18) & GENMASK(23, 18))
592#define HSIO_S6G_IB_CFG5_IB_MIN_HP_M GENMASK(23, 18)
593#define HSIO_S6G_IB_CFG5_IB_MIN_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
594#define HSIO_S6G_IB_CFG5_IB_MIN_MID(x) (((x) << 12) & GENMASK(17, 12))
595#define HSIO_S6G_IB_CFG5_IB_MIN_MID_M GENMASK(17, 12)
596#define HSIO_S6G_IB_CFG5_IB_MIN_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)
597#define HSIO_S6G_IB_CFG5_IB_MIN_LP(x) (((x) << 6) & GENMASK(11, 6))
598#define HSIO_S6G_IB_CFG5_IB_MIN_LP_M GENMASK(11, 6)
599#define HSIO_S6G_IB_CFG5_IB_MIN_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)
600#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET(x) ((x) & GENMASK(5, 0))
601#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET_M GENMASK(5, 0)
602
603#define HSIO_S6G_OB_CFG_OB_IDLE BIT(31)
604#define HSIO_S6G_OB_CFG_OB_ENA1V_MODE BIT(30)
605#define HSIO_S6G_OB_CFG_OB_POL BIT(29)
606#define HSIO_S6G_OB_CFG_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))
607#define HSIO_S6G_OB_CFG_OB_POST0_M GENMASK(28, 23)
608#define HSIO_S6G_OB_CFG_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)
609#define HSIO_S6G_OB_CFG_OB_PREC(x) (((x) << 18) & GENMASK(22, 18))
610#define HSIO_S6G_OB_CFG_OB_PREC_M GENMASK(22, 18)
611#define HSIO_S6G_OB_CFG_OB_PREC_X(x) (((x) & GENMASK(22, 18)) >> 18)
612#define HSIO_S6G_OB_CFG_OB_R_ADJ_MUX BIT(17)
613#define HSIO_S6G_OB_CFG_OB_R_ADJ_PDR BIT(16)
614#define HSIO_S6G_OB_CFG_OB_POST1(x) (((x) << 11) & GENMASK(15, 11))
615#define HSIO_S6G_OB_CFG_OB_POST1_M GENMASK(15, 11)
616#define HSIO_S6G_OB_CFG_OB_POST1_X(x) (((x) & GENMASK(15, 11)) >> 11)
617#define HSIO_S6G_OB_CFG_OB_R_COR BIT(10)
618#define HSIO_S6G_OB_CFG_OB_SEL_RCTRL BIT(9)
619#define HSIO_S6G_OB_CFG_OB_SR_H BIT(8)
620#define HSIO_S6G_OB_CFG_OB_SR(x) (((x) << 4) & GENMASK(7, 4))
621#define HSIO_S6G_OB_CFG_OB_SR_M GENMASK(7, 4)
622#define HSIO_S6G_OB_CFG_OB_SR_X(x) (((x) & GENMASK(7, 4)) >> 4)
623#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
624#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0)
625
626#define HSIO_S6G_OB_CFG1_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6))
627#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_M GENMASK(8, 6)
628#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6)
629#define HSIO_S6G_OB_CFG1_OB_LEV(x) ((x) & GENMASK(5, 0))
630#define HSIO_S6G_OB_CFG1_OB_LEV_M GENMASK(5, 0)
631
632#define HSIO_S6G_SER_CFG_SER_4TAP_ENA BIT(8)
633#define HSIO_S6G_SER_CFG_SER_CPMD_SEL BIT(7)
634#define HSIO_S6G_SER_CFG_SER_SWAP_CPMD BIT(6)
635#define HSIO_S6G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4))
636#define HSIO_S6G_SER_CFG_SER_ALISEL_M GENMASK(5, 4)
637#define HSIO_S6G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4)
638#define HSIO_S6G_SER_CFG_SER_ENHYS BIT(3)
639#define HSIO_S6G_SER_CFG_SER_BIG_WIN BIT(2)
640#define HSIO_S6G_SER_CFG_SER_EN_WIN BIT(1)
641#define HSIO_S6G_SER_CFG_SER_ENALI BIT(0)
642
643#define HSIO_S6G_COMMON_CFG_SYS_RST BIT(17)
644#define HSIO_S6G_COMMON_CFG_SE_DIV2_ENA BIT(16)
645#define HSIO_S6G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(15)
646#define HSIO_S6G_COMMON_CFG_ENA_LANE BIT(14)
647#define HSIO_S6G_COMMON_CFG_PWD_RX BIT(13)
648#define HSIO_S6G_COMMON_CFG_PWD_TX BIT(12)
649#define HSIO_S6G_COMMON_CFG_LANE_CTRL(x) (((x) << 9) & GENMASK(11, 9))
650#define HSIO_S6G_COMMON_CFG_LANE_CTRL_M GENMASK(11, 9)
651#define HSIO_S6G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(11, 9)) >> 9)
652#define HSIO_S6G_COMMON_CFG_ENA_DIRECT BIT(8)
653#define HSIO_S6G_COMMON_CFG_ENA_ELOOP BIT(7)
654#define HSIO_S6G_COMMON_CFG_ENA_FLOOP BIT(6)
655#define HSIO_S6G_COMMON_CFG_ENA_ILOOP BIT(5)
656#define HSIO_S6G_COMMON_CFG_ENA_PLOOP BIT(4)
657#define HSIO_S6G_COMMON_CFG_HRATE BIT(3)
658#define HSIO_S6G_COMMON_CFG_QRATE BIT(2)
659#define HSIO_S6G_COMMON_CFG_IF_MODE(x) ((x) & GENMASK(1, 0))
660#define HSIO_S6G_COMMON_CFG_IF_MODE_M GENMASK(1, 0)
661
662#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS(x) (((x) << 16) & GENMASK(17, 16))
663#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_M GENMASK(17, 16)
664#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_X(x) (((x) & GENMASK(17, 16)) >> 16)
665#define HSIO_S6G_PLL_CFG_PLL_DIV4 BIT(15)
666#define HSIO_S6G_PLL_CFG_PLL_ENA_ROT BIT(14)
667#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6))
668#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(13, 6)
669#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6)
670#define HSIO_S6G_PLL_CFG_PLL_FSM_ENA BIT(5)
671#define HSIO_S6G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(4)
672#define HSIO_S6G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(3)
673#define HSIO_S6G_PLL_CFG_PLL_RB_DATA_SEL BIT(2)
674#define HSIO_S6G_PLL_CFG_PLL_ROT_DIR BIT(1)
675#define HSIO_S6G_PLL_CFG_PLL_ROT_FRQ BIT(0)
676
677#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_N BIT(5)
678#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_P BIT(4)
679#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_CLK BIT(3)
680#define HSIO_S6G_ACJTAG_CFG_OB_DIRECT BIT(2)
681#define HSIO_S6G_ACJTAG_CFG_ACJTAG_ENA BIT(1)
682#define HSIO_S6G_ACJTAG_CFG_JTAG_CTRL_ENA BIT(0)
683
684#define HSIO_S6G_GP_CFG_GP_MSB(x) (((x) << 16) & GENMASK(31, 16))
685#define HSIO_S6G_GP_CFG_GP_MSB_M GENMASK(31, 16)
686#define HSIO_S6G_GP_CFG_GP_MSB_X(x) (((x) & GENMASK(31, 16)) >> 16)
687#define HSIO_S6G_GP_CFG_GP_LSB(x) ((x) & GENMASK(15, 0))
688#define HSIO_S6G_GP_CFG_GP_LSB_M GENMASK(15, 0)
689
690#define HSIO_S6G_IB_STATUS0_IB_CAL_DONE BIT(8)
691#define HSIO_S6G_IB_STATUS0_IB_HP_GAIN_ACT BIT(7)
692#define HSIO_S6G_IB_STATUS0_IB_MID_GAIN_ACT BIT(6)
693#define HSIO_S6G_IB_STATUS0_IB_LP_GAIN_ACT BIT(5)
694#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ACT BIT(4)
695#define HSIO_S6G_IB_STATUS0_IB_OFFSET_VLD BIT(3)
696#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ERR BIT(2)
697#define HSIO_S6G_IB_STATUS0_IB_OFFSDIR BIT(1)
698#define HSIO_S6G_IB_STATUS0_IB_SIG_DET BIT(0)
699
700#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT(x) (((x) << 18) & GENMASK(23, 18))
701#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_M GENMASK(23, 18)
702#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_X(x) (((x) & GENMASK(23, 18)) >> 18)
703#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT(x) (((x) << 12) & GENMASK(17, 12))
704#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_M GENMASK(17, 12)
705#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_X(x) (((x) & GENMASK(17, 12)) >> 12)
706#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT(x) (((x) << 6) & GENMASK(11, 6))
707#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_M GENMASK(11, 6)
708#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_X(x) (((x) & GENMASK(11, 6)) >> 6)
709#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT(x) ((x) & GENMASK(5, 0))
710#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT_M GENMASK(5, 0)
711
712#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_N BIT(2)
713#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_P BIT(1)
714#define HSIO_S6G_ACJTAG_STATUS_IB_DIRECT BIT(0)
715
716#define HSIO_S6G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(10)
717#define HSIO_S6G_PLL_STATUS_PLL_CAL_ERR BIT(9)
718#define HSIO_S6G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(8)
719#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0))
720#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0)
721
722#define HSIO_S6G_REVID_SERDES_REV(x) (((x) << 26) & GENMASK(31, 26))
723#define HSIO_S6G_REVID_SERDES_REV_M GENMASK(31, 26)
724#define HSIO_S6G_REVID_SERDES_REV_X(x) (((x) & GENMASK(31, 26)) >> 26)
725#define HSIO_S6G_REVID_RCPLL_REV(x) (((x) << 21) & GENMASK(25, 21))
726#define HSIO_S6G_REVID_RCPLL_REV_M GENMASK(25, 21)
727#define HSIO_S6G_REVID_RCPLL_REV_X(x) (((x) & GENMASK(25, 21)) >> 21)
728#define HSIO_S6G_REVID_SER_REV(x) (((x) << 16) & GENMASK(20, 16))
729#define HSIO_S6G_REVID_SER_REV_M GENMASK(20, 16)
730#define HSIO_S6G_REVID_SER_REV_X(x) (((x) & GENMASK(20, 16)) >> 16)
731#define HSIO_S6G_REVID_DES_REV(x) (((x) << 10) & GENMASK(15, 10))
732#define HSIO_S6G_REVID_DES_REV_M GENMASK(15, 10)
733#define HSIO_S6G_REVID_DES_REV_X(x) (((x) & GENMASK(15, 10)) >> 10)
734#define HSIO_S6G_REVID_OB_REV(x) (((x) << 5) & GENMASK(9, 5))
735#define HSIO_S6G_REVID_OB_REV_M GENMASK(9, 5)
736#define HSIO_S6G_REVID_OB_REV_X(x) (((x) & GENMASK(9, 5)) >> 5)
737#define HSIO_S6G_REVID_IB_REV(x) ((x) & GENMASK(4, 0))
738#define HSIO_S6G_REVID_IB_REV_M GENMASK(4, 0)
739
740#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT BIT(31)
741#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT BIT(30)
742#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(x) ((x) & GENMASK(24, 0))
743#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR_M GENMASK(24, 0)
744
745#define HSIO_HW_CFG_DEV2G5_10_MODE BIT(6)
746#define HSIO_HW_CFG_DEV1G_9_MODE BIT(5)
747#define HSIO_HW_CFG_DEV1G_6_MODE BIT(4)
748#define HSIO_HW_CFG_DEV1G_5_MODE BIT(3)
749#define HSIO_HW_CFG_DEV1G_4_MODE BIT(2)
750#define HSIO_HW_CFG_PCIE_ENA BIT(1)
751#define HSIO_HW_CFG_QSGMII_ENA BIT(0)
752
753#define HSIO_HW_QSGMII_CFG_SHYST_DIS BIT(3)
754#define HSIO_HW_QSGMII_CFG_E_DET_ENA BIT(2)
755#define HSIO_HW_QSGMII_CFG_USE_I1_ENA BIT(1)
756#define HSIO_HW_QSGMII_CFG_FLIP_LANES BIT(0)
757
758#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS(x) (((x) << 1) & GENMASK(6, 1))
759#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_M GENMASK(6, 1)
760#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_X(x) (((x) & GENMASK(6, 1)) >> 1)
761#define HSIO_HW_QSGMII_STAT_SYNC BIT(0)
762
763#define HSIO_CLK_CFG_CLKDIV_PHY(x) (((x) << 1) & GENMASK(8, 1))
764#define HSIO_CLK_CFG_CLKDIV_PHY_M GENMASK(8, 1)
765#define HSIO_CLK_CFG_CLKDIV_PHY_X(x) (((x) & GENMASK(8, 1)) >> 1)
766#define HSIO_CLK_CFG_CLKDIV_PHY_DIS BIT(0)
767
768#define HSIO_TEMP_SENSOR_CTRL_FORCE_TEMP_RD BIT(5)
769#define HSIO_TEMP_SENSOR_CTRL_FORCE_RUN BIT(4)
770#define HSIO_TEMP_SENSOR_CTRL_FORCE_NO_RST BIT(3)
771#define HSIO_TEMP_SENSOR_CTRL_FORCE_POWER_UP BIT(2)
772#define HSIO_TEMP_SENSOR_CTRL_FORCE_CLK BIT(1)
773#define HSIO_TEMP_SENSOR_CTRL_SAMPLE_ENA BIT(0)
774
775#define HSIO_TEMP_SENSOR_CFG_RUN_WID(x) (((x) << 8) & GENMASK(15, 8))
776#define HSIO_TEMP_SENSOR_CFG_RUN_WID_M GENMASK(15, 8)
777#define HSIO_TEMP_SENSOR_CFG_RUN_WID_X(x) (((x) & GENMASK(15, 8)) >> 8)
778#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER(x) ((x) & GENMASK(7, 0))
779#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER_M GENMASK(7, 0)
780
781#define HSIO_TEMP_SENSOR_STAT_TEMP_VALID BIT(8)
782#define HSIO_TEMP_SENSOR_STAT_TEMP(x) ((x) & GENMASK(7, 0))
783#define HSIO_TEMP_SENSOR_STAT_TEMP_M GENMASK(7, 0)
784
785#endif
diff --git a/drivers/net/ethernet/mscc/ocelot_io.c b/drivers/net/ethernet/mscc/ocelot_io.c
new file mode 100644
index 000000000000..c6db8ad31fdf
--- /dev/null
+++ b/drivers/net/ethernet/mscc/ocelot_io.c
@@ -0,0 +1,116 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <linux/io.h>
8#include <linux/kernel.h>
9#include <linux/platform_device.h>
10
11#include "ocelot.h"
12
13u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset)
14{
15 u16 target = reg >> TARGET_OFFSET;
16 u32 val;
17
18 WARN_ON(!target);
19
20 regmap_read(ocelot->targets[target],
21 ocelot->map[target][reg & REG_MASK] + offset, &val);
22 return val;
23}
24EXPORT_SYMBOL(__ocelot_read_ix);
25
26void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset)
27{
28 u16 target = reg >> TARGET_OFFSET;
29
30 WARN_ON(!target);
31
32 regmap_write(ocelot->targets[target],
33 ocelot->map[target][reg & REG_MASK] + offset, val);
34}
35EXPORT_SYMBOL(__ocelot_write_ix);
36
37void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
38 u32 offset)
39{
40 u16 target = reg >> TARGET_OFFSET;
41
42 WARN_ON(!target);
43
44 regmap_update_bits(ocelot->targets[target],
45 ocelot->map[target][reg & REG_MASK] + offset,
46 mask, val);
47}
48EXPORT_SYMBOL(__ocelot_rmw_ix);
49
50u32 ocelot_port_readl(struct ocelot_port *port, u32 reg)
51{
52 return readl(port->regs + reg);
53}
54EXPORT_SYMBOL(ocelot_port_readl);
55
56void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg)
57{
58 writel(val, port->regs + reg);
59}
60EXPORT_SYMBOL(ocelot_port_writel);
61
62int ocelot_regfields_init(struct ocelot *ocelot,
63 const struct reg_field *const regfields)
64{
65 unsigned int i;
66 u16 target;
67
68 for (i = 0; i < REGFIELD_MAX; i++) {
69 struct reg_field regfield = {};
70 u32 reg = regfields[i].reg;
71
72 if (!reg)
73 continue;
74
75 target = regfields[i].reg >> TARGET_OFFSET;
76
77 regfield.reg = ocelot->map[target][reg & REG_MASK];
78 regfield.lsb = regfields[i].lsb;
79 regfield.msb = regfields[i].msb;
80
81 ocelot->regfields[i] =
82 devm_regmap_field_alloc(ocelot->dev,
83 ocelot->targets[target],
84 regfield);
85
86 if (IS_ERR(ocelot->regfields[i]))
87 return PTR_ERR(ocelot->regfields[i]);
88 }
89
90 return 0;
91}
92EXPORT_SYMBOL(ocelot_regfields_init);
93
94static struct regmap_config ocelot_regmap_config = {
95 .reg_bits = 32,
96 .val_bits = 32,
97 .reg_stride = 4,
98};
99
100struct regmap *ocelot_io_platform_init(struct ocelot *ocelot,
101 struct platform_device *pdev,
102 const char *name)
103{
104 struct resource *res;
105 void __iomem *regs;
106
107 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
108 regs = devm_ioremap_resource(ocelot->dev, res);
109 if (IS_ERR(regs))
110 return ERR_CAST(regs);
111
112 ocelot_regmap_config.name = name;
113 return devm_regmap_init_mmio(ocelot->dev, regs,
114 &ocelot_regmap_config);
115}
116EXPORT_SYMBOL(ocelot_io_platform_init);
diff --git a/drivers/net/ethernet/mscc/ocelot_qs.h b/drivers/net/ethernet/mscc/ocelot_qs.h
new file mode 100644
index 000000000000..d18ae726c01d
--- /dev/null
+++ b/drivers/net/ethernet/mscc/ocelot_qs.h
@@ -0,0 +1,78 @@
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_QS_H_
9#define _MSCC_OCELOT_QS_H_
10
11/* TODO handle BE */
12#define XTR_EOF_0 0x00000080U
13#define XTR_EOF_1 0x01000080U
14#define XTR_EOF_2 0x02000080U
15#define XTR_EOF_3 0x03000080U
16#define XTR_PRUNED 0x04000080U
17#define XTR_ABORT 0x05000080U
18#define XTR_ESCAPE 0x06000080U
19#define XTR_NOT_READY 0x07000080U
20#define XTR_VALID_BYTES(x) (4 - (((x) >> 24) & 3))
21
22#define QS_XTR_GRP_CFG_RSZ 0x4
23
24#define QS_XTR_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2))
25#define QS_XTR_GRP_CFG_MODE_M GENMASK(3, 2)
26#define QS_XTR_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2)
27#define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
28#define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
29
30#define QS_XTR_RD_RSZ 0x4
31
32#define QS_XTR_FRM_PRUNING_RSZ 0x4
33
34#define QS_XTR_CFG_DP_WM(x) (((x) << 5) & GENMASK(7, 5))
35#define QS_XTR_CFG_DP_WM_M GENMASK(7, 5)
36#define QS_XTR_CFG_DP_WM_X(x) (((x) & GENMASK(7, 5)) >> 5)
37#define QS_XTR_CFG_SCH_WM(x) (((x) << 2) & GENMASK(4, 2))
38#define QS_XTR_CFG_SCH_WM_M GENMASK(4, 2)
39#define QS_XTR_CFG_SCH_WM_X(x) (((x) & GENMASK(4, 2)) >> 2)
40#define QS_XTR_CFG_OFLW_ERR_STICKY(x) ((x) & GENMASK(1, 0))
41#define QS_XTR_CFG_OFLW_ERR_STICKY_M GENMASK(1, 0)
42
43#define QS_INJ_GRP_CFG_RSZ 0x4
44
45#define QS_INJ_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2))
46#define QS_INJ_GRP_CFG_MODE_M GENMASK(3, 2)
47#define QS_INJ_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2)
48#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
49
50#define QS_INJ_WR_RSZ 0x4
51
52#define QS_INJ_CTRL_RSZ 0x4
53
54#define QS_INJ_CTRL_GAP_SIZE(x) (((x) << 21) & GENMASK(24, 21))
55#define QS_INJ_CTRL_GAP_SIZE_M GENMASK(24, 21)
56#define QS_INJ_CTRL_GAP_SIZE_X(x) (((x) & GENMASK(24, 21)) >> 21)
57#define QS_INJ_CTRL_ABORT BIT(20)
58#define QS_INJ_CTRL_EOF BIT(19)
59#define QS_INJ_CTRL_SOF BIT(18)
60#define QS_INJ_CTRL_VLD_BYTES(x) (((x) << 16) & GENMASK(17, 16))
61#define QS_INJ_CTRL_VLD_BYTES_M GENMASK(17, 16)
62#define QS_INJ_CTRL_VLD_BYTES_X(x) (((x) & GENMASK(17, 16)) >> 16)
63
64#define QS_INJ_STATUS_WMARK_REACHED(x) (((x) << 4) & GENMASK(5, 4))
65#define QS_INJ_STATUS_WMARK_REACHED_M GENMASK(5, 4)
66#define QS_INJ_STATUS_WMARK_REACHED_X(x) (((x) & GENMASK(5, 4)) >> 4)
67#define QS_INJ_STATUS_FIFO_RDY(x) (((x) << 2) & GENMASK(3, 2))
68#define QS_INJ_STATUS_FIFO_RDY_M GENMASK(3, 2)
69#define QS_INJ_STATUS_FIFO_RDY_X(x) (((x) & GENMASK(3, 2)) >> 2)
70#define QS_INJ_STATUS_INJ_IN_PROGRESS(x) ((x) & GENMASK(1, 0))
71#define QS_INJ_STATUS_INJ_IN_PROGRESS_M GENMASK(1, 0)
72
73#define QS_INJ_ERR_RSZ 0x4
74
75#define QS_INJ_ERR_ABORT_ERR_STICKY BIT(1)
76#define QS_INJ_ERR_WR_ERR_STICKY BIT(0)
77
78#endif
diff --git a/drivers/net/ethernet/mscc/ocelot_qsys.h b/drivers/net/ethernet/mscc/ocelot_qsys.h
new file mode 100644
index 000000000000..aa7267d5ca77
--- /dev/null
+++ b/drivers/net/ethernet/mscc/ocelot_qsys.h
@@ -0,0 +1,270 @@
1/*
2 * Microsemi Ocelot Switch driver
3 *
4 * License: Dual MIT/GPL
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_QSYS_H_
9#define _MSCC_OCELOT_QSYS_H_
10
11#define QSYS_PORT_MODE_RSZ 0x4
12
13#define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1)
14#define QSYS_PORT_MODE_DEQUEUE_LATE BIT(0)
15
16#define QSYS_SWITCH_PORT_MODE_RSZ 0x4
17
18#define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(14)
19#define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(x) (((x) << 11) & GENMASK(13, 11))
20#define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_M GENMASK(13, 11)
21#define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_X(x) (((x) & GENMASK(13, 11)) >> 11)
22#define QSYS_SWITCH_PORT_MODE_YEL_RSRVD BIT(10)
23#define QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE BIT(9)
24#define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA(x) (((x) << 1) & GENMASK(8, 1))
25#define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_M GENMASK(8, 1)
26#define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_X(x) (((x) & GENMASK(8, 1)) >> 1)
27#define QSYS_SWITCH_PORT_MODE_TX_PFC_MODE BIT(0)
28
29#define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE BIT(5)
30#define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4)
31#define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3)
32#define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE BIT(2)
33#define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE BIT(1)
34#define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS BIT(0)
35
36#define QSYS_EEE_CFG_RSZ 0x4
37
38#define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8))
39#define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
40#define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8)
41#define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0))
42#define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0)
43
44#define QSYS_SW_STATUS_RSZ 0x4
45
46#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8))
47#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)
48#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8)
49#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0))
50#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0)
51
52#define QSYS_QMAP_GSZ 0x4
53
54#define QSYS_QMAP_SE_BASE(x) (((x) << 5) & GENMASK(12, 5))
55#define QSYS_QMAP_SE_BASE_M GENMASK(12, 5)
56#define QSYS_QMAP_SE_BASE_X(x) (((x) & GENMASK(12, 5)) >> 5)
57#define QSYS_QMAP_SE_IDX_SEL(x) (((x) << 2) & GENMASK(4, 2))
58#define QSYS_QMAP_SE_IDX_SEL_M GENMASK(4, 2)
59#define QSYS_QMAP_SE_IDX_SEL_X(x) (((x) & GENMASK(4, 2)) >> 2)
60#define QSYS_QMAP_SE_INP_SEL(x) ((x) & GENMASK(1, 0))
61#define QSYS_QMAP_SE_INP_SEL_M GENMASK(1, 0)
62
63#define QSYS_ISDX_SGRP_GSZ 0x4
64
65#define QSYS_TIMED_FRAME_ENTRY_GSZ 0x4
66
67#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x) (((x) << 9) & GENMASK(18, 9))
68#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M GENMASK(18, 9)
69#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_X(x) (((x) & GENMASK(18, 9)) >> 9)
70#define QSYS_TFRM_MISC_TIMED_CANCEL_1SHOT BIT(8)
71#define QSYS_TFRM_MISC_TIMED_SLOT_MODE_MC BIT(7)
72#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT(x) ((x) & GENMASK(6, 0))
73#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M GENMASK(6, 0)
74
75#define QSYS_RED_PROFILE_RSZ 0x4
76
77#define QSYS_RED_PROFILE_WM_RED_LOW(x) (((x) << 8) & GENMASK(15, 8))
78#define QSYS_RED_PROFILE_WM_RED_LOW_M GENMASK(15, 8)
79#define QSYS_RED_PROFILE_WM_RED_LOW_X(x) (((x) & GENMASK(15, 8)) >> 8)
80#define QSYS_RED_PROFILE_WM_RED_HIGH(x) ((x) & GENMASK(7, 0))
81#define QSYS_RED_PROFILE_WM_RED_HIGH_M GENMASK(7, 0)
82
83#define QSYS_RES_CFG_GSZ 0x8
84
85#define QSYS_RES_STAT_GSZ 0x8
86
87#define QSYS_RES_STAT_INUSE(x) (((x) << 12) & GENMASK(23, 12))
88#define QSYS_RES_STAT_INUSE_M GENMASK(23, 12)
89#define QSYS_RES_STAT_INUSE_X(x) (((x) & GENMASK(23, 12)) >> 12)
90#define QSYS_RES_STAT_MAXUSE(x) ((x) & GENMASK(11, 0))
91#define QSYS_RES_STAT_MAXUSE_M GENMASK(11, 0)
92
93#define QSYS_EVENTS_CORE_EV_FDC(x) (((x) << 2) & GENMASK(4, 2))
94#define QSYS_EVENTS_CORE_EV_FDC_M GENMASK(4, 2)
95#define QSYS_EVENTS_CORE_EV_FDC_X(x) (((x) & GENMASK(4, 2)) >> 2)
96#define QSYS_EVENTS_CORE_EV_FRD(x) ((x) & GENMASK(1, 0))
97#define QSYS_EVENTS_CORE_EV_FRD_M GENMASK(1, 0)
98
99#define QSYS_QMAXSDU_CFG_0_RSZ 0x4
100
101#define QSYS_QMAXSDU_CFG_1_RSZ 0x4
102
103#define QSYS_QMAXSDU_CFG_2_RSZ 0x4
104
105#define QSYS_QMAXSDU_CFG_3_RSZ 0x4
106
107#define QSYS_QMAXSDU_CFG_4_RSZ 0x4
108
109#define QSYS_QMAXSDU_CFG_5_RSZ 0x4
110
111#define QSYS_QMAXSDU_CFG_6_RSZ 0x4
112
113#define QSYS_QMAXSDU_CFG_7_RSZ 0x4
114
115#define QSYS_PREEMPTION_CFG_RSZ 0x4
116
117#define QSYS_PREEMPTION_CFG_P_QUEUES(x) ((x) & GENMASK(7, 0))
118#define QSYS_PREEMPTION_CFG_P_QUEUES_M GENMASK(7, 0)
119#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE(x) (((x) << 8) & GENMASK(9, 8))
120#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_M GENMASK(9, 8)
121#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(x) (((x) & GENMASK(9, 8)) >> 8)
122#define QSYS_PREEMPTION_CFG_STRICT_IPG(x) (((x) << 12) & GENMASK(13, 12))
123#define QSYS_PREEMPTION_CFG_STRICT_IPG_M GENMASK(13, 12)
124#define QSYS_PREEMPTION_CFG_STRICT_IPG_X(x) (((x) & GENMASK(13, 12)) >> 12)
125#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE(x) (((x) << 16) & GENMASK(31, 16))
126#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_M GENMASK(31, 16)
127#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_X(x) (((x) & GENMASK(31, 16)) >> 16)
128
129#define QSYS_CIR_CFG_GSZ 0x80
130
131#define QSYS_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
132#define QSYS_CIR_CFG_CIR_RATE_M GENMASK(20, 6)
133#define QSYS_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
134#define QSYS_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0))
135#define QSYS_CIR_CFG_CIR_BURST_M GENMASK(5, 0)
136
137#define QSYS_EIR_CFG_GSZ 0x80
138
139#define QSYS_EIR_CFG_EIR_RATE(x) (((x) << 7) & GENMASK(21, 7))
140#define QSYS_EIR_CFG_EIR_RATE_M GENMASK(21, 7)
141#define QSYS_EIR_CFG_EIR_RATE_X(x) (((x) & GENMASK(21, 7)) >> 7)
142#define QSYS_EIR_CFG_EIR_BURST(x) (((x) << 1) & GENMASK(6, 1))
143#define QSYS_EIR_CFG_EIR_BURST_M GENMASK(6, 1)
144#define QSYS_EIR_CFG_EIR_BURST_X(x) (((x) & GENMASK(6, 1)) >> 1)
145#define QSYS_EIR_CFG_EIR_MARK_ENA BIT(0)
146
147#define QSYS_SE_CFG_GSZ 0x80
148
149#define QSYS_SE_CFG_SE_DWRR_CNT(x) (((x) << 6) & GENMASK(9, 6))
150#define QSYS_SE_CFG_SE_DWRR_CNT_M GENMASK(9, 6)
151#define QSYS_SE_CFG_SE_DWRR_CNT_X(x) (((x) & GENMASK(9, 6)) >> 6)
152#define QSYS_SE_CFG_SE_RR_ENA BIT(5)
153#define QSYS_SE_CFG_SE_AVB_ENA BIT(4)
154#define QSYS_SE_CFG_SE_FRM_MODE(x) (((x) << 2) & GENMASK(3, 2))
155#define QSYS_SE_CFG_SE_FRM_MODE_M GENMASK(3, 2)
156#define QSYS_SE_CFG_SE_FRM_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2)
157#define QSYS_SE_CFG_SE_EXC_ENA BIT(1)
158#define QSYS_SE_CFG_SE_EXC_FWD BIT(0)
159
160#define QSYS_SE_DWRR_CFG_GSZ 0x80
161#define QSYS_SE_DWRR_CFG_RSZ 0x4
162
163#define QSYS_SE_CONNECT_GSZ 0x80
164
165#define QSYS_SE_CONNECT_SE_OUTP_IDX(x) (((x) << 17) & GENMASK(24, 17))
166#define QSYS_SE_CONNECT_SE_OUTP_IDX_M GENMASK(24, 17)
167#define QSYS_SE_CONNECT_SE_OUTP_IDX_X(x) (((x) & GENMASK(24, 17)) >> 17)
168#define QSYS_SE_CONNECT_SE_INP_IDX(x) (((x) << 9) & GENMASK(16, 9))
169#define QSYS_SE_CONNECT_SE_INP_IDX_M GENMASK(16, 9)
170#define QSYS_SE_CONNECT_SE_INP_IDX_X(x) (((x) & GENMASK(16, 9)) >> 9)
171#define QSYS_SE_CONNECT_SE_OUTP_CON(x) (((x) << 5) & GENMASK(8, 5))
172#define QSYS_SE_CONNECT_SE_OUTP_CON_M GENMASK(8, 5)
173#define QSYS_SE_CONNECT_SE_OUTP_CON_X(x) (((x) & GENMASK(8, 5)) >> 5)
174#define QSYS_SE_CONNECT_SE_INP_CNT(x) (((x) << 1) & GENMASK(4, 1))
175#define QSYS_SE_CONNECT_SE_INP_CNT_M GENMASK(4, 1)
176#define QSYS_SE_CONNECT_SE_INP_CNT_X(x) (((x) & GENMASK(4, 1)) >> 1)
177#define QSYS_SE_CONNECT_SE_TERMINAL BIT(0)
178
179#define QSYS_SE_DLB_SENSE_GSZ 0x80
180
181#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO(x) (((x) << 11) & GENMASK(13, 11))
182#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_M GENMASK(13, 11)
183#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_X(x) (((x) & GENMASK(13, 11)) >> 11)
184#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT(x) (((x) << 7) & GENMASK(10, 7))
185#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_M GENMASK(10, 7)
186#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_X(x) (((x) & GENMASK(10, 7)) >> 7)
187#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT(x) (((x) << 3) & GENMASK(6, 3))
188#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_M GENMASK(6, 3)
189#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_X(x) (((x) & GENMASK(6, 3)) >> 3)
190#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(2)
191#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_ENA BIT(1)
192#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0)
193
194#define QSYS_CIR_STATE_GSZ 0x80
195
196#define QSYS_CIR_STATE_CIR_LVL(x) (((x) << 4) & GENMASK(25, 4))
197#define QSYS_CIR_STATE_CIR_LVL_M GENMASK(25, 4)
198#define QSYS_CIR_STATE_CIR_LVL_X(x) (((x) & GENMASK(25, 4)) >> 4)
199#define QSYS_CIR_STATE_SHP_TIME(x) ((x) & GENMASK(3, 0))
200#define QSYS_CIR_STATE_SHP_TIME_M GENMASK(3, 0)
201
202#define QSYS_EIR_STATE_GSZ 0x80
203
204#define QSYS_SE_STATE_GSZ 0x80
205
206#define QSYS_SE_STATE_SE_OUTP_LVL(x) (((x) << 1) & GENMASK(2, 1))
207#define QSYS_SE_STATE_SE_OUTP_LVL_M GENMASK(2, 1)
208#define QSYS_SE_STATE_SE_OUTP_LVL_X(x) (((x) & GENMASK(2, 1)) >> 1)
209#define QSYS_SE_STATE_SE_WAS_YEL BIT(0)
210
211#define QSYS_HSCH_MISC_CFG_SE_CONNECT_VLD BIT(8)
212#define QSYS_HSCH_MISC_CFG_FRM_ADJ(x) (((x) << 3) & GENMASK(7, 3))
213#define QSYS_HSCH_MISC_CFG_FRM_ADJ_M GENMASK(7, 3)
214#define QSYS_HSCH_MISC_CFG_FRM_ADJ_X(x) (((x) & GENMASK(7, 3)) >> 3)
215#define QSYS_HSCH_MISC_CFG_LEAK_DIS BIT(2)
216#define QSYS_HSCH_MISC_CFG_QSHP_EXC_ENA BIT(1)
217#define QSYS_HSCH_MISC_CFG_PFC_BYP_UPD BIT(0)
218
219#define QSYS_TAG_CONFIG_RSZ 0x4
220
221#define QSYS_TAG_CONFIG_ENABLE BIT(0)
222#define QSYS_TAG_CONFIG_LINK_SPEED(x) (((x) << 4) & GENMASK(5, 4))
223#define QSYS_TAG_CONFIG_LINK_SPEED_M GENMASK(5, 4)
224#define QSYS_TAG_CONFIG_LINK_SPEED_X(x) (((x) & GENMASK(5, 4)) >> 4)
225#define QSYS_TAG_CONFIG_INIT_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
226#define QSYS_TAG_CONFIG_INIT_GATE_STATE_M GENMASK(15, 8)
227#define QSYS_TAG_CONFIG_INIT_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
228#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(x) (((x) << 16) & GENMASK(23, 16))
229#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M GENMASK(23, 16)
230#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_X(x) (((x) & GENMASK(23, 16)) >> 16)
231
232#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(x) ((x) & GENMASK(7, 0))
233#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M GENMASK(7, 0)
234#define QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q BIT(8)
235#define QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE BIT(16)
236
237#define QSYS_PORT_MAX_SDU_RSZ 0x4
238
239#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
240#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
241#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16))
242#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_M GENMASK(31, 16)
243#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16)
244
245#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0))
246#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0)
247#define QSYS_GCL_CFG_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
248#define QSYS_GCL_CFG_REG_1_GATE_STATE_M GENMASK(15, 8)
249#define QSYS_GCL_CFG_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
250
251#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
252#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
253#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16))
254#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_M GENMASK(31, 16)
255#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16)
256
257#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
258#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0)
259#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE(x) (((x) << 16) & GENMASK(23, 16))
260#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_M GENMASK(23, 16)
261#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_X(x) (((x) & GENMASK(23, 16)) >> 16)
262#define QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING BIT(24)
263
264#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0))
265#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0)
266#define QSYS_GCL_STATUS_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
267#define QSYS_GCL_STATUS_REG_1_GATE_STATE_M GENMASK(15, 8)
268#define QSYS_GCL_STATUS_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
269
270#endif
diff --git a/drivers/net/ethernet/mscc/ocelot_regs.c b/drivers/net/ethernet/mscc/ocelot_regs.c
new file mode 100644
index 000000000000..e334b406c40c
--- /dev/null
+++ b/drivers/net/ethernet/mscc/ocelot_regs.c
@@ -0,0 +1,497 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include "ocelot.h"
8
9static const u32 ocelot_ana_regmap[] = {
10 REG(ANA_ADVLEARN, 0x009000),
11 REG(ANA_VLANMASK, 0x009004),
12 REG(ANA_PORT_B_DOMAIN, 0x009008),
13 REG(ANA_ANAGEFIL, 0x00900c),
14 REG(ANA_ANEVENTS, 0x009010),
15 REG(ANA_STORMLIMIT_BURST, 0x009014),
16 REG(ANA_STORMLIMIT_CFG, 0x009018),
17 REG(ANA_ISOLATED_PORTS, 0x009028),
18 REG(ANA_COMMUNITY_PORTS, 0x00902c),
19 REG(ANA_AUTOAGE, 0x009030),
20 REG(ANA_MACTOPTIONS, 0x009034),
21 REG(ANA_LEARNDISC, 0x009038),
22 REG(ANA_AGENCTRL, 0x00903c),
23 REG(ANA_MIRRORPORTS, 0x009040),
24 REG(ANA_EMIRRORPORTS, 0x009044),
25 REG(ANA_FLOODING, 0x009048),
26 REG(ANA_FLOODING_IPMC, 0x00904c),
27 REG(ANA_SFLOW_CFG, 0x009050),
28 REG(ANA_PORT_MODE, 0x009080),
29 REG(ANA_PGID_PGID, 0x008c00),
30 REG(ANA_TABLES_ANMOVED, 0x008b30),
31 REG(ANA_TABLES_MACHDATA, 0x008b34),
32 REG(ANA_TABLES_MACLDATA, 0x008b38),
33 REG(ANA_TABLES_MACACCESS, 0x008b3c),
34 REG(ANA_TABLES_MACTINDX, 0x008b40),
35 REG(ANA_TABLES_VLANACCESS, 0x008b44),
36 REG(ANA_TABLES_VLANTIDX, 0x008b48),
37 REG(ANA_TABLES_ISDXACCESS, 0x008b4c),
38 REG(ANA_TABLES_ISDXTIDX, 0x008b50),
39 REG(ANA_TABLES_ENTRYLIM, 0x008b00),
40 REG(ANA_TABLES_PTP_ID_HIGH, 0x008b54),
41 REG(ANA_TABLES_PTP_ID_LOW, 0x008b58),
42 REG(ANA_MSTI_STATE, 0x008e00),
43 REG(ANA_PORT_VLAN_CFG, 0x007000),
44 REG(ANA_PORT_DROP_CFG, 0x007004),
45 REG(ANA_PORT_QOS_CFG, 0x007008),
46 REG(ANA_PORT_VCAP_CFG, 0x00700c),
47 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007010),
48 REG(ANA_PORT_VCAP_S2_CFG, 0x00701c),
49 REG(ANA_PORT_PCP_DEI_MAP, 0x007020),
50 REG(ANA_PORT_CPU_FWD_CFG, 0x007060),
51 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007064),
52 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007068),
53 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00706c),
54 REG(ANA_PORT_PORT_CFG, 0x007070),
55 REG(ANA_PORT_POL_CFG, 0x007074),
56 REG(ANA_PORT_PTP_CFG, 0x007078),
57 REG(ANA_PORT_PTP_DLY1_CFG, 0x00707c),
58 REG(ANA_OAM_UPM_LM_CNT, 0x007c00),
59 REG(ANA_PORT_PTP_DLY2_CFG, 0x007080),
60 REG(ANA_PFC_PFC_CFG, 0x008800),
61 REG(ANA_PFC_PFC_TIMER, 0x008804),
62 REG(ANA_IPT_OAM_MEP_CFG, 0x008000),
63 REG(ANA_IPT_IPT, 0x008004),
64 REG(ANA_PPT_PPT, 0x008ac0),
65 REG(ANA_FID_MAP_FID_MAP, 0x000000),
66 REG(ANA_AGGR_CFG, 0x0090b4),
67 REG(ANA_CPUQ_CFG, 0x0090b8),
68 REG(ANA_CPUQ_CFG2, 0x0090bc),
69 REG(ANA_CPUQ_8021_CFG, 0x0090c0),
70 REG(ANA_DSCP_CFG, 0x009100),
71 REG(ANA_DSCP_REWR_CFG, 0x009200),
72 REG(ANA_VCAP_RNG_TYPE_CFG, 0x009240),
73 REG(ANA_VCAP_RNG_VAL_CFG, 0x009260),
74 REG(ANA_VRAP_CFG, 0x009280),
75 REG(ANA_VRAP_HDR_DATA, 0x009284),
76 REG(ANA_VRAP_HDR_MASK, 0x009288),
77 REG(ANA_DISCARD_CFG, 0x00928c),
78 REG(ANA_FID_CFG, 0x009290),
79 REG(ANA_POL_PIR_CFG, 0x004000),
80 REG(ANA_POL_CIR_CFG, 0x004004),
81 REG(ANA_POL_MODE_CFG, 0x004008),
82 REG(ANA_POL_PIR_STATE, 0x00400c),
83 REG(ANA_POL_CIR_STATE, 0x004010),
84 REG(ANA_POL_STATE, 0x004014),
85 REG(ANA_POL_FLOWC, 0x008b80),
86 REG(ANA_POL_HYST, 0x008bec),
87 REG(ANA_POL_MISC_CFG, 0x008bf0),
88};
89
90static const u32 ocelot_qs_regmap[] = {
91 REG(QS_XTR_GRP_CFG, 0x000000),
92 REG(QS_XTR_RD, 0x000008),
93 REG(QS_XTR_FRM_PRUNING, 0x000010),
94 REG(QS_XTR_FLUSH, 0x000018),
95 REG(QS_XTR_DATA_PRESENT, 0x00001c),
96 REG(QS_XTR_CFG, 0x000020),
97 REG(QS_INJ_GRP_CFG, 0x000024),
98 REG(QS_INJ_WR, 0x00002c),
99 REG(QS_INJ_CTRL, 0x000034),
100 REG(QS_INJ_STATUS, 0x00003c),
101 REG(QS_INJ_ERR, 0x000040),
102 REG(QS_INH_DBG, 0x000048),
103};
104
105static const u32 ocelot_hsio_regmap[] = {
106 REG(HSIO_PLL5G_CFG0, 0x000000),
107 REG(HSIO_PLL5G_CFG1, 0x000004),
108 REG(HSIO_PLL5G_CFG2, 0x000008),
109 REG(HSIO_PLL5G_CFG3, 0x00000c),
110 REG(HSIO_PLL5G_CFG4, 0x000010),
111 REG(HSIO_PLL5G_CFG5, 0x000014),
112 REG(HSIO_PLL5G_CFG6, 0x000018),
113 REG(HSIO_PLL5G_STATUS0, 0x00001c),
114 REG(HSIO_PLL5G_STATUS1, 0x000020),
115 REG(HSIO_PLL5G_BIST_CFG0, 0x000024),
116 REG(HSIO_PLL5G_BIST_CFG1, 0x000028),
117 REG(HSIO_PLL5G_BIST_CFG2, 0x00002c),
118 REG(HSIO_PLL5G_BIST_STAT0, 0x000030),
119 REG(HSIO_PLL5G_BIST_STAT1, 0x000034),
120 REG(HSIO_RCOMP_CFG0, 0x000038),
121 REG(HSIO_RCOMP_STATUS, 0x00003c),
122 REG(HSIO_SYNC_ETH_CFG, 0x000040),
123 REG(HSIO_SYNC_ETH_PLL_CFG, 0x000048),
124 REG(HSIO_S1G_DES_CFG, 0x00004c),
125 REG(HSIO_S1G_IB_CFG, 0x000050),
126 REG(HSIO_S1G_OB_CFG, 0x000054),
127 REG(HSIO_S1G_SER_CFG, 0x000058),
128 REG(HSIO_S1G_COMMON_CFG, 0x00005c),
129 REG(HSIO_S1G_PLL_CFG, 0x000060),
130 REG(HSIO_S1G_PLL_STATUS, 0x000064),
131 REG(HSIO_S1G_DFT_CFG0, 0x000068),
132 REG(HSIO_S1G_DFT_CFG1, 0x00006c),
133 REG(HSIO_S1G_DFT_CFG2, 0x000070),
134 REG(HSIO_S1G_TP_CFG, 0x000074),
135 REG(HSIO_S1G_RC_PLL_BIST_CFG, 0x000078),
136 REG(HSIO_S1G_MISC_CFG, 0x00007c),
137 REG(HSIO_S1G_DFT_STATUS, 0x000080),
138 REG(HSIO_S1G_MISC_STATUS, 0x000084),
139 REG(HSIO_MCB_S1G_ADDR_CFG, 0x000088),
140 REG(HSIO_S6G_DIG_CFG, 0x00008c),
141 REG(HSIO_S6G_DFT_CFG0, 0x000090),
142 REG(HSIO_S6G_DFT_CFG1, 0x000094),
143 REG(HSIO_S6G_DFT_CFG2, 0x000098),
144 REG(HSIO_S6G_TP_CFG0, 0x00009c),
145 REG(HSIO_S6G_TP_CFG1, 0x0000a0),
146 REG(HSIO_S6G_RC_PLL_BIST_CFG, 0x0000a4),
147 REG(HSIO_S6G_MISC_CFG, 0x0000a8),
148 REG(HSIO_S6G_OB_ANEG_CFG, 0x0000ac),
149 REG(HSIO_S6G_DFT_STATUS, 0x0000b0),
150 REG(HSIO_S6G_ERR_CNT, 0x0000b4),
151 REG(HSIO_S6G_MISC_STATUS, 0x0000b8),
152 REG(HSIO_S6G_DES_CFG, 0x0000bc),
153 REG(HSIO_S6G_IB_CFG, 0x0000c0),
154 REG(HSIO_S6G_IB_CFG1, 0x0000c4),
155 REG(HSIO_S6G_IB_CFG2, 0x0000c8),
156 REG(HSIO_S6G_IB_CFG3, 0x0000cc),
157 REG(HSIO_S6G_IB_CFG4, 0x0000d0),
158 REG(HSIO_S6G_IB_CFG5, 0x0000d4),
159 REG(HSIO_S6G_OB_CFG, 0x0000d8),
160 REG(HSIO_S6G_OB_CFG1, 0x0000dc),
161 REG(HSIO_S6G_SER_CFG, 0x0000e0),
162 REG(HSIO_S6G_COMMON_CFG, 0x0000e4),
163 REG(HSIO_S6G_PLL_CFG, 0x0000e8),
164 REG(HSIO_S6G_ACJTAG_CFG, 0x0000ec),
165 REG(HSIO_S6G_GP_CFG, 0x0000f0),
166 REG(HSIO_S6G_IB_STATUS0, 0x0000f4),
167 REG(HSIO_S6G_IB_STATUS1, 0x0000f8),
168 REG(HSIO_S6G_ACJTAG_STATUS, 0x0000fc),
169 REG(HSIO_S6G_PLL_STATUS, 0x000100),
170 REG(HSIO_S6G_REVID, 0x000104),
171 REG(HSIO_MCB_S6G_ADDR_CFG, 0x000108),
172 REG(HSIO_HW_CFG, 0x00010c),
173 REG(HSIO_HW_QSGMII_CFG, 0x000110),
174 REG(HSIO_HW_QSGMII_STAT, 0x000114),
175 REG(HSIO_CLK_CFG, 0x000118),
176 REG(HSIO_TEMP_SENSOR_CTRL, 0x00011c),
177 REG(HSIO_TEMP_SENSOR_CFG, 0x000120),
178 REG(HSIO_TEMP_SENSOR_STAT, 0x000124),
179};
180
181static const u32 ocelot_qsys_regmap[] = {
182 REG(QSYS_PORT_MODE, 0x011200),
183 REG(QSYS_SWITCH_PORT_MODE, 0x011234),
184 REG(QSYS_STAT_CNT_CFG, 0x011264),
185 REG(QSYS_EEE_CFG, 0x011268),
186 REG(QSYS_EEE_THRES, 0x011294),
187 REG(QSYS_IGR_NO_SHARING, 0x011298),
188 REG(QSYS_EGR_NO_SHARING, 0x01129c),
189 REG(QSYS_SW_STATUS, 0x0112a0),
190 REG(QSYS_EXT_CPU_CFG, 0x0112d0),
191 REG(QSYS_PAD_CFG, 0x0112d4),
192 REG(QSYS_CPU_GROUP_MAP, 0x0112d8),
193 REG(QSYS_QMAP, 0x0112dc),
194 REG(QSYS_ISDX_SGRP, 0x011400),
195 REG(QSYS_TIMED_FRAME_ENTRY, 0x014000),
196 REG(QSYS_TFRM_MISC, 0x011310),
197 REG(QSYS_TFRM_PORT_DLY, 0x011314),
198 REG(QSYS_TFRM_TIMER_CFG_1, 0x011318),
199 REG(QSYS_TFRM_TIMER_CFG_2, 0x01131c),
200 REG(QSYS_TFRM_TIMER_CFG_3, 0x011320),
201 REG(QSYS_TFRM_TIMER_CFG_4, 0x011324),
202 REG(QSYS_TFRM_TIMER_CFG_5, 0x011328),
203 REG(QSYS_TFRM_TIMER_CFG_6, 0x01132c),
204 REG(QSYS_TFRM_TIMER_CFG_7, 0x011330),
205 REG(QSYS_TFRM_TIMER_CFG_8, 0x011334),
206 REG(QSYS_RED_PROFILE, 0x011338),
207 REG(QSYS_RES_QOS_MODE, 0x011378),
208 REG(QSYS_RES_CFG, 0x012000),
209 REG(QSYS_RES_STAT, 0x012004),
210 REG(QSYS_EGR_DROP_MODE, 0x01137c),
211 REG(QSYS_EQ_CTRL, 0x011380),
212 REG(QSYS_EVENTS_CORE, 0x011384),
213 REG(QSYS_CIR_CFG, 0x000000),
214 REG(QSYS_EIR_CFG, 0x000004),
215 REG(QSYS_SE_CFG, 0x000008),
216 REG(QSYS_SE_DWRR_CFG, 0x00000c),
217 REG(QSYS_SE_CONNECT, 0x00003c),
218 REG(QSYS_SE_DLB_SENSE, 0x000040),
219 REG(QSYS_CIR_STATE, 0x000044),
220 REG(QSYS_EIR_STATE, 0x000048),
221 REG(QSYS_SE_STATE, 0x00004c),
222 REG(QSYS_HSCH_MISC_CFG, 0x011388),
223};
224
225static const u32 ocelot_rew_regmap[] = {
226 REG(REW_PORT_VLAN_CFG, 0x000000),
227 REG(REW_TAG_CFG, 0x000004),
228 REG(REW_PORT_CFG, 0x000008),
229 REG(REW_DSCP_CFG, 0x00000c),
230 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
231 REG(REW_PTP_CFG, 0x000050),
232 REG(REW_PTP_DLY1_CFG, 0x000054),
233 REG(REW_DSCP_REMAP_DP1_CFG, 0x000690),
234 REG(REW_DSCP_REMAP_CFG, 0x000790),
235 REG(REW_STAT_CFG, 0x000890),
236 REG(REW_PPT, 0x000680),
237};
238
239static const u32 ocelot_sys_regmap[] = {
240 REG(SYS_COUNT_RX_OCTETS, 0x000000),
241 REG(SYS_COUNT_RX_UNICAST, 0x000004),
242 REG(SYS_COUNT_RX_MULTICAST, 0x000008),
243 REG(SYS_COUNT_RX_BROADCAST, 0x00000c),
244 REG(SYS_COUNT_RX_SHORTS, 0x000010),
245 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
246 REG(SYS_COUNT_RX_JABBERS, 0x000018),
247 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c),
248 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020),
249 REG(SYS_COUNT_RX_64, 0x000024),
250 REG(SYS_COUNT_RX_65_127, 0x000028),
251 REG(SYS_COUNT_RX_128_255, 0x00002c),
252 REG(SYS_COUNT_RX_256_1023, 0x000030),
253 REG(SYS_COUNT_RX_1024_1526, 0x000034),
254 REG(SYS_COUNT_RX_1527_MAX, 0x000038),
255 REG(SYS_COUNT_RX_PAUSE, 0x00003c),
256 REG(SYS_COUNT_RX_CONTROL, 0x000040),
257 REG(SYS_COUNT_RX_LONGS, 0x000044),
258 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x000048),
259 REG(SYS_COUNT_TX_OCTETS, 0x000100),
260 REG(SYS_COUNT_TX_UNICAST, 0x000104),
261 REG(SYS_COUNT_TX_MULTICAST, 0x000108),
262 REG(SYS_COUNT_TX_BROADCAST, 0x00010c),
263 REG(SYS_COUNT_TX_COLLISION, 0x000110),
264 REG(SYS_COUNT_TX_DROPS, 0x000114),
265 REG(SYS_COUNT_TX_PAUSE, 0x000118),
266 REG(SYS_COUNT_TX_64, 0x00011c),
267 REG(SYS_COUNT_TX_65_127, 0x000120),
268 REG(SYS_COUNT_TX_128_511, 0x000124),
269 REG(SYS_COUNT_TX_512_1023, 0x000128),
270 REG(SYS_COUNT_TX_1024_1526, 0x00012c),
271 REG(SYS_COUNT_TX_1527_MAX, 0x000130),
272 REG(SYS_COUNT_TX_AGING, 0x000170),
273 REG(SYS_RESET_CFG, 0x000508),
274 REG(SYS_CMID, 0x00050c),
275 REG(SYS_VLAN_ETYPE_CFG, 0x000510),
276 REG(SYS_PORT_MODE, 0x000514),
277 REG(SYS_FRONT_PORT_MODE, 0x000548),
278 REG(SYS_FRM_AGING, 0x000574),
279 REG(SYS_STAT_CFG, 0x000578),
280 REG(SYS_SW_STATUS, 0x00057c),
281 REG(SYS_MISC_CFG, 0x0005ac),
282 REG(SYS_REW_MAC_HIGH_CFG, 0x0005b0),
283 REG(SYS_REW_MAC_LOW_CFG, 0x0005dc),
284 REG(SYS_CM_ADDR, 0x000500),
285 REG(SYS_CM_DATA, 0x000504),
286 REG(SYS_PAUSE_CFG, 0x000608),
287 REG(SYS_PAUSE_TOT_CFG, 0x000638),
288 REG(SYS_ATOP, 0x00063c),
289 REG(SYS_ATOP_TOT_CFG, 0x00066c),
290 REG(SYS_MAC_FC_CFG, 0x000670),
291 REG(SYS_MMGT, 0x00069c),
292 REG(SYS_MMGT_FAST, 0x0006a0),
293 REG(SYS_EVENTS_DIF, 0x0006a4),
294 REG(SYS_EVENTS_CORE, 0x0006b4),
295 REG(SYS_CNT, 0x000000),
296 REG(SYS_PTP_STATUS, 0x0006b8),
297 REG(SYS_PTP_TXSTAMP, 0x0006bc),
298 REG(SYS_PTP_NXT, 0x0006c0),
299 REG(SYS_PTP_CFG, 0x0006c4),
300};
301
302static const u32 *ocelot_regmap[] = {
303 [ANA] = ocelot_ana_regmap,
304 [QS] = ocelot_qs_regmap,
305 [HSIO] = ocelot_hsio_regmap,
306 [QSYS] = ocelot_qsys_regmap,
307 [REW] = ocelot_rew_regmap,
308 [SYS] = ocelot_sys_regmap,
309};
310
311static const struct reg_field ocelot_regfields[] = {
312 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11),
313 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10),
314 [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27),
315 [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26),
316 [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25),
317 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24),
318 [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23),
319 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22),
320 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21),
321 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20),
322 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19),
323 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
324 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17),
325 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16),
326 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15),
327 [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14),
328 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13),
329 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12),
330 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
331 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
332 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9),
333 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8),
334 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7),
335 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
336 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
337 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4),
338 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3),
339 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2),
340 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1),
341 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0),
342 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18),
343 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11),
344 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9),
345 [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20),
346 [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19),
347 [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7),
348 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3),
349 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0),
350 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2),
351 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1),
352 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0),
353};
354
355static const struct ocelot_stat_layout ocelot_stats_layout[] = {
356 { .name = "rx_octets", .offset = 0x00, },
357 { .name = "rx_unicast", .offset = 0x01, },
358 { .name = "rx_multicast", .offset = 0x02, },
359 { .name = "rx_broadcast", .offset = 0x03, },
360 { .name = "rx_shorts", .offset = 0x04, },
361 { .name = "rx_fragments", .offset = 0x05, },
362 { .name = "rx_jabbers", .offset = 0x06, },
363 { .name = "rx_crc_align_errs", .offset = 0x07, },
364 { .name = "rx_sym_errs", .offset = 0x08, },
365 { .name = "rx_frames_below_65_octets", .offset = 0x09, },
366 { .name = "rx_frames_65_to_127_octets", .offset = 0x0A, },
367 { .name = "rx_frames_128_to_255_octets", .offset = 0x0B, },
368 { .name = "rx_frames_256_to_511_octets", .offset = 0x0C, },
369 { .name = "rx_frames_512_to_1023_octets", .offset = 0x0D, },
370 { .name = "rx_frames_1024_to_1526_octets", .offset = 0x0E, },
371 { .name = "rx_frames_over_1526_octets", .offset = 0x0F, },
372 { .name = "rx_pause", .offset = 0x10, },
373 { .name = "rx_control", .offset = 0x11, },
374 { .name = "rx_longs", .offset = 0x12, },
375 { .name = "rx_classified_drops", .offset = 0x13, },
376 { .name = "rx_red_prio_0", .offset = 0x14, },
377 { .name = "rx_red_prio_1", .offset = 0x15, },
378 { .name = "rx_red_prio_2", .offset = 0x16, },
379 { .name = "rx_red_prio_3", .offset = 0x17, },
380 { .name = "rx_red_prio_4", .offset = 0x18, },
381 { .name = "rx_red_prio_5", .offset = 0x19, },
382 { .name = "rx_red_prio_6", .offset = 0x1A, },
383 { .name = "rx_red_prio_7", .offset = 0x1B, },
384 { .name = "rx_yellow_prio_0", .offset = 0x1C, },
385 { .name = "rx_yellow_prio_1", .offset = 0x1D, },
386 { .name = "rx_yellow_prio_2", .offset = 0x1E, },
387 { .name = "rx_yellow_prio_3", .offset = 0x1F, },
388 { .name = "rx_yellow_prio_4", .offset = 0x20, },
389 { .name = "rx_yellow_prio_5", .offset = 0x21, },
390 { .name = "rx_yellow_prio_6", .offset = 0x22, },
391 { .name = "rx_yellow_prio_7", .offset = 0x23, },
392 { .name = "rx_green_prio_0", .offset = 0x24, },
393 { .name = "rx_green_prio_1", .offset = 0x25, },
394 { .name = "rx_green_prio_2", .offset = 0x26, },
395 { .name = "rx_green_prio_3", .offset = 0x27, },
396 { .name = "rx_green_prio_4", .offset = 0x28, },
397 { .name = "rx_green_prio_5", .offset = 0x29, },
398 { .name = "rx_green_prio_6", .offset = 0x2A, },
399 { .name = "rx_green_prio_7", .offset = 0x2B, },
400 { .name = "tx_octets", .offset = 0x40, },
401 { .name = "tx_unicast", .offset = 0x41, },
402 { .name = "tx_multicast", .offset = 0x42, },
403 { .name = "tx_broadcast", .offset = 0x43, },
404 { .name = "tx_collision", .offset = 0x44, },
405 { .name = "tx_drops", .offset = 0x45, },
406 { .name = "tx_pause", .offset = 0x46, },
407 { .name = "tx_frames_below_65_octets", .offset = 0x47, },
408 { .name = "tx_frames_65_to_127_octets", .offset = 0x48, },
409 { .name = "tx_frames_128_255_octets", .offset = 0x49, },
410 { .name = "tx_frames_256_511_octets", .offset = 0x4A, },
411 { .name = "tx_frames_512_1023_octets", .offset = 0x4B, },
412 { .name = "tx_frames_1024_1526_octets", .offset = 0x4C, },
413 { .name = "tx_frames_over_1526_octets", .offset = 0x4D, },
414 { .name = "tx_yellow_prio_0", .offset = 0x4E, },
415 { .name = "tx_yellow_prio_1", .offset = 0x4F, },
416 { .name = "tx_yellow_prio_2", .offset = 0x50, },
417 { .name = "tx_yellow_prio_3", .offset = 0x51, },
418 { .name = "tx_yellow_prio_4", .offset = 0x52, },
419 { .name = "tx_yellow_prio_5", .offset = 0x53, },
420 { .name = "tx_yellow_prio_6", .offset = 0x54, },
421 { .name = "tx_yellow_prio_7", .offset = 0x55, },
422 { .name = "tx_green_prio_0", .offset = 0x56, },
423 { .name = "tx_green_prio_1", .offset = 0x57, },
424 { .name = "tx_green_prio_2", .offset = 0x58, },
425 { .name = "tx_green_prio_3", .offset = 0x59, },
426 { .name = "tx_green_prio_4", .offset = 0x5A, },
427 { .name = "tx_green_prio_5", .offset = 0x5B, },
428 { .name = "tx_green_prio_6", .offset = 0x5C, },
429 { .name = "tx_green_prio_7", .offset = 0x5D, },
430 { .name = "tx_aged", .offset = 0x5E, },
431 { .name = "drop_local", .offset = 0x80, },
432 { .name = "drop_tail", .offset = 0x81, },
433 { .name = "drop_yellow_prio_0", .offset = 0x82, },
434 { .name = "drop_yellow_prio_1", .offset = 0x83, },
435 { .name = "drop_yellow_prio_2", .offset = 0x84, },
436 { .name = "drop_yellow_prio_3", .offset = 0x85, },
437 { .name = "drop_yellow_prio_4", .offset = 0x86, },
438 { .name = "drop_yellow_prio_5", .offset = 0x87, },
439 { .name = "drop_yellow_prio_6", .offset = 0x88, },
440 { .name = "drop_yellow_prio_7", .offset = 0x89, },
441 { .name = "drop_green_prio_0", .offset = 0x8A, },
442 { .name = "drop_green_prio_1", .offset = 0x8B, },
443 { .name = "drop_green_prio_2", .offset = 0x8C, },
444 { .name = "drop_green_prio_3", .offset = 0x8D, },
445 { .name = "drop_green_prio_4", .offset = 0x8E, },
446 { .name = "drop_green_prio_5", .offset = 0x8F, },
447 { .name = "drop_green_prio_6", .offset = 0x90, },
448 { .name = "drop_green_prio_7", .offset = 0x91, },
449};
450
451static void ocelot_pll5_init(struct ocelot *ocelot)
452{
453 /* Configure PLL5. This will need a proper CCF driver
454 * The values are coming from the VTSS API for Ocelot
455 */
456 ocelot_write(ocelot, HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
457 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8), HSIO_PLL5G_CFG4);
458 ocelot_write(ocelot, HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
459 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) |
460 HSIO_PLL5G_CFG0_ENA_BIAS |
461 HSIO_PLL5G_CFG0_ENA_VCO_BUF |
462 HSIO_PLL5G_CFG0_ENA_CP1 |
463 HSIO_PLL5G_CFG0_SELCPI(2) |
464 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) |
465 HSIO_PLL5G_CFG0_SELBGV820(4) |
466 HSIO_PLL5G_CFG0_DIV4 |
467 HSIO_PLL5G_CFG0_ENA_CLKTREE |
468 HSIO_PLL5G_CFG0_ENA_LANE, HSIO_PLL5G_CFG0);
469 ocelot_write(ocelot, HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
470 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN |
471 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) |
472 HSIO_PLL5G_CFG2_ENA_AMPCTRL |
473 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N |
474 HSIO_PLL5G_CFG2_AMPC_SEL(0x10), HSIO_PLL5G_CFG2);
475}
476
477int ocelot_chip_init(struct ocelot *ocelot)
478{
479 int ret;
480
481 ocelot->map = ocelot_regmap;
482 ocelot->stats_layout = ocelot_stats_layout;
483 ocelot->num_stats = ARRAY_SIZE(ocelot_stats_layout);
484 ocelot->shared_queue_sz = 224 * 1024;
485
486 ret = ocelot_regfields_init(ocelot, ocelot_regfields);
487 if (ret)
488 return ret;
489
490 ocelot_pll5_init(ocelot);
491
492 eth_random_addr(ocelot->base_mac);
493 ocelot->base_mac[5] &= 0xf0;
494
495 return 0;
496}
497EXPORT_SYMBOL(ocelot_chip_init);
diff --git a/drivers/net/ethernet/mscc/ocelot_rew.h b/drivers/net/ethernet/mscc/ocelot_rew.h
new file mode 100644
index 000000000000..210914b7e20f
--- /dev/null
+++ b/drivers/net/ethernet/mscc/ocelot_rew.h
@@ -0,0 +1,81 @@
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_REW_H_
9#define _MSCC_OCELOT_REW_H_
10
11#define REW_PORT_VLAN_CFG_GSZ 0x80
12
13#define REW_PORT_VLAN_CFG_PORT_TPID(x) (((x) << 16) & GENMASK(31, 16))
14#define REW_PORT_VLAN_CFG_PORT_TPID_M GENMASK(31, 16)
15#define REW_PORT_VLAN_CFG_PORT_TPID_X(x) (((x) & GENMASK(31, 16)) >> 16)
16#define REW_PORT_VLAN_CFG_PORT_DEI BIT(15)
17#define REW_PORT_VLAN_CFG_PORT_PCP(x) (((x) << 12) & GENMASK(14, 12))
18#define REW_PORT_VLAN_CFG_PORT_PCP_M GENMASK(14, 12)
19#define REW_PORT_VLAN_CFG_PORT_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12)
20#define REW_PORT_VLAN_CFG_PORT_VID(x) ((x) & GENMASK(11, 0))
21#define REW_PORT_VLAN_CFG_PORT_VID_M GENMASK(11, 0)
22
23#define REW_TAG_CFG_GSZ 0x80
24
25#define REW_TAG_CFG_TAG_CFG(x) (((x) << 7) & GENMASK(8, 7))
26#define REW_TAG_CFG_TAG_CFG_M GENMASK(8, 7)
27#define REW_TAG_CFG_TAG_CFG_X(x) (((x) & GENMASK(8, 7)) >> 7)
28#define REW_TAG_CFG_TAG_TPID_CFG(x) (((x) << 5) & GENMASK(6, 5))
29#define REW_TAG_CFG_TAG_TPID_CFG_M GENMASK(6, 5)
30#define REW_TAG_CFG_TAG_TPID_CFG_X(x) (((x) & GENMASK(6, 5)) >> 5)
31#define REW_TAG_CFG_TAG_VID_CFG BIT(4)
32#define REW_TAG_CFG_TAG_PCP_CFG(x) (((x) << 2) & GENMASK(3, 2))
33#define REW_TAG_CFG_TAG_PCP_CFG_M GENMASK(3, 2)
34#define REW_TAG_CFG_TAG_PCP_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2)
35#define REW_TAG_CFG_TAG_DEI_CFG(x) ((x) & GENMASK(1, 0))
36#define REW_TAG_CFG_TAG_DEI_CFG_M GENMASK(1, 0)
37
38#define REW_PORT_CFG_GSZ 0x80
39
40#define REW_PORT_CFG_ES0_EN BIT(5)
41#define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG(x) (((x) << 3) & GENMASK(4, 3))
42#define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_M GENMASK(4, 3)
43#define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_X(x) (((x) & GENMASK(4, 3)) >> 3)
44#define REW_PORT_CFG_FCS_UPDATE_CPU_ENA BIT(2)
45#define REW_PORT_CFG_FLUSH_ENA BIT(1)
46#define REW_PORT_CFG_AGE_DIS BIT(0)
47
48#define REW_DSCP_CFG_GSZ 0x80
49
50#define REW_PCP_DEI_QOS_MAP_CFG_GSZ 0x80
51#define REW_PCP_DEI_QOS_MAP_CFG_RSZ 0x4
52
53#define REW_PCP_DEI_QOS_MAP_CFG_DEI_QOS_VAL BIT(3)
54#define REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL(x) ((x) & GENMASK(2, 0))
55#define REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL_M GENMASK(2, 0)
56
57#define REW_PTP_CFG_GSZ 0x80
58
59#define REW_PTP_CFG_PTP_BACKPLANE_MODE BIT(7)
60#define REW_PTP_CFG_GP_CFG_UNUSED(x) (((x) << 3) & GENMASK(6, 3))
61#define REW_PTP_CFG_GP_CFG_UNUSED_M GENMASK(6, 3)
62#define REW_PTP_CFG_GP_CFG_UNUSED_X(x) (((x) & GENMASK(6, 3)) >> 3)
63#define REW_PTP_CFG_PTP_1STEP_DIS BIT(2)
64#define REW_PTP_CFG_PTP_2STEP_DIS BIT(1)
65#define REW_PTP_CFG_PTP_UDP_KEEP BIT(0)
66
67#define REW_PTP_DLY1_CFG_GSZ 0x80
68
69#define REW_RED_TAG_CFG_GSZ 0x80
70
71#define REW_RED_TAG_CFG_RED_TAG_CFG BIT(0)
72
73#define REW_DSCP_REMAP_DP1_CFG_RSZ 0x4
74
75#define REW_DSCP_REMAP_CFG_RSZ 0x4
76
77#define REW_REW_STICKY_ES0_TAGB_PUSH_FAILED BIT(0)
78
79#define REW_PPT_RSZ 0x4
80
81#endif
diff --git a/drivers/net/ethernet/mscc/ocelot_sys.h b/drivers/net/ethernet/mscc/ocelot_sys.h
new file mode 100644
index 000000000000..16f91e172bcb
--- /dev/null
+++ b/drivers/net/ethernet/mscc/ocelot_sys.h
@@ -0,0 +1,144 @@
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_SYS_H_
9#define _MSCC_OCELOT_SYS_H_
10
11#define SYS_COUNT_RX_OCTETS_RSZ 0x4
12
13#define SYS_COUNT_TX_OCTETS_RSZ 0x4
14
15#define SYS_PORT_MODE_RSZ 0x4
16
17#define SYS_PORT_MODE_DATA_WO_TS(x) (((x) << 5) & GENMASK(6, 5))
18#define SYS_PORT_MODE_DATA_WO_TS_M GENMASK(6, 5)
19#define SYS_PORT_MODE_DATA_WO_TS_X(x) (((x) & GENMASK(6, 5)) >> 5)
20#define SYS_PORT_MODE_INCL_INJ_HDR(x) (((x) << 3) & GENMASK(4, 3))
21#define SYS_PORT_MODE_INCL_INJ_HDR_M GENMASK(4, 3)
22#define SYS_PORT_MODE_INCL_INJ_HDR_X(x) (((x) & GENMASK(4, 3)) >> 3)
23#define SYS_PORT_MODE_INCL_XTR_HDR(x) (((x) << 1) & GENMASK(2, 1))
24#define SYS_PORT_MODE_INCL_XTR_HDR_M GENMASK(2, 1)
25#define SYS_PORT_MODE_INCL_XTR_HDR_X(x) (((x) & GENMASK(2, 1)) >> 1)
26#define SYS_PORT_MODE_INJ_HDR_ERR BIT(0)
27
28#define SYS_FRONT_PORT_MODE_RSZ 0x4
29
30#define SYS_FRONT_PORT_MODE_HDX_MODE BIT(0)
31
32#define SYS_FRM_AGING_AGE_TX_ENA BIT(20)
33#define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0))
34#define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0)
35
36#define SYS_STAT_CFG_STAT_CLEAR_SHOT(x) (((x) << 10) & GENMASK(16, 10))
37#define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10)
38#define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x) (((x) & GENMASK(16, 10)) >> 10)
39#define SYS_STAT_CFG_STAT_VIEW(x) ((x) & GENMASK(9, 0))
40#define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0)
41
42#define SYS_SW_STATUS_RSZ 0x4
43
44#define SYS_SW_STATUS_PORT_RX_PAUSED BIT(0)
45
46#define SYS_MISC_CFG_PTP_RSRV_CLR BIT(1)
47#define SYS_MISC_CFG_PTP_DIS_NEG_RO BIT(0)
48
49#define SYS_REW_MAC_HIGH_CFG_RSZ 0x4
50
51#define SYS_REW_MAC_LOW_CFG_RSZ 0x4
52
53#define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x) (((x) << 6) & GENMASK(21, 6))
54#define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6)
55#define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x) (((x) & GENMASK(21, 6)) >> 6)
56#define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET(x) ((x) & GENMASK(5, 0))
57#define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET_M GENMASK(5, 0)
58
59#define SYS_PAUSE_CFG_RSZ 0x4
60
61#define SYS_PAUSE_CFG_PAUSE_START(x) (((x) << 10) & GENMASK(18, 10))
62#define SYS_PAUSE_CFG_PAUSE_START_M GENMASK(18, 10)
63#define SYS_PAUSE_CFG_PAUSE_START_X(x) (((x) & GENMASK(18, 10)) >> 10)
64#define SYS_PAUSE_CFG_PAUSE_STOP(x) (((x) << 1) & GENMASK(9, 1))
65#define SYS_PAUSE_CFG_PAUSE_STOP_M GENMASK(9, 1)
66#define SYS_PAUSE_CFG_PAUSE_STOP_X(x) (((x) & GENMASK(9, 1)) >> 1)
67#define SYS_PAUSE_CFG_PAUSE_ENA BIT(0)
68
69#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START(x) (((x) << 9) & GENMASK(17, 9))
70#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_M GENMASK(17, 9)
71#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_X(x) (((x) & GENMASK(17, 9)) >> 9)
72#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP(x) ((x) & GENMASK(8, 0))
73#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP_M GENMASK(8, 0)
74
75#define SYS_ATOP_RSZ 0x4
76
77#define SYS_MAC_FC_CFG_RSZ 0x4
78
79#define SYS_MAC_FC_CFG_FC_LINK_SPEED(x) (((x) << 26) & GENMASK(27, 26))
80#define SYS_MAC_FC_CFG_FC_LINK_SPEED_M GENMASK(27, 26)
81#define SYS_MAC_FC_CFG_FC_LINK_SPEED_X(x) (((x) & GENMASK(27, 26)) >> 26)
82#define SYS_MAC_FC_CFG_FC_LATENCY_CFG(x) (((x) << 20) & GENMASK(25, 20))
83#define SYS_MAC_FC_CFG_FC_LATENCY_CFG_M GENMASK(25, 20)
84#define SYS_MAC_FC_CFG_FC_LATENCY_CFG_X(x) (((x) & GENMASK(25, 20)) >> 20)
85#define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18)
86#define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17)
87#define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16)
88#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG(x) ((x) & GENMASK(15, 0))
89#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_M GENMASK(15, 0)
90
91#define SYS_MMGT_RELCNT(x) (((x) << 16) & GENMASK(31, 16))
92#define SYS_MMGT_RELCNT_M GENMASK(31, 16)
93#define SYS_MMGT_RELCNT_X(x) (((x) & GENMASK(31, 16)) >> 16)
94#define SYS_MMGT_FREECNT(x) ((x) & GENMASK(15, 0))
95#define SYS_MMGT_FREECNT_M GENMASK(15, 0)
96
97#define SYS_MMGT_FAST_FREEVLD(x) (((x) << 4) & GENMASK(7, 4))
98#define SYS_MMGT_FAST_FREEVLD_M GENMASK(7, 4)
99#define SYS_MMGT_FAST_FREEVLD_X(x) (((x) & GENMASK(7, 4)) >> 4)
100#define SYS_MMGT_FAST_RELVLD(x) ((x) & GENMASK(3, 0))
101#define SYS_MMGT_FAST_RELVLD_M GENMASK(3, 0)
102
103#define SYS_EVENTS_DIF_RSZ 0x4
104
105#define SYS_EVENTS_DIF_EV_DRX(x) (((x) << 6) & GENMASK(8, 6))
106#define SYS_EVENTS_DIF_EV_DRX_M GENMASK(8, 6)
107#define SYS_EVENTS_DIF_EV_DRX_X(x) (((x) & GENMASK(8, 6)) >> 6)
108#define SYS_EVENTS_DIF_EV_DTX(x) ((x) & GENMASK(5, 0))
109#define SYS_EVENTS_DIF_EV_DTX_M GENMASK(5, 0)
110
111#define SYS_EVENTS_CORE_EV_FWR BIT(2)
112#define SYS_EVENTS_CORE_EV_ANA(x) ((x) & GENMASK(1, 0))
113#define SYS_EVENTS_CORE_EV_ANA_M GENMASK(1, 0)
114
115#define SYS_CNT_GSZ 0x4
116
117#define SYS_PTP_STATUS_PTP_TXSTAMP_OAM BIT(29)
118#define SYS_PTP_STATUS_PTP_OVFL BIT(28)
119#define SYS_PTP_STATUS_PTP_MESS_VLD BIT(27)
120#define SYS_PTP_STATUS_PTP_MESS_ID(x) (((x) << 21) & GENMASK(26, 21))
121#define SYS_PTP_STATUS_PTP_MESS_ID_M GENMASK(26, 21)
122#define SYS_PTP_STATUS_PTP_MESS_ID_X(x) (((x) & GENMASK(26, 21)) >> 21)
123#define SYS_PTP_STATUS_PTP_MESS_TXPORT(x) (((x) << 16) & GENMASK(20, 16))
124#define SYS_PTP_STATUS_PTP_MESS_TXPORT_M GENMASK(20, 16)
125#define SYS_PTP_STATUS_PTP_MESS_TXPORT_X(x) (((x) & GENMASK(20, 16)) >> 16)
126#define SYS_PTP_STATUS_PTP_MESS_SEQ_ID(x) ((x) & GENMASK(15, 0))
127#define SYS_PTP_STATUS_PTP_MESS_SEQ_ID_M GENMASK(15, 0)
128
129#define SYS_PTP_TXSTAMP_PTP_TXSTAMP(x) ((x) & GENMASK(29, 0))
130#define SYS_PTP_TXSTAMP_PTP_TXSTAMP_M GENMASK(29, 0)
131#define SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC BIT(31)
132
133#define SYS_PTP_NXT_PTP_NXT BIT(0)
134
135#define SYS_PTP_CFG_PTP_STAMP_WID(x) (((x) << 2) & GENMASK(7, 2))
136#define SYS_PTP_CFG_PTP_STAMP_WID_M GENMASK(7, 2)
137#define SYS_PTP_CFG_PTP_STAMP_WID_X(x) (((x) & GENMASK(7, 2)) >> 2)
138#define SYS_PTP_CFG_PTP_CF_ROLL_MODE(x) ((x) & GENMASK(1, 0))
139#define SYS_PTP_CFG_PTP_CF_ROLL_MODE_M GENMASK(1, 0)
140
141#define SYS_RAM_INIT_RAM_INIT BIT(1)
142#define SYS_RAM_INIT_RAM_CFG_HOOK BIT(0)
143
144#endif
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 19a5778a7ec7..0e2305ccc91f 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -123,6 +123,13 @@ config MDIO_MOXART
123 This driver supports the MDIO interface found in the network 123 This driver supports the MDIO interface found in the network
124 interface units of the MOXA ART SoC 124 interface units of the MOXA ART SoC
125 125
126config MDIO_MSCC_MIIM
127 tristate "Microsemi MIIM interface support"
128 depends on HAS_IOMEM
129 help
130 This driver supports the MIIM (MDIO) interface found in the network
131 switches of the Microsemi SoCs
132
126config MDIO_OCTEON 133config MDIO_OCTEON
127 tristate "Octeon and some ThunderX SOCs MDIO buses" 134 tristate "Octeon and some ThunderX SOCs MDIO buses"
128 depends on 64BIT 135 depends on 64BIT
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 738246960e3b..5805c0b7d60e 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
34obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o 34obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
35obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o 35obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o
36obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o 36obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o
37obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o
37obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o 38obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
38obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o 39obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o
39obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o 40obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o
diff --git a/drivers/net/phy/mdio-mscc-miim.c b/drivers/net/phy/mdio-mscc-miim.c
new file mode 100644
index 000000000000..8c689ccfdbca
--- /dev/null
+++ b/drivers/net/phy/mdio-mscc-miim.c
@@ -0,0 +1,197 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Driver for the MDIO interface of Microsemi network switches.
4 *
5 * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
6 * Copyright (c) 2017 Microsemi Corporation
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/phy.h>
12#include <linux/platform_device.h>
13#include <linux/bitops.h>
14#include <linux/io.h>
15#include <linux/iopoll.h>
16#include <linux/of_mdio.h>
17
18#define MSCC_MIIM_REG_STATUS 0x0
19#define MSCC_MIIM_STATUS_STAT_BUSY BIT(3)
20#define MSCC_MIIM_REG_CMD 0x8
21#define MSCC_MIIM_CMD_OPR_WRITE BIT(1)
22#define MSCC_MIIM_CMD_OPR_READ BIT(2)
23#define MSCC_MIIM_CMD_WRDATA_SHIFT 4
24#define MSCC_MIIM_CMD_REGAD_SHIFT 20
25#define MSCC_MIIM_CMD_PHYAD_SHIFT 25
26#define MSCC_MIIM_CMD_VLD BIT(31)
27#define MSCC_MIIM_REG_DATA 0xC
28#define MSCC_MIIM_DATA_ERROR (BIT(16) | BIT(17))
29
30#define MSCC_PHY_REG_PHY_CFG 0x0
31#define PHY_CFG_PHY_ENA (BIT(0) | BIT(1) | BIT(2) | BIT(3))
32#define PHY_CFG_PHY_COMMON_RESET BIT(4)
33#define PHY_CFG_PHY_RESET (BIT(5) | BIT(6) | BIT(7) | BIT(8))
34#define MSCC_PHY_REG_PHY_STATUS 0x4
35
36struct mscc_miim_dev {
37 void __iomem *regs;
38 void __iomem *phy_regs;
39};
40
41static int mscc_miim_wait_ready(struct mii_bus *bus)
42{
43 struct mscc_miim_dev *miim = bus->priv;
44 u32 val;
45
46 readl_poll_timeout(miim->regs + MSCC_MIIM_REG_STATUS, val,
47 !(val & MSCC_MIIM_STATUS_STAT_BUSY), 100, 250000);
48 if (val & MSCC_MIIM_STATUS_STAT_BUSY)
49 return -ETIMEDOUT;
50
51 return 0;
52}
53
54static int mscc_miim_read(struct mii_bus *bus, int mii_id, int regnum)
55{
56 struct mscc_miim_dev *miim = bus->priv;
57 u32 val;
58 int ret;
59
60 ret = mscc_miim_wait_ready(bus);
61 if (ret)
62 goto out;
63
64 writel(MSCC_MIIM_CMD_VLD | (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
65 (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | MSCC_MIIM_CMD_OPR_READ,
66 miim->regs + MSCC_MIIM_REG_CMD);
67
68 ret = mscc_miim_wait_ready(bus);
69 if (ret)
70 goto out;
71
72 val = readl(miim->regs + MSCC_MIIM_REG_DATA);
73 if (val & MSCC_MIIM_DATA_ERROR) {
74 ret = -EIO;
75 goto out;
76 }
77
78 ret = val & 0xFFFF;
79out:
80 return ret;
81}
82
83static int mscc_miim_write(struct mii_bus *bus, int mii_id,
84 int regnum, u16 value)
85{
86 struct mscc_miim_dev *miim = bus->priv;
87 int ret;
88
89 ret = mscc_miim_wait_ready(bus);
90 if (ret < 0)
91 goto out;
92
93 writel(MSCC_MIIM_CMD_VLD | (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
94 (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
95 (value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
96 MSCC_MIIM_CMD_OPR_WRITE,
97 miim->regs + MSCC_MIIM_REG_CMD);
98
99out:
100 return ret;
101}
102
103static int mscc_miim_reset(struct mii_bus *bus)
104{
105 struct mscc_miim_dev *miim = bus->priv;
106
107 if (miim->phy_regs) {
108 writel(0, miim->phy_regs + MSCC_PHY_REG_PHY_CFG);
109 writel(0x1ff, miim->phy_regs + MSCC_PHY_REG_PHY_CFG);
110 mdelay(500);
111 }
112
113 return 0;
114}
115
116static int mscc_miim_probe(struct platform_device *pdev)
117{
118 struct resource *res;
119 struct mii_bus *bus;
120 struct mscc_miim_dev *dev;
121 int ret;
122
123 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
124 if (!res)
125 return -ENODEV;
126
127 bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*dev));
128 if (!bus)
129 return -ENOMEM;
130
131 bus->name = "mscc_miim";
132 bus->read = mscc_miim_read;
133 bus->write = mscc_miim_write;
134 bus->reset = mscc_miim_reset;
135 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
136 bus->parent = &pdev->dev;
137
138 dev = bus->priv;
139 dev->regs = devm_ioremap_resource(&pdev->dev, res);
140 if (IS_ERR(dev->regs)) {
141 dev_err(&pdev->dev, "Unable to map MIIM registers\n");
142 return PTR_ERR(dev->regs);
143 }
144
145 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
146 if (res) {
147 dev->phy_regs = devm_ioremap_resource(&pdev->dev, res);
148 if (IS_ERR(dev->phy_regs)) {
149 dev_err(&pdev->dev, "Unable to map internal phy registers\n");
150 return PTR_ERR(dev->phy_regs);
151 }
152 }
153
154 if (pdev->dev.of_node)
155 ret = of_mdiobus_register(bus, pdev->dev.of_node);
156 else
157 ret = mdiobus_register(bus);
158
159 if (ret < 0) {
160 dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);
161 return ret;
162 }
163
164 platform_set_drvdata(pdev, bus);
165
166 return 0;
167}
168
169static int mscc_miim_remove(struct platform_device *pdev)
170{
171 struct mii_bus *bus = platform_get_drvdata(pdev);
172
173 mdiobus_unregister(bus);
174
175 return 0;
176}
177
178static const struct of_device_id mscc_miim_match[] = {
179 { .compatible = "mscc,ocelot-miim" },
180 { }
181};
182MODULE_DEVICE_TABLE(of, mscc_miim_match);
183
184static struct platform_driver mscc_miim_driver = {
185 .probe = mscc_miim_probe,
186 .remove = mscc_miim_remove,
187 .driver = {
188 .name = "mscc-miim",
189 .of_match_table = mscc_miim_match,
190 },
191};
192
193module_platform_driver(mscc_miim_driver);
194
195MODULE_DESCRIPTION("Microsemi MIIM driver");
196MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
197MODULE_LICENSE("Dual MIT/GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 00:06:37 -0400