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authorAlex Deucher <alexander.deucher@amd.com>2015-08-16 22:48:26 -0400
committerAlex Deucher <alexander.deucher@amd.com>2015-08-17 16:50:12 -0400
commit0b492a4c92050862a9780b941d52c05923fcd669 (patch)
tree174e668c9052d8ea029895ab015991226fe689c1
parent404b2fa3385565b1c472a0482f6564a1550fc8d1 (diff)
drm/amdgpu: cleanup context structure v2
The comment is misleading and incorrect, remove it. Printing the id is completely meaningless and this practice can cause a race conditions on command submission. The flags and hangs fields are completely unused. Give all fields a common indentation. v2: remove fpriv reference and unused flags as well, fix debug message. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h50
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c28
2 files changed, 29 insertions, 49 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 548e2bb72d99..069cc28941ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -179,6 +179,7 @@ struct amdgpu_ring;
179struct amdgpu_semaphore; 179struct amdgpu_semaphore;
180struct amdgpu_cs_parser; 180struct amdgpu_cs_parser;
181struct amdgpu_irq_src; 181struct amdgpu_irq_src;
182struct amdgpu_fpriv;
182 183
183enum amdgpu_cp_irq { 184enum amdgpu_cp_irq {
184 AMDGPU_CP_IRQ_GFX_EOP = 0, 185 AMDGPU_CP_IRQ_GFX_EOP = 0,
@@ -984,27 +985,32 @@ struct amdgpu_vm_manager {
984 * context related structures 985 * context related structures
985 */ 986 */
986 987
987struct amdgpu_ctx_state {
988 uint64_t flags;
989 uint32_t hangs;
990};
991
992struct amdgpu_ctx { 988struct amdgpu_ctx {
993 /* call kref_get()before CS start and kref_put() after CS fence signaled */ 989 struct kref refcount;
994 struct kref refcount; 990 unsigned reset_counter;
995 struct amdgpu_fpriv *fpriv;
996 struct amdgpu_ctx_state state;
997 uint32_t id;
998 unsigned reset_counter;
999}; 991};
1000 992
1001struct amdgpu_ctx_mgr { 993struct amdgpu_ctx_mgr {
1002 struct amdgpu_device *adev; 994 struct amdgpu_device *adev;
1003 struct idr ctx_handles; 995 struct mutex lock;
1004 /* lock for IDR system */ 996 /* protected by lock */
1005 struct mutex lock; 997 struct idr ctx_handles;
1006}; 998};
1007 999
1000int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
1001 uint32_t *id);
1002int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
1003 uint32_t id);
1004
1005void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv);
1006
1007struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1008int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1009
1010int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1011 struct drm_file *filp);
1012
1013
1008/* 1014/*
1009 * file private structure 1015 * file private structure
1010 */ 1016 */
@@ -1013,7 +1019,7 @@ struct amdgpu_fpriv {
1013 struct amdgpu_vm vm; 1019 struct amdgpu_vm vm;
1014 struct mutex bo_list_lock; 1020 struct mutex bo_list_lock;
1015 struct idr bo_list_handles; 1021 struct idr bo_list_handles;
1016 struct amdgpu_ctx_mgr ctx_mgr; 1022 struct amdgpu_ctx_mgr ctx_mgr;
1017}; 1023};
1018 1024
1019/* 1025/*
@@ -1850,18 +1856,6 @@ struct amdgpu_atcs {
1850 struct amdgpu_atcs_functions functions; 1856 struct amdgpu_atcs_functions functions;
1851}; 1857};
1852 1858
1853int amdgpu_ctx_alloc(struct amdgpu_device *adev,struct amdgpu_fpriv *fpriv,
1854 uint32_t *id,uint32_t flags);
1855int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
1856 uint32_t id);
1857
1858void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv);
1859struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1860int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1861
1862extern int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1863 struct drm_file *filp);
1864
1865/* 1859/*
1866 * CGS 1860 * CGS
1867 */ 1861 */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 6c66ac8a1891..e63cfb7fa390 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -28,16 +28,13 @@
28static void amdgpu_ctx_do_release(struct kref *ref) 28static void amdgpu_ctx_do_release(struct kref *ref)
29{ 29{
30 struct amdgpu_ctx *ctx; 30 struct amdgpu_ctx *ctx;
31 struct amdgpu_ctx_mgr *mgr;
32 31
33 ctx = container_of(ref, struct amdgpu_ctx, refcount); 32 ctx = container_of(ref, struct amdgpu_ctx, refcount);
34 mgr = &ctx->fpriv->ctx_mgr;
35
36 idr_remove(&mgr->ctx_handles, ctx->id);
37 kfree(ctx); 33 kfree(ctx);
38} 34}
39 35
40int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t *id, uint32_t flags) 36int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
37 uint32_t *id)
41{ 38{
42 int r; 39 int r;
43 struct amdgpu_ctx *ctx; 40 struct amdgpu_ctx *ctx;
@@ -57,8 +54,6 @@ int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uin
57 *id = (uint32_t)r; 54 *id = (uint32_t)r;
58 55
59 memset(ctx, 0, sizeof(*ctx)); 56 memset(ctx, 0, sizeof(*ctx));
60 ctx->id = *id;
61 ctx->fpriv = fpriv;
62 kref_init(&ctx->refcount); 57 kref_init(&ctx->refcount);
63 mutex_unlock(&mgr->lock); 58 mutex_unlock(&mgr->lock);
64 59
@@ -73,6 +68,7 @@ int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint
73 mutex_lock(&mgr->lock); 68 mutex_lock(&mgr->lock);
74 ctx = idr_find(&mgr->ctx_handles, id); 69 ctx = idr_find(&mgr->ctx_handles, id);
75 if (ctx) { 70 if (ctx) {
71 idr_remove(&mgr->ctx_handles, id);
76 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 72 kref_put(&ctx->refcount, amdgpu_ctx_do_release);
77 mutex_unlock(&mgr->lock); 73 mutex_unlock(&mgr->lock);
78 return 0; 74 return 0;
@@ -97,8 +93,8 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev,
97 } 93 }
98 94
99 /* TODO: these two are always zero */ 95 /* TODO: these two are always zero */
100 out->state.flags = ctx->state.flags; 96 out->state.flags = 0x0;
101 out->state.hangs = ctx->state.hangs; 97 out->state.hangs = 0x0;
102 98
103 /* determine if a GPU reset has occured since the last call */ 99 /* determine if a GPU reset has occured since the last call */
104 reset_counter = atomic_read(&adev->gpu_reset_counter); 100 reset_counter = atomic_read(&adev->gpu_reset_counter);
@@ -123,7 +119,7 @@ void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv)
123 119
124 idr_for_each_entry(idp,ctx,id) { 120 idr_for_each_entry(idp,ctx,id) {
125 if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1) 121 if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
126 DRM_ERROR("ctx (id=%ul) is still alive\n",ctx->id); 122 DRM_ERROR("ctx %p is still alive\n", ctx);
127 } 123 }
128 124
129 mutex_destroy(&mgr->lock); 125 mutex_destroy(&mgr->lock);
@@ -134,7 +130,6 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
134{ 130{
135 int r; 131 int r;
136 uint32_t id; 132 uint32_t id;
137 uint32_t flags;
138 133
139 union drm_amdgpu_ctx *args = data; 134 union drm_amdgpu_ctx *args = data;
140 struct amdgpu_device *adev = dev->dev_private; 135 struct amdgpu_device *adev = dev->dev_private;
@@ -142,11 +137,10 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
142 137
143 r = 0; 138 r = 0;
144 id = args->in.ctx_id; 139 id = args->in.ctx_id;
145 flags = args->in.flags;
146 140
147 switch (args->in.op) { 141 switch (args->in.op) {
148 case AMDGPU_CTX_OP_ALLOC_CTX: 142 case AMDGPU_CTX_OP_ALLOC_CTX:
149 r = amdgpu_ctx_alloc(adev, fpriv, &id, flags); 143 r = amdgpu_ctx_alloc(adev, fpriv, &id);
150 args->out.alloc.ctx_id = id; 144 args->out.alloc.ctx_id = id;
151 break; 145 break;
152 case AMDGPU_CTX_OP_FREE_CTX: 146 case AMDGPU_CTX_OP_FREE_CTX:
@@ -177,17 +171,9 @@ struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id)
177 171
178int amdgpu_ctx_put(struct amdgpu_ctx *ctx) 172int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
179{ 173{
180 struct amdgpu_fpriv *fpriv;
181 struct amdgpu_ctx_mgr *mgr;
182
183 if (ctx == NULL) 174 if (ctx == NULL)
184 return -EINVAL; 175 return -EINVAL;
185 176
186 fpriv = ctx->fpriv;
187 mgr = &fpriv->ctx_mgr;
188 mutex_lock(&mgr->lock);
189 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 177 kref_put(&ctx->refcount, amdgpu_ctx_do_release);
190 mutex_unlock(&mgr->lock);
191
192 return 0; 178 return 0;
193} 179}