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authorArnd Bergmann <arnd@arndb.de>2017-11-07 10:12:46 -0500
committerArnd Bergmann <arnd@arndb.de>2017-11-07 10:14:51 -0500
commit0b30cf2fb435310ae0e8aefa6d14511da9f0f72b (patch)
tree4b63b76200e0a157814a88d25ae3c5d001f0f5b1
parent9c7f85ad3f0e05f631e733c6c772fc2edc1aa96d (diff)
parentf2f221c7810b824e15b57fe3d6c30b354299120f (diff)
Merge tag 'sunxi-dt-for-4.15-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Pull "Allwinner DT changes for 4.15, take 2" from Maxime Ripard: Here are a few commits that would be great to get in 4.15, given how long they've been hanging around. The first and most important one is the reintroduction of the EMAC DT changes after they've been reverted at the last minute in 4.13. There's a arm64 patch that crept in because the H5 and H3 share a common DTSI that is located in arch/arm, and merging that patch through the arm64 PR, especially given the pull requests that have already been sent, would just have generated too many conflicts. * tag 'sunxi-dt-for-4.15-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: dts: sun8i: a711: Enable USB OTG ARM: dts: sun8i: a711: Add regulator support ARM: dts: sun8i: a83t: bananapi-m3: Enable AP6212 WiFi on mmc1 ARM: dts: sun8i: a83t: cubietruck-plus: Enable AP6330 WiFi on mmc1 ARM: dts: sun8i: a83t: Move mmc1 pinctrl setting to dtsi file ARM: dts: sun8i: a83t: allwinner-h8homlet-v2: Add AXP818 regulator nodes ARM: dts: sun8i: a83t: bananapi-m3: Add AXP813 regulator nodes ARM: dts: sun8i: a83t: cubietruck-plus: Add AXP818 regulator nodes ARM: dts: sunxi: Add dtsi for AXP81x PMIC arm64: dts: allwinner: H5: Restore EMAC changes ARM: dts: sunxi: Restore EMAC changes (boards) ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac arm: dts: sunxi: h3/h5: Restore EMAC changes dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY dt-bindings: net: Restore sun8i dwmac binding
Diffstat
-rw-r--r--Documentation/devicetree/bindings/net/dwmac-sun8i.txt207
-rw-r--r--arch/arm/boot/dts/axp81x.dtsi139
-rw-r--r--arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts147
-rw-r--r--arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts169
-rw-r--r--arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts187
-rw-r--r--arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts174
-rw-r--r--arch/arm/boot/dts/sun8i-a83t.dtsi2
-rw-r--r--arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts9
-rw-r--r--arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts19
-rw-r--r--arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts29
-rw-r--r--arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts7
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-2.dts8
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-one.dts8
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts5
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts8
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts22
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts16
-rw-r--r--arch/arm/boot/dts/sunxi-h3-h5.dtsi49
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts17
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts17
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts17
21 files changed, 1210 insertions, 46 deletions
diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
new file mode 100644
index 000000000000..3d6d5fa0c4d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
@@ -0,0 +1,207 @@
1* Allwinner sun8i GMAC ethernet controller
2
3This device is a platform glue layer for stmmac.
4Please see stmmac.txt for the other unchanged properties.
5
6Required properties:
7- compatible: must be one of the following string:
8 "allwinner,sun8i-a83t-emac"
9 "allwinner,sun8i-h3-emac"
10 "allwinner,sun8i-v3s-emac"
11 "allwinner,sun50i-a64-emac"
12- reg: address and length of the register for the device.
13- interrupts: interrupt for the device
14- interrupt-names: must be "macirq"
15- clocks: A phandle to the reference clock for this device
16- clock-names: must be "stmmaceth"
17- resets: A phandle to the reset control for this device
18- reset-names: must be "stmmaceth"
19- phy-mode: See ethernet.txt
20- phy-handle: See ethernet.txt
21- #address-cells: shall be 1
22- #size-cells: shall be 0
23- syscon: A phandle to the syscon of the SoC with one of the following
24 compatible string:
25 - allwinner,sun8i-h3-system-controller
26 - allwinner,sun8i-v3s-system-controller
27 - allwinner,sun50i-a64-system-controller
28 - allwinner,sun8i-a83t-system-controller
29
30Optional properties:
31- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
32- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
33Both delay properties need to be a multiple of 100. They control the delay for
34external PHY.
35
36Optional properties for the following compatibles:
37 - "allwinner,sun8i-h3-emac",
38 - "allwinner,sun8i-v3s-emac":
39- allwinner,leds-active-low: EPHY LEDs are active low
40
41Required child node of emac:
42- mdio bus node: should be named mdio with compatible "snps,dwmac-mdio"
43
44Required properties of the mdio node:
45- #address-cells: shall be 1
46- #size-cells: shall be 0
47
48The device node referenced by "phy" or "phy-handle" must be a child node
49of the mdio node. See phy.txt for the generic PHY bindings.
50
51The following compatibles require that the emac node have a mdio-mux child
52node called "mdio-mux":
53 - "allwinner,sun8i-h3-emac"
54 - "allwinner,sun8i-v3s-emac":
55Required properties for the mdio-mux node:
56 - compatible = "allwinner,sun8i-h3-mdio-mux"
57 - mdio-parent-bus: a phandle to EMAC mdio
58 - one child mdio for the integrated mdio with the compatible
59 "allwinner,sun8i-h3-mdio-internal"
60 - one child mdio for the external mdio if present (V3s have none)
61Required properties for the mdio-mux children node:
62 - reg: 1 for internal MDIO bus, 2 for external MDIO bus
63
64The following compatibles require a PHY node representing the integrated
65PHY, under the integrated MDIO bus node if an mdio-mux node is used:
66 - "allwinner,sun8i-h3-emac",
67 - "allwinner,sun8i-v3s-emac":
68
69Additional information regarding generic multiplexer properties can be found
70at Documentation/devicetree/bindings/net/mdio-mux.txt
71
72Required properties of the integrated phy node:
73- clocks: a phandle to the reference clock for the EPHY
74- resets: a phandle to the reset control for the EPHY
75- Must be a child of the integrated mdio
76
77Example with integrated PHY:
78emac: ethernet@1c0b000 {
79 compatible = "allwinner,sun8i-h3-emac";
80 syscon = <&syscon>;
81 reg = <0x01c0b000 0x104>;
82 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
83 interrupt-names = "macirq";
84 resets = <&ccu RST_BUS_EMAC>;
85 reset-names = "stmmaceth";
86 clocks = <&ccu CLK_BUS_EMAC>;
87 clock-names = "stmmaceth";
88 #address-cells = <1>;
89 #size-cells = <0>;
90
91 phy-handle = <&int_mii_phy>;
92 phy-mode = "mii";
93 allwinner,leds-active-low;
94
95 mdio: mdio {
96 #address-cells = <1>;
97 #size-cells = <0>;
98 compatible = "snps,dwmac-mdio";
99 };
100
101 mdio-mux {
102 compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux";
103 #address-cells = <1>;
104 #size-cells = <0>;
105
106 mdio-parent-bus = <&mdio>;
107
108 int_mdio: mdio@1 {
109 compatible = "allwinner,sun8i-h3-mdio-internal";
110 reg = <1>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113 int_mii_phy: ethernet-phy@1 {
114 reg = <1>;
115 clocks = <&ccu CLK_BUS_EPHY>;
116 resets = <&ccu RST_BUS_EPHY>;
117 phy-is-integrated;
118 };
119 };
120 ext_mdio: mdio@2 {
121 reg = <2>;
122 #address-cells = <1>;
123 #size-cells = <0>;
124 };
125 };
126};
127
128Example with external PHY:
129emac: ethernet@1c0b000 {
130 compatible = "allwinner,sun8i-h3-emac";
131 syscon = <&syscon>;
132 reg = <0x01c0b000 0x104>;
133 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-names = "macirq";
135 resets = <&ccu RST_BUS_EMAC>;
136 reset-names = "stmmaceth";
137 clocks = <&ccu CLK_BUS_EMAC>;
138 clock-names = "stmmaceth";
139 #address-cells = <1>;
140 #size-cells = <0>;
141
142 phy-handle = <&ext_rgmii_phy>;
143 phy-mode = "rgmii";
144 allwinner,leds-active-low;
145
146 mdio: mdio {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "snps,dwmac-mdio";
150 };
151
152 mdio-mux {
153 compatible = "allwinner,sun8i-h3-mdio-mux";
154 #address-cells = <1>;
155 #size-cells = <0>;
156
157 mdio-parent-bus = <&mdio>;
158
159 int_mdio: mdio@1 {
160 compatible = "allwinner,sun8i-h3-mdio-internal";
161 reg = <1>;
162 #address-cells = <1>;
163 #size-cells = <0>;
164 int_mii_phy: ethernet-phy@1 {
165 reg = <1>;
166 clocks = <&ccu CLK_BUS_EPHY>;
167 resets = <&ccu RST_BUS_EPHY>;
168 };
169 };
170 ext_mdio: mdio@2 {
171 reg = <2>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 ext_rgmii_phy: ethernet-phy@1 {
175 reg = <1>;
176 };
177 }:
178 };
179};
180
181Example with SoC without integrated PHY
182
183emac: ethernet@1c0b000 {
184 compatible = "allwinner,sun8i-a83t-emac";
185 syscon = <&syscon>;
186 reg = <0x01c0b000 0x104>;
187 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
188 interrupt-names = "macirq";
189 resets = <&ccu RST_BUS_EMAC>;
190 reset-names = "stmmaceth";
191 clocks = <&ccu CLK_BUS_EMAC>;
192 clock-names = "stmmaceth";
193 #address-cells = <1>;
194 #size-cells = <0>;
195
196 phy-handle = <&ext_rgmii_phy>;
197 phy-mode = "rgmii";
198
199 mdio: mdio {
200 compatible = "snps,dwmac-mdio";
201 #address-cells = <1>;
202 #size-cells = <0>;
203 ext_rgmii_phy: ethernet-phy@1 {
204 reg = <1>;
205 };
206 };
207};
diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi
new file mode 100644
index 000000000000..73b761f850c5
--- /dev/null
+++ b/arch/arm/boot/dts/axp81x.dtsi
@@ -0,0 +1,139 @@
1/*
2 * Copyright 2017 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45/* AXP813/818 Integrated Power Management Chip */
46
47&axp81x {
48 interrupt-controller;
49 #interrupt-cells = <1>;
50
51 regulators {
52 /* Default work frequency for buck regulators */
53 x-powers,dcdc-freq = <3000>;
54
55 reg_dcdc1: dcdc1 {
56 };
57
58 reg_dcdc2: dcdc2 {
59 };
60
61 reg_dcdc3: dcdc3 {
62 };
63
64 reg_dcdc4: dcdc4 {
65 };
66
67 reg_dcdc5: dcdc5 {
68 };
69
70 reg_dcdc6: dcdc6 {
71 };
72
73 reg_dcdc7: dcdc7 {
74 };
75
76 reg_aldo1: aldo1 {
77 };
78
79 reg_aldo2: aldo2 {
80 };
81
82 reg_aldo3: aldo3 {
83 };
84
85 reg_dldo1: dldo1 {
86 };
87
88 reg_dldo2: dldo2 {
89 };
90
91 reg_dldo3: dldo3 {
92 };
93
94 reg_dldo4: dldo4 {
95 };
96
97 reg_eldo1: eldo1 {
98 };
99
100 reg_eldo2: eldo2 {
101 };
102
103 reg_eldo3: eldo3 {
104 };
105
106 reg_fldo1: fldo1 {
107 };
108
109 reg_fldo2: fldo2 {
110 };
111
112 reg_fldo3: fldo3 {
113 };
114
115 reg_ldo_io0: ldo-io0 {
116 /* Disable by default to avoid conflicts with GPIO */
117 status = "disabled";
118 };
119
120 reg_ldo_io1: ldo-io1 {
121 /* Disable by default to avoid conflicts with GPIO */
122 status = "disabled";
123 };
124
125 reg_rtc_ldo: rtc-ldo {
126 /* RTC_LDO is a fixed, always-on regulator */
127 regulator-always-on;
128 regulator-min-microvolt = <1800000>;
129 regulator-max-microvolt = <1800000>;
130 };
131
132 reg_sw: sw {
133 };
134
135 reg_drivevbus: drivevbus {
136 status = "disabled";
137 };
138 };
139};
diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index 1f0d60afb25b..5091cecbcd1e 100644
--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -43,7 +43,8 @@
43 43
44/dts-v1/; 44/dts-v1/;
45#include "sun8i-a83t.dtsi" 45#include "sun8i-a83t.dtsi"
46#include "sunxi-common-regulators.dtsi" 46
47#include <dt-bindings/gpio/gpio.h>
47 48
48/ { 49/ {
49 model = "Allwinner A83T H8Homlet Proto Dev Board v2.0"; 50 model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
@@ -56,6 +57,26 @@
56 chosen { 57 chosen {
57 stdout-path = "serial0:115200n8"; 58 stdout-path = "serial0:115200n8";
58 }; 59 };
60
61 reg_usb0_vbus: reg-usb0-vbus {
62 compatible = "regulator-fixed";
63 regulator-name = "usb0-vbus";
64 regulator-min-microvolt = <5000000>;
65 regulator-max-microvolt = <5000000>;
66 regulator-boot-on;
67 enable-active-high;
68 gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
69 };
70
71 reg_usb1_vbus: reg-usb1-vbus {
72 compatible = "regulator-fixed";
73 regulator-name = "usb1-vbus";
74 regulator-min-microvolt = <5000000>;
75 regulator-max-microvolt = <5000000>;
76 regulator-boot-on;
77 enable-active-high;
78 gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
79 };
59}; 80};
60 81
61&ehci0 { 82&ehci0 {
@@ -65,7 +86,7 @@
65&mmc0 { 86&mmc0 {
66 pinctrl-names = "default"; 87 pinctrl-names = "default";
67 pinctrl-0 = <&mmc0_pins>; 88 pinctrl-0 = <&mmc0_pins>;
68 vmmc-supply = <&reg_vcc3v0>; 89 vmmc-supply = <&reg_dcdc1>;
69 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ 90 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
70 bus-width = <4>; 91 bus-width = <4>;
71 cd-inverted; 92 cd-inverted;
@@ -75,7 +96,8 @@
75&mmc2 { 96&mmc2 {
76 pinctrl-names = "default"; 97 pinctrl-names = "default";
77 pinctrl-0 = <&mmc2_8bit_emmc_pins>; 98 pinctrl-0 = <&mmc2_8bit_emmc_pins>;
78 vmmc-supply = <&reg_vcc3v0>; 99 vmmc-supply = <&reg_dcdc1>;
100 vqmmc-supply = <&reg_dcdc1>;
79 bus-width = <8>; 101 bus-width = <8>;
80 non-removable; 102 non-removable;
81 cap-mmc-hw-reset; 103 cap-mmc-hw-reset;
@@ -86,16 +108,6 @@
86 status = "okay"; 108 status = "okay";
87}; 109};
88 110
89&reg_usb0_vbus {
90 gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
91 status = "okay";
92};
93
94&reg_usb1_vbus {
95 gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
96 status = "okay";
97};
98
99&r_rsb { 111&r_rsb {
100 status = "okay"; 112 status = "okay";
101 113
@@ -104,6 +116,8 @@
104 reg = <0x3a3>; 116 reg = <0x3a3>;
105 interrupt-parent = <&r_intc>; 117 interrupt-parent = <&r_intc>;
106 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 118 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
119 eldoin-supply = <&reg_dcdc1>;
120 swin-supply = <&reg_dcdc1>;
107 }; 121 };
108 122
109 ac100: codec@e89 { 123 ac100: codec@e89 {
@@ -131,6 +145,113 @@
131 }; 145 };
132}; 146};
133 147
148#include "axp81x.dtsi"
149
150&reg_aldo1 {
151 regulator-always-on;
152 regulator-min-microvolt = <1800000>;
153 regulator-max-microvolt = <1800000>;
154 regulator-name = "vcc-1v8";
155};
156
157&reg_aldo2 {
158 regulator-always-on;
159 regulator-min-microvolt = <1800000>;
160 regulator-max-microvolt = <1800000>;
161 regulator-name = "dram-pll";
162};
163
164&reg_aldo3 {
165 regulator-always-on;
166 regulator-min-microvolt = <3000000>;
167 regulator-max-microvolt = <3000000>;
168 regulator-name = "avcc";
169};
170
171&reg_dcdc1 {
172 regulator-always-on;
173 regulator-min-microvolt = <3300000>;
174 regulator-max-microvolt = <3300000>;
175 regulator-name = "vcc-3v3";
176};
177
178&reg_dcdc2 {
179 regulator-always-on;
180 regulator-min-microvolt = <700000>;
181 regulator-max-microvolt = <1100000>;
182 regulator-name = "vdd-cpua";
183};
184
185&reg_dcdc3 {
186 regulator-always-on;
187 regulator-min-microvolt = <700000>;
188 regulator-max-microvolt = <1100000>;
189 regulator-name = "vdd-cpub";
190};
191
192&reg_dcdc4 {
193 regulator-min-microvolt = <700000>;
194 regulator-max-microvolt = <1100000>;
195 regulator-name = "vdd-gpu";
196};
197
198&reg_dcdc5 {
199 regulator-always-on;
200 regulator-min-microvolt = <1500000>;
201 regulator-max-microvolt = <1500000>;
202 regulator-name = "vcc-dram";
203};
204
205&reg_dcdc6 {
206 regulator-always-on;
207 regulator-min-microvolt = <900000>;
208 regulator-max-microvolt = <900000>;
209 regulator-name = "vdd-sys";
210};
211
212&reg_dldo2 {
213 regulator-min-microvolt = <3300000>;
214 regulator-max-microvolt = <3300000>;
215 regulator-name = "vcc-mipi";
216};
217
218&reg_dldo4 {
219 /*
220 * The PHY requires 20ms after all voltages are applied until core
221 * logic is ready and 30ms after the reset pin is de-asserted.
222 * Set a 100ms delay to account for PMIC ramp time and board traces.
223 */
224 regulator-enable-ramp-delay = <100000>;
225 regulator-min-microvolt = <3300000>;
226 regulator-max-microvolt = <3300000>;
227 regulator-name = "vcc-ephy";
228};
229
230&reg_fldo1 {
231 regulator-min-microvolt = <1080000>;
232 regulator-max-microvolt = <1320000>;
233 regulator-name = "vdd12-hsic";
234};
235
236&reg_fldo2 {
237 /*
238 * Despite the embedded CPUs core not being used in any way,
239 * this must remain on or the system will hang.
240 */
241 regulator-always-on;
242 regulator-min-microvolt = <700000>;
243 regulator-max-microvolt = <1100000>;
244 regulator-name = "vdd-cpus";
245};
246
247&reg_rtc_ldo {
248 regulator-name = "vcc-rtc";
249};
250
251&reg_sw {
252 regulator-name = "vcc-wifi";
253};
254
134&uart0 { 255&uart0 {
135 pinctrl-names = "default"; 256 pinctrl-names = "default";
136 pinctrl-0 = <&uart0_pb_pins>; 257 pinctrl-0 = <&uart0_pb_pins>;
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 2bafd7e99ef7..c606af3dbfed 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -44,7 +44,6 @@
44 44
45/dts-v1/; 45/dts-v1/;
46#include "sun8i-a83t.dtsi" 46#include "sun8i-a83t.dtsi"
47#include "sunxi-common-regulators.dtsi"
48 47
49#include <dt-bindings/gpio/gpio.h> 48#include <dt-bindings/gpio/gpio.h>
50 49
@@ -59,6 +58,27 @@
59 chosen { 58 chosen {
60 stdout-path = "serial0:115200n8"; 59 stdout-path = "serial0:115200n8";
61 }; 60 };
61
62 reg_usb1_vbus: reg-usb1-vbus {
63 compatible = "regulator-fixed";
64 regulator-name = "usb1-vbus";
65 regulator-min-microvolt = <5000000>;
66 regulator-max-microvolt = <5000000>;
67 regulator-boot-on;
68 enable-active-high;
69 gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
70 };
71
72 wifi_pwrseq: wifi_pwrseq {
73 compatible = "mmc-pwrseq-simple";
74 clocks = <&ac100_rtc 1>;
75 clock-names = "ext_clock";
76 /* The WiFi low power clock must be 32768 Hz */
77 assigned-clocks = <&ac100_rtc 1>;
78 assigned-clock-rates = <32768>;
79 /* enables internal regulator and de-asserts reset */
80 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
81 };
62}; 82};
63 83
64&ehci0 { 84&ehci0 {
@@ -71,17 +91,35 @@
71&mmc0 { 91&mmc0 {
72 pinctrl-names = "default"; 92 pinctrl-names = "default";
73 pinctrl-0 = <&mmc0_pins>; 93 pinctrl-0 = <&mmc0_pins>;
74 vmmc-supply = <&reg_vcc3v3>; 94 vmmc-supply = <&reg_dcdc1>;
75 bus-width = <4>; 95 bus-width = <4>;
76 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ 96 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
77 cd-inverted; 97 cd-inverted;
78 status = "okay"; 98 status = "okay";
79}; 99};
80 100
101&mmc1 {
102 vmmc-supply = <&reg_dldo1>;
103 vqmmc-supply = <&reg_dldo1>;
104 mmc-pwrseq = <&wifi_pwrseq>;
105 bus-width = <4>;
106 non-removable;
107 status = "okay";
108
109 brcmf: wifi@1 {
110 reg = <1>;
111 compatible = "brcm,bcm4329-fmac";
112 interrupt-parent = <&r_pio>;
113 interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>;
114 interrupt-names = "host-wake";
115 };
116};
117
81&mmc2 { 118&mmc2 {
82 pinctrl-names = "default"; 119 pinctrl-names = "default";
83 pinctrl-0 = <&mmc2_8bit_emmc_pins>; 120 pinctrl-0 = <&mmc2_8bit_emmc_pins>;
84 vmmc-supply = <&reg_vcc3v3>; 121 vmmc-supply = <&reg_dcdc1>;
122 vqmmc-supply = <&reg_dcdc1>;
85 bus-width = <8>; 123 bus-width = <8>;
86 non-removable; 124 non-removable;
87 cap-mmc-hw-reset; 125 cap-mmc-hw-reset;
@@ -96,6 +134,10 @@
96 reg = <0x3a3>; 134 reg = <0x3a3>;
97 interrupt-parent = <&r_intc>; 135 interrupt-parent = <&r_intc>;
98 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 136 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
137 eldoin-supply = <&reg_dcdc1>;
138 fldoin-supply = <&reg_dcdc5>;
139 swin-supply = <&reg_dcdc1>;
140 x-powers,drive-vbus-en;
99 }; 141 };
100 142
101 ac100: codec@e89 { 143 ac100: codec@e89 {
@@ -123,17 +165,126 @@
123 }; 165 };
124}; 166};
125 167
126&reg_usb1_vbus { 168#include "axp81x.dtsi"
127 gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ 169
170&reg_aldo1 {
171 regulator-always-on;
172 regulator-min-microvolt = <1800000>;
173 regulator-max-microvolt = <1800000>;
174 regulator-name = "vcc-1v8";
175};
176
177&reg_aldo2 {
178 regulator-always-on;
179 regulator-min-microvolt = <1800000>;
180 regulator-max-microvolt = <1800000>;
181 regulator-name = "dram-pll";
182};
183
184&reg_aldo3 {
185 regulator-always-on;
186 regulator-min-microvolt = <3000000>;
187 regulator-max-microvolt = <3000000>;
188 regulator-name = "avcc";
189};
190
191&reg_dcdc1 {
192 /* schematics says 3.1V but FEX file says 3.3V */
193 regulator-always-on;
194 regulator-min-microvolt = <3300000>;
195 regulator-max-microvolt = <3300000>;
196 regulator-name = "vcc-3v3";
197};
198
199&reg_dcdc2 {
200 regulator-always-on;
201 regulator-min-microvolt = <700000>;
202 regulator-max-microvolt = <1100000>;
203 regulator-name = "vdd-cpua";
204};
205
206&reg_dcdc3 {
207 regulator-always-on;
208 regulator-min-microvolt = <700000>;
209 regulator-max-microvolt = <1100000>;
210 regulator-name = "vdd-cpub";
211};
212
213&reg_dcdc4 {
214 regulator-min-microvolt = <700000>;
215 regulator-max-microvolt = <1100000>;
216 regulator-name = "vdd-gpu";
217};
218
219&reg_dcdc5 {
220 regulator-always-on;
221 regulator-min-microvolt = <1200000>;
222 regulator-max-microvolt = <1200000>;
223 regulator-name = "vcc-dram";
224};
225
226&reg_dcdc6 {
227 regulator-always-on;
228 regulator-min-microvolt = <900000>;
229 regulator-max-microvolt = <900000>;
230 regulator-name = "vdd-sys";
231};
232
233&reg_dldo1 {
234 /*
235 * This powers both the WiFi/BT module's main power, I/O supply,
236 * and external pull-ups on all the data lines. It should be set
237 * to the same voltage as the I/O supply (DCDC1 in this case) to
238 * avoid any leakage or mismatch.
239 */
240 regulator-min-microvolt = <3300000>;
241 regulator-max-microvolt = <3300000>;
242 regulator-name = "vcc-wifi";
243};
244
245&reg_dldo3 {
246 regulator-always-on;
247 regulator-min-microvolt = <2500000>;
248 regulator-max-microvolt = <2500000>;
249 regulator-name = "vcc-pd";
250};
251
252&reg_drivevbus {
253 regulator-name = "usb0-vbus";
128 status = "okay"; 254 status = "okay";
129}; 255};
130 256
131&reg_vcc3v0 { 257&reg_fldo1 {
132 status = "disabled"; 258 regulator-min-microvolt = <1080000>;
259 regulator-max-microvolt = <1320000>;
260 regulator-name = "vdd12-hsic";
261};
262
263&reg_fldo2 {
264 /*
265 * Despite the embedded CPUs core not being used in any way,
266 * this must remain on or the system will hang.
267 */
268 regulator-always-on;
269 regulator-min-microvolt = <700000>;
270 regulator-max-microvolt = <1100000>;
271 regulator-name = "vdd-cpus";
272};
273
274&reg_rtc_ldo {
275 regulator-name = "vcc-rtc";
133}; 276};
134 277
135&reg_vcc5v0 { 278&reg_sw {
136 status = "disabled"; 279 /*
280 * The PHY requires 20ms after all voltages
281 * are applied until core logic is ready and
282 * 30ms after the reset pin is de-asserted.
283 * Set a 100ms delay to account for PMIC
284 * ramp time and board traces.
285 */
286 regulator-enable-ramp-delay = <100000>;
287 regulator-name = "vcc-ephy";
137}; 288};
138 289
139&uart0 { 290&uart0 {
diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
index 716a205c6dbb..7f0a3f6d0cf2 100644
--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
@@ -44,7 +44,6 @@
44 44
45/dts-v1/; 45/dts-v1/;
46#include "sun8i-a83t.dtsi" 46#include "sun8i-a83t.dtsi"
47#include "sunxi-common-regulators.dtsi"
48 47
49#include <dt-bindings/gpio/gpio.h> 48#include <dt-bindings/gpio/gpio.h>
50 49
@@ -95,6 +94,26 @@
95 refclk-frequency = <19200000>; 94 refclk-frequency = <19200000>;
96 }; 95 };
97 96
97 reg_usb1_vbus: reg-usb1-vbus {
98 compatible = "regulator-fixed";
99 regulator-name = "usb1-vbus";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 regulator-boot-on;
103 enable-active-high;
104 gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */
105 };
106
107 reg_usb2_vbus: reg-usb2-vbus {
108 compatible = "regulator-fixed";
109 regulator-name = "usb2-vbus";
110 regulator-min-microvolt = <5000000>;
111 regulator-max-microvolt = <5000000>;
112 regulator-boot-on;
113 enable-active-high;
114 gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
115 };
116
98 sound { 117 sound {
99 compatible = "simple-audio-card"; 118 compatible = "simple-audio-card";
100 simple-audio-card,name = "On-board SPDIF"; 119 simple-audio-card,name = "On-board SPDIF";
@@ -112,6 +131,17 @@
112 #sound-dai-cells = <0>; 131 #sound-dai-cells = <0>;
113 compatible = "linux,spdif-dit"; 132 compatible = "linux,spdif-dit";
114 }; 133 };
134
135 wifi_pwrseq: wifi_pwrseq {
136 compatible = "mmc-pwrseq-simple";
137 clocks = <&ac100_rtc 1>;
138 clock-names = "ext_clock";
139 /* The WiFi low power clock must be 32768 Hz */
140 assigned-clocks = <&ac100_rtc 1>;
141 assigned-clock-rates = <32768>;
142 /* enables internal regulator and de-asserts reset */
143 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
144 };
115}; 145};
116 146
117&ehci0 { 147&ehci0 {
@@ -127,17 +157,26 @@
127&mmc0 { 157&mmc0 {
128 pinctrl-names = "default"; 158 pinctrl-names = "default";
129 pinctrl-0 = <&mmc0_pins>; 159 pinctrl-0 = <&mmc0_pins>;
130 vmmc-supply = <&reg_vcc3v3>; 160 vmmc-supply = <&reg_dcdc1>;
131 bus-width = <4>; 161 bus-width = <4>;
132 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ 162 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
133 cd-inverted; 163 cd-inverted;
134 status = "okay"; 164 status = "okay";
135}; 165};
136 166
167&mmc1 {
168 vmmc-supply = <&reg_dcdc1>;
169 vqmmc-supply = <&reg_sw>;
170 mmc-pwrseq = <&wifi_pwrseq>;
171 bus-width = <4>;
172 non-removable;
173 status = "okay";
174};
175
137&mmc2 { 176&mmc2 {
138 pinctrl-names = "default"; 177 pinctrl-names = "default";
139 pinctrl-0 = <&mmc2_8bit_emmc_pins>; 178 pinctrl-0 = <&mmc2_8bit_emmc_pins>;
140 vmmc-supply = <&reg_vcc3v3>; 179 vmmc-supply = <&reg_dcdc1>;
141 bus-width = <8>; 180 bus-width = <8>;
142 non-removable; 181 non-removable;
143 cap-mmc-hw-reset; 182 cap-mmc-hw-reset;
@@ -152,6 +191,9 @@
152 reg = <0x3a3>; 191 reg = <0x3a3>;
153 interrupt-parent = <&r_intc>; 192 interrupt-parent = <&r_intc>;
154 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 193 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
194 eldoin-supply = <&reg_dcdc1>;
195 swin-supply = <&reg_dcdc1>;
196 x-powers,drive-vbus-en;
155 }; 197 };
156 198
157 ac100: codec@e89 { 199 ac100: codec@e89 {
@@ -179,22 +221,143 @@
179 }; 221 };
180}; 222};
181 223
182&reg_usb1_vbus { 224#include "axp81x.dtsi"
183 gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */ 225
184 status = "okay"; 226&reg_aldo1 {
227 regulator-always-on;
228 regulator-min-microvolt = <1800000>;
229 regulator-max-microvolt = <1800000>;
230 regulator-name = "vcc-1v8";
231};
232
233&reg_aldo2 {
234 regulator-always-on;
235 regulator-min-microvolt = <1800000>;
236 regulator-max-microvolt = <1800000>;
237 regulator-name = "dram-pll";
238};
239
240&reg_aldo3 {
241 regulator-always-on;
242 regulator-min-microvolt = <3000000>;
243 regulator-max-microvolt = <3000000>;
244 regulator-name = "avcc";
185}; 245};
186 246
187&reg_usb2_vbus { 247&reg_dcdc1 {
188 gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ 248 /*
249 * The schematics say this should be 3.3V, but the FEX file says
250 * it should be 3V. The latter makes sense, as the WiFi module's
251 * I/O is indirectly powered from DCDC1, through SW. It is rated
252 * at 2.98V maximum.
253 */
254 regulator-always-on;
255 regulator-min-microvolt = <3000000>;
256 regulator-max-microvolt = <3000000>;
257 regulator-name = "vcc-3v";
258};
259
260&reg_dcdc2 {
261 regulator-always-on;
262 regulator-min-microvolt = <700000>;
263 regulator-max-microvolt = <1100000>;
264 regulator-name = "vdd-cpua";
265};
266
267&reg_dcdc3 {
268 regulator-always-on;
269 regulator-min-microvolt = <700000>;
270 regulator-max-microvolt = <1100000>;
271 regulator-name = "vdd-cpub";
272};
273
274&reg_dcdc4 {
275 regulator-min-microvolt = <700000>;
276 regulator-max-microvolt = <1100000>;
277 regulator-name = "vdd-gpu";
278};
279
280&reg_dcdc5 {
281 regulator-always-on;
282 regulator-min-microvolt = <1500000>;
283 regulator-max-microvolt = <1500000>;
284 regulator-name = "vcc-dram";
285};
286
287&reg_dcdc6 {
288 regulator-always-on;
289 regulator-min-microvolt = <900000>;
290 regulator-max-microvolt = <900000>;
291 regulator-name = "vdd-sys";
292};
293
294&reg_dldo2 {
295 regulator-min-microvolt = <3300000>;
296 regulator-max-microvolt = <3300000>;
297 regulator-name = "dp-pwr";
298};
299
300&reg_dldo3 {
301 regulator-always-on;
302 regulator-min-microvolt = <2500000>;
303 regulator-max-microvolt = <2500000>;
304 regulator-name = "ephy-io";
305};
306
307&reg_dldo4 {
308 /*
309 * The PHY requires 20ms after all voltages are applied until core
310 * logic is ready and 30ms after the reset pin is de-asserted.
311 * Set a 100ms delay to account for PMIC ramp time and board traces.
312 */
313 regulator-enable-ramp-delay = <100000>;
314 regulator-min-microvolt = <3300000>;
315 regulator-max-microvolt = <3300000>;
316 regulator-name = "ephy";
317};
318
319&reg_drivevbus {
320 regulator-name = "usb0-vbus";
189 status = "okay"; 321 status = "okay";
190}; 322};
191 323
192&reg_vcc3v0 { 324&reg_eldo1 {
193 status = "disabled"; 325 regulator-min-microvolt = <1200000>;
326 regulator-max-microvolt = <1200000>;
327 regulator-name = "dp-bridge-1";
328};
329
330&reg_eldo2 {
331 regulator-min-microvolt = <1200000>;
332 regulator-max-microvolt = <1200000>;
333 regulator-name = "dp-bridge-2";
334};
335
336&reg_fldo1 {
337 /* TODO should be handled by USB PHY */
338 regulator-always-on;
339 regulator-min-microvolt = <1080000>;
340 regulator-max-microvolt = <1320000>;
341 regulator-name = "vdd12-hsic";
342};
343
344&reg_fldo2 {
345 /*
346 * Despite the embedded CPUs core not being used in any way,
347 * this must remain on or the system will hang.
348 */
349 regulator-always-on;
350 regulator-min-microvolt = <700000>;
351 regulator-max-microvolt = <1100000>;
352 regulator-name = "vdd-cpus";
353};
354
355&reg_rtc_ldo {
356 regulator-name = "vcc-rtc";
194}; 357};
195 358
196&reg_vcc5v0 { 359&reg_sw {
197 status = "disabled"; 360 regulator-name = "vcc-wifi-io";
198}; 361};
199 362
200&spdif { 363&spdif {
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 723641f56a74..98715538932f 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -43,7 +43,8 @@
43 43
44/dts-v1/; 44/dts-v1/;
45#include "sun8i-a83t.dtsi" 45#include "sun8i-a83t.dtsi"
46#include "sunxi-common-regulators.dtsi" 46
47#include <dt-bindings/gpio/gpio.h>
47 48
48/ { 49/ {
49 model = "TBS A711 Tablet"; 50 model = "TBS A711 Tablet";
@@ -105,7 +106,7 @@
105}; 106};
106 107
107&mmc0 { 108&mmc0 {
108 vmmc-supply = <&reg_vcc3v3>; 109 vmmc-supply = <&reg_dcdc1>;
109 pinctrl-names = "default"; 110 pinctrl-names = "default";
110 pinctrl-0 = <&mmc0_pins>; 111 pinctrl-0 = <&mmc0_pins>;
111 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; 112 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
@@ -115,10 +116,8 @@
115&mmc1 { 116&mmc1 {
116 mmc-pwrseq = <&wifi_pwrseq>; 117 mmc-pwrseq = <&wifi_pwrseq>;
117 bus-width = <4>; 118 bus-width = <4>;
118 pinctrl-names = "default"; 119 vmmc-supply = <&reg_dldo1>;
119 pinctrl-0 = <&mmc1_pins>; 120 vqmmc-supply = <&reg_dldo1>;
120 vmmc-supply = <&reg_vcc3v3>;
121 vqmmc-supply = <&reg_vcc3v3>;
122 non-removable; 121 non-removable;
123 wakeup-source; 122 wakeup-source;
124 status = "okay"; 123 status = "okay";
@@ -135,8 +134,8 @@
135&mmc2 { 134&mmc2 {
136 pinctrl-0 = <&mmc2_8bit_emmc_pins>; 135 pinctrl-0 = <&mmc2_8bit_emmc_pins>;
137 pinctrl-names = "default"; 136 pinctrl-names = "default";
138 vmmc-supply = <&reg_vcc3v3>; 137 vmmc-supply = <&reg_dcdc1>;
139 vqmmc-supply = <&reg_vcc3v3>; 138 vqmmc-supply = <&reg_dcdc1>;
140 bus-width = <8>; 139 bus-width = <8>;
141 non-removable; 140 non-removable;
142 cap-mmc-hw-reset; 141 cap-mmc-hw-reset;
@@ -146,11 +145,12 @@
146&r_rsb { 145&r_rsb {
147 status = "okay"; 146 status = "okay";
148 147
149 axp813: pmic@3a3 { 148 axp81x: pmic@3a3 {
150 compatible = "x-powers,axp813";
151 reg = <0x3a3>; 149 reg = <0x3a3>;
152 interrupt-parent = <&r_intc>; 150 interrupt-parent = <&r_intc>;
153 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 151 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
152 swin-supply = <&reg_dcdc1>;
153 x-powers,drive-vbus-en;
154 }; 154 };
155 155
156 ac100: codec@e89 { 156 ac100: codec@e89 {
@@ -179,6 +179,149 @@
179 179
180}; 180};
181 181
182#include "axp81x.dtsi"
183
184&reg_aldo1 {
185 regulator-min-microvolt = <1800000>;
186 regulator-max-microvolt = <1800000>;
187 regulator-name = "vcc-1.8";
188};
189
190&reg_aldo2 {
191 regulator-min-microvolt = <1800000>;
192 regulator-max-microvolt = <1800000>;
193 regulator-always-on;
194 regulator-name = "vdd-drampll";
195};
196
197&reg_aldo3 {
198 regulator-min-microvolt = <3000000>;
199 regulator-max-microvolt = <3000000>;
200 regulator-always-on;
201 regulator-name = "avcc";
202};
203
204&reg_dcdc1 {
205 regulator-min-microvolt = <3100000>;
206 regulator-max-microvolt = <3100000>;
207 regulator-always-on;
208 regulator-name = "vcc-io";
209};
210
211&reg_dcdc2 {
212 regulator-min-microvolt = <700000>;
213 regulator-max-microvolt = <1100000>;
214 regulator-always-on;
215 regulator-name = "vdd-cpu-A";
216};
217
218&reg_dcdc3 {
219 regulator-min-microvolt = <700000>;
220 regulator-max-microvolt = <1100000>;
221 regulator-always-on;
222 regulator-name = "vdd-cpu-B";
223};
224
225&reg_dcdc4 {
226 regulator-min-microvolt = <700000>;
227 regulator-max-microvolt = <1100000>;
228 regulator-name = "vdd-gpu";
229};
230
231&reg_dcdc5 {
232 regulator-min-microvolt = <1200000>;
233 regulator-max-microvolt = <1500000>;
234 regulator-always-on;
235 regulator-name = "vcc-dram";
236};
237
238&reg_dcdc6 {
239 regulator-min-microvolt = <900000>;
240 regulator-max-microvolt = <900000>;
241 regulator-always-on;
242 regulator-name = "vdd-sys";
243};
244
245&reg_dldo1 {
246 regulator-min-microvolt = <3100000>;
247 regulator-max-microvolt = <3100000>;
248 regulator-name = "vcc-wifi-io";
249};
250
251&reg_dldo2 {
252 regulator-min-microvolt = <2800000>;
253 regulator-max-microvolt = <4200000>;
254 regulator-name = "vcc-mipi";
255};
256
257&reg_dldo3 {
258 regulator-min-microvolt = <2800000>;
259 regulator-max-microvolt = <2800000>;
260 regulator-name = "vdd-csi";
261};
262
263&reg_dldo4 {
264 regulator-min-microvolt = <2800000>;
265 regulator-max-microvolt = <2800000>;
266 regulator-name = "avdd-csi";
267};
268
269&reg_drivevbus {
270 regulator-name = "usb0-vbus";
271 status = "okay";
272};
273
274&reg_eldo1 {
275 regulator-min-microvolt = <1200000>;
276 regulator-max-microvolt = <1800000>;
277 regulator-name = "dvdd-csi-r";
278};
279
280&reg_eldo2 {
281 regulator-min-microvolt = <1800000>;
282 regulator-max-microvolt = <1800000>;
283 regulator-name = "vcc-dsi";
284};
285
286&reg_eldo3 {
287 regulator-min-microvolt = <1200000>;
288 regulator-max-microvolt = <1800000>;
289 regulator-name = "dvdd-csi-f";
290};
291
292&reg_fldo1 {
293 regulator-min-microvolt = <1200000>;
294 regulator-max-microvolt = <1200000>;
295 regulator-name = "vcc-hsic";
296};
297
298&reg_fldo2 {
299 regulator-min-microvolt = <700000>;
300 regulator-max-microvolt = <1100000>;
301 regulator-always-on;
302 regulator-name = "vdd-cpus";
303};
304
305&reg_ldo_io0 {
306 regulator-min-microvolt = <3100000>;
307 regulator-max-microvolt = <3100000>;
308 regulator-name = "vcc-ctp";
309 status = "okay";
310};
311
312&reg_ldo_io1 {
313 regulator-min-microvolt = <3100000>;
314 regulator-max-microvolt = <3100000>;
315 regulator-name = "vcc-vb";
316 status = "okay";
317};
318
319&reg_sw {
320 regulator-min-microvolt = <3100000>;
321 regulator-max-microvolt = <3100000>;
322 regulator-name = "vcc-lcd";
323};
324
182&uart0 { 325&uart0 {
183 pinctrl-names = "default"; 326 pinctrl-names = "default";
184 pinctrl-0 = <&uart0_pb_pins>; 327 pinctrl-0 = <&uart0_pb_pins>;
@@ -192,8 +335,15 @@
192 status = "okay"; 335 status = "okay";
193}; 336};
194 337
338&usb_otg {
339 dr_mode = "otg";
340 status = "okay";
341};
342
195&usbphy { 343&usbphy {
196 usb1_vbus_supply = <&reg_vcc5v0>; 344 usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
197 usb2_vbus_supply = <&reg_vcc5v0>; 345 usb0_vbus-supply = <&reg_drivevbus>;
346 usb1_vbus_supply = <&reg_vmain>;
347 usb2_vbus_supply = <&reg_vmain>;
198 status = "okay"; 348 status = "okay";
199}; 349};
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index ce6e887c8938..19acae1b4089 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -212,6 +212,8 @@
212 resets = <&ccu RST_BUS_MMC1>; 212 resets = <&ccu RST_BUS_MMC1>;
213 reset-names = "ahb"; 213 reset-names = "ahb";
214 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 214 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
215 pinctrl-names = "default";
216 pinctrl-0 = <&mmc1_pins>;
215 status = "disabled"; 217 status = "disabled";
216 #address-cells = <1>; 218 #address-cells = <1>;
217 #size-cells = <0>; 219 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index b1502df7b509..6713d0f2b3f4 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -56,6 +56,8 @@
56 56
57 aliases { 57 aliases {
58 serial0 = &uart0; 58 serial0 = &uart0;
59 /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
60 ethernet0 = &emac;
59 ethernet1 = &xr819; 61 ethernet1 = &xr819;
60 }; 62 };
61 63
@@ -102,6 +104,13 @@
102 status = "okay"; 104 status = "okay";
103}; 105};
104 106
107&emac {
108 phy-handle = <&int_mii_phy>;
109 phy-mode = "mii";
110 allwinner,leds-active-low;
111 status = "okay";
112};
113
105&mmc0 { 114&mmc0 {
106 pinctrl-names = "default"; 115 pinctrl-names = "default";
107 pinctrl-0 = <&mmc0_pins_a>; 116 pinctrl-0 = <&mmc0_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index e1dba9ffa94b..f2292deaa590 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -52,6 +52,7 @@
52 compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; 52 compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
53 53
54 aliases { 54 aliases {
55 ethernet0 = &emac;
55 serial0 = &uart0; 56 serial0 = &uart0;
56 serial1 = &uart1; 57 serial1 = &uart1;
57 }; 58 };
@@ -111,6 +112,24 @@
111 status = "okay"; 112 status = "okay";
112}; 113};
113 114
115&emac {
116 pinctrl-names = "default";
117 pinctrl-0 = <&emac_rgmii_pins>;
118 phy-supply = <&reg_gmac_3v3>;
119 phy-handle = <&ext_rgmii_phy>;
120 phy-mode = "rgmii";
121
122 allwinner,leds-active-low;
123 status = "okay";
124};
125
126&external_mdio {
127 ext_rgmii_phy: ethernet-phy@1 {
128 compatible = "ethernet-phy-ieee802.3-c22";
129 reg = <0>;
130 };
131};
132
114&ir { 133&ir {
115 pinctrl-names = "default"; 134 pinctrl-names = "default";
116 pinctrl-0 = <&ir_pins_a>; 135 pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
index 73766d38ee6c..0a8b79cf5954 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -51,6 +51,16 @@
51 ethernet1 = &sdio_wifi; 51 ethernet1 = &sdio_wifi;
52 }; 52 };
53 53
54 reg_gmac_3v3: gmac-3v3 {
55 compatible = "regulator-fixed";
56 regulator-name = "gmac-3v3";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 startup-delay-us = <100000>;
60 enable-active-high;
61 gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
62 };
63
54 wifi_pwrseq: wifi_pwrseq { 64 wifi_pwrseq: wifi_pwrseq {
55 compatible = "mmc-pwrseq-simple"; 65 compatible = "mmc-pwrseq-simple";
56 pinctrl-names = "default"; 66 pinctrl-names = "default";
@@ -66,6 +76,25 @@
66 status = "okay"; 76 status = "okay";
67}; 77};
68 78
79&emac {
80 pinctrl-names = "default";
81 pinctrl-0 = <&emac_rgmii_pins>;
82 phy-supply = <&reg_gmac_3v3>;
83 phy-handle = <&ext_rgmii_phy>;
84 phy-mode = "rgmii";
85
86 allwinner,leds-active-low;
87
88 status = "okay";
89};
90
91&external_mdio {
92 ext_rgmii_phy: ethernet-phy@1 {
93 compatible = "ethernet-phy-ieee802.3-c22";
94 reg = <7>;
95 };
96};
97
69&ir { 98&ir {
70 pinctrl-names = "default"; 99 pinctrl-names = "default";
71 pinctrl-0 = <&ir_pins_a>; 100 pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 8d2cc6e9a03f..78f6c24952dd 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -46,3 +46,10 @@
46 model = "FriendlyARM NanoPi NEO"; 46 model = "FriendlyARM NanoPi NEO";
47 compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; 47 compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
48}; 48};
49
50&emac {
51 phy-handle = <&int_mii_phy>;
52 phy-mode = "mii";
53 allwinner,leds-active-low;
54 status = "okay";
55};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 1bf51802f5aa..b20be95b49d5 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -54,6 +54,7 @@
54 aliases { 54 aliases {
55 serial0 = &uart0; 55 serial0 = &uart0;
56 /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ 56 /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
57 ethernet0 = &emac;
57 ethernet1 = &rtl8189; 58 ethernet1 = &rtl8189;
58 }; 59 };
59 60
@@ -117,6 +118,13 @@
117 status = "okay"; 118 status = "okay";
118}; 119};
119 120
121&emac {
122 phy-handle = <&int_mii_phy>;
123 phy-mode = "mii";
124 allwinner,leds-active-low;
125 status = "okay";
126};
127
120&ir { 128&ir {
121 pinctrl-names = "default"; 129 pinctrl-names = "default";
122 pinctrl-0 = <&ir_pins_a>; 130 pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index a1c6ff6fd05d..82e5d28cd698 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -52,6 +52,7 @@
52 compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; 52 compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
53 53
54 aliases { 54 aliases {
55 ethernet0 = &emac;
55 serial0 = &uart0; 56 serial0 = &uart0;
56 }; 57 };
57 58
@@ -97,6 +98,13 @@
97 status = "okay"; 98 status = "okay";
98}; 99};
99 100
101&emac {
102 phy-handle = <&int_mii_phy>;
103 phy-mode = "mii";
104 allwinner,leds-active-low;
105 status = "okay";
106};
107
100&mmc0 { 108&mmc0 {
101 pinctrl-names = "default"; 109 pinctrl-names = "default";
102 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; 110 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
index 8b93f5c781a7..a10281b455f5 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
@@ -53,6 +53,11 @@
53 }; 53 };
54}; 54};
55 55
56&emac {
57 /* LEDs changed to active high on the plus */
58 /delete-property/ allwinner,leds-active-low;
59};
60
56&mmc1 { 61&mmc1 {
57 pinctrl-names = "default"; 62 pinctrl-names = "default";
58 pinctrl-0 = <&mmc1_pins_a>; 63 pinctrl-0 = <&mmc1_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index ea4e0029c0d4..d22546df1b82 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -52,6 +52,7 @@
52 compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; 52 compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
53 53
54 aliases { 54 aliases {
55 ethernet0 = &emac;
55 serial0 = &uart0; 56 serial0 = &uart0;
56 }; 57 };
57 58
@@ -113,6 +114,13 @@
113 status = "okay"; 114 status = "okay";
114}; 115};
115 116
117&emac {
118 phy-handle = <&int_mii_phy>;
119 phy-mode = "mii";
120 allwinner,leds-active-low;
121 status = "okay";
122};
123
116&ir { 124&ir {
117 pinctrl-names = "default"; 125 pinctrl-names = "default";
118 pinctrl-0 = <&ir_pins_a>; 126 pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
index 72ca01b93f1b..cbc499b04de4 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -47,6 +47,10 @@
47 model = "Xunlong Orange Pi Plus / Plus 2"; 47 model = "Xunlong Orange Pi Plus / Plus 2";
48 compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; 48 compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
49 49
50 aliases {
51 ethernet0 = &emac;
52 };
53
50 reg_gmac_3v3: gmac-3v3 { 54 reg_gmac_3v3: gmac-3v3 {
51 compatible = "regulator-fixed"; 55 compatible = "regulator-fixed";
52 regulator-name = "gmac-3v3"; 56 regulator-name = "gmac-3v3";
@@ -74,6 +78,24 @@
74 status = "okay"; 78 status = "okay";
75}; 79};
76 80
81&emac {
82 pinctrl-names = "default";
83 pinctrl-0 = <&emac_rgmii_pins>;
84 phy-supply = <&reg_gmac_3v3>;
85 phy-handle = <&ext_rgmii_phy>;
86 phy-mode = "rgmii";
87
88 allwinner,leds-active-low;
89 status = "okay";
90};
91
92&external_mdio {
93 ext_rgmii_phy: ethernet-phy@1 {
94 compatible = "ethernet-phy-ieee802.3-c22";
95 reg = <0>;
96 };
97};
98
77&mmc2 { 99&mmc2 {
78 pinctrl-names = "default"; 100 pinctrl-names = "default";
79 pinctrl-0 = <&mmc2_8bit_pins>; 101 pinctrl-0 = <&mmc2_8bit_pins>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
index 97920b12a944..6dbf7b2e0c13 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
@@ -61,3 +61,19 @@
61 gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ 61 gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
62 }; 62 };
63}; 63};
64
65&emac {
66 pinctrl-names = "default";
67 pinctrl-0 = <&emac_rgmii_pins>;
68 phy-supply = <&reg_gmac_3v3>;
69 phy-handle = <&ext_rgmii_phy>;
70 phy-mode = "rgmii";
71 status = "okay";
72};
73
74&external_mdio {
75 ext_rgmii_phy: ethernet-phy@1 {
76 compatible = "ethernet-phy-ieee802.3-c22";
77 reg = <1>;
78 };
79};
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index d7a71e726a9f..8d40c00d64bb 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -396,6 +396,55 @@
396 clocks = <&osc24M>; 396 clocks = <&osc24M>;
397 }; 397 };
398 398
399 emac: ethernet@1c30000 {
400 compatible = "allwinner,sun8i-h3-emac";
401 syscon = <&syscon>;
402 reg = <0x01c30000 0x10000>;
403 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
404 interrupt-names = "macirq";
405 resets = <&ccu RST_BUS_EMAC>;
406 reset-names = "stmmaceth";
407 clocks = <&ccu CLK_BUS_EMAC>;
408 clock-names = "stmmaceth";
409 #address-cells = <1>;
410 #size-cells = <0>;
411 status = "disabled";
412
413 mdio: mdio {
414 #address-cells = <1>;
415 #size-cells = <0>;
416 compatible = "snps,dwmac-mdio";
417 };
418
419 mdio-mux {
420 compatible = "allwinner,sun8i-h3-mdio-mux";
421 #address-cells = <1>;
422 #size-cells = <0>;
423
424 mdio-parent-bus = <&mdio>;
425 /* Only one MDIO is usable at the time */
426 internal_mdio: mdio@1 {
427 compatible = "allwinner,sun8i-h3-mdio-internal";
428 reg = <1>;
429 #address-cells = <1>;
430 #size-cells = <0>;
431
432 int_mii_phy: ethernet-phy@1 {
433 compatible = "ethernet-phy-ieee802.3-c22";
434 reg = <1>;
435 clocks = <&ccu CLK_BUS_EPHY>;
436 resets = <&ccu RST_BUS_EPHY>;
437 };
438 };
439
440 external_mdio: mdio@2 {
441 reg = <2>;
442 #address-cells = <1>;
443 #size-cells = <0>;
444 };
445 };
446 };
447
399 spi0: spi@1c68000 { 448 spi0: spi@1c68000 {
400 compatible = "allwinner,sun8i-h3-spi"; 449 compatible = "allwinner,sun8i-h3-spi";
401 reg = <0x01c68000 0x1000>; 450 reg = <0x01c68000 0x1000>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
index 1c2387bd5df6..6eb8092d8e57 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
@@ -50,6 +50,7 @@
50 compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; 50 compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
51 51
52 aliases { 52 aliases {
53 ethernet0 = &emac;
53 serial0 = &uart0; 54 serial0 = &uart0;
54 }; 55 };
55 56
@@ -108,6 +109,22 @@
108 status = "okay"; 109 status = "okay";
109}; 110};
110 111
112&emac {
113 pinctrl-names = "default";
114 pinctrl-0 = <&emac_rgmii_pins>;
115 phy-supply = <&reg_gmac_3v3>;
116 phy-handle = <&ext_rgmii_phy>;
117 phy-mode = "rgmii";
118 status = "okay";
119};
120
121&external_mdio {
122 ext_rgmii_phy: ethernet-phy@7 {
123 compatible = "ethernet-phy-ieee802.3-c22";
124 reg = <7>;
125 };
126};
127
111&mmc0 { 128&mmc0 {
112 pinctrl-names = "default"; 129 pinctrl-names = "default";
113 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; 130 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
index 4f77c8470f6c..a0ca925175aa 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
@@ -59,6 +59,7 @@
59 }; 59 };
60 60
61 aliases { 61 aliases {
62 ethernet0 = &emac;
62 serial0 = &uart0; 63 serial0 = &uart0;
63 }; 64 };
64 65
@@ -136,6 +137,22 @@
136 status = "okay"; 137 status = "okay";
137}; 138};
138 139
140&emac {
141 pinctrl-names = "default";
142 pinctrl-0 = <&emac_rgmii_pins>;
143 phy-supply = <&reg_gmac_3v3>;
144 phy-handle = <&ext_rgmii_phy>;
145 phy-mode = "rgmii";
146 status = "okay";
147};
148
149&external_mdio {
150 ext_rgmii_phy: ethernet-phy@1 {
151 compatible = "ethernet-phy-ieee802.3-c22";
152 reg = <1>;
153 };
154};
155
139&ir { 156&ir {
140 pinctrl-names = "default"; 157 pinctrl-names = "default";
141 pinctrl-0 = <&ir_pins_a>; 158 pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
index 6be06873e5af..b47790650144 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
@@ -54,6 +54,7 @@
54 compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5"; 54 compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5";
55 55
56 aliases { 56 aliases {
57 ethernet0 = &emac;
57 serial0 = &uart0; 58 serial0 = &uart0;
58 }; 59 };
59 60
@@ -143,6 +144,22 @@
143 status = "okay"; 144 status = "okay";
144}; 145};
145 146
147&emac {
148 pinctrl-names = "default";
149 pinctrl-0 = <&emac_rgmii_pins>;
150 phy-supply = <&reg_gmac_3v3>;
151 phy-handle = <&ext_rgmii_phy>;
152 phy-mode = "rgmii";
153 status = "okay";
154};
155
156&external_mdio {
157 ext_rgmii_phy: ethernet-phy@1 {
158 compatible = "ethernet-phy-ieee802.3-c22";
159 reg = <1>;
160 };
161};
162
146&ir { 163&ir {
147 pinctrl-names = "default"; 164 pinctrl-names = "default";
148 pinctrl-0 = <&ir_pins_a>; 165 pinctrl-0 = <&ir_pins_a>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 03:06:43 -0400