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authorGeert Uytterhoeven <geert+renesas@glider.be>2015-11-10 12:59:28 -0500
committerGeert Uytterhoeven <geert+renesas@glider.be>2015-12-17 05:19:08 -0500
commit0a036681888f417e365e0b2935ff6f3f0273f843 (patch)
treef0e3bd8c8c10448f0b4fde3684971a1549348acf
parent6441d314b4d898d871f21196fb5e6e4f82caedc7 (diff)
sh: sh7734: Correct SCIF type for BRG
The SCIF variant in the sh7734 SoC is not the common "SH-4(A)" variant, but a derivative with added "Baud Rate Generator for External Clock" (BRG). Correct the regtype value in platform data to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7734.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
index f617bcb734df..69b8a50310d9 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
@@ -28,7 +28,7 @@ static struct plat_sci_port scif0_platform_data = {
28 .flags = UPF_BOOT_AUTOCONF, 28 .flags = UPF_BOOT_AUTOCONF,
29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
30 .type = PORT_SCIF, 30 .type = PORT_SCIF,
31 .regtype = SCIx_SH4_SCIF_REGTYPE, 31 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
32}; 32};
33 33
34static struct resource scif0_resources[] = { 34static struct resource scif0_resources[] = {
@@ -50,7 +50,7 @@ static struct plat_sci_port scif1_platform_data = {
50 .flags = UPF_BOOT_AUTOCONF, 50 .flags = UPF_BOOT_AUTOCONF,
51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
52 .type = PORT_SCIF, 52 .type = PORT_SCIF,
53 .regtype = SCIx_SH4_SCIF_REGTYPE, 53 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
54}; 54};
55 55
56static struct resource scif1_resources[] = { 56static struct resource scif1_resources[] = {
@@ -72,7 +72,7 @@ static struct plat_sci_port scif2_platform_data = {
72 .flags = UPF_BOOT_AUTOCONF, 72 .flags = UPF_BOOT_AUTOCONF,
73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
74 .type = PORT_SCIF, 74 .type = PORT_SCIF,
75 .regtype = SCIx_SH4_SCIF_REGTYPE, 75 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
76}; 76};
77 77
78static struct resource scif2_resources[] = { 78static struct resource scif2_resources[] = {
@@ -94,7 +94,7 @@ static struct plat_sci_port scif3_platform_data = {
94 .flags = UPF_BOOT_AUTOCONF, 94 .flags = UPF_BOOT_AUTOCONF,
95 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 95 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
96 .type = PORT_SCIF, 96 .type = PORT_SCIF,
97 .regtype = SCIx_SH4_SCIF_REGTYPE, 97 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
98}; 98};
99 99
100static struct resource scif3_resources[] = { 100static struct resource scif3_resources[] = {
@@ -116,7 +116,7 @@ static struct plat_sci_port scif4_platform_data = {
116 .flags = UPF_BOOT_AUTOCONF, 116 .flags = UPF_BOOT_AUTOCONF,
117 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 117 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
118 .type = PORT_SCIF, 118 .type = PORT_SCIF,
119 .regtype = SCIx_SH4_SCIF_REGTYPE, 119 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
120}; 120};
121 121
122static struct resource scif4_resources[] = { 122static struct resource scif4_resources[] = {
@@ -138,7 +138,7 @@ static struct plat_sci_port scif5_platform_data = {
138 .flags = UPF_BOOT_AUTOCONF, 138 .flags = UPF_BOOT_AUTOCONF,
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
140 .type = PORT_SCIF, 140 .type = PORT_SCIF,
141 .regtype = SCIx_SH4_SCIF_REGTYPE, 141 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
142}; 142};
143 143
144static struct resource scif5_resources[] = { 144static struct resource scif5_resources[] = {