diff options
author | Anson Huang <Anson.Huang@nxp.com> | 2018-08-31 03:53:16 -0400 |
---|---|---|
committer | Stephen Boyd <sboyd@kernel.org> | 2018-10-17 14:15:51 -0400 |
commit | 09d47620d0f839bc4bf3d3061aabee0c9539407a (patch) | |
tree | fe5d09bfb391b0cd85f5703ee06a46e0fbd90e35 | |
parent | aac7ff2048a881975fceb41ae6545730dee310d2 (diff) |
clk: imx6sl: add mmdc ipg clocks
i.MX6SL has MMDC0 and MMDC1 ipg clock in CCM CCGR, add them into
clock tree for clock management.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
-rw-r--r-- | drivers/clk/imx/clk-imx6sl.c | 2 | ||||
-rw-r--r-- | include/dt-bindings/clock/imx6sl-clock.h | 4 |
2 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c index eb6bcbf345a3..6fcfbbd907a5 100644 --- a/drivers/clk/imx/clk-imx6sl.c +++ b/drivers/clk/imx/clk-imx6sl.c | |||
@@ -386,6 +386,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) | |||
386 | clks[IMX6SL_CLK_LCDIF_AXI] = imx_clk_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6); | 386 | clks[IMX6SL_CLK_LCDIF_AXI] = imx_clk_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6); |
387 | clks[IMX6SL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8); | 387 | clks[IMX6SL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8); |
388 | clks[IMX6SL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10); | 388 | clks[IMX6SL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10); |
389 | clks[IMX6SL_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); | ||
390 | clks[IMX6SL_CLK_MMDC_P1_IPG] = imx_clk_gate2("mmdc_p1_ipg", "ipg", base + 0x74, 26); | ||
389 | clks[IMX6SL_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28); | 391 | clks[IMX6SL_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28); |
390 | clks[IMX6SL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); | 392 | clks[IMX6SL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); |
391 | clks[IMX6SL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); | 393 | clks[IMX6SL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); |
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h index e14573e293c5..cfbfc39d1878 100644 --- a/include/dt-bindings/clock/imx6sl-clock.h +++ b/include/dt-bindings/clock/imx6sl-clock.h | |||
@@ -175,6 +175,8 @@ | |||
175 | #define IMX6SL_CLK_SSI2_IPG 162 | 175 | #define IMX6SL_CLK_SSI2_IPG 162 |
176 | #define IMX6SL_CLK_SSI3_IPG 163 | 176 | #define IMX6SL_CLK_SSI3_IPG 163 |
177 | #define IMX6SL_CLK_SPDIF_GCLK 164 | 177 | #define IMX6SL_CLK_SPDIF_GCLK 164 |
178 | #define IMX6SL_CLK_END 165 | 178 | #define IMX6SL_CLK_MMDC_P0_IPG 165 |
179 | #define IMX6SL_CLK_MMDC_P1_IPG 166 | ||
180 | #define IMX6SL_CLK_END 167 | ||
179 | 181 | ||
180 | #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ | 182 | #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ |