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authorRex Zhu <Rex.Zhu@amd.com>2018-03-22 02:38:37 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-03-23 10:42:42 -0400
commit09695ad78f1f5f315c7e9c5090f0c7b846a43690 (patch)
tree51912434d694d0fe1d1174719442aaec6d9ee468
parent5b2933556fe02b3576758609918694a9e2a031d0 (diff)
drm/amd/pp: clean header file hwmgr.h
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h3
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/hwmgr.h15
2 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
index 6429dc2f2df9..d37d16e4b613 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
@@ -27,6 +27,9 @@ struct pp_atomctrl_voltage_table;
27struct pp_hwmgr; 27struct pp_hwmgr;
28struct phm_ppt_v1_voltage_lookup_table; 28struct phm_ppt_v1_voltage_lookup_table;
29 29
30uint8_t convert_to_vid(uint16_t vddc);
31uint16_t convert_to_vddc(uint8_t vid);
32
30extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr, 33extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
31 uint32_t index, 34 uint32_t index,
32 uint32_t value, uint32_t mask); 35 uint32_t value, uint32_t mask);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index d742d9d087f0..17f811d181c8 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -39,9 +39,6 @@ struct pp_atomctrl_voltage_table;
39 39
40#define VOLTAGE_SCALE 4 40#define VOLTAGE_SCALE 4
41 41
42uint8_t convert_to_vid(uint16_t vddc);
43uint16_t convert_to_vddc(uint8_t vid);
44
45enum DISPLAY_GAP { 42enum DISPLAY_GAP {
46 DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */ 43 DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
47 DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */ 44 DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
@@ -784,12 +781,12 @@ struct pp_hwmgr {
784 uint32_t workload_setting[Workload_Policy_Max]; 781 uint32_t workload_setting[Workload_Policy_Max];
785}; 782};
786 783
787extern int hwmgr_early_init(struct pp_hwmgr *hwmgr); 784int hwmgr_early_init(struct pp_hwmgr *hwmgr);
788extern int hwmgr_hw_init(struct pp_hwmgr *hwmgr); 785int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
789extern int hwmgr_hw_fini(struct pp_hwmgr *hwmgr); 786int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
790extern int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr); 787int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
791extern int hwmgr_hw_resume(struct pp_hwmgr *hwmgr); 788int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
792extern int hwmgr_handle_task(struct pp_hwmgr *hwmgr, 789int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
793 enum amd_pp_task task_id, 790 enum amd_pp_task task_id,
794 enum amd_pm_state_type *user_state); 791 enum amd_pm_state_type *user_state);
795 792