diff options
author | Dave Airlie <airlied@redhat.com> | 2014-07-09 20:09:33 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2014-07-09 20:09:33 -0400 |
commit | 093fa5d05332f3e53396ca2dc10a25c50d58b68b (patch) | |
tree | 2b991520dcc975b441cb95f44ef64c0c9a453d56 | |
parent | 4f440cd534359f689cb577c68f8491d1eddf0b76 (diff) | |
parent | 0b4e8e7fd506d4ddb96f71230252d14066ce1597 (diff) |
Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-fixes
A couple of DP regression fixes, kepler memory reclocking fixes, and a fix for an annoying display issue that can pop up on resume.
* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6:
drm/nouveau/ram: fix test for gpio presence
drm/nouveau/dp: workaround broken display
drm/nouveau/dp: fix required link bandwidth calculations
drm/nouveau/kms: restore fbcon after display has been resumed
drm/nv50-/kms: pass a non-zero value for head to sor dpms methods
drm/nouveau/fb: Prevent inlining of ramfuc_reg
drm/gk104/ram: bash mpll bit 31 on
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nv50.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drm.c | 17 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_fbcon.c | 13 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_fbcon.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_display.c | 3 |
10 files changed, 29 insertions, 31 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c index 26e962b7e702..2283c442a10d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c | |||
@@ -1516,11 +1516,11 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) | |||
1516 | } | 1516 | } |
1517 | 1517 | ||
1518 | switch ((ctrl & 0x000f0000) >> 16) { | 1518 | switch ((ctrl & 0x000f0000) >> 16) { |
1519 | case 6: datarate = pclk * 30 / 8; break; | 1519 | case 6: datarate = pclk * 30; break; |
1520 | case 5: datarate = pclk * 24 / 8; break; | 1520 | case 5: datarate = pclk * 24; break; |
1521 | case 2: | 1521 | case 2: |
1522 | default: | 1522 | default: |
1523 | datarate = pclk * 18 / 8; | 1523 | datarate = pclk * 18; |
1524 | break; | 1524 | break; |
1525 | } | 1525 | } |
1526 | 1526 | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c index 48aa38a87e3f..fa30d8196f35 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c | |||
@@ -1159,11 +1159,11 @@ nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head) | |||
1159 | if (outp->info.type == DCB_OUTPUT_DP) { | 1159 | if (outp->info.type == DCB_OUTPUT_DP) { |
1160 | u32 sync = nv_rd32(priv, 0x660404 + (head * 0x300)); | 1160 | u32 sync = nv_rd32(priv, 0x660404 + (head * 0x300)); |
1161 | switch ((sync & 0x000003c0) >> 6) { | 1161 | switch ((sync & 0x000003c0) >> 6) { |
1162 | case 6: pclk = pclk * 30 / 8; break; | 1162 | case 6: pclk = pclk * 30; break; |
1163 | case 5: pclk = pclk * 24 / 8; break; | 1163 | case 5: pclk = pclk * 24; break; |
1164 | case 2: | 1164 | case 2: |
1165 | default: | 1165 | default: |
1166 | pclk = pclk * 18 / 8; | 1166 | pclk = pclk * 18; |
1167 | break; | 1167 | break; |
1168 | } | 1168 | } |
1169 | 1169 | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c b/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c index 52c299c3d300..eb2d7789555d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c | |||
@@ -34,7 +34,7 @@ nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait) | |||
34 | struct nvkm_output_dp *outp = (void *)base; | 34 | struct nvkm_output_dp *outp = (void *)base; |
35 | bool retrain = true; | 35 | bool retrain = true; |
36 | u8 link[2], stat[3]; | 36 | u8 link[2], stat[3]; |
37 | u32 rate; | 37 | u32 linkrate; |
38 | int ret, i; | 38 | int ret, i; |
39 | 39 | ||
40 | /* check that the link is trained at a high enough rate */ | 40 | /* check that the link is trained at a high enough rate */ |
@@ -44,8 +44,10 @@ nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait) | |||
44 | goto done; | 44 | goto done; |
45 | } | 45 | } |
46 | 46 | ||
47 | rate = link[0] * 27000 * (link[1] & DPCD_LC01_LANE_COUNT_SET); | 47 | linkrate = link[0] * 27000 * (link[1] & DPCD_LC01_LANE_COUNT_SET); |
48 | if (rate < ((datarate / 8) * 10)) { | 48 | linkrate = (linkrate * 8) / 10; /* 8B/10B coding overhead */ |
49 | datarate = (datarate + 9) / 10; /* -> decakilobits */ | ||
50 | if (linkrate < datarate) { | ||
49 | DBG("link not trained at sufficient rate\n"); | 51 | DBG("link not trained at sufficient rate\n"); |
50 | goto done; | 52 | goto done; |
51 | } | 53 | } |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c index e1832778e8b6..7a1ebdfa9e1b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c | |||
@@ -87,6 +87,7 @@ nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size) | |||
87 | struct nvkm_output_dp *outpdp = (void *)outp; | 87 | struct nvkm_output_dp *outpdp = (void *)outp; |
88 | switch (data) { | 88 | switch (data) { |
89 | case NV94_DISP_SOR_DP_PWR_STATE_OFF: | 89 | case NV94_DISP_SOR_DP_PWR_STATE_OFF: |
90 | nouveau_event_put(outpdp->irq); | ||
90 | ((struct nvkm_output_dp_impl *)nv_oclass(outp)) | 91 | ((struct nvkm_output_dp_impl *)nv_oclass(outp)) |
91 | ->lnk_pwr(outpdp, 0); | 92 | ->lnk_pwr(outpdp, 0); |
92 | atomic_set(&outpdp->lt.done, 0); | 93 | atomic_set(&outpdp->lt.done, 0); |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h index 0f57fcfe0bbf..2af9cfd2c60f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h | |||
@@ -26,7 +26,7 @@ ramfuc_reg2(u32 addr1, u32 addr2) | |||
26 | }; | 26 | }; |
27 | } | 27 | } |
28 | 28 | ||
29 | static inline struct ramfuc_reg | 29 | static noinline struct ramfuc_reg |
30 | ramfuc_reg(u32 addr) | 30 | ramfuc_reg(u32 addr) |
31 | { | 31 | { |
32 | return ramfuc_reg2(addr, addr); | 32 | return ramfuc_reg2(addr, addr); |
@@ -107,7 +107,7 @@ ramfuc_nsec(struct ramfuc *ram, u32 nsec) | |||
107 | 107 | ||
108 | #define ram_init(s,p) ramfuc_init(&(s)->base, (p)) | 108 | #define ram_init(s,p) ramfuc_init(&(s)->base, (p)) |
109 | #define ram_exec(s,e) ramfuc_exec(&(s)->base, (e)) | 109 | #define ram_exec(s,e) ramfuc_exec(&(s)->base, (e)) |
110 | #define ram_have(s,r) ((s)->r_##r.addr != 0x000000) | 110 | #define ram_have(s,r) ((s)->r_##r.addr[0] != 0x000000) |
111 | #define ram_rd32(s,r) ramfuc_rd32(&(s)->base, &(s)->r_##r) | 111 | #define ram_rd32(s,r) ramfuc_rd32(&(s)->base, &(s)->r_##r) |
112 | #define ram_wr32(s,r,d) ramfuc_wr32(&(s)->base, &(s)->r_##r, (d)) | 112 | #define ram_wr32(s,r,d) ramfuc_wr32(&(s)->base, &(s)->r_##r, (d)) |
113 | #define ram_nuke(s,r) ramfuc_nuke(&(s)->base, &(s)->r_##r) | 113 | #define ram_nuke(s,r) ramfuc_nuke(&(s)->base, &(s)->r_##r) |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c index 1ad3ea503133..c5b46e302319 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c | |||
@@ -200,6 +200,7 @@ r1373f4_init(struct nve0_ramfuc *fuc) | |||
200 | /* (re)program mempll, if required */ | 200 | /* (re)program mempll, if required */ |
201 | if (ram->mode == 2) { | 201 | if (ram->mode == 2) { |
202 | ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000); | 202 | ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000); |
203 | ram_mask(fuc, 0x132000, 0x80000000, 0x80000000); | ||
203 | ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); | 204 | ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); |
204 | ram_mask(fuc, 0x132004, 0x103fffff, mcoef); | 205 | ram_mask(fuc, 0x132004, 0x103fffff, mcoef); |
205 | ram_mask(fuc, 0x132000, 0x00000001, 0x00000001); | 206 | ram_mask(fuc, 0x132000, 0x00000001, 0x00000001); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index ddd83756b9a2..5425ffe3931d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c | |||
@@ -652,12 +652,12 @@ int nouveau_pmops_resume(struct device *dev) | |||
652 | ret = nouveau_do_resume(drm_dev); | 652 | ret = nouveau_do_resume(drm_dev); |
653 | if (ret) | 653 | if (ret) |
654 | return ret; | 654 | return ret; |
655 | if (drm_dev->mode_config.num_crtc) | ||
656 | nouveau_fbcon_set_suspend(drm_dev, 0); | ||
657 | 655 | ||
658 | nouveau_fbcon_zfill_all(drm_dev); | 656 | if (drm_dev->mode_config.num_crtc) { |
659 | if (drm_dev->mode_config.num_crtc) | ||
660 | nouveau_display_resume(drm_dev); | 657 | nouveau_display_resume(drm_dev); |
658 | nouveau_fbcon_set_suspend(drm_dev, 0); | ||
659 | } | ||
660 | |||
661 | return 0; | 661 | return 0; |
662 | } | 662 | } |
663 | 663 | ||
@@ -683,11 +683,12 @@ static int nouveau_pmops_thaw(struct device *dev) | |||
683 | ret = nouveau_do_resume(drm_dev); | 683 | ret = nouveau_do_resume(drm_dev); |
684 | if (ret) | 684 | if (ret) |
685 | return ret; | 685 | return ret; |
686 | if (drm_dev->mode_config.num_crtc) | 686 | |
687 | nouveau_fbcon_set_suspend(drm_dev, 0); | 687 | if (drm_dev->mode_config.num_crtc) { |
688 | nouveau_fbcon_zfill_all(drm_dev); | ||
689 | if (drm_dev->mode_config.num_crtc) | ||
690 | nouveau_display_resume(drm_dev); | 688 | nouveau_display_resume(drm_dev); |
689 | nouveau_fbcon_set_suspend(drm_dev, 0); | ||
690 | } | ||
691 | |||
691 | return 0; | 692 | return 0; |
692 | } | 693 | } |
693 | 694 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index 64a42cfd3717..191665ee7f52 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c | |||
@@ -531,17 +531,10 @@ nouveau_fbcon_set_suspend(struct drm_device *dev, int state) | |||
531 | if (state == 1) | 531 | if (state == 1) |
532 | nouveau_fbcon_save_disable_accel(dev); | 532 | nouveau_fbcon_save_disable_accel(dev); |
533 | fb_set_suspend(drm->fbcon->helper.fbdev, state); | 533 | fb_set_suspend(drm->fbcon->helper.fbdev, state); |
534 | if (state == 0) | 534 | if (state == 0) { |
535 | nouveau_fbcon_restore_accel(dev); | 535 | nouveau_fbcon_restore_accel(dev); |
536 | nouveau_fbcon_zfill(dev, drm->fbcon); | ||
537 | } | ||
536 | console_unlock(); | 538 | console_unlock(); |
537 | } | 539 | } |
538 | } | 540 | } |
539 | |||
540 | void | ||
541 | nouveau_fbcon_zfill_all(struct drm_device *dev) | ||
542 | { | ||
543 | struct nouveau_drm *drm = nouveau_drm(dev); | ||
544 | if (drm->fbcon) { | ||
545 | nouveau_fbcon_zfill(dev, drm->fbcon); | ||
546 | } | ||
547 | } | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.h b/drivers/gpu/drm/nouveau/nouveau_fbcon.h index fdfc0c94fbcc..fcff797d2084 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.h +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.h | |||
@@ -61,7 +61,6 @@ void nouveau_fbcon_gpu_lockup(struct fb_info *info); | |||
61 | int nouveau_fbcon_init(struct drm_device *dev); | 61 | int nouveau_fbcon_init(struct drm_device *dev); |
62 | void nouveau_fbcon_fini(struct drm_device *dev); | 62 | void nouveau_fbcon_fini(struct drm_device *dev); |
63 | void nouveau_fbcon_set_suspend(struct drm_device *dev, int state); | 63 | void nouveau_fbcon_set_suspend(struct drm_device *dev, int state); |
64 | void nouveau_fbcon_zfill_all(struct drm_device *dev); | ||
65 | void nouveau_fbcon_save_disable_accel(struct drm_device *dev); | 64 | void nouveau_fbcon_save_disable_accel(struct drm_device *dev); |
66 | void nouveau_fbcon_restore_accel(struct drm_device *dev); | 65 | void nouveau_fbcon_restore_accel(struct drm_device *dev); |
67 | 66 | ||
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index afdf607df3e6..4c534b7b04da 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c | |||
@@ -1741,7 +1741,8 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode) | |||
1741 | } | 1741 | } |
1742 | } | 1742 | } |
1743 | 1743 | ||
1744 | mthd = (ffs(nv_encoder->dcb->sorconf.link) - 1) << 2; | 1744 | mthd = (ffs(nv_encoder->dcb->heads) - 1) << 3; |
1745 | mthd |= (ffs(nv_encoder->dcb->sorconf.link) - 1) << 2; | ||
1745 | mthd |= nv_encoder->or; | 1746 | mthd |= nv_encoder->or; |
1746 | 1747 | ||
1747 | if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { | 1748 | if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { |