m68k: coldfire: add dspi0 module support

This patch adds initial module base address and irq for dspi0.
It also defines the dspi0 clock to be used by the Freescale driver.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>

2 files changed, 8 insertions, 1 deletions

diff --git a/arch/m68k/coldfire/m5441x.c b/arch/m68k/coldfire/m5441x.c
index 315d14b0dca0..55392af845fb 100644
--- a/arch/m68k/coldfire/m5441x.c
+++ b/arch/m68k/coldfire/m5441x.c
@@ -27,7 +27,7 @@ DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
 DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
 DEFINE_CLK(0, "intc.2", 20, MCF_CLK);
 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
-DEFINE_CLK(0, "mcfdspi.0", 23, MCF_CLK);
+DEFINE_CLK(0, "fsl-dspi.0", 23, MCF_CLK);
 DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
 DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
 DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
@@ -140,6 +140,7 @@ static struct clk * const enable_clks[] __initconst = {
         &__clk_0_18, /* intc0 */
         &__clk_0_19, /* intc0 */
         &__clk_0_20, /* intc0 */
+        &__clk_0_23, /* dspi.0 */
         &__clk_0_24, /* uart0 */
         &__clk_0_25, /* uart1 */
         &__clk_0_26, /* uart2 */
diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h
index 4e9095b9480a..c87556d5581c 100644
--- a/arch/m68k/include/asm/m5441xsim.h
+++ b/arch/m68k/include/asm/m5441xsim.h
@@ -278,4 +278,10 @@
 #define MCFGPIO_IRQ_VECBASE     (MCFINT_VECBASE - MCFGPIO_IRQ_MIN)
 #define MCFGPIO_PIN_MAX         87
 
+/*
+ *  DSPI module.
+ */
+#define MCFDSPI_BASE0           0xfc05c000
+#define MCF_IRQ_DSPI0           (MCFINT0_VECBASE + MCFINT0_DSPI0)
+
 #endif /* m5441xsim_h */