aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorVineet Gupta <vgupta@synopsys.com>2016-12-19 14:38:38 -0500
committerVineet Gupta <vgupta@synopsys.com>2016-12-19 14:55:17 -0500
commit08fe007968b2b45e831daf74899f79a54d73f773 (patch)
treecee4913c5c57caf93c839489bcbeb5de1c07c867
parentf64915be2d8c629e7b55ad37f90bd8db2713426e (diff)
ARC: mm: arc700: Don't assume 2 colours for aliasing VIPT dcache
An ARC700 customer reported linux boot crashes when upgrading to bigger L1 dcache (64K from 32K). Turns out they had an aliasing VIPT config and current code only assumed 2 colours, while theirs had 4. So default to 4 colours and complain if there are fewer. Ideally this needs to be a Kconfig option, but heck that's too much of hassle for a single user. Cc: stable@vger.kernel.org Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
-rw-r--r--arch/arc/include/asm/cacheflush.h6
-rw-r--r--arch/arc/mm/cache.c13
2 files changed, 13 insertions, 6 deletions
diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h
index a093adbdb017..fc662f49c55a 100644
--- a/arch/arc/include/asm/cacheflush.h
+++ b/arch/arc/include/asm/cacheflush.h
@@ -85,6 +85,10 @@ void flush_anon_page(struct vm_area_struct *vma,
85 */ 85 */
86#define PG_dc_clean PG_arch_1 86#define PG_dc_clean PG_arch_1
87 87
88#define CACHE_COLORS_NUM 4
89#define CACHE_COLORS_MSK (CACHE_COLORS_NUM - 1)
90#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & CACHE_COLORS_MSK)
91
88/* 92/*
89 * Simple wrapper over config option 93 * Simple wrapper over config option
90 * Bootup code ensures that hardware matches kernel configuration 94 * Bootup code ensures that hardware matches kernel configuration
@@ -94,8 +98,6 @@ static inline int cache_is_vipt_aliasing(void)
94 return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); 98 return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
95} 99}
96 100
97#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 1)
98
99/* 101/*
100 * checks if two addresses (after page aligning) index into same cache set 102 * checks if two addresses (after page aligning) index into same cache set
101 */ 103 */
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index a0ce8ff1e59c..ec86ac0e3321 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -972,11 +972,16 @@ void arc_cache_init(void)
972 /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */ 972 /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */
973 if (is_isa_arcompact()) { 973 if (is_isa_arcompact()) {
974 int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); 974 int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
975 975 int num_colors = dc->sz_k/dc->assoc/TO_KB(PAGE_SIZE);
976 if (dc->alias && !handled) 976
977 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); 977 if (dc->alias) {
978 else if (!dc->alias && handled) 978 if (!handled)
979 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
980 if (CACHE_COLORS_NUM != num_colors)
981 panic("CACHE_COLORS_NUM not optimized for config\n");
982 } else if (!dc->alias && handled) {
979 panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); 983 panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
984 }
980 } 985 }
981 } 986 }
982 987