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authorBalbir Singh <bsingharora@gmail.com>2017-02-02 00:03:43 -0500
committerMichael Ellerman <mpe@ellerman.id.au>2017-02-15 04:02:42 -0500
commit08d96e0b127e07c3b90e10f1939caf70b456793e (patch)
treefcb8ab8b93289aff4ee7025d9fa97b1da9259236
parentcc7639ce18b950086c7b06e00350652db3732183 (diff)
powerpc/xmon: Apply binutils changes to upgrade disassembly
The following commit-ids from the binutils project were applied on the xmon branch and relicensed with the permission of the authors under GPLv2 for the following files: ppc-opc.c ppc-dis.c ppc.h Working off of binutils commit 65b650b4c746 we have now moved up to binutils commit a5721ba270dd. Some commit logs have been taken verbatim, some are summarized for ease of understanding. Here is a summary of the commits: 33e8d5ac613d PPC7450 New. (powerpc_opcodes): Use it in dcba. c3d65c1ced61 New opcodes and mask 8dbcd839b1bb Instruction Sorting 91eb7075e370 (powerpc_opcodes): Fix the first two operands of dquaiq. 548b1dcfcbab ppc-opc.c (powerpc_opcodes): Remove the dcffix and dcffix. 930bb4cfae30 Support optional L form mtmsr. de866fccd87d (powerpc_opcodes): Order and format. 19a6653ce8c6 ppc e500mc support fa452fa6833c (ppc_cpu_t): New typedef. c8187e1509b2 (parse_cpu): Handle -m464. 081ba1b3c08b Define. (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI) 9b4e57660d38 Rename altivec_or_spe to retain_flags. Handle -mvsx and -mpower7. 899d85beadd0 (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300. e1c93c699b7d (extract_sprg): Correct operand range check. 2f3bb96af796 (powerpc_init_dialect): Do not set PPC_OPCODE_BOOKE 1cb0a7674666 (ppc_setup_opcodes): Remove PPC_OPCODE_NOPOWER4 test 21169fcfadfa (print_insn_powerpc): Skip insn if it is deprecated 80890a619b85 ("dcbt", "dcbtst") 0e55be1624c2 ("lfdepx", "stfdepx") 066be9f7bd8e (parse_cpu): Extend -mpower7 to accept power7 and isel instructions. c72ab5f2c55d (powerpc_opcodes): Reorder the opcode table so that instructions 69fe9ce501f5 (ppc_parse_cpu): New function. (powerpc_init_dialect) e401b04ca7cd (powerpc_opcodes) <"dcbzl">: Merge the POWER4 and E500MC entries. 70dc4e324b9a (powerpc_init_dialect): Do not choose a default dialect due to -many/-Many. 858d7a6db20b (powerpc_opcodes) <"tlbilxlpid", "tlbilxpid", "tlbilxva", "tlbilx" bdc7fcfe59f1 (powerpc_macros <extrdi>): Allow n+b of 64 e0d602ecffb0 (md_show_usage): Document -mpcca2 b961e85b6ebe (ppc_cpu_t): Typedef to uint64_t 8765b5569284 (powerpc_opcodes): Remove support for the the "lxsdux", "lxvd2ux" 634b50f2a623 Rename "ppca2" to "a2" 9fe54b1ca1c0 (md_show_usage): Document -m476 0dc9305793c8 Add bfd_mach_ppc_e500mc64 ce3d2015b21b Define. bfd/ * archures.c (bfd_mach_ppc_titan) cdc51b0748c4 Add -mpwr4, -mpwr5, -mpwr5x, -mpwr6 and -mpwr7 63d0fa4e9e57 Add PPC_OPCODE_E500MC for "e500mc64" cee62821d472 New Define. ("dccci"): Enable for PPCA2 85d4ac0b3c0b Correct wclr encoding. 51b5d4a8c5e5 (powerpc_opcodes): Enable divdeu, devweu, divde, divwe, divdeuo e01d869a3be2 (md_assemble): Emit APUinfo section for PPC_OPCODE_E500 09a8ad8d8f56 (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf and mtocrf on EFS. f2bae120dcef (PPC_OPCODE_COMMON): Expand comment. 81a0b7e2ae09 (PPCPWR2): Add PPC_OPCODE_COMMON. (powerpc_opcodes): Add "subc" bdc70b4a03fd (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC) 7102e95e4943 (ppc_set_cpu): Cast PPC_OPCODE_xxx to ppc_cpu_t before inverting f383de6633cb (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate on E500 and E500MC 6b069ee70de3 Remove PPC_OPCODE_PPCPS 2f7f77101279 (powerpc_opcodes): Enable icswx for POWER7 989993d80a97 (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX, RBX) a08fc94222d1 <drrndq, drrndq., dtstexq, dctqpq, dctqpq., dctfixq, dctfixq. 8ebac3aae962 (ISA_V2): Define and use for relevant BO field tests aea77599d0db Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR b240011aba98 (disassemble_init_for_target): Handle ppc init. d668828207c2 (powerpc_opcd_indices): Bump array size b9c361e0ad33 Add support for PowerPC VLE. e1dad58d73dc (has_tls_reloc, has_tls_get_addr_call, has_vle_insns, is_ppc_vle) df7b86aa4cb6 Add check that sysdep.h has been included before 98c76446ea6b (extract_sprg): Use ALLOW8_SPRG to include VLE. a4ebc835cbcb (powerpc_macros): Add entries for e_extlwi to e_clrlslwi 94caa966375d (has_vle_insns, is_ppc_vle): Delete c7a8dbf91f37 Change RA to RA0 d908c8af5a1d Add necessary casts for printing integer values 03edbe3bfb93 Add/remove PPCVLE for some 32-bit insns 9f6a6cc022e1 <xnop, yield, mdoio, mdoom>: New extended mnemonics 588925d06545 <RSQ, RTQ>: Use PPC_OPERAND_GPR 8baf7b78b5d9 <"lswx">: Use RAX for the second and RBX for the third operand e67ed0e885d6 Changed opcode for vabsdub, vabsduh, vabsduw, mviwsplt fb048c26f19f (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK, VXVDVA_MASK 382c72e90441 (VXASHB_MASK): New define c7a5aa9c64fc (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2 ab4437c3224f <vcfpsxws>: Fix opcode spelling 62082a42b9cd "lfdp" and "stfdp" use DS offset. 776fc41826bb (ppc_parse_cpu): Update prototype 943d398f4c52 (insert_sci8, extract_sci8): Rewrite. 5817ffd1f81c New define (PPC_OPCODE_HTM/POWER8) 9f0682fe89d9 (extract_vlesi): Properly sign extend c0637f3af686 (powerpc_init_dialect): Set default dialect to power8. 58ae08f29af8 (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu 4f6ffcd38d90 (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect 4b95cf5c0c75 Update copyright years a47622ac1bad Allow both signed and unsigned fields in PowerPC cmpli insn 12e87fac5c76 ppc: enable msgclr and msgsnd on Power8 8514e4db84cc Don't deprecate powerpc mftb insn db76a70026ab Power4 should treat mftb as extended mfspr mnemonic b90efa5b79ac ChangeLog rotatation and copyright year update c4e676f19656 powerpc: Add slbfee. instruction 27c49e9a8fc0 powerpc: Only initialise opcode indices once 4fff86c517ab DCBT_EO): New define 4bc0608a8b69 Fix some PPC assembler errors dc302c00611b Add hwsync extended mnemonic 99a2c5612124 Remove unused MTMSRD_L macro and re-add accidentally deleted comment 11a0cf2ec0ed Allow for optional operands with non-zero default values 7b9341139a69 PPC sync instruction accepts invalid and incompatible operands ef5a96d564a2 Remove ppc860, ppc750cl, ppc7450 insns from common ppc 43e65147c07b Remove trailing spaces in opcodes 6dca4fd141fd Add dscr and ctrl SPR mnemonics b6518b387185 Fix compile time warnings generated when compiling with clang 36f7a9411dcd Patches for illegal ppc 500 instructions a680de9a980e Add assembler, disassembler and linker support for power9 dd2887fc3de4 Reorder some power9 insns b817670b52b7 Enable 2 operand form of powerpc mfcr with -many 6f2750feaf28 Copyright update for binutils afa8d4054b8e Delete opcodes that have been removed from ISA 3.0 1178da445ad5 Accept valid one byte signed and unsigned values for the IMM8 operand e43de63c8fd1 Fix powerpc subis range 514e58b72633 Correct "Fix powerpc subis range" 19dfcc89e8d9 Add support for new POWER ISA 3.0 instructions 1fe0971e41a4 add more extern C 026122a67044 Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu 14b57c7c6a53 PowerPC VLE 6fd3a02da554 Add support for yet some more new ISA 3.0 instructions dfdaec14b0db Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions fd486b633e87 Modify POWER9 support to match final ISA 3.0 documentation a5721ba270dd Disallow 3-operand cmp[l][i] for ppc64 This updates the disassembly capabilities to add support for newer processors. Signed-off-by: Balbir Singh <bsingharora@gmail.com> [mpe: Reformat commit list for brevity] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat
-rw-r--r--arch/powerpc/xmon/ppc-dis.c710
-rw-r--r--arch/powerpc/xmon/ppc-opc.c8555
-rw-r--r--arch/powerpc/xmon/ppc.h222
3 files changed, 6292 insertions, 3195 deletions
diff --git a/arch/powerpc/xmon/ppc-dis.c b/arch/powerpc/xmon/ppc-dis.c
index 2545a36f21a5..c382d13c88a3 100644
--- a/arch/powerpc/xmon/ppc-dis.c
+++ b/arch/powerpc/xmon/ppc-dis.c
@@ -1,6 +1,5 @@
1/* ppc-dis.c -- Disassemble PowerPC instructions 1/* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support 3 Written by Ian Lance Taylor, Cygnus Support
5 4
6This file is part of GDB, GAS, and the GNU binutils. 5This file is part of GDB, GAS, and the GNU binutils.
@@ -19,9 +18,12 @@ You should have received a copy of the GNU General Public License
19along with this file; see the file COPYING. If not, write to the Free 18along with this file; see the file COPYING. If not, write to the Free
20Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 19Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
21 20
22#include <stdio.h>
23#include "sysdep.h" 21#include "sysdep.h"
22#include <stdio.h>
24#include "dis-asm.h" 23#include "dis-asm.h"
24#include "elf-bfd.h"
25#include "elf/ppc.h"
26#include "opintl.h"
25#include "opcode/ppc.h" 27#include "opcode/ppc.h"
26 28
27/* This file provides several disassembler functions, all of which use 29/* This file provides several disassembler functions, all of which use
@@ -29,76 +31,380 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
29 are provided because this file handles disassembly for the PowerPC 31 are provided because this file handles disassembly for the PowerPC
30 in both big and little endian mode and also for the POWER (RS/6000) 32 in both big and little endian mode and also for the POWER (RS/6000)
31 chip. */ 33 chip. */
34static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
35 ppc_cpu_t);
32 36
33static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int); 37struct dis_private
38{
39 /* Stash the result of parsing disassembler_options here. */
40 ppc_cpu_t dialect;
41} private;
42
43#define POWERPC_DIALECT(INFO) \
44 (((struct dis_private *) ((INFO)->private_data))->dialect)
45
46struct ppc_mopt {
47 const char *opt;
48 ppc_cpu_t cpu;
49 ppc_cpu_t sticky;
50};
51
52struct ppc_mopt ppc_opts[] = {
53 { "403", PPC_OPCODE_PPC | PPC_OPCODE_403,
54 0 },
55 { "405", PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
56 0 },
57 { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
58 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
59 0 },
60 { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
61 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
62 0 },
63 { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
64 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
65 0 },
66 { "601", PPC_OPCODE_PPC | PPC_OPCODE_601,
67 0 },
68 { "603", PPC_OPCODE_PPC,
69 0 },
70 { "604", PPC_OPCODE_PPC,
71 0 },
72 { "620", PPC_OPCODE_PPC | PPC_OPCODE_64,
73 0 },
74 { "7400", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
75 0 },
76 { "7410", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
77 0 },
78 { "7450", PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
79 0 },
80 { "7455", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
81 0 },
82 { "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
83 , 0 },
84 { "821", PPC_OPCODE_PPC | PPC_OPCODE_860,
85 0 },
86 { "850", PPC_OPCODE_PPC | PPC_OPCODE_860,
87 0 },
88 { "860", PPC_OPCODE_PPC | PPC_OPCODE_860,
89 0 },
90 { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
91 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
92 | PPC_OPCODE_A2),
93 0 },
94 { "altivec", PPC_OPCODE_PPC,
95 PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 },
96 { "any", 0,
97 PPC_OPCODE_ANY },
98 { "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
99 0 },
100 { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
101 0 },
102 { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
103 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
104 0 },
105 { "com", PPC_OPCODE_COMMON,
106 0 },
107 { "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
108 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
109 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
110 | PPC_OPCODE_E500 | PPC_OPCODE_E200Z4),
111 PPC_OPCODE_VLE },
112 { "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
113 0 },
114 { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
115 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
116 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
117 | PPC_OPCODE_E500),
118 0 },
119 { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
120 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
121 | PPC_OPCODE_E500MC),
122 0 },
123 { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
124 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
125 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
126 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
127 0 },
128 { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
129 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
130 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
131 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
132 | PPC_OPCODE_POWER7),
133 0 },
134 { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
135 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
136 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
137 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
138 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
139 0 },
140 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
141 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
142 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
143 | PPC_OPCODE_E500),
144 0 },
145 { "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
146 0 },
147 { "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
148 0 },
149 { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
150 | PPC_OPCODE_POWER5),
151 0 },
152 { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
153 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
154 0 },
155 { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
156 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
157 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
158 0 },
159 { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
160 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
161 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
162 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
163 0 },
164 { "power9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
165 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
166 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
167 | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
168 | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
169 0 },
170 { "ppc", PPC_OPCODE_PPC,
171 0 },
172 { "ppc32", PPC_OPCODE_PPC,
173 0 },
174 { "ppc64", PPC_OPCODE_PPC | PPC_OPCODE_64,
175 0 },
176 { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
177 0 },
178 { "ppcps", PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
179 0 },
180 { "pwr", PPC_OPCODE_POWER,
181 0 },
182 { "pwr2", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
183 0 },
184 { "pwr4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
185 0 },
186 { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
187 | PPC_OPCODE_POWER5),
188 0 },
189 { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
190 | PPC_OPCODE_POWER5),
191 0 },
192 { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
193 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
194 0 },
195 { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
196 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
197 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
198 0 },
199 { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
200 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
201 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
202 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
203 0 },
204 { "pwr9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
205 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
206 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
207 | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
208 | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
209 0 },
210 { "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
211 0 },
212 { "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
213 PPC_OPCODE_SPE },
214 { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
215 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
216 0 },
217 { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
218 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
219 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
220 | PPC_OPCODE_E500),
221 PPC_OPCODE_VLE },
222 { "vsx", PPC_OPCODE_PPC,
223 PPC_OPCODE_VSX | PPC_OPCODE_VSX3 },
224 { "htm", PPC_OPCODE_PPC,
225 PPC_OPCODE_HTM },
226};
227
228/* Switch between Booke and VLE dialects for interlinked dumps. */
229static ppc_cpu_t
230get_powerpc_dialect (struct disassemble_info *info)
231{
232 ppc_cpu_t dialect = 0;
34 233
35/* Determine which set of machines to disassemble for. PPC403/601 or 234 dialect = POWERPC_DIALECT (info);
36 BookE. For convenience, also disassemble instructions supported
37 by the AltiVec vector unit. */
38 235
39static int 236 /* Disassemble according to the section headers flags for VLE-mode. */
40powerpc_dialect (struct disassemble_info *info) 237 if (dialect & PPC_OPCODE_VLE
41{ 238 && info->section->owner != NULL
42 int dialect = PPC_OPCODE_PPC; 239 && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
43 240 && elf_object_id (info->section->owner) == PPC32_ELF_DATA
44 if (BFD_DEFAULT_TARGET_SIZE == 64) 241 && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
45 dialect |= PPC_OPCODE_64; 242 return dialect;
46
47 if (info->disassembler_options
48 && strstr (info->disassembler_options, "booke") != NULL)
49 dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
50 else if ((info->mach == bfd_mach_ppc_e500)
51 || (info->disassembler_options
52 && strstr (info->disassembler_options, "e500") != NULL))
53 dialect |= (PPC_OPCODE_BOOKE
54 | PPC_OPCODE_SPE | PPC_OPCODE_ISEL
55 | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
56 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
57 | PPC_OPCODE_RFMCI);
58 else if (info->disassembler_options
59 && strstr (info->disassembler_options, "efs") != NULL)
60 dialect |= PPC_OPCODE_EFS;
61 else if (info->disassembler_options
62 && strstr (info->disassembler_options, "e300") != NULL)
63 dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON;
64 else if (info->disassembler_options
65 && strstr (info->disassembler_options, "440") != NULL)
66 dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32
67 | PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI;
68 else 243 else
69 dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC 244 return dialect & ~ PPC_OPCODE_VLE;
70 | PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC); 245}
246
247/* Handle -m and -M options that set cpu type, and .machine arg. */
71 248
72 if (info->disassembler_options 249ppc_cpu_t
73 && strstr (info->disassembler_options, "power4") != NULL) 250ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
74 dialect |= PPC_OPCODE_POWER4; 251{
252 unsigned int i;
253
254 for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
255 if (strcmp (ppc_opts[i].opt, arg) == 0)
256 {
257 if (ppc_opts[i].sticky)
258 {
259 *sticky |= ppc_opts[i].sticky;
260 if ((ppc_cpu & ~*sticky) != 0)
261 break;
262 }
263 ppc_cpu = ppc_opts[i].cpu;
264 break;
265 }
266 if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
267 return 0;
268
269 ppc_cpu |= *sticky;
270 return ppc_cpu;
271}
75 272
76 if (info->disassembler_options 273/* Determine which set of machines to disassemble for. */
77 && strstr (info->disassembler_options, "power5") != NULL)
78 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5;
79 274
80 if (info->disassembler_options 275static void
81 && strstr (info->disassembler_options, "cell") != NULL) 276powerpc_init_dialect (struct disassemble_info *info)
82 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC; 277{
278 ppc_cpu_t dialect = 0;
279 ppc_cpu_t sticky = 0;
280 char *arg;
281 struct dis_private *priv = calloc (sizeof (*priv), 1);
83 282
84 if (info->disassembler_options 283 if (priv == NULL)
85 && strstr (info->disassembler_options, "power6") != NULL) 284 priv = &private;
86 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC;
87 285
88 if (info->disassembler_options 286 switch (info->mach)
89 && strstr (info->disassembler_options, "any") != NULL) 287 {
90 dialect |= PPC_OPCODE_ANY; 288 case bfd_mach_ppc_403:
289 case bfd_mach_ppc_403gc:
290 dialect = ppc_parse_cpu (dialect, &sticky, "403");
291 break;
292 case bfd_mach_ppc_405:
293 dialect = ppc_parse_cpu (dialect, &sticky, "405");
294 break;
295 case bfd_mach_ppc_601:
296 dialect = ppc_parse_cpu (dialect, &sticky, "601");
297 break;
298 case bfd_mach_ppc_a35:
299 case bfd_mach_ppc_rs64ii:
300 case bfd_mach_ppc_rs64iii:
301 dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
302 break;
303 case bfd_mach_ppc_e500:
304 dialect = ppc_parse_cpu (dialect, &sticky, "e500");
305 break;
306 case bfd_mach_ppc_e500mc:
307 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
308 break;
309 case bfd_mach_ppc_e500mc64:
310 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
311 break;
312 case bfd_mach_ppc_e5500:
313 dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
314 break;
315 case bfd_mach_ppc_e6500:
316 dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
317 break;
318 case bfd_mach_ppc_titan:
319 dialect = ppc_parse_cpu (dialect, &sticky, "titan");
320 break;
321 case bfd_mach_ppc_vle:
322 dialect = ppc_parse_cpu (dialect, &sticky, "vle");
323 break;
324 default:
325 dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
326 }
91 327
92 if (info->disassembler_options) 328 arg = info->disassembler_options;
329 while (arg != NULL)
93 { 330 {
94 if (strstr (info->disassembler_options, "32") != NULL) 331 ppc_cpu_t new_cpu = 0;
95 dialect &= ~PPC_OPCODE_64; 332 char *end = strchr (arg, ',');
96 else if (strstr (info->disassembler_options, "64") != NULL) 333
334 if (end != NULL)
335 *end = 0;
336
337 if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0)
338 dialect = new_cpu;
339 else if (strcmp (arg, "32") == 0)
340 dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
341 else if (strcmp (arg, "64") == 0)
97 dialect |= PPC_OPCODE_64; 342 dialect |= PPC_OPCODE_64;
343 else
344 fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
345
346 if (end != NULL)
347 *end++ = ',';
348 arg = end;
349 }
350
351 info->private_data = priv;
352 POWERPC_DIALECT(info) = dialect;
353}
354
355#define PPC_OPCD_SEGS 64
356static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
357#define VLE_OPCD_SEGS 32
358static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
359
360/* Calculate opcode table indices to speed up disassembly,
361 and init dialect. */
362
363void
364disassemble_init_powerpc (struct disassemble_info *info)
365{
366 int i;
367 unsigned short last;
368
369 if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
370 {
371
372 i = powerpc_num_opcodes;
373 while (--i >= 0)
374 {
375 unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
376
377 powerpc_opcd_indices[op] = i;
378 }
379
380 last = powerpc_num_opcodes;
381 for (i = PPC_OPCD_SEGS; i > 0; --i)
382 {
383 if (powerpc_opcd_indices[i] == 0)
384 powerpc_opcd_indices[i] = last;
385 last = powerpc_opcd_indices[i];
386 }
387
388 i = vle_num_opcodes;
389 while (--i >= 0)
390 {
391 unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
392 unsigned seg = VLE_OP_TO_SEG (op);
393
394 vle_opcd_indices[seg] = i;
395 }
396
397 last = vle_num_opcodes;
398 for (i = VLE_OPCD_SEGS; i > 0; --i)
399 {
400 if (vle_opcd_indices[i] == 0)
401 vle_opcd_indices[i] = last;
402 last = vle_opcd_indices[i];
403 }
98 } 404 }
99 405
100 info->private_data = (char *) 0 + dialect; 406 if (info->arch == bfd_arch_powerpc)
101 return dialect; 407 powerpc_init_dialect (info);
102} 408}
103 409
104/* Print a big endian PowerPC instruction. */ 410/* Print a big endian PowerPC instruction. */
@@ -106,8 +412,7 @@ powerpc_dialect (struct disassemble_info *info)
106int 412int
107print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) 413print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
108{ 414{
109 int dialect = (char *) info->private_data - (char *) 0; 415 return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
110 return print_insn_powerpc (memaddr, info, 1, dialect);
111} 416}
112 417
113/* Print a little endian PowerPC instruction. */ 418/* Print a little endian PowerPC instruction. */
@@ -115,8 +420,7 @@ print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
115int 420int
116print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) 421print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
117{ 422{
118 int dialect = (char *) info->private_data - (char *) 0; 423 return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
119 return print_insn_powerpc (memaddr, info, 0, dialect);
120} 424}
121 425
122/* Print a POWER (RS/6000) instruction. */ 426/* Print a POWER (RS/6000) instruction. */
@@ -131,7 +435,7 @@ print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
131 435
132static long 436static long
133operand_value_powerpc (const struct powerpc_operand *operand, 437operand_value_powerpc (const struct powerpc_operand *operand,
134 unsigned long insn, int dialect) 438 unsigned long insn, ppc_cpu_t dialect)
135{ 439{
136 long value; 440 long value;
137 int invalid; 441 int invalid;
@@ -140,11 +444,14 @@ operand_value_powerpc (const struct powerpc_operand *operand,
140 value = (*operand->extract) (insn, dialect, &invalid); 444 value = (*operand->extract) (insn, dialect, &invalid);
141 else 445 else
142 { 446 {
143 value = (insn >> operand->shift) & operand->bitm; 447 if (operand->shift >= 0)
448 value = (insn >> operand->shift) & operand->bitm;
449 else
450 value = (insn << -operand->shift) & operand->bitm;
144 if ((operand->flags & PPC_OPERAND_SIGNED) != 0) 451 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
145 { 452 {
146 /* BITM is always some number of zeros followed by some 453 /* BITM is always some number of zeros followed by some
147 number of ones, followed by some numer of zeros. */ 454 number of ones, followed by some number of zeros. */
148 unsigned long top = operand->bitm; 455 unsigned long top = operand->bitm;
149 /* top & -top gives the rightmost 1 bit, so this 456 /* top & -top gives the rightmost 1 bit, so this
150 fills in any trailing zeros. */ 457 fills in any trailing zeros. */
@@ -161,7 +468,7 @@ operand_value_powerpc (const struct powerpc_operand *operand,
161 468
162static int 469static int
163skip_optional_operands (const unsigned char *opindex, 470skip_optional_operands (const unsigned char *opindex,
164 unsigned long insn, int dialect) 471 unsigned long insn, ppc_cpu_t dialect)
165{ 472{
166 const struct powerpc_operand *operand; 473 const struct powerpc_operand *operand;
167 474
@@ -170,36 +477,148 @@ skip_optional_operands (const unsigned char *opindex,
170 operand = &powerpc_operands[*opindex]; 477 operand = &powerpc_operands[*opindex];
171 if ((operand->flags & PPC_OPERAND_NEXT) != 0 478 if ((operand->flags & PPC_OPERAND_NEXT) != 0
172 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 479 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
173 && operand_value_powerpc (operand, insn, dialect) != 0)) 480 && operand_value_powerpc (operand, insn, dialect) !=
481 ppc_optional_operand_value (operand)))
174 return 0; 482 return 0;
175 } 483 }
176 484
177 return 1; 485 return 1;
178} 486}
179 487
488/* Find a match for INSN in the opcode table, given machine DIALECT.
489 A DIALECT of -1 is special, matching all machine opcode variations. */
490
491static const struct powerpc_opcode *
492lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
493{
494 const struct powerpc_opcode *opcode;
495 const struct powerpc_opcode *opcode_end;
496 unsigned long op;
497
498 /* Get the major opcode of the instruction. */
499 op = PPC_OP (insn);
500
501 /* Find the first match in the opcode table for this major opcode. */
502 opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
503 for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
504 opcode < opcode_end;
505 ++opcode)
506 {
507 const unsigned char *opindex;
508 const struct powerpc_operand *operand;
509 int invalid;
510
511 if ((insn & opcode->mask) != opcode->opcode
512 || (dialect != (ppc_cpu_t) -1
513 && ((opcode->flags & dialect) == 0
514 || (opcode->deprecated & dialect) != 0)))
515 continue;
516
517 /* Check validity of operands. */
518 invalid = 0;
519 for (opindex = opcode->operands; *opindex != 0; opindex++)
520 {
521 operand = powerpc_operands + *opindex;
522 if (operand->extract)
523 (*operand->extract) (insn, dialect, &invalid);
524 }
525 if (invalid)
526 continue;
527
528 return opcode;
529 }
530
531 return NULL;
532}
533
534/* Find a match for INSN in the VLE opcode table. */
535
536static const struct powerpc_opcode *
537lookup_vle (unsigned long insn)
538{
539 const struct powerpc_opcode *opcode;
540 const struct powerpc_opcode *opcode_end;
541 unsigned op, seg;
542
543 op = PPC_OP (insn);
544 if (op >= 0x20 && op <= 0x37)
545 {
546 /* This insn has a 4-bit opcode. */
547 op &= 0x3c;
548 }
549 seg = VLE_OP_TO_SEG (op);
550
551 /* Find the first match in the opcode table for this major opcode. */
552 opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
553 for (opcode = vle_opcodes + vle_opcd_indices[seg];
554 opcode < opcode_end;
555 ++opcode)
556 {
557 unsigned long table_opcd = opcode->opcode;
558 unsigned long table_mask = opcode->mask;
559 bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
560 unsigned long insn2;
561 const unsigned char *opindex;
562 const struct powerpc_operand *operand;
563 int invalid;
564
565 insn2 = insn;
566 if (table_op_is_short)
567 insn2 >>= 16;
568 if ((insn2 & table_mask) != table_opcd)
569 continue;
570
571 /* Check validity of operands. */
572 invalid = 0;
573 for (opindex = opcode->operands; *opindex != 0; ++opindex)
574 {
575 operand = powerpc_operands + *opindex;
576 if (operand->extract)
577 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
578 }
579 if (invalid)
580 continue;
581
582 return opcode;
583 }
584
585 return NULL;
586}
587
180/* Print a PowerPC or POWER instruction. */ 588/* Print a PowerPC or POWER instruction. */
181 589
182static int 590static int
183print_insn_powerpc (bfd_vma memaddr, 591print_insn_powerpc (bfd_vma memaddr,
184 struct disassemble_info *info, 592 struct disassemble_info *info,
185 int bigendian, 593 int bigendian,
186 int dialect) 594 ppc_cpu_t dialect)
187{ 595{
188 bfd_byte buffer[4]; 596 bfd_byte buffer[4];
189 int status; 597 int status;
190 unsigned long insn; 598 unsigned long insn;
191 const struct powerpc_opcode *opcode; 599 const struct powerpc_opcode *opcode;
192 const struct powerpc_opcode *opcode_end; 600 bfd_boolean insn_is_short;
193 unsigned long op;
194
195 if (dialect == 0)
196 dialect = powerpc_dialect (info);
197 601
198 status = (*info->read_memory_func) (memaddr, buffer, 4, info); 602 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
199 if (status != 0) 603 if (status != 0)
200 { 604 {
201 (*info->memory_error_func) (status, memaddr, info); 605 /* The final instruction may be a 2-byte VLE insn. */
202 return -1; 606 if ((dialect & PPC_OPCODE_VLE) != 0)
607 {
608 /* Clear buffer so unused bytes will not have garbage in them. */
609 buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
610 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
611 if (status != 0)
612 {
613 (*info->memory_error_func) (status, memaddr, info);
614 return -1;
615 }
616 }
617 else
618 {
619 (*info->memory_error_func) (status, memaddr, info);
620 return -1;
621 }
203 } 622 }
204 623
205 if (bigendian) 624 if (bigendian)
@@ -207,52 +626,37 @@ print_insn_powerpc (bfd_vma memaddr,
207 else 626 else
208 insn = bfd_getl32 (buffer); 627 insn = bfd_getl32 (buffer);
209 628
210 /* Get the major opcode of the instruction. */ 629 /* Get the major opcode of the insn. */
211 op = PPC_OP (insn); 630 opcode = NULL;
631 insn_is_short = FALSE;
632 if ((dialect & PPC_OPCODE_VLE) != 0)
633 {
634 opcode = lookup_vle (insn);
635 if (opcode != NULL)
636 insn_is_short = PPC_OP_SE_VLE(opcode->mask);
637 }
638 if (opcode == NULL)
639 opcode = lookup_powerpc (insn, dialect);
640 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
641 opcode = lookup_powerpc (insn, (ppc_cpu_t) -1);
212 642
213 /* Find the first match in the opcode table. We could speed this up 643 if (opcode != NULL)
214 a bit by doing a binary search on the major opcode. */
215 opcode_end = powerpc_opcodes + powerpc_num_opcodes;
216 again:
217 for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
218 { 644 {
219 unsigned long table_op;
220 const unsigned char *opindex; 645 const unsigned char *opindex;
221 const struct powerpc_operand *operand; 646 const struct powerpc_operand *operand;
222 int invalid;
223 int need_comma; 647 int need_comma;
224 int need_paren; 648 int need_paren;
225 int skip_optional; 649 int skip_optional;
226 650
227 table_op = PPC_OP (opcode->opcode);
228 if (op < table_op)
229 break;
230 if (op > table_op)
231 continue;
232
233 if ((insn & opcode->mask) != opcode->opcode
234 || (opcode->flags & dialect) == 0)
235 continue;
236
237 /* Make two passes over the operands. First see if any of them
238 have extraction functions, and, if they do, make sure the
239 instruction is valid. */
240 invalid = 0;
241 for (opindex = opcode->operands; *opindex != 0; opindex++)
242 {
243 operand = powerpc_operands + *opindex;
244 if (operand->extract)
245 (*operand->extract) (insn, dialect, &invalid);
246 }
247 if (invalid)
248 continue;
249
250 /* The instruction is valid. */
251 if (opcode->operands[0] != 0) 651 if (opcode->operands[0] != 0)
252 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name); 652 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
253 else 653 else
254 (*info->fprintf_func) (info->stream, "%s", opcode->name); 654 (*info->fprintf_func) (info->stream, "%s", opcode->name);
255 655
656 if (insn_is_short)
657 /* The operands will be fetched out of the 16-bit instruction. */
658 insn >>= 16;
659
256 /* Now extract and print the operands. */ 660 /* Now extract and print the operands. */
257 need_comma = 0; 661 need_comma = 0;
258 need_paren = 0; 662 need_paren = 0;
@@ -296,30 +700,38 @@ print_insn_powerpc (bfd_vma memaddr,
296 (*info->fprintf_func) (info->stream, "f%ld", value); 700 (*info->fprintf_func) (info->stream, "f%ld", value);
297 else if ((operand->flags & PPC_OPERAND_VR) != 0) 701 else if ((operand->flags & PPC_OPERAND_VR) != 0)
298 (*info->fprintf_func) (info->stream, "v%ld", value); 702 (*info->fprintf_func) (info->stream, "v%ld", value);
703 else if ((operand->flags & PPC_OPERAND_VSR) != 0)
704 (*info->fprintf_func) (info->stream, "vs%ld", value);
299 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) 705 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
300 (*info->print_address_func) (memaddr + value, info); 706 (*info->print_address_func) (memaddr + value, info);
301 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) 707 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
302 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); 708 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
303 else if ((operand->flags & PPC_OPERAND_CR) == 0 709 else if ((operand->flags & PPC_OPERAND_FSL) != 0)
304 || (dialect & PPC_OPCODE_PPC) == 0) 710 (*info->fprintf_func) (info->stream, "fsl%ld", value);
711 else if ((operand->flags & PPC_OPERAND_FCR) != 0)
712 (*info->fprintf_func) (info->stream, "fcr%ld", value);
713 else if ((operand->flags & PPC_OPERAND_UDI) != 0)
305 (*info->fprintf_func) (info->stream, "%ld", value); 714 (*info->fprintf_func) (info->stream, "%ld", value);
306 else 715 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
716 && (((dialect & PPC_OPCODE_PPC) != 0)
717 || ((dialect & PPC_OPCODE_VLE) != 0)))
718 (*info->fprintf_func) (info->stream, "cr%ld", value);
719 else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
720 && (((dialect & PPC_OPCODE_PPC) != 0)
721 || ((dialect & PPC_OPCODE_VLE) != 0)))
307 { 722 {
308 if (operand->bitm == 7) 723 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
309 (*info->fprintf_func) (info->stream, "cr%ld", value); 724 int cr;
310 else 725 int cc;
311 { 726
312 static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; 727 cr = value >> 2;
313 int cr; 728 if (cr != 0)
314 int cc; 729 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
315 730 cc = value & 3;
316 cr = value >> 2; 731 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
317 if (cr != 0)
318 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
319 cc = value & 3;
320 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
321 }
322 } 732 }
733 else
734 (*info->fprintf_func) (info->stream, "%d", (int) value);
323 735
324 if (need_paren) 736 if (need_paren)
325 { 737 {
@@ -336,14 +748,16 @@ print_insn_powerpc (bfd_vma memaddr,
336 } 748 }
337 } 749 }
338 750
339 /* We have found and printed an instruction; return. */ 751 /* We have found and printed an instruction.
340 return 4; 752 If it was a short VLE instruction we have more to do. */
341 } 753 if (insn_is_short)
342 754 {
343 if ((dialect & PPC_OPCODE_ANY) != 0) 755 memaddr += 2;
344 { 756 return 2;
345 dialect = ~PPC_OPCODE_ANY; 757 }
346 goto again; 758 else
759 /* Otherwise, return. */
760 return 4;
347 } 761 }
348 762
349 /* We could not find a match. */ 763 /* We could not find a match. */
@@ -355,18 +769,20 @@ print_insn_powerpc (bfd_vma memaddr,
355void 769void
356print_ppc_disassembler_options (FILE *stream) 770print_ppc_disassembler_options (FILE *stream)
357{ 771{
358 fprintf (stream, "\n\ 772 unsigned int i, col;
773
774 fprintf (stream, _("\n\
359The following PPC specific disassembler options are supported for use with\n\ 775The following PPC specific disassembler options are supported for use with\n\
360the -M switch:\n"); 776the -M switch:\n"));
361 777
362 fprintf (stream, " booke|booke32|booke64 Disassemble the BookE instructions\n"); 778 for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
363 fprintf (stream, " e300 Disassemble the e300 instructions\n"); 779 {
364 fprintf (stream, " e500|e500x2 Disassemble the e500 instructions\n"); 780 col += fprintf (stream, " %s,", ppc_opts[i].opt);
365 fprintf (stream, " 440 Disassemble the 440 instructions\n"); 781 if (col > 66)
366 fprintf (stream, " efs Disassemble the EFS instructions\n"); 782 {
367 fprintf (stream, " power4 Disassemble the Power4 instructions\n"); 783 fprintf (stream, "\n");
368 fprintf (stream, " power5 Disassemble the Power5 instructions\n"); 784 col = 0;
369 fprintf (stream, " power6 Disassemble the Power6 instructions\n"); 785 }
370 fprintf (stream, " 32 Do not disassemble 64-bit instructions\n"); 786 }
371 fprintf (stream, " 64 Allow disassembly of 64-bit instructions\n"); 787 fprintf (stream, " 32, 64\n");
372} 788}
diff --git a/arch/powerpc/xmon/ppc-opc.c b/arch/powerpc/xmon/ppc-opc.c
index 5995f81de9ff..e3ad69c3be07 100644
--- a/arch/powerpc/xmon/ppc-opc.c
+++ b/arch/powerpc/xmon/ppc-opc.c
@@ -1,6 +1,5 @@
1/* ppc-opc.c -- PowerPC opcode list 1/* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004, 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 2005, 2006, 2007 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support 3 Written by Ian Lance Taylor, Cygnus Support
5 4
6 This file is part of GDB, GAS, and the GNU binutils. 5 This file is part of GDB, GAS, and the GNU binutils.
@@ -20,8 +19,8 @@
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */ 20 02110-1301, USA. */
22 21
23#include <stdio.h>
24#include "sysdep.h" 22#include "sysdep.h"
23#include <stdio.h>
25#include "opcode/ppc.h" 24#include "opcode/ppc.h"
26#include "opintl.h" 25#include "opintl.h"
27 26
@@ -38,41 +37,93 @@
38 37
39/* Local insertion and extraction functions. */ 38/* Local insertion and extraction functions. */
40 39
41static unsigned long insert_bat (unsigned long, long, int, const char **); 40static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
42static long extract_bat (unsigned long, int, int *); 41static long extract_arx (unsigned long, ppc_cpu_t, int *);
43static unsigned long insert_bba (unsigned long, long, int, const char **); 42static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
44static long extract_bba (unsigned long, int, int *); 43static long extract_ary (unsigned long, ppc_cpu_t, int *);
45static unsigned long insert_bdm (unsigned long, long, int, const char **); 44static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
46static long extract_bdm (unsigned long, int, int *); 45static long extract_bat (unsigned long, ppc_cpu_t, int *);
47static unsigned long insert_bdp (unsigned long, long, int, const char **); 46static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
48static long extract_bdp (unsigned long, int, int *); 47static long extract_bba (unsigned long, ppc_cpu_t, int *);
49static unsigned long insert_bo (unsigned long, long, int, const char **); 48static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
50static long extract_bo (unsigned long, int, int *); 49static long extract_bdm (unsigned long, ppc_cpu_t, int *);
51static unsigned long insert_boe (unsigned long, long, int, const char **); 50static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
52static long extract_boe (unsigned long, int, int *); 51static long extract_bdp (unsigned long, ppc_cpu_t, int *);
53static unsigned long insert_fxm (unsigned long, long, int, const char **); 52static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
54static long extract_fxm (unsigned long, int, int *); 53static long extract_bo (unsigned long, ppc_cpu_t, int *);
55static unsigned long insert_mbe (unsigned long, long, int, const char **); 54static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
56static long extract_mbe (unsigned long, int, int *); 55static long extract_boe (unsigned long, ppc_cpu_t, int *);
57static unsigned long insert_mb6 (unsigned long, long, int, const char **); 56static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **);
58static long extract_mb6 (unsigned long, int, int *); 57static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **);
59static long extract_nb (unsigned long, int, int *); 58static long extract_dcmxs (unsigned long, ppc_cpu_t, int *);
60static unsigned long insert_nsi (unsigned long, long, int, const char **); 59static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **);
61static long extract_nsi (unsigned long, int, int *); 60static long extract_dxd (unsigned long, ppc_cpu_t, int *);
62static unsigned long insert_ral (unsigned long, long, int, const char **); 61static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **);
63static unsigned long insert_ram (unsigned long, long, int, const char **); 62static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
64static unsigned long insert_raq (unsigned long, long, int, const char **); 63static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
65static unsigned long insert_ras (unsigned long, long, int, const char **); 64static long extract_fxm (unsigned long, ppc_cpu_t, int *);
66static unsigned long insert_rbs (unsigned long, long, int, const char **); 65static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
67static long extract_rbs (unsigned long, int, int *); 66static long extract_li20 (unsigned long, ppc_cpu_t, int *);
68static unsigned long insert_sh6 (unsigned long, long, int, const char **); 67static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
69static long extract_sh6 (unsigned long, int, int *); 68static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
70static unsigned long insert_spr (unsigned long, long, int, const char **); 69static long extract_mbe (unsigned long, ppc_cpu_t, int *);
71static long extract_spr (unsigned long, int, int *); 70static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
72static unsigned long insert_sprg (unsigned long, long, int, const char **); 71static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
73static long extract_sprg (unsigned long, int, int *); 72static long extract_nb (unsigned long, ppc_cpu_t, int *);
74static unsigned long insert_tbr (unsigned long, long, int, const char **); 73static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
75static long extract_tbr (unsigned long, int, int *); 74static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
75static long extract_nsi (unsigned long, ppc_cpu_t, int *);
76static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
77static long extract_oimm (unsigned long, ppc_cpu_t, int *);
78static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
79static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
80static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
81static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
82static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
83static long extract_rbs (unsigned long, ppc_cpu_t, int *);
84static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
85static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
86static long extract_rx (unsigned long, ppc_cpu_t, int *);
87static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
88static long extract_ry (unsigned long, ppc_cpu_t, int *);
89static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
90static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
91static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
92static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
93static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
94static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
95static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
96static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
97static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
98static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
99static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
100static long extract_spr (unsigned long, ppc_cpu_t, int *);
101static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
102static long extract_sprg (unsigned long, ppc_cpu_t, int *);
103static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
104static long extract_tbr (unsigned long, ppc_cpu_t, int *);
105static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
106static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
107static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **);
108static long extract_xtq6 (unsigned long, ppc_cpu_t, int *);
109static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
110static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
111static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
112static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
113static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
114static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
115static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
116static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
117static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
118static long extract_dm (unsigned long, ppc_cpu_t, int *);
119static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
120static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
121static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
122static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
123static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
124static long extract_vleui (unsigned long, ppc_cpu_t, int *);
125static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
126static long extract_vleil (unsigned long, ppc_cpu_t, int *);
76 127
77/* The operands table. 128/* The operands table.
78 129
@@ -97,7 +148,7 @@ const struct powerpc_operand powerpc_operands[] =
97 /* The BI field in a B form or XL form instruction. */ 148 /* The BI field in a B form or XL form instruction. */
98#define BI BA 149#define BI BA
99#define BI_MASK (0x1f << 16) 150#define BI_MASK (0x1f << 16)
100 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR }, 151 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
101 152
102 /* The BA field in an XL form instruction when it must be the same 153 /* The BA field in an XL form instruction when it must be the same
103 as the BT field in the same instruction. */ 154 as the BT field in the same instruction. */
@@ -107,11 +158,14 @@ const struct powerpc_operand powerpc_operands[] =
107 /* The BB field in an XL form instruction. */ 158 /* The BB field in an XL form instruction. */
108#define BB BAT + 1 159#define BB BAT + 1
109#define BB_MASK (0x1f << 11) 160#define BB_MASK (0x1f << 11)
110 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR }, 161 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
111 162
112 /* The BB field in an XL form instruction when it must be the same 163 /* The BB field in an XL form instruction when it must be the same
113 as the BA field in the same instruction. */ 164 as the BA field in the same instruction. */
114#define BBA BB + 1 165#define BBA BB + 1
166 /* The VB field in a VX form instruction when it must be the same
167 as the VA field in the same instruction. */
168#define VBA BBA
115 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, 169 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
116 170
117 /* The BD field in a B form instruction. The lower two bits are 171 /* The BD field in a B form instruction. The lower two bits are
@@ -128,31 +182,33 @@ const struct powerpc_operand powerpc_operands[] =
128 This sets the y bit of the BO field appropriately. */ 182 This sets the y bit of the BO field appropriately. */
129#define BDM BDA + 1 183#define BDM BDA + 1
130 { 0xfffc, 0, insert_bdm, extract_bdm, 184 { 0xfffc, 0, insert_bdm, extract_bdm,
131 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 185 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
132 186
133 /* The BD field in a B form instruction when the - modifier is used 187 /* The BD field in a B form instruction when the - modifier is used
134 and absolute address is used. */ 188 and absolute address is used. */
135#define BDMA BDM + 1 189#define BDMA BDM + 1
136 { 0xfffc, 0, insert_bdm, extract_bdm, 190 { 0xfffc, 0, insert_bdm, extract_bdm,
137 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 191 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
138 192
139 /* The BD field in a B form instruction when the + modifier is used. 193 /* The BD field in a B form instruction when the + modifier is used.
140 This sets the y bit of the BO field appropriately. */ 194 This sets the y bit of the BO field appropriately. */
141#define BDP BDMA + 1 195#define BDP BDMA + 1
142 { 0xfffc, 0, insert_bdp, extract_bdp, 196 { 0xfffc, 0, insert_bdp, extract_bdp,
143 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 197 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
144 198
145 /* The BD field in a B form instruction when the + modifier is used 199 /* The BD field in a B form instruction when the + modifier is used
146 and absolute addressing is used. */ 200 and absolute addressing is used. */
147#define BDPA BDP + 1 201#define BDPA BDP + 1
148 { 0xfffc, 0, insert_bdp, extract_bdp, 202 { 0xfffc, 0, insert_bdp, extract_bdp,
149 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 203 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
150 204
151 /* The BF field in an X or XL form instruction. */ 205 /* The BF field in an X or XL form instruction. */
152#define BF BDPA + 1 206#define BF BDPA + 1
153 /* The CRFD field in an X form instruction. */ 207 /* The CRFD field in an X form instruction. */
154#define CRFD BF 208#define CRFD BF
155 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR }, 209 /* The CRD field in an XL form instruction. */
210#define CRD BF
211 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
156 212
157 /* The BF field in an X or XL form instruction. */ 213 /* The BF field in an X or XL form instruction. */
158#define BFF BF + 1 214#define BFF BF + 1
@@ -161,11 +217,11 @@ const struct powerpc_operand powerpc_operands[] =
161 /* An optional BF field. This is used for comparison instructions, 217 /* An optional BF field. This is used for comparison instructions,
162 in which an omitted BF field is taken as zero. */ 218 in which an omitted BF field is taken as zero. */
163#define OBF BFF + 1 219#define OBF BFF + 1
164 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 220 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
165 221
166 /* The BFA field in an X or XL form instruction. */ 222 /* The BFA field in an X or XL form instruction. */
167#define BFA OBF + 1 223#define BFA OBF + 1
168 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR }, 224 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
169 225
170 /* The BO field in a B form instruction. Certain values are 226 /* The BO field in a B form instruction. Certain values are
171 illegal. */ 227 illegal. */
@@ -178,19 +234,49 @@ const struct powerpc_operand powerpc_operands[] =
178#define BOE BO + 1 234#define BOE BO + 1
179 { 0x1e, 21, insert_boe, extract_boe, 0 }, 235 { 0x1e, 21, insert_boe, extract_boe, 0 },
180 236
181#define BH BOE + 1 237 /* The RM field in an X form instruction. */
238#define RM BOE + 1
239 { 0x3, 11, NULL, NULL, 0 },
240
241#define BH RM + 1
182 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 242 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
183 243
184 /* The BT field in an X or XL form instruction. */ 244 /* The BT field in an X or XL form instruction. */
185#define BT BH + 1 245#define BT BH + 1
186 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR }, 246 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
247
248 /* The BI16 field in a BD8 form instruction. */
249#define BI16 BT + 1
250 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
251
252 /* The BI32 field in a BD15 form instruction. */
253#define BI32 BI16 + 1
254 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
255
256 /* The BO32 field in a BD15 form instruction. */
257#define BO32 BI32 + 1
258 { 0x3, 20, NULL, NULL, 0 },
259
260 /* The B8 field in a BD8 form instruction. */
261#define B8 BO32 + 1
262 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
263
264 /* The B15 field in a BD15 form instruction. The lowest bit is
265 forced to zero. */
266#define B15 B8 + 1
267 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
268
269 /* The B24 field in a BD24 form instruction. The lowest bit is
270 forced to zero. */
271#define B24 B15 + 1
272 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
187 273
188 /* The condition register number portion of the BI field in a B form 274 /* The condition register number portion of the BI field in a B form
189 or XL form instruction. This is used for the extended 275 or XL form instruction. This is used for the extended
190 conditional branch mnemonics, which set the lower two bits of the 276 conditional branch mnemonics, which set the lower two bits of the
191 BI field. This field is optional. */ 277 BI field. This field is optional. */
192#define CR BT + 1 278#define CR B24 + 1
193 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 279 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
194 280
195 /* The CRB field in an X form instruction. */ 281 /* The CRB field in an X form instruction. */
196#define CRB CR + 1 282#define CRB CR + 1
@@ -199,12 +285,19 @@ const struct powerpc_operand powerpc_operands[] =
199#define MB_MASK (0x1f << 6) 285#define MB_MASK (0x1f << 6)
200 { 0x1f, 6, NULL, NULL, 0 }, 286 { 0x1f, 6, NULL, NULL, 0 },
201 287
288 /* The CRD32 field in an XL form instruction. */
289#define CRD32 CRB + 1
290 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
291
202 /* The CRFS field in an X form instruction. */ 292 /* The CRFS field in an X form instruction. */
203#define CRFS CRB + 1 293#define CRFS CRD32 + 1
204 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR }, 294 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
295
296#define CRS CRFS + 1
297 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
205 298
206 /* The CT field in an X form instruction. */ 299 /* The CT field in an X form instruction. */
207#define CT CRFS + 1 300#define CT CRS + 1
208 /* The MO field in an mbar instruction. */ 301 /* The MO field in an mbar instruction. */
209#define MO CT 302#define MO CT
210 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 303 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
@@ -215,19 +308,23 @@ const struct powerpc_operand powerpc_operands[] =
215#define D CT + 1 308#define D CT + 1
216 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 309 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
217 310
218 /* The DE field in a DE form instruction. This is like D, but is 12 311 /* The D8 field in a D form instruction. This is a displacement off
219 bits only. */ 312 a register, and implies that the next operand is a register in
220#define DE D + 1 313 parentheses. */
221 { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 314#define D8 D + 1
315 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
316
317 /* The DCMX field in an X form instruction. */
318#define DCMX D8 + 1
319 { 0x7f, 16, NULL, NULL, 0 },
222 320
223 /* The DES field in a DES form instruction. This is like DS, but is 14 321 /* The split DCMX field in an X form instruction. */
224 bits only (12 stored.) */ 322#define DCMXS DCMX + 1
225#define DES DE + 1 323 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },
226 { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
227 324
228 /* The DQ field in a DQ form instruction. This is like D, but the 325 /* The DQ field in a DQ form instruction. This is like D, but the
229 lower four bits are forced to zero. */ 326 lower four bits are forced to zero. */
230#define DQ DES + 1 327#define DQ DCMXS + 1
231 { 0xfff0, 0, NULL, NULL, 328 { 0xfff0, 0, NULL, NULL,
232 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, 329 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
233 330
@@ -237,8 +334,29 @@ const struct powerpc_operand powerpc_operands[] =
237 { 0xfffc, 0, NULL, NULL, 334 { 0xfffc, 0, NULL, NULL,
238 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, 335 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
239 336
337 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
338 unsigned imediate */
339#define DUIS DS + 1
340#define BHRBE DUIS
341 { 0x3ff, 11, NULL, NULL, 0 },
342
343 /* The split D field in a DX form instruction. */
344#define DXD DUIS + 1
345 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
346 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
347
348 /* The split ND field in a DX form instruction.
349 This is the same as the DX field, only negated. */
350#define NDXD DXD + 1
351 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
352 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
353
240 /* The E field in a wrteei instruction. */ 354 /* The E field in a wrteei instruction. */
241#define E DS + 1 355 /* And the W bit in the pair singles instructions. */
356 /* And the ST field in a VX form instruction. */
357#define E NDXD + 1
358#define PSW E
359#define ST E
242 { 0x1, 15, NULL, NULL, 0 }, 360 { 0x1, 15, NULL, NULL, 0 },
243 361
244 /* The FL1 field in a POWER SC form instruction. */ 362 /* The FL1 field in a POWER SC form instruction. */
@@ -260,13 +378,21 @@ const struct powerpc_operand powerpc_operands[] =
260#define FRA_MASK (0x1f << 16) 378#define FRA_MASK (0x1f << 16)
261 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, 379 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
262 380
381 /* The FRAp field of DFP instructions. */
382#define FRAp FRA + 1
383 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
384
263 /* The FRB field in an X or A form instruction. */ 385 /* The FRB field in an X or A form instruction. */
264#define FRB FRA + 1 386#define FRB FRAp + 1
265#define FRB_MASK (0x1f << 11) 387#define FRB_MASK (0x1f << 11)
266 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, 388 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
267 389
390 /* The FRBp field of DFP instructions. */
391#define FRBp FRB + 1
392 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
393
268 /* The FRC field in an A form instruction. */ 394 /* The FRC field in an A form instruction. */
269#define FRC FRB + 1 395#define FRC FRBp + 1
270#define FRC_MASK (0x1f << 6) 396#define FRC_MASK (0x1f << 6)
271 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, 397 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
272 398
@@ -276,20 +402,47 @@ const struct powerpc_operand powerpc_operands[] =
276#define FRT FRS 402#define FRT FRS
277 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, 403 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
278 404
405 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
406 instructions. */
407#define FRSp FRS + 1
408#define FRTp FRSp
409 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
410
279 /* The FXM field in an XFX instruction. */ 411 /* The FXM field in an XFX instruction. */
280#define FXM FRS + 1 412#define FXM FRSp + 1
281 { 0xff, 12, insert_fxm, extract_fxm, 0 }, 413 { 0xff, 12, insert_fxm, extract_fxm, 0 },
282 414
283 /* Power4 version for mfcr. */ 415 /* Power4 version for mfcr. */
284#define FXM4 FXM + 1 416#define FXM4 FXM + 1
285 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, 417 { 0xff, 12, insert_fxm, extract_fxm,
418 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
419 /* If the FXM4 operand is ommitted, use the sentinel value -1. */
420 { -1, -1, NULL, NULL, 0},
421
422 /* The IMM20 field in an LI instruction. */
423#define IMM20 FXM4 + 2
424 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
286 425
287 /* The L field in a D or X form instruction. */ 426 /* The L field in a D or X form instruction. */
288#define L FXM4 + 1 427#define L IMM20 + 1
428 { 0x1, 21, NULL, NULL, 0 },
429
430 /* The optional L field in tlbie and tlbiel instructions. */
431#define LOPT L + 1
432 /* The R field in a HTM X form instruction. */
433#define HTM_R LOPT
289 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 434 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
290 435
436 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
437#define L32OPT LOPT + 1
438 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
439
440 /* The L field in dcbf instruction. */
441#define L2OPT L32OPT + 1
442 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
443
291 /* The LEV field in a POWER SVC form instruction. */ 444 /* The LEV field in a POWER SVC form instruction. */
292#define SVC_LEV L + 1 445#define SVC_LEV L2OPT + 1
293 { 0x7f, 5, NULL, NULL, 0 }, 446 { 0x7f, 5, NULL, NULL, 0 },
294 447
295 /* The LEV field in an SC form instruction. */ 448 /* The LEV field in an SC form instruction. */
@@ -306,9 +459,10 @@ const struct powerpc_operand powerpc_operands[] =
306#define LIA LI + 1 459#define LIA LI + 1
307 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 460 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
308 461
309 /* The LS field in an X (sync) form instruction. */ 462 /* The LS or WC field in an X (sync or wait) form instruction. */
310#define LS LIA + 1 463#define LS LIA + 1
311 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 464#define WC LS
465 { 0x3, 21, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
312 466
313 /* The ME field in an M form instruction. */ 467 /* The ME field in an M form instruction. */
314#define ME LS + 1 468#define ME LS + 1
@@ -335,14 +489,25 @@ const struct powerpc_operand powerpc_operands[] =
335#define NB MB6 + 1 489#define NB MB6 + 1
336 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, 490 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
337 491
492 /* The NBI field in an lswi instruction, which has special value
493 restrictions. The value 32 is stored as 0. */
494#define NBI NB + 1
495 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
496
338 /* The NSI field in a D form instruction. This is the same as the 497 /* The NSI field in a D form instruction. This is the same as the
339 SI field, only negated. */ 498 SI field, only negated. */
340#define NSI NB + 1 499#define NSI NBI + 1
341 { 0xffff, 0, insert_nsi, extract_nsi, 500 { 0xffff, 0, insert_nsi, extract_nsi,
342 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 501 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
502
503 /* The NSI field in a D form instruction when we accept a wide range
504 of positive values. */
505#define NSISIGNOPT NSI + 1
506 { 0xffff, 0, insert_nsi, extract_nsi,
507 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
343 508
344 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ 509 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
345#define RA NSI + 1 510#define RA NSISIGNOPT + 1
346#define RA_MASK (0x1f << 16) 511#define RA_MASK (0x1f << 16)
347 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, 512 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
348 513
@@ -350,9 +515,10 @@ const struct powerpc_operand powerpc_operands[] =
350#define RA0 RA + 1 515#define RA0 RA + 1
351 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, 516 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
352 517
353 /* The RA field in the DQ form lq instruction, which has special 518 /* The RA field in the DQ form lq or an lswx instruction, which have special
354 value restrictions. */ 519 value restrictions. */
355#define RAQ RA0 + 1 520#define RAQ RA0 + 1
521#define RAX RAQ
356 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, 522 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
357 523
358 /* The RA field in a D or X form instruction which is an updating 524 /* The RA field in a D or X form instruction which is an updating
@@ -372,7 +538,8 @@ const struct powerpc_operand powerpc_operands[] =
372#define RAS RAM + 1 538#define RAS RAM + 1
373 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, 539 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
374 540
375 /* The RA field of the tlbwe instruction, which is optional. */ 541 /* The RA field of the tlbwe, dccci and iccci instructions,
542 which are optional. */
376#define RAOPT RAS + 1 543#define RAOPT RAS + 1
377 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 544 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
378 545
@@ -387,36 +554,95 @@ const struct powerpc_operand powerpc_operands[] =
387#define RBS RB + 1 554#define RBS RB + 1
388 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, 555 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
389 556
557 /* The RB field in an lswx instruction, which has special value
558 restrictions. */
559#define RBX RBS + 1
560 { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
561
562 /* The RB field of the dccci and iccci instructions, which are optional. */
563#define RBOPT RBX + 1
564 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
565
566 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
567#define RC RBOPT + 1
568 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },
569
390 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form 570 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
391 instruction or the RT field in a D, DS, X, XFX or XO form 571 instruction or the RT field in a D, DS, X, XFX or XO form
392 instruction. */ 572 instruction. */
393#define RS RBS + 1 573#define RS RC + 1
394#define RT RS 574#define RT RS
395#define RT_MASK (0x1f << 21) 575#define RT_MASK (0x1f << 21)
576#define RD RS
396 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, 577 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
397 578
398 /* The RS and RT fields of the DS form stq instruction, which have 579 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
399 special value restrictions. */ 580 which have special value restrictions. */
400#define RSQ RS + 1 581#define RSQ RS + 1
401#define RTQ RSQ 582#define RTQ RSQ
402 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 }, 583 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
403 584
404 /* The RS field of the tlbwe instruction, which is optional. */ 585 /* The RS field of the tlbwe instruction, which is optional. */
405#define RSO RSQ + 1 586#define RSO RSQ + 1
406#define RTO RSO 587#define RTO RSO
407 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 588 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
408 589
590 /* The RX field of the SE_RR form instruction. */
591#define RX RSO + 1
592 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
593
594 /* The ARX field of the SE_RR form instruction. */
595#define ARX RX + 1
596 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
597
598 /* The RY field of the SE_RR form instruction. */
599#define RY ARX + 1
600#define RZ RY
601 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
602
603 /* The ARY field of the SE_RR form instruction. */
604#define ARY RY + 1
605 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
606
607 /* The SCLSCI8 field in a D form instruction. */
608#define SCLSCI8 ARY + 1
609 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
610
611 /* The SCLSCI8N field in a D form instruction. This is the same as the
612 SCLSCI8 field, only negated. */
613#define SCLSCI8N SCLSCI8 + 1
614 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
615 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
616
617 /* The SD field of the SD4 form instruction. */
618#define SE_SD SCLSCI8N + 1
619 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
620
621 /* The SD field of the SD4 form instruction, for halfword. */
622#define SE_SDH SE_SD + 1
623 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
624
625 /* The SD field of the SD4 form instruction, for word. */
626#define SE_SDW SE_SDH + 1
627 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
628
409 /* The SH field in an X or M form instruction. */ 629 /* The SH field in an X or M form instruction. */
410#define SH RSO + 1 630#define SH SE_SDW + 1
411#define SH_MASK (0x1f << 11) 631#define SH_MASK (0x1f << 11)
412 /* The other UIMM field in a EVX form instruction. */ 632 /* The other UIMM field in a EVX form instruction. */
413#define EVUIMM SH 633#define EVUIMM SH
634 /* The FC field in an atomic X form instruction. */
635#define FC SH
414 { 0x1f, 11, NULL, NULL, 0 }, 636 { 0x1f, 11, NULL, NULL, 0 },
415 637
638 /* The SI field in a HTM X form instruction. */
639#define HTM_SI SH + 1
640 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
641
416 /* The SH field in an MD form instruction. This is split. */ 642 /* The SH field in an MD form instruction. This is split. */
417#define SH6 SH + 1 643#define SH6 HTM_SI + 1
418#define SH6_MASK ((0x1f << 11) | (1 << 1)) 644#define SH6_MASK ((0x1f << 11) | (1 << 1))
419 { 0x3f, -1, insert_sh6, extract_sh6, 0 }, 645 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
420 646
421 /* The SH field of the tlbwe instruction, which is optional. */ 647 /* The SH field of the tlbwe instruction, which is optional. */
422#define SHO SH6 + 1 648#define SHO SH6 + 1
@@ -431,10 +657,15 @@ const struct powerpc_operand powerpc_operands[] =
431#define SISIGNOPT SI + 1 657#define SISIGNOPT SI + 1
432 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 658 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
433 659
660 /* The SI8 field in a D form instruction. */
661#define SI8 SISIGNOPT + 1
662 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
663
434 /* The SPR field in an XFX form instruction. This is flipped--the 664 /* The SPR field in an XFX form instruction. This is flipped--the
435 lower 5 bits are stored in the upper 5 and vice- versa. */ 665 lower 5 bits are stored in the upper 5 and vice- versa. */
436#define SPR SISIGNOPT + 1 666#define SPR SI8 + 1
437#define PMR SPR 667#define PMR SPR
668#define TMR SPR
438#define SPR_MASK (0x3ff << 11) 669#define SPR_MASK (0x3ff << 11)
439 { 0x3ff, 11, insert_spr, extract_spr, 0 }, 670 { 0x3ff, 11, insert_spr, extract_spr, 0 },
440 671
@@ -449,23 +680,37 @@ const struct powerpc_operand powerpc_operands[] =
449 680
450 /* The SR field in an X form instruction. */ 681 /* The SR field in an X form instruction. */
451#define SR SPRG + 1 682#define SR SPRG + 1
683 /* The 4-bit UIMM field in a VX form instruction. */
684#define UIMM4 SR
452 { 0xf, 16, NULL, NULL, 0 }, 685 { 0xf, 16, NULL, NULL, 0 },
453 686
454 /* The STRM field in an X AltiVec form instruction. */ 687 /* The STRM field in an X AltiVec form instruction. */
455#define STRM SR + 1 688#define STRM SR + 1
689 /* The T field in a tlbilx form instruction. */
690#define T STRM
691 /* The L field in wclr instructions. */
692#define L2 STRM
456 { 0x3, 21, NULL, NULL, 0 }, 693 { 0x3, 21, NULL, NULL, 0 },
457 694
695 /* The ESYNC field in an X (sync) form instruction. */
696#define ESYNC STRM + 1
697 { 0xf, 16, insert_esync, NULL, PPC_OPERAND_OPTIONAL },
698
458 /* The SV field in a POWER SC form instruction. */ 699 /* The SV field in a POWER SC form instruction. */
459#define SV STRM + 1 700#define SV ESYNC + 1
460 { 0x3fff, 2, NULL, NULL, 0 }, 701 { 0x3fff, 2, NULL, NULL, 0 },
461 702
462 /* The TBR field in an XFX form instruction. This is like the SPR 703 /* The TBR field in an XFX form instruction. This is like the SPR
463 field, but it is optional. */ 704 field, but it is optional. */
464#define TBR SV + 1 705#define TBR SV + 1
465 { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, 706 { 0x3ff, 11, insert_tbr, extract_tbr,
707 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
708 /* If the TBR operand is ommitted, use the value 268. */
709 { -1, 268, NULL, NULL, 0},
466 710
467 /* The TO field in a D or X form instruction. */ 711 /* The TO field in a D or X form instruction. */
468#define TO TBR + 1 712#define TO TBR + 2
713#define DUI TO
469#define TO_MASK (0x1f << 21) 714#define TO_MASK (0x1f << 21)
470 { 0x1f, 21, NULL, NULL, 0 }, 715 { 0x1f, 21, NULL, NULL, 0 },
471 716
@@ -473,8 +718,23 @@ const struct powerpc_operand powerpc_operands[] =
473#define UI TO + 1 718#define UI TO + 1
474 { 0xffff, 0, NULL, NULL, 0 }, 719 { 0xffff, 0, NULL, NULL, 0 },
475 720
721#define UISIGNOPT UI + 1
722 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
723
724 /* The IMM field in an SE_IM5 instruction. */
725#define UI5 UISIGNOPT + 1
726 { 0x1f, 4, NULL, NULL, 0 },
727
728 /* The OIMM field in an SE_OIM5 instruction. */
729#define OIMM5 UI5 + 1
730 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
731
732 /* The UI7 field in an SE_LI instruction. */
733#define UI7 OIMM5 + 1
734 { 0x7f, 4, NULL, NULL, 0 },
735
476 /* The VA field in a VA, VX or VXR form instruction. */ 736 /* The VA field in a VA, VX or VXR form instruction. */
477#define VA UI + 1 737#define VA UI7 + 1
478 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, 738 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
479 739
480 /* The VB field in a VA, VX or VXR form instruction. */ 740 /* The VB field in a VA, VX or VXR form instruction. */
@@ -490,17 +750,34 @@ const struct powerpc_operand powerpc_operands[] =
490#define VS VD 750#define VS VD
491 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, 751 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
492 752
493 /* The SIMM field in a VX form instruction. */ 753 /* The SIMM field in a VX form instruction, and TE in Z form. */
494#define SIMM VD + 1 754#define SIMM VD + 1
755#define TE SIMM
495 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, 756 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
496 757
497 /* The UIMM field in a VX form instruction, and TE in Z form. */ 758 /* The UIMM field in a VX form instruction. */
498#define UIMM SIMM + 1 759#define UIMM SIMM + 1
499#define TE UIMM 760#define DCTL UIMM
500 { 0x1f, 16, NULL, NULL, 0 }, 761 { 0x1f, 16, NULL, NULL, 0 },
501 762
763 /* The 3-bit UIMM field in a VX form instruction. */
764#define UIMM3 UIMM + 1
765 { 0x7, 16, NULL, NULL, 0 },
766
767 /* The 6-bit UIM field in a X form instruction. */
768#define UIM6 UIMM3 + 1
769 { 0x3f, 16, NULL, NULL, 0 },
770
771 /* The SIX field in a VX form instruction. */
772#define SIX UIM6 + 1
773 { 0xf, 11, NULL, NULL, 0 },
774
775 /* The PS field in a VX form instruction. */
776#define PS SIX + 1
777 { 0x1, 9, NULL, NULL, 0 },
778
502 /* The SHB field in a VA form instruction. */ 779 /* The SHB field in a VA form instruction. */
503#define SHB UIMM + 1 780#define SHB PS + 1
504 { 0xf, 6, NULL, NULL, 0 }, 781 { 0xf, 6, NULL, NULL, 0 },
505 782
506 /* The other UIMM field in a half word EVX form instruction. */ 783 /* The other UIMM field in a half word EVX form instruction. */
@@ -515,29 +792,64 @@ const struct powerpc_operand powerpc_operands[] =
515#define EVUIMM_8 EVUIMM_4 + 1 792#define EVUIMM_8 EVUIMM_4 + 1
516 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, 793 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
517 794
518 /* The WS field. */ 795 /* The WS or DRM field in an X form instruction. */
519#define WS EVUIMM_8 + 1 796#define WS EVUIMM_8 + 1
797#define DRM WS
520 { 0x7, 11, NULL, NULL, 0 }, 798 { 0x7, 11, NULL, NULL, 0 },
521 799
522 /* The L field in an mtmsrd or A form instruction or W in an X form. */ 800 /* PowerPC paired singles extensions. */
523#define A_L WS + 1 801 /* W bit in the pair singles instructions for x type instructions. */
802#define PSWM WS + 1
803 /* The BO16 field in a BD8 form instruction. */
804#define BO16 PSWM
805 { 0x1, 10, 0, 0, 0 },
806
807 /* IDX bits for quantization in the pair singles instructions. */
808#define PSQ PSWM + 1
809 { 0x7, 12, 0, 0, 0 },
810
811 /* IDX bits for quantization in the pair singles x-type instructions. */
812#define PSQM PSQ + 1
813 { 0x7, 7, 0, 0, 0 },
814
815 /* Smaller D field for quantization in the pair singles instructions. */
816#define PSD PSQM + 1
817 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
818
819 /* The L field in an mtmsrd or A form instruction or R or W in an X form. */
820#define A_L PSD + 1
524#define W A_L 821#define W A_L
822#define X_R A_L
525 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, 823 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
526 824
825 /* The RMC or CY field in a Z23 form instruction. */
527#define RMC A_L + 1 826#define RMC A_L + 1
827#define CY RMC
528 { 0x3, 9, NULL, NULL, 0 }, 828 { 0x3, 9, NULL, NULL, 0 },
529 829
530#define R RMC + 1 830#define R RMC + 1
531 { 0x1, 16, NULL, NULL, 0 }, 831 { 0x1, 16, NULL, NULL, 0 },
532 832
533#define SP R + 1 833#define RIC R + 1
834 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },
835
836#define PRS RIC + 1
837 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
838
839#define SP PRS + 1
534 { 0x3, 19, NULL, NULL, 0 }, 840 { 0x3, 19, NULL, NULL, 0 },
535 841
536#define S SP + 1 842#define S SP + 1
537 { 0x1, 20, NULL, NULL, 0 }, 843 { 0x1, 20, NULL, NULL, 0 },
538 844
845 /* The S field in a XL form instruction. */
846#define SXL S + 1
847 { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
848 /* If the SXL operand is ommitted, use the value 1. */
849 { -1, 1, NULL, NULL, 0},
850
539 /* SH field starting at bit position 16. */ 851 /* SH field starting at bit position 16. */
540#define SH16 S + 1 852#define SH16 SXL + 2
541 /* The DCM and DGM fields in a Z form instruction. */ 853 /* The DCM and DGM fields in a Z form instruction. */
542#define DCM SH16 854#define DCM SH16
543#define DGM DCM 855#define DGM DCM
@@ -548,8 +860,106 @@ const struct powerpc_operand powerpc_operands[] =
548 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, 860 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
549 861
550 /* The L field in an mtfsf or XFL form instruction. */ 862 /* The L field in an mtfsf or XFL form instruction. */
863 /* The A field in a HTM X form instruction. */
551#define XFL_L EH + 1 864#define XFL_L EH + 1
865#define HTM_A XFL_L
552 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, 866 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
867
868 /* Xilinx APU related masks and macros */
869#define FCRT XFL_L + 1
870#define FCRT_MASK (0x1f << 21)
871 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
872
873 /* Xilinx FSL related masks and macros */
874#define FSL FCRT + 1
875#define FSL_MASK (0x1f << 11)
876 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
877
878 /* Xilinx UDI related masks and macros */
879#define URT FSL + 1
880 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
881
882#define URA URT + 1
883 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
884
885#define URB URA + 1
886 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
887
888#define URC URB + 1
889 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
890
891 /* The VLESIMM field in a D form instruction. */
892#define VLESIMM URC + 1
893 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
894 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
895
896 /* The VLENSIMM field in a D form instruction. */
897#define VLENSIMM VLESIMM + 1
898 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
899 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
900
901 /* The VLEUIMM field in a D form instruction. */
902#define VLEUIMM VLENSIMM + 1
903 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
904
905 /* The VLEUIMML field in a D form instruction. */
906#define VLEUIMML VLEUIMM + 1
907 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
908
909 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
910#define XS6 VLEUIMML + 1
911#define XT6 XS6
912 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
913
914 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
915#define XSQ6 XT6 + 1
916#define XTQ6 XSQ6
917 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
918
919 /* The XA field in an XX3 form instruction. This is split. */
920#define XA6 XTQ6 + 1
921 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
922
923 /* The XB field in an XX2 or XX3 form instruction. This is split. */
924#define XB6 XA6 + 1
925 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
926
927 /* The XB field in an XX3 form instruction when it must be the same as
928 the XA field in the instruction. This is used in extended mnemonics
929 like xvmovdp. This is split. */
930#define XB6S XB6 + 1
931 { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
932
933 /* The XC field in an XX4 form instruction. This is split. */
934#define XC6 XB6S + 1
935 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
936
937 /* The DM or SHW field in an XX3 form instruction. */
938#define DM XC6 + 1
939#define SHW DM
940 { 0x3, 8, NULL, NULL, 0 },
941
942 /* The DM field in an extended mnemonic XX3 form instruction. */
943#define DMEX DM + 1
944 { 0x3, 8, insert_dm, extract_dm, 0 },
945
946 /* The UIM field in an XX2 form instruction. */
947#define UIM DMEX + 1
948 /* The 2-bit UIMM field in a VX form instruction. */
949#define UIMM2 UIM
950 /* The 2-bit L field in a darn instruction. */
951#define LRAND UIM
952 { 0x3, 16, NULL, NULL, 0 },
953
954#define ERAT_T UIM + 1
955 { 0x7, 21, NULL, NULL, 0 },
956
957#define IH ERAT_T + 1
958 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
959
960 /* The 8-bit IMM8 field in a XX1 form instruction. */
961#define IMM8 IH + 1
962 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
553}; 963};
554 964
555const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) 965const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -557,6 +967,112 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
557 967
558/* The functions used to insert and extract complicated operands. */ 968/* The functions used to insert and extract complicated operands. */
559 969
970/* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
971
972static unsigned long
973insert_arx (unsigned long insn,
974 long value,
975 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
976 const char **errmsg ATTRIBUTE_UNUSED)
977{
978 if (value >= 8 && value < 24)
979 return insn | ((value - 8) & 0xf);
980 else
981 {
982 *errmsg = _("invalid register");
983 return 0;
984 }
985}
986
987static long
988extract_arx (unsigned long insn,
989 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
990 int *invalid ATTRIBUTE_UNUSED)
991{
992 return (insn & 0xf) + 8;
993}
994
995static unsigned long
996insert_ary (unsigned long insn,
997 long value,
998 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
999 const char **errmsg ATTRIBUTE_UNUSED)
1000{
1001 if (value >= 8 && value < 24)
1002 return insn | (((value - 8) & 0xf) << 4);
1003 else
1004 {
1005 *errmsg = _("invalid register");
1006 return 0;
1007 }
1008}
1009
1010static long
1011extract_ary (unsigned long insn,
1012 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1013 int *invalid ATTRIBUTE_UNUSED)
1014{
1015 return ((insn >> 4) & 0xf) + 8;
1016}
1017
1018static unsigned long
1019insert_rx (unsigned long insn,
1020 long value,
1021 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1022 const char **errmsg)
1023{
1024 if (value >= 0 && value < 8)
1025 return insn | value;
1026 else if (value >= 24 && value <= 31)
1027 return insn | (value - 16);
1028 else
1029 {
1030 *errmsg = _("invalid register");
1031 return 0;
1032 }
1033}
1034
1035static long
1036extract_rx (unsigned long insn,
1037 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1038 int *invalid ATTRIBUTE_UNUSED)
1039{
1040 int value = insn & 0xf;
1041 if (value >= 0 && value < 8)
1042 return value;
1043 else
1044 return value + 16;
1045}
1046
1047static unsigned long
1048insert_ry (unsigned long insn,
1049 long value,
1050 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1051 const char **errmsg)
1052{
1053 if (value >= 0 && value < 8)
1054 return insn | (value << 4);
1055 else if (value >= 24 && value <= 31)
1056 return insn | ((value - 16) << 4);
1057 else
1058 {
1059 *errmsg = _("invalid register");
1060 return 0;
1061 }
1062}
1063
1064static long
1065extract_ry (unsigned long insn,
1066 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1067 int *invalid ATTRIBUTE_UNUSED)
1068{
1069 int value = (insn >> 4) & 0xf;
1070 if (value >= 0 && value < 8)
1071 return value;
1072 else
1073 return value + 16;
1074}
1075
560/* The BA field in an XL form instruction when it must be the same as 1076/* The BA field in an XL form instruction when it must be the same as
561 the BT field in the same instruction. This operand is marked FAKE. 1077 the BT field in the same instruction. This operand is marked FAKE.
562 The insertion function just copies the BT field into the BA field, 1078 The insertion function just copies the BT field into the BA field,
@@ -566,7 +1082,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
566static unsigned long 1082static unsigned long
567insert_bat (unsigned long insn, 1083insert_bat (unsigned long insn,
568 long value ATTRIBUTE_UNUSED, 1084 long value ATTRIBUTE_UNUSED,
569 int dialect ATTRIBUTE_UNUSED, 1085 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
570 const char **errmsg ATTRIBUTE_UNUSED) 1086 const char **errmsg ATTRIBUTE_UNUSED)
571{ 1087{
572 return insn | (((insn >> 21) & 0x1f) << 16); 1088 return insn | (((insn >> 21) & 0x1f) << 16);
@@ -574,7 +1090,7 @@ insert_bat (unsigned long insn,
574 1090
575static long 1091static long
576extract_bat (unsigned long insn, 1092extract_bat (unsigned long insn,
577 int dialect ATTRIBUTE_UNUSED, 1093 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
578 int *invalid) 1094 int *invalid)
579{ 1095{
580 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) 1096 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
@@ -591,7 +1107,7 @@ extract_bat (unsigned long insn,
591static unsigned long 1107static unsigned long
592insert_bba (unsigned long insn, 1108insert_bba (unsigned long insn,
593 long value ATTRIBUTE_UNUSED, 1109 long value ATTRIBUTE_UNUSED,
594 int dialect ATTRIBUTE_UNUSED, 1110 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
595 const char **errmsg ATTRIBUTE_UNUSED) 1111 const char **errmsg ATTRIBUTE_UNUSED)
596{ 1112{
597 return insn | (((insn >> 16) & 0x1f) << 11); 1113 return insn | (((insn >> 16) & 0x1f) << 11);
@@ -599,7 +1115,7 @@ insert_bba (unsigned long insn,
599 1115
600static long 1116static long
601extract_bba (unsigned long insn, 1117extract_bba (unsigned long insn,
602 int dialect ATTRIBUTE_UNUSED, 1118 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
603 int *invalid) 1119 int *invalid)
604{ 1120{
605 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) 1121 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
@@ -624,13 +1140,15 @@ extract_bba (unsigned long insn,
624 extract_bdp always occur in pairs. One or the other will always 1140 extract_bdp always occur in pairs. One or the other will always
625 be valid. */ 1141 be valid. */
626 1142
1143#define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1144
627static unsigned long 1145static unsigned long
628insert_bdm (unsigned long insn, 1146insert_bdm (unsigned long insn,
629 long value, 1147 long value,
630 int dialect, 1148 ppc_cpu_t dialect,
631 const char **errmsg ATTRIBUTE_UNUSED) 1149 const char **errmsg ATTRIBUTE_UNUSED)
632{ 1150{
633 if ((dialect & PPC_OPCODE_POWER4) == 0) 1151 if ((dialect & ISA_V2) == 0)
634 { 1152 {
635 if ((value & 0x8000) != 0) 1153 if ((value & 0x8000) != 0)
636 insn |= 1 << 21; 1154 insn |= 1 << 21;
@@ -647,10 +1165,10 @@ insert_bdm (unsigned long insn,
647 1165
648static long 1166static long
649extract_bdm (unsigned long insn, 1167extract_bdm (unsigned long insn,
650 int dialect, 1168 ppc_cpu_t dialect,
651 int *invalid) 1169 int *invalid)
652{ 1170{
653 if ((dialect & PPC_OPCODE_POWER4) == 0) 1171 if ((dialect & ISA_V2) == 0)
654 { 1172 {
655 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) 1173 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
656 *invalid = 1; 1174 *invalid = 1;
@@ -672,10 +1190,10 @@ extract_bdm (unsigned long insn,
672static unsigned long 1190static unsigned long
673insert_bdp (unsigned long insn, 1191insert_bdp (unsigned long insn,
674 long value, 1192 long value,
675 int dialect, 1193 ppc_cpu_t dialect,
676 const char **errmsg ATTRIBUTE_UNUSED) 1194 const char **errmsg ATTRIBUTE_UNUSED)
677{ 1195{
678 if ((dialect & PPC_OPCODE_POWER4) == 0) 1196 if ((dialect & ISA_V2) == 0)
679 { 1197 {
680 if ((value & 0x8000) == 0) 1198 if ((value & 0x8000) == 0)
681 insn |= 1 << 21; 1199 insn |= 1 << 21;
@@ -692,10 +1210,10 @@ insert_bdp (unsigned long insn,
692 1210
693static long 1211static long
694extract_bdp (unsigned long insn, 1212extract_bdp (unsigned long insn,
695 int dialect, 1213 ppc_cpu_t dialect,
696 int *invalid) 1214 int *invalid)
697{ 1215{
698 if ((dialect & PPC_OPCODE_POWER4) == 0) 1216 if ((dialect & ISA_V2) == 0)
699 { 1217 {
700 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) 1218 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
701 *invalid = 1; 1219 *invalid = 1;
@@ -710,52 +1228,41 @@ extract_bdp (unsigned long insn,
710 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 1228 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
711} 1229}
712 1230
713/* Check for legal values of a BO field. */ 1231static inline int
714 1232valid_bo_pre_v2 (long value)
715static int
716valid_bo (long value, int dialect, int extract)
717{ 1233{
718 if ((dialect & PPC_OPCODE_POWER4) == 0) 1234 /* Certain encodings have bits that are required to be zero.
719 { 1235 These are (z must be zero, y may be anything):
720 int valid; 1236 0000y
721 /* Certain encodings have bits that are required to be zero. 1237 0001y
722 These are (z must be zero, y may be anything): 1238 001zy
723 001zy 1239 0100y
724 011zy 1240 0101y
725 1z00y 1241 011zy
726 1z01y 1242 1z00y
727 1z1zz 1243 1z01y
728 */ 1244 1z1zz
729 switch (value & 0x14) 1245 */
730 { 1246 if ((value & 0x14) == 0)
731 default: 1247 return 1;
732 case 0: 1248 else if ((value & 0x14) == 0x4)
733 valid = 1; 1249 return (value & 0x2) == 0;
734 break; 1250 else if ((value & 0x14) == 0x10)
735 case 0x4: 1251 return (value & 0x8) == 0;
736 valid = (value & 0x2) == 0; 1252 else
737 break; 1253 return value == 0x14;
738 case 0x10: 1254}
739 valid = (value & 0x8) == 0;
740 break;
741 case 0x14:
742 valid = value == 0x14;
743 break;
744 }
745 /* When disassembling with -Many, accept power4 encodings too. */
746 if (valid
747 || (dialect & PPC_OPCODE_ANY) == 0
748 || !extract)
749 return valid;
750 }
751 1255
1256static inline int
1257valid_bo_post_v2 (long value)
1258{
752 /* Certain encodings have bits that are required to be zero. 1259 /* Certain encodings have bits that are required to be zero.
753 These are (z must be zero, a & t may be anything): 1260 These are (z must be zero, a & t may be anything):
754 0000z 1261 0000z
755 0001z 1262 0001z
1263 001at
756 0100z 1264 0100z
757 0101z 1265 0101z
758 001at
759 011at 1266 011at
760 1a00t 1267 1a00t
761 1a01t 1268 1a01t
@@ -769,23 +1276,43 @@ valid_bo (long value, int dialect, int extract)
769 return 1; 1276 return 1;
770} 1277}
771 1278
1279/* Check for legal values of a BO field. */
1280
1281static int
1282valid_bo (long value, ppc_cpu_t dialect, int extract)
1283{
1284 int valid_y = valid_bo_pre_v2 (value);
1285 int valid_at = valid_bo_post_v2 (value);
1286
1287 /* When disassembling with -Many, accept either encoding on the
1288 second pass through opcodes. */
1289 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
1290 return valid_y || valid_at;
1291 if ((dialect & ISA_V2) == 0)
1292 return valid_y;
1293 else
1294 return valid_at;
1295}
1296
772/* The BO field in a B form instruction. Warn about attempts to set 1297/* The BO field in a B form instruction. Warn about attempts to set
773 the field to an illegal value. */ 1298 the field to an illegal value. */
774 1299
775static unsigned long 1300static unsigned long
776insert_bo (unsigned long insn, 1301insert_bo (unsigned long insn,
777 long value, 1302 long value,
778 int dialect, 1303 ppc_cpu_t dialect,
779 const char **errmsg) 1304 const char **errmsg)
780{ 1305{
781 if (!valid_bo (value, dialect, 0)) 1306 if (!valid_bo (value, dialect, 0))
782 *errmsg = _("invalid conditional option"); 1307 *errmsg = _("invalid conditional option");
1308 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1309 *errmsg = _("invalid counter access");
783 return insn | ((value & 0x1f) << 21); 1310 return insn | ((value & 0x1f) << 21);
784} 1311}
785 1312
786static long 1313static long
787extract_bo (unsigned long insn, 1314extract_bo (unsigned long insn,
788 int dialect, 1315 ppc_cpu_t dialect,
789 int *invalid) 1316 int *invalid)
790{ 1317{
791 long value; 1318 long value;
@@ -803,11 +1330,13 @@ extract_bo (unsigned long insn,
803static unsigned long 1330static unsigned long
804insert_boe (unsigned long insn, 1331insert_boe (unsigned long insn,
805 long value, 1332 long value,
806 int dialect, 1333 ppc_cpu_t dialect,
807 const char **errmsg) 1334 const char **errmsg)
808{ 1335{
809 if (!valid_bo (value, dialect, 0)) 1336 if (!valid_bo (value, dialect, 0))
810 *errmsg = _("invalid conditional option"); 1337 *errmsg = _("invalid conditional option");
1338 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1339 *errmsg = _("invalid counter access");
811 else if ((value & 1) != 0) 1340 else if ((value & 1) != 0)
812 *errmsg = _("attempt to set y bit when using + or - modifier"); 1341 *errmsg = _("attempt to set y bit when using + or - modifier");
813 1342
@@ -816,7 +1345,7 @@ insert_boe (unsigned long insn,
816 1345
817static long 1346static long
818extract_boe (unsigned long insn, 1347extract_boe (unsigned long insn,
819 int dialect, 1348 ppc_cpu_t dialect,
820 int *invalid) 1349 int *invalid)
821{ 1350{
822 long value; 1351 long value;
@@ -827,12 +1356,70 @@ extract_boe (unsigned long insn,
827 return value & 0x1e; 1356 return value & 0x1e;
828} 1357}
829 1358
1359/* The DCMX field in a X form instruction when the field is split
1360 into separate DC, DM and DX fields. */
1361
1362static unsigned long
1363insert_dcmxs (unsigned long insn,
1364 long value,
1365 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1366 const char **errmsg ATTRIBUTE_UNUSED)
1367{
1368 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40);
1369}
1370
1371static long
1372extract_dcmxs (unsigned long insn,
1373 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1374 int *invalid ATTRIBUTE_UNUSED)
1375{
1376 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1377}
1378
1379/* The D field in a DX form instruction when the field is split
1380 into separate D0, D1 and D2 fields. */
1381
1382static unsigned long
1383insert_dxd (unsigned long insn,
1384 long value,
1385 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1386 const char **errmsg ATTRIBUTE_UNUSED)
1387{
1388 return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
1389}
1390
1391static long
1392extract_dxd (unsigned long insn,
1393 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1394 int *invalid ATTRIBUTE_UNUSED)
1395{
1396 unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
1397 return (dxd ^ 0x8000) - 0x8000;
1398}
1399
1400static unsigned long
1401insert_dxdn (unsigned long insn,
1402 long value,
1403 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1404 const char **errmsg ATTRIBUTE_UNUSED)
1405{
1406 return insert_dxd (insn, -value, dialect, errmsg);
1407}
1408
1409static long
1410extract_dxdn (unsigned long insn,
1411 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1412 int *invalid ATTRIBUTE_UNUSED)
1413{
1414 return -extract_dxd (insn, dialect, invalid);
1415}
1416
830/* FXM mask in mfcr and mtcrf instructions. */ 1417/* FXM mask in mfcr and mtcrf instructions. */
831 1418
832static unsigned long 1419static unsigned long
833insert_fxm (unsigned long insn, 1420insert_fxm (unsigned long insn,
834 long value, 1421 long value,
835 int dialect, 1422 ppc_cpu_t dialect,
836 const char **errmsg) 1423 const char **errmsg)
837{ 1424{
838 /* If we're handling the mfocrf and mtocrf insns ensure that exactly 1425 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
@@ -846,19 +1433,13 @@ insert_fxm (unsigned long insn,
846 } 1433 }
847 } 1434 }
848 1435
849 /* If the optional field on mfcr is missing that means we want to use
850 the old form of the instruction that moves the whole cr. In that
851 case we'll have VALUE zero. There doesn't seem to be a way to
852 distinguish this from the case where someone writes mfcr %r3,0. */
853 else if (value == 0)
854 ;
855
856 /* If only one bit of the FXM field is set, we can use the new form 1436 /* If only one bit of the FXM field is set, we can use the new form
857 of the instruction, which is faster. Unlike the Power4 branch hint 1437 of the instruction, which is faster. Unlike the Power4 branch hint
858 encoding, this is not backward compatible. Do not generate the 1438 encoding, this is not backward compatible. Do not generate the
859 new form unless -mpower4 has been given, or -many and the two 1439 new form unless -mpower4 has been given, or -many and the two
860 operand form of mfcr was used. */ 1440 operand form of mfcr was used. */
861 else if ((value & -value) == value 1441 else if (value > 0
1442 && (value & -value) == value
862 && ((dialect & PPC_OPCODE_POWER4) != 0 1443 && ((dialect & PPC_OPCODE_POWER4) != 0
863 || ((dialect & PPC_OPCODE_ANY) != 0 1444 || ((dialect & PPC_OPCODE_ANY) != 0
864 && (insn & (0x3ff << 1)) == 19 << 1))) 1445 && (insn & (0x3ff << 1)) == 19 << 1)))
@@ -867,7 +1448,10 @@ insert_fxm (unsigned long insn,
867 /* Any other value on mfcr is an error. */ 1448 /* Any other value on mfcr is an error. */
868 else if ((insn & (0x3ff << 1)) == 19 << 1) 1449 else if ((insn & (0x3ff << 1)) == 19 << 1)
869 { 1450 {
870 *errmsg = _("ignoring invalid mfcr mask"); 1451 /* A value of -1 means we used the one operand form of
1452 mfcr which is valid. */
1453 if (value != -1)
1454 *errmsg = _("invalid mfcr mask");
871 value = 0; 1455 value = 0;
872 } 1456 }
873 1457
@@ -876,7 +1460,7 @@ insert_fxm (unsigned long insn,
876 1460
877static long 1461static long
878extract_fxm (unsigned long insn, 1462extract_fxm (unsigned long insn,
879 int dialect ATTRIBUTE_UNUSED, 1463 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
880 int *invalid) 1464 int *invalid)
881{ 1465{
882 long mask = (insn >> 12) & 0xff; 1466 long mask = (insn >> 12) & 0xff;
@@ -894,11 +1478,88 @@ extract_fxm (unsigned long insn,
894 { 1478 {
895 if (mask != 0) 1479 if (mask != 0)
896 *invalid = 1; 1480 *invalid = 1;
1481 else
1482 mask = -1;
897 } 1483 }
898 1484
899 return mask; 1485 return mask;
900} 1486}
901 1487
1488static unsigned long
1489insert_li20 (unsigned long insn,
1490 long value,
1491 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1492 const char **errmsg ATTRIBUTE_UNUSED)
1493{
1494 return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1495}
1496
1497static long
1498extract_li20 (unsigned long insn,
1499 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1500 int *invalid ATTRIBUTE_UNUSED)
1501{
1502 long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1503
1504 return ext
1505 | (((insn >> 11) & 0xf) << 16)
1506 | (((insn >> 17) & 0xf) << 12)
1507 | (((insn >> 16) & 0x1) << 11)
1508 | (insn & 0x7ff);
1509}
1510
1511/* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
1512 For SYNC, some L values are reserved:
1513 * Value 3 is reserved on newer server cpus.
1514 * Values 2 and 3 are reserved on all other cpus. */
1515
1516static unsigned long
1517insert_ls (unsigned long insn,
1518 long value,
1519 ppc_cpu_t dialect,
1520 const char **errmsg)
1521{
1522 /* For SYNC, some L values are illegal. */
1523 if (((insn >> 1) & 0x3ff) == 598)
1524 {
1525 long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
1526 if (value > max_lvalue)
1527 {
1528 *errmsg = _("illegal L operand value");
1529 return insn;
1530 }
1531 }
1532
1533 return insn | ((value & 0x3) << 21);
1534}
1535
1536/* The 4-bit E field in a sync instruction that accepts 2 operands.
1537 If ESYNC is non-zero, then the L field must be either 0 or 1 and
1538 the complement of ESYNC-bit2. */
1539
1540static unsigned long
1541insert_esync (unsigned long insn,
1542 long value,
1543 ppc_cpu_t dialect,
1544 const char **errmsg)
1545{
1546 unsigned long ls = (insn >> 21) & 0x03;
1547
1548 if (value == 0)
1549 {
1550 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
1551 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
1552 *errmsg = _("illegal L operand value");
1553 return insn;
1554 }
1555
1556 if ((ls & ~0x1)
1557 || (((value >> 1) & 0x1) ^ ls) == 0)
1558 *errmsg = _("incompatible L operand value");
1559
1560 return insn | ((value & 0xf) << 16);
1561}
1562
902/* The MB and ME fields in an M form instruction expressed as a single 1563/* The MB and ME fields in an M form instruction expressed as a single
903 operand which is itself a bitmask. The extraction function always 1564 operand which is itself a bitmask. The extraction function always
904 marks it as invalid, since we never want to recognize an 1565 marks it as invalid, since we never want to recognize an
@@ -907,7 +1568,7 @@ extract_fxm (unsigned long insn,
907static unsigned long 1568static unsigned long
908insert_mbe (unsigned long insn, 1569insert_mbe (unsigned long insn,
909 long value, 1570 long value,
910 int dialect ATTRIBUTE_UNUSED, 1571 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
911 const char **errmsg) 1572 const char **errmsg)
912{ 1573{
913 unsigned long uval, mask; 1574 unsigned long uval, mask;
@@ -959,7 +1620,7 @@ insert_mbe (unsigned long insn,
959 1620
960static long 1621static long
961extract_mbe (unsigned long insn, 1622extract_mbe (unsigned long insn,
962 int dialect ATTRIBUTE_UNUSED, 1623 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
963 int *invalid) 1624 int *invalid)
964{ 1625{
965 long ret; 1626 long ret;
@@ -993,7 +1654,7 @@ extract_mbe (unsigned long insn,
993static unsigned long 1654static unsigned long
994insert_mb6 (unsigned long insn, 1655insert_mb6 (unsigned long insn,
995 long value, 1656 long value,
996 int dialect ATTRIBUTE_UNUSED, 1657 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
997 const char **errmsg ATTRIBUTE_UNUSED) 1658 const char **errmsg ATTRIBUTE_UNUSED)
998{ 1659{
999 return insn | ((value & 0x1f) << 6) | (value & 0x20); 1660 return insn | ((value & 0x1f) << 6) | (value & 0x20);
@@ -1001,7 +1662,7 @@ insert_mb6 (unsigned long insn,
1001 1662
1002static long 1663static long
1003extract_mb6 (unsigned long insn, 1664extract_mb6 (unsigned long insn,
1004 int dialect ATTRIBUTE_UNUSED, 1665 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1005 int *invalid ATTRIBUTE_UNUSED) 1666 int *invalid ATTRIBUTE_UNUSED)
1006{ 1667{
1007 return ((insn >> 6) & 0x1f) | (insn & 0x20); 1668 return ((insn >> 6) & 0x1f) | (insn & 0x20);
@@ -1012,7 +1673,7 @@ extract_mb6 (unsigned long insn,
1012 1673
1013static long 1674static long
1014extract_nb (unsigned long insn, 1675extract_nb (unsigned long insn,
1015 int dialect ATTRIBUTE_UNUSED, 1676 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1016 int *invalid ATTRIBUTE_UNUSED) 1677 int *invalid ATTRIBUTE_UNUSED)
1017{ 1678{
1018 long ret; 1679 long ret;
@@ -1023,6 +1684,26 @@ extract_nb (unsigned long insn,
1023 return ret; 1684 return ret;
1024} 1685}
1025 1686
1687/* The NB field in an lswi instruction, which has special value
1688 restrictions. The value 32 is stored as 0. */
1689
1690static unsigned long
1691insert_nbi (unsigned long insn,
1692 long value,
1693 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1694 const char **errmsg ATTRIBUTE_UNUSED)
1695{
1696 long rtvalue = (insn & RT_MASK) >> 21;
1697 long ravalue = (insn & RA_MASK) >> 16;
1698
1699 if (value == 0)
1700 value = 32;
1701 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1702 : ravalue))
1703 *errmsg = _("address register in load range");
1704 return insn | ((value & 0x1f) << 11);
1705}
1706
1026/* The NSI field in a D form instruction. This is the same as the SI 1707/* The NSI field in a D form instruction. This is the same as the SI
1027 field, only negated. The extraction function always marks it as 1708 field, only negated. The extraction function always marks it as
1028 invalid, since we never want to recognize an instruction which uses 1709 invalid, since we never want to recognize an instruction which uses
@@ -1031,7 +1712,7 @@ extract_nb (unsigned long insn,
1031static unsigned long 1712static unsigned long
1032insert_nsi (unsigned long insn, 1713insert_nsi (unsigned long insn,
1033 long value, 1714 long value,
1034 int dialect ATTRIBUTE_UNUSED, 1715 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1035 const char **errmsg ATTRIBUTE_UNUSED) 1716 const char **errmsg ATTRIBUTE_UNUSED)
1036{ 1717{
1037 return insn | (-value & 0xffff); 1718 return insn | (-value & 0xffff);
@@ -1039,7 +1720,7 @@ insert_nsi (unsigned long insn,
1039 1720
1040static long 1721static long
1041extract_nsi (unsigned long insn, 1722extract_nsi (unsigned long insn,
1042 int dialect ATTRIBUTE_UNUSED, 1723 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1043 int *invalid) 1724 int *invalid)
1044{ 1725{
1045 *invalid = 1; 1726 *invalid = 1;
@@ -1053,7 +1734,7 @@ extract_nsi (unsigned long insn,
1053static unsigned long 1734static unsigned long
1054insert_ral (unsigned long insn, 1735insert_ral (unsigned long insn,
1055 long value, 1736 long value,
1056 int dialect ATTRIBUTE_UNUSED, 1737 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1057 const char **errmsg) 1738 const char **errmsg)
1058{ 1739{
1059 if (value == 0 1740 if (value == 0
@@ -1068,7 +1749,7 @@ insert_ral (unsigned long insn,
1068static unsigned long 1749static unsigned long
1069insert_ram (unsigned long insn, 1750insert_ram (unsigned long insn,
1070 long value, 1751 long value,
1071 int dialect ATTRIBUTE_UNUSED, 1752 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1072 const char **errmsg) 1753 const char **errmsg)
1073{ 1754{
1074 if ((unsigned long) value >= ((insn >> 21) & 0x1f)) 1755 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
@@ -1076,13 +1757,13 @@ insert_ram (unsigned long insn,
1076 return insn | ((value & 0x1f) << 16); 1757 return insn | ((value & 0x1f) << 16);
1077} 1758}
1078 1759
1079/* The RA field in the DQ form lq instruction, which has special 1760/* The RA field in the DQ form lq or an lswx instruction, which have special
1080 value restrictions. */ 1761 value restrictions. */
1081 1762
1082static unsigned long 1763static unsigned long
1083insert_raq (unsigned long insn, 1764insert_raq (unsigned long insn,
1084 long value, 1765 long value,
1085 int dialect ATTRIBUTE_UNUSED, 1766 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1086 const char **errmsg) 1767 const char **errmsg)
1087{ 1768{
1088 long rtvalue = (insn & RT_MASK) >> 21; 1769 long rtvalue = (insn & RT_MASK) >> 21;
@@ -1099,7 +1780,7 @@ insert_raq (unsigned long insn,
1099static unsigned long 1780static unsigned long
1100insert_ras (unsigned long insn, 1781insert_ras (unsigned long insn,
1101 long value, 1782 long value,
1102 int dialect ATTRIBUTE_UNUSED, 1783 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1103 const char **errmsg) 1784 const char **errmsg)
1104{ 1785{
1105 if (value == 0) 1786 if (value == 0)
@@ -1116,7 +1797,7 @@ insert_ras (unsigned long insn,
1116static unsigned long 1797static unsigned long
1117insert_rbs (unsigned long insn, 1798insert_rbs (unsigned long insn,
1118 long value ATTRIBUTE_UNUSED, 1799 long value ATTRIBUTE_UNUSED,
1119 int dialect ATTRIBUTE_UNUSED, 1800 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1120 const char **errmsg ATTRIBUTE_UNUSED) 1801 const char **errmsg ATTRIBUTE_UNUSED)
1121{ 1802{
1122 return insn | (((insn >> 21) & 0x1f) << 11); 1803 return insn | (((insn >> 21) & 0x1f) << 11);
@@ -1124,7 +1805,7 @@ insert_rbs (unsigned long insn,
1124 1805
1125static long 1806static long
1126extract_rbs (unsigned long insn, 1807extract_rbs (unsigned long insn,
1127 int dialect ATTRIBUTE_UNUSED, 1808 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1128 int *invalid) 1809 int *invalid)
1129{ 1810{
1130 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) 1811 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
@@ -1132,23 +1813,182 @@ extract_rbs (unsigned long insn,
1132 return 0; 1813 return 0;
1133} 1814}
1134 1815
1816/* The RB field in an lswx instruction, which has special value
1817 restrictions. */
1818
1819static unsigned long
1820insert_rbx (unsigned long insn,
1821 long value,
1822 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1823 const char **errmsg)
1824{
1825 long rtvalue = (insn & RT_MASK) >> 21;
1826
1827 if (value == rtvalue)
1828 *errmsg = _("source and target register operands must be different");
1829 return insn | ((value & 0x1f) << 11);
1830}
1831
1832/* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1833static unsigned long
1834insert_sci8 (unsigned long insn,
1835 long value,
1836 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1837 const char **errmsg)
1838{
1839 unsigned int fill_scale = 0;
1840 unsigned long ui8 = value;
1841
1842 if ((ui8 & 0xffffff00) == 0)
1843 ;
1844 else if ((ui8 & 0xffffff00) == 0xffffff00)
1845 fill_scale = 0x400;
1846 else if ((ui8 & 0xffff00ff) == 0)
1847 {
1848 fill_scale = 1 << 8;
1849 ui8 >>= 8;
1850 }
1851 else if ((ui8 & 0xffff00ff) == 0xffff00ff)
1852 {
1853 fill_scale = 0x400 | (1 << 8);
1854 ui8 >>= 8;
1855 }
1856 else if ((ui8 & 0xff00ffff) == 0)
1857 {
1858 fill_scale = 2 << 8;
1859 ui8 >>= 16;
1860 }
1861 else if ((ui8 & 0xff00ffff) == 0xff00ffff)
1862 {
1863 fill_scale = 0x400 | (2 << 8);
1864 ui8 >>= 16;
1865 }
1866 else if ((ui8 & 0x00ffffff) == 0)
1867 {
1868 fill_scale = 3 << 8;
1869 ui8 >>= 24;
1870 }
1871 else if ((ui8 & 0x00ffffff) == 0x00ffffff)
1872 {
1873 fill_scale = 0x400 | (3 << 8);
1874 ui8 >>= 24;
1875 }
1876 else
1877 {
1878 *errmsg = _("illegal immediate value");
1879 ui8 = 0;
1880 }
1881
1882 return insn | fill_scale | (ui8 & 0xff);
1883}
1884
1885static long
1886extract_sci8 (unsigned long insn,
1887 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1888 int *invalid ATTRIBUTE_UNUSED)
1889{
1890 int fill = insn & 0x400;
1891 int scale_factor = (insn & 0x300) >> 5;
1892 long value = (insn & 0xff) << scale_factor;
1893
1894 if (fill != 0)
1895 value |= ~((long) 0xff << scale_factor);
1896 return value;
1897}
1898
1899static unsigned long
1900insert_sci8n (unsigned long insn,
1901 long value,
1902 ppc_cpu_t dialect,
1903 const char **errmsg)
1904{
1905 return insert_sci8 (insn, -value, dialect, errmsg);
1906}
1907
1908static long
1909extract_sci8n (unsigned long insn,
1910 ppc_cpu_t dialect,
1911 int *invalid)
1912{
1913 return -extract_sci8 (insn, dialect, invalid);
1914}
1915
1916static unsigned long
1917insert_sd4h (unsigned long insn,
1918 long value,
1919 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1920 const char **errmsg ATTRIBUTE_UNUSED)
1921{
1922 return insn | ((value & 0x1e) << 7);
1923}
1924
1925static long
1926extract_sd4h (unsigned long insn,
1927 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1928 int *invalid ATTRIBUTE_UNUSED)
1929{
1930 return ((insn >> 8) & 0xf) << 1;
1931}
1932
1933static unsigned long
1934insert_sd4w (unsigned long insn,
1935 long value,
1936 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1937 const char **errmsg ATTRIBUTE_UNUSED)
1938{
1939 return insn | ((value & 0x3c) << 6);
1940}
1941
1942static long
1943extract_sd4w (unsigned long insn,
1944 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1945 int *invalid ATTRIBUTE_UNUSED)
1946{
1947 return ((insn >> 8) & 0xf) << 2;
1948}
1949
1950static unsigned long
1951insert_oimm (unsigned long insn,
1952 long value,
1953 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1954 const char **errmsg ATTRIBUTE_UNUSED)
1955{
1956 return insn | (((value - 1) & 0x1f) << 4);
1957}
1958
1959static long
1960extract_oimm (unsigned long insn,
1961 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1962 int *invalid ATTRIBUTE_UNUSED)
1963{
1964 return ((insn >> 4) & 0x1f) + 1;
1965}
1966
1135/* The SH field in an MD form instruction. This is split. */ 1967/* The SH field in an MD form instruction. This is split. */
1136 1968
1137static unsigned long 1969static unsigned long
1138insert_sh6 (unsigned long insn, 1970insert_sh6 (unsigned long insn,
1139 long value, 1971 long value,
1140 int dialect ATTRIBUTE_UNUSED, 1972 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1141 const char **errmsg ATTRIBUTE_UNUSED) 1973 const char **errmsg ATTRIBUTE_UNUSED)
1142{ 1974{
1143 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 1975 /* SH6 operand in the rldixor instructions. */
1976 if (PPC_OP (insn) == 4)
1977 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5);
1978 else
1979 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1144} 1980}
1145 1981
1146static long 1982static long
1147extract_sh6 (unsigned long insn, 1983extract_sh6 (unsigned long insn,
1148 int dialect ATTRIBUTE_UNUSED, 1984 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1149 int *invalid ATTRIBUTE_UNUSED) 1985 int *invalid ATTRIBUTE_UNUSED)
1150{ 1986{
1151 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); 1987 /* SH6 operand in the rldixor instructions. */
1988 if (PPC_OP (insn) == 4)
1989 return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20);
1990 else
1991 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1152} 1992}
1153 1993
1154/* The SPR field in an XFX form instruction. This is flipped--the 1994/* The SPR field in an XFX form instruction. This is flipped--the
@@ -1157,7 +1997,7 @@ extract_sh6 (unsigned long insn,
1157static unsigned long 1997static unsigned long
1158insert_spr (unsigned long insn, 1998insert_spr (unsigned long insn,
1159 long value, 1999 long value,
1160 int dialect ATTRIBUTE_UNUSED, 2000 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1161 const char **errmsg ATTRIBUTE_UNUSED) 2001 const char **errmsg ATTRIBUTE_UNUSED)
1162{ 2002{
1163 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 2003 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
@@ -1165,26 +2005,23 @@ insert_spr (unsigned long insn,
1165 2005
1166static long 2006static long
1167extract_spr (unsigned long insn, 2007extract_spr (unsigned long insn,
1168 int dialect ATTRIBUTE_UNUSED, 2008 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1169 int *invalid ATTRIBUTE_UNUSED) 2009 int *invalid ATTRIBUTE_UNUSED)
1170{ 2010{
1171 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 2011 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1172} 2012}
1173 2013
1174/* Some dialects have 8 SPRG registers instead of the standard 4. */ 2014/* Some dialects have 8 SPRG registers instead of the standard 4. */
2015#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
1175 2016
1176static unsigned long 2017static unsigned long
1177insert_sprg (unsigned long insn, 2018insert_sprg (unsigned long insn,
1178 long value, 2019 long value,
1179 int dialect, 2020 ppc_cpu_t dialect,
1180 const char **errmsg) 2021 const char **errmsg)
1181{ 2022{
1182 /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1183 as a synonym. If ever a 405 specific dialect is added this
1184 check should use that instead. */
1185 if (value > 7 2023 if (value > 7
1186 || (value > 3 2024 || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
1187 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1188 *errmsg = _("invalid sprg number"); 2025 *errmsg = _("invalid sprg number");
1189 2026
1190 /* If this is mfsprg4..7 then use spr 260..263 which can be read in 2027 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
@@ -1197,54 +2034,272 @@ insert_sprg (unsigned long insn,
1197 2034
1198static long 2035static long
1199extract_sprg (unsigned long insn, 2036extract_sprg (unsigned long insn,
1200 int dialect, 2037 ppc_cpu_t dialect,
1201 int *invalid) 2038 int *invalid)
1202{ 2039{
1203 unsigned long val = (insn >> 16) & 0x1f; 2040 unsigned long val = (insn >> 16) & 0x1f;
1204 2041
1205 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 2042 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1206 If not BOOKE or 405, then both use only 272..275. */ 2043 If not BOOKE, 405 or VLE, then both use only 272..275. */
1207 if (val <= 3 2044 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
1208 || (val < 0x10 && (insn & 0x100) != 0) 2045 || (val - 0x10 > 7 && (insn & 0x100) != 0)
1209 || (val - 0x10 > 3 2046 || val <= 3
1210 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0)) 2047 || (val & 8) != 0)
1211 *invalid = 1; 2048 *invalid = 1;
1212 return val & 7; 2049 return val & 7;
1213} 2050}
1214 2051
1215/* The TBR field in an XFX instruction. This is just like SPR, but it 2052/* The TBR field in an XFX instruction. This is just like SPR, but it
1216 is optional. When TBR is omitted, it must be inserted as 268 (the 2053 is optional. */
1217 magic number of the TB register). These functions treat 0
1218 (indicating an omitted optional operand) as 268. This means that
1219 ``mftb 4,0'' is not handled correctly. This does not matter very
1220 much, since the architecture manual does not define mftb as
1221 accepting any values other than 268 or 269. */
1222
1223#define TB (268)
1224 2054
1225static unsigned long 2055static unsigned long
1226insert_tbr (unsigned long insn, 2056insert_tbr (unsigned long insn,
1227 long value, 2057 long value,
1228 int dialect ATTRIBUTE_UNUSED, 2058 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1229 const char **errmsg ATTRIBUTE_UNUSED) 2059 const char **errmsg)
1230{ 2060{
1231 if (value == 0) 2061 if (value != 268 && value != 269)
1232 value = TB; 2062 *errmsg = _("invalid tbr number");
1233 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 2063 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1234} 2064}
1235 2065
1236static long 2066static long
1237extract_tbr (unsigned long insn, 2067extract_tbr (unsigned long insn,
1238 int dialect ATTRIBUTE_UNUSED, 2068 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1239 int *invalid ATTRIBUTE_UNUSED) 2069 int *invalid)
1240{ 2070{
1241 long ret; 2071 long ret;
1242 2072
1243 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 2073 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1244 if (ret == TB) 2074 if (ret != 268 && ret != 269)
1245 ret = 0; 2075 *invalid = 1;
1246 return ret; 2076 return ret;
1247} 2077}
2078
2079/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
2080
2081static unsigned long
2082insert_xt6 (unsigned long insn,
2083 long value,
2084 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2085 const char **errmsg ATTRIBUTE_UNUSED)
2086{
2087 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
2088}
2089
2090static long
2091extract_xt6 (unsigned long insn,
2092 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2093 int *invalid ATTRIBUTE_UNUSED)
2094{
2095 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
2096}
2097
2098/* The XT and XS fields in an DQ form VSX instruction. This is split. */
2099static unsigned long
2100insert_xtq6 (unsigned long insn,
2101 long value,
2102 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2103 const char **errmsg ATTRIBUTE_UNUSED)
2104{
2105 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
2106}
2107
2108static long
2109extract_xtq6 (unsigned long insn,
2110 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2111 int *invalid ATTRIBUTE_UNUSED)
2112{
2113 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
2114}
2115
2116/* The XA field in an XX3 form instruction. This is split. */
2117
2118static unsigned long
2119insert_xa6 (unsigned long insn,
2120 long value,
2121 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2122 const char **errmsg ATTRIBUTE_UNUSED)
2123{
2124 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
2125}
2126
2127static long
2128extract_xa6 (unsigned long insn,
2129 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2130 int *invalid ATTRIBUTE_UNUSED)
2131{
2132 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
2133}
2134
2135/* The XB field in an XX3 form instruction. This is split. */
2136
2137static unsigned long
2138insert_xb6 (unsigned long insn,
2139 long value,
2140 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2141 const char **errmsg ATTRIBUTE_UNUSED)
2142{
2143 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2144}
2145
2146static long
2147extract_xb6 (unsigned long insn,
2148 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2149 int *invalid ATTRIBUTE_UNUSED)
2150{
2151 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
2152}
2153
2154/* The XB field in an XX3 form instruction when it must be the same as
2155 the XA field in the instruction. This is used for extended
2156 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
2157 function just copies the XA field into the XB field, and the
2158 extraction function just checks that the fields are the same. */
2159
2160static unsigned long
2161insert_xb6s (unsigned long insn,
2162 long value ATTRIBUTE_UNUSED,
2163 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2164 const char **errmsg ATTRIBUTE_UNUSED)
2165{
2166 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
2167}
2168
2169static long
2170extract_xb6s (unsigned long insn,
2171 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2172 int *invalid)
2173{
2174 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
2175 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
2176 *invalid = 1;
2177 return 0;
2178}
2179
2180/* The XC field in an XX4 form instruction. This is split. */
2181
2182static unsigned long
2183insert_xc6 (unsigned long insn,
2184 long value,
2185 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2186 const char **errmsg ATTRIBUTE_UNUSED)
2187{
2188 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
2189}
2190
2191static long
2192extract_xc6 (unsigned long insn,
2193 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2194 int *invalid ATTRIBUTE_UNUSED)
2195{
2196 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
2197}
2198
2199static unsigned long
2200insert_dm (unsigned long insn,
2201 long value,
2202 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2203 const char **errmsg)
2204{
2205 if (value != 0 && value != 1)
2206 *errmsg = _("invalid constant");
2207 return insn | (((value) ? 3 : 0) << 8);
2208}
2209
2210static long
2211extract_dm (unsigned long insn,
2212 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2213 int *invalid)
2214{
2215 long value;
2216
2217 value = (insn >> 8) & 3;
2218 if (value != 0 && value != 3)
2219 *invalid = 1;
2220 return (value) ? 1 : 0;
2221}
2222
2223/* The VLESIMM field in an I16A form instruction. This is split. */
2224
2225static unsigned long
2226insert_vlesi (unsigned long insn,
2227 long value,
2228 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2229 const char **errmsg ATTRIBUTE_UNUSED)
2230{
2231 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2232}
2233
2234static long
2235extract_vlesi (unsigned long insn,
2236 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2237 int *invalid ATTRIBUTE_UNUSED)
2238{
2239 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2240 value = (value ^ 0x8000) - 0x8000;
2241 return value;
2242}
2243
2244static unsigned long
2245insert_vlensi (unsigned long insn,
2246 long value,
2247 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2248 const char **errmsg ATTRIBUTE_UNUSED)
2249{
2250 value = -value;
2251 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2252}
2253static long
2254extract_vlensi (unsigned long insn,
2255 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2256 int *invalid ATTRIBUTE_UNUSED)
2257{
2258 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2259 value = (value ^ 0x8000) - 0x8000;
2260 /* Don't use for disassembly. */
2261 *invalid = 1;
2262 return -value;
2263}
2264
2265/* The VLEUIMM field in an I16A form instruction. This is split. */
2266
2267static unsigned long
2268insert_vleui (unsigned long insn,
2269 long value,
2270 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2271 const char **errmsg ATTRIBUTE_UNUSED)
2272{
2273 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2274}
2275
2276static long
2277extract_vleui (unsigned long insn,
2278 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2279 int *invalid ATTRIBUTE_UNUSED)
2280{
2281 return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2282}
2283
2284/* The VLEUIMML field in an I16L form instruction. This is split. */
2285
2286static unsigned long
2287insert_vleil (unsigned long insn,
2288 long value,
2289 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2290 const char **errmsg ATTRIBUTE_UNUSED)
2291{
2292 return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2293}
2294
2295static long
2296extract_vleil (unsigned long insn,
2297 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2298 int *invalid ATTRIBUTE_UNUSED)
2299{
2300 return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2301}
2302
1248 2303
1249/* Macros used to form opcodes. */ 2304/* Macros used to form opcodes. */
1250 2305
@@ -1264,6 +2319,17 @@ extract_tbr (unsigned long insn,
1264#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) 2319#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1265#define OPL_MASK OPL (0x3f,1) 2320#define OPL_MASK OPL (0x3f,1)
1266 2321
2322/* The main opcode combined with an update code in D form instruction.
2323 Used for extended mnemonics for VLE memory instructions. */
2324#define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2325#define OPVUP_MASK OPVUP (0x3f, 0xff)
2326
2327/* The main opcode combined with an update code and the RT fields specified in
2328 D form instruction. Used for VLE volatile context save/restore
2329 instructions. */
2330#define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21))
2331#define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
2332
1267/* An A form instruction. */ 2333/* An A form instruction. */
1268#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) 2334#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1269#define A_MASK A (0x3f, 0x1f, 1) 2335#define A_MASK A (0x3f, 0x1f, 1)
@@ -1284,6 +2350,43 @@ extract_tbr (unsigned long insn,
1284#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) 2350#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1285#define B_MASK B (0x3f, 1, 1) 2351#define B_MASK B (0x3f, 1, 1)
1286 2352
2353/* A BD8 form instruction. This is a 16-bit instruction. */
2354#define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2355#define BD8_MASK BD8 (0x3f, 1, 1)
2356
2357/* Another BD8 form instruction. This is a 16-bit instruction. */
2358#define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2359#define BD8IO_MASK BD8IO (0x1f)
2360
2361/* A BD8 form instruction for simplified mnemonics. */
2362#define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2363/* A mask that excludes BO32 and BI32. */
2364#define EBD8IO1_MASK 0xf800
2365/* A mask that includes BO32 and excludes BI32. */
2366#define EBD8IO2_MASK 0xfc00
2367/* A mask that include BO32 AND BI32. */
2368#define EBD8IO3_MASK 0xff00
2369
2370/* A BD15 form instruction. */
2371#define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2372#define BD15_MASK BD15 (0x3f, 0xf, 1)
2373
2374/* A BD15 form instruction for extended conditional branch mnemonics. */
2375#define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2376#define EBD15_MASK 0xfff00001
2377
2378/* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2379#define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2380 | (((aa) & 0xf) << 22) \
2381 | (((bo) & 0x3) << 20) \
2382 | (((bi) & 0x3) << 16) \
2383 | ((lk) & 1)
2384#define EBD15BI_MASK 0xfff30001
2385
2386/* A BD24 form instruction. */
2387#define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2388#define BD24_MASK BD24 (0x3f, 1, 1)
2389
1287/* A B form instruction setting the BO field. */ 2390/* A B form instruction setting the BO field. */
1288#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 2391#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1289#define BBO_MASK BBO (0x3f, 0x1f, 1, 1) 2392#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
@@ -1291,7 +2394,7 @@ extract_tbr (unsigned long insn,
1291/* A BBO_MASK with the y bit of the BO field removed. This permits 2394/* A BBO_MASK with the y bit of the BO field removed. This permits
1292 matching a conditional branch regardless of the setting of the y 2395 matching a conditional branch regardless of the setting of the y
1293 bit. Similarly for the 'at' bits used for power4 branch hints. */ 2396 bit. Similarly for the 'at' bits used for power4 branch hints. */
1294#define Y_MASK (((unsigned long) 1) << 21) 2397#define Y_MASK (((unsigned long) 1) << 21)
1295#define AT1_MASK (((unsigned long) 3) << 21) 2398#define AT1_MASK (((unsigned long) 3) << 21)
1296#define AT2_MASK (((unsigned long) 9) << 21) 2399#define AT2_MASK (((unsigned long) 9) << 21)
1297#define BBOY_MASK (BBO_MASK &~ Y_MASK) 2400#define BBOY_MASK (BBO_MASK &~ Y_MASK)
@@ -1312,6 +2415,12 @@ extract_tbr (unsigned long insn,
1312#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) 2415#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1313#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) 2416#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1314 2417
2418/* A VLE C form instruction. */
2419#define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2420#define C_LK_MASK C_LK(0x7fff, 1)
2421#define C(x) ((((unsigned long)(x)) & 0xffff))
2422#define C_MASK C(0xffff)
2423
1315/* An Context form instruction. */ 2424/* An Context form instruction. */
1316#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) 2425#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1317#define CTX_MASK CTX(0x3f, 0x7) 2426#define CTX_MASK CTX(0x3f, 0x7)
@@ -1323,22 +2432,46 @@ extract_tbr (unsigned long insn,
1323/* The main opcode mask with the RA field clear. */ 2432/* The main opcode mask with the RA field clear. */
1324#define DRA_MASK (OP_MASK | RA_MASK) 2433#define DRA_MASK (OP_MASK | RA_MASK)
1325 2434
2435/* A DQ form VSX instruction. */
2436#define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2437#define DQX_MASK DQX (0x3f, 7)
2438
1326/* A DS form instruction. */ 2439/* A DS form instruction. */
1327#define DSO(op, xop) (OP (op) | ((xop) & 0x3)) 2440#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1328#define DS_MASK DSO (0x3f, 3) 2441#define DS_MASK DSO (0x3f, 3)
1329 2442
1330/* A DE form instruction. */ 2443/* An DX form instruction. */
1331#define DEO(op, xop) (OP (op) | ((xop) & 0xf)) 2444#define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1332#define DE_MASK DEO (0x3e, 0xf) 2445#define DX_MASK DX (0x3f, 0x1f)
1333 2446
1334/* An EVSEL form instruction. */ 2447/* An EVSEL form instruction. */
1335#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) 2448#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1336#define EVSEL_MASK EVSEL(0x3f, 0xff) 2449#define EVSEL_MASK EVSEL(0x3f, 0xff)
1337 2450
2451/* An IA16 form instruction. */
2452#define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2453#define IA16_MASK IA16(0x3f, 0x1f)
2454
2455/* An I16A form instruction. */
2456#define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2457#define I16A_MASK I16A(0x3f, 0x1f)
2458
2459/* An I16L form instruction. */
2460#define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2461#define I16L_MASK I16L(0x3f, 0x1f)
2462
2463/* An IM7 form instruction. */
2464#define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2465#define IM7_MASK IM7(0x1f)
2466
1338/* An M form instruction. */ 2467/* An M form instruction. */
1339#define M(op, rc) (OP (op) | ((rc) & 1)) 2468#define M(op, rc) (OP (op) | ((rc) & 1))
1340#define M_MASK M (0x3f, 1) 2469#define M_MASK M (0x3f, 1)
1341 2470
2471/* An LI20 form instruction. */
2472#define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2473#define LI20_MASK LI20(0x3f, 0x1)
2474
1342/* An M form instruction with the ME field specified. */ 2475/* An M form instruction with the ME field specified. */
1343#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) 2476#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1344 2477
@@ -1369,48 +2502,189 @@ extract_tbr (unsigned long insn,
1369#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) 2502#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1370#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) 2503#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1371 2504
1372/* An VX form instruction. */ 2505/* An SCI8 form instruction. */
2506#define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2507#define SCI8_MASK SCI8(0x3f, 0x1f)
2508
2509/* An SCI8 form instruction. */
2510#define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2511#define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2512
2513/* An SD4 form instruction. This is a 16-bit instruction. */
2514#define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2515#define SD4_MASK SD4(0xf)
2516
2517/* An SE_IM5 form instruction. This is a 16-bit instruction. */
2518#define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2519#define SE_IM5_MASK SE_IM5(0x3f, 1)
2520
2521/* An SE_R form instruction. This is a 16-bit instruction. */
2522#define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2523#define SE_R_MASK SE_R(0x3f, 0x3f)
2524
2525/* An SE_RR form instruction. This is a 16-bit instruction. */
2526#define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2527#define SE_RR_MASK SE_RR(0x3f, 3)
2528
2529/* A VX form instruction. */
1373#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) 2530#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1374 2531
1375/* The mask for an VX form instruction. */ 2532/* The mask for an VX form instruction. */
1376#define VX_MASK VX(0x3f, 0x7ff) 2533#define VX_MASK VX(0x3f, 0x7ff)
1377 2534
1378/* An VA form instruction. */ 2535/* A VX_MASK with the VA field fixed. */
2536#define VXVA_MASK (VX_MASK | (0x1f << 16))
2537
2538/* A VX_MASK with the VB field fixed. */
2539#define VXVB_MASK (VX_MASK | (0x1f << 11))
2540
2541/* A VX_MASK with the VA and VB fields fixed. */
2542#define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2543
2544/* A VX_MASK with the VD and VA fields fixed. */
2545#define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2546
2547/* A VX_MASK with a UIMM4 field. */
2548#define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2549
2550/* A VX_MASK with a UIMM3 field. */
2551#define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2552
2553/* A VX_MASK with a UIMM2 field. */
2554#define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2555
2556/* A VX_MASK with a PS field. */
2557#define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2558
2559/* A VX_MASK with the VA field fixed with a PS field. */
2560#define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
2561
2562/* A VA form instruction. */
1379#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) 2563#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1380 2564
1381/* The mask for an VA form instruction. */ 2565/* The mask for an VA form instruction. */
1382#define VXA_MASK VXA(0x3f, 0x3f) 2566#define VXA_MASK VXA(0x3f, 0x3f)
1383 2567
1384/* An VXR form instruction. */ 2568/* A VXA_MASK with a SHB field. */
2569#define VXASHB_MASK (VXA_MASK | (1 << 10))
2570
2571/* A VXR form instruction. */
1385#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) 2572#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1386 2573
1387/* The mask for a VXR form instruction. */ 2574/* The mask for a VXR form instruction. */
1388#define VXR_MASK VXR(0x3f, 0x3ff, 1) 2575#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1389 2576
2577/* A VX form instruction with a VA tertiary opcode. */
2578#define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
2579
2580#define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2581#define VXASH_MASK VXASH (0x3f, 0x1f)
2582
1390/* An X form instruction. */ 2583/* An X form instruction. */
1391#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 2584#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1392 2585
2586/* A X form instruction for Quad-Precision FP Instructions. */
2587#define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
2588
2589/* An EX form instruction. */
2590#define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2591
2592/* The mask for an EX form instruction. */
2593#define EX_MASK EX (0x3f, 0x7ff)
2594
2595/* An XX2 form instruction. */
2596#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2597
2598/* A XX2 form instruction with the VA bits specified. */
2599#define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
2600
2601/* An XX3 form instruction. */
2602#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2603
2604/* An XX3 form instruction with the RC bit specified. */
2605#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2606
2607/* An XX4 form instruction. */
2608#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2609
1393/* A Z form instruction. */ 2610/* A Z form instruction. */
1394#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) 2611#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1395 2612
1396/* An X form instruction with the RC bit specified. */ 2613/* An X form instruction with the RC bit specified. */
1397#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) 2614#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1398 2615
2616/* A X form instruction for Quad-Precision FP Instructions with RC bit. */
2617#define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
2618
2619/* An X form instruction with the RA bits specified as two ops. */
2620#define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16)
2621
1399/* A Z form instruction with the RC bit specified. */ 2622/* A Z form instruction with the RC bit specified. */
1400#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) 2623#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1401 2624
1402/* The mask for an X form instruction. */ 2625/* The mask for an X form instruction. */
1403#define X_MASK XRC (0x3f, 0x3ff, 1) 2626#define X_MASK XRC (0x3f, 0x3ff, 1)
1404 2627
2628/* The mask for an X form instruction with the BF bits specified. */
2629#define XBF_MASK (X_MASK | (3 << 21))
2630
2631/* An X form wait instruction with everything filled in except the WC field. */
2632#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2633
2634/* The mask for an XX1 form instruction. */
2635#define XX1_MASK X (0x3f, 0x3ff)
2636
2637/* An XX1_MASK with the RB field fixed. */
2638#define XX1RB_MASK (XX1_MASK | RB_MASK)
2639
2640/* The mask for an XX2 form instruction. */
2641#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2642
2643/* The mask for an XX2 form instruction with the UIM bits specified. */
2644#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2645
2646/* The mask for an XX2 form instruction with the 4 UIM bits specified. */
2647#define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
2648
2649/* The mask for an XX2 form instruction with the BF bits specified. */
2650#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2651
2652/* The mask for an XX2 form instruction with the BF and DCMX bits specified. */
2653#define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
2654
2655/* The mask for an XX2 form instruction with a split DCMX bits specified. */
2656#define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
2657
2658/* The mask for an XX3 form instruction. */
2659#define XX3_MASK XX3 (0x3f, 0xff)
2660
2661/* The mask for an XX3 form instruction with the BF bits specified. */
2662#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2663
2664/* The mask for an XX3 form instruction with the DM or SHW bits specified. */
2665#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2666#define XX3SHW_MASK XX3DM_MASK
2667
2668/* The mask for an XX4 form instruction. */
2669#define XX4_MASK XX4 (0x3f, 0x3)
2670
2671/* An X form wait instruction with everything filled in except the WC field. */
2672#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2673
2674/* The mask for an XMMF form instruction. */
2675#define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
2676
1405/* The mask for a Z form instruction. */ 2677/* The mask for a Z form instruction. */
1406#define Z_MASK ZRC (0x3f, 0x1ff, 1) 2678#define Z_MASK ZRC (0x3f, 0x1ff, 1)
1407#define Z2_MASK ZRC (0x3f, 0xff, 1) 2679#define Z2_MASK ZRC (0x3f, 0xff, 1)
1408 2680
1409/* An X_MASK with the RA field fixed. */ 2681/* An X_MASK with the RA/VA field fixed. */
1410#define XRA_MASK (X_MASK | RA_MASK) 2682#define XRA_MASK (X_MASK | RA_MASK)
2683#define XVA_MASK XRA_MASK
1411 2684
1412/* An XRA_MASK with the W field clear. */ 2685/* An XRA_MASK with the A_L/W field clear. */
1413#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16)) 2686#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2687#define XRLA_MASK XWRA_MASK
1414 2688
1415/* An X_MASK with the RB field fixed. */ 2689/* An X_MASK with the RB field fixed. */
1416#define XRB_MASK (X_MASK | RB_MASK) 2690#define XRB_MASK (X_MASK | RB_MASK)
@@ -1424,18 +2698,54 @@ extract_tbr (unsigned long insn,
1424/* An X_MASK with the RA and RB fields fixed. */ 2698/* An X_MASK with the RA and RB fields fixed. */
1425#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) 2699#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1426 2700
2701/* An XBF_MASK with the RA and RB fields fixed. */
2702#define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
2703
1427/* An XRARB_MASK, but with the L bit clear. */ 2704/* An XRARB_MASK, but with the L bit clear. */
1428#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) 2705#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1429 2706
2707/* An XRARB_MASK, but with the L bits in a darn instruction clear. */
2708#define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16))
2709
1430/* An X_MASK with the RT and RA fields fixed. */ 2710/* An X_MASK with the RT and RA fields fixed. */
1431#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) 2711#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1432 2712
2713/* An X_MASK with the RT and RB fields fixed. */
2714#define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2715
1433/* An XRTRA_MASK, but with L bit clear. */ 2716/* An XRTRA_MASK, but with L bit clear. */
1434#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) 2717#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1435 2718
2719/* An X_MASK with the RT, RA and RB fields fixed. */
2720#define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2721
2722/* An XRTRARB_MASK, but with L bit clear. */
2723#define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
2724
2725/* An XRTRARB_MASK, but with A bit clear. */
2726#define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
2727
2728/* An XRTRARB_MASK, but with BF bits clear. */
2729#define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
2730
1436/* An X form instruction with the L bit specified. */ 2731/* An X form instruction with the L bit specified. */
1437#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) 2732#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1438 2733
2734/* An X form instruction with the L bits specified. */
2735#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2736
2737/* An X form instruction with the L bit and RC bit specified. */
2738#define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
2739
2740/* An X form instruction with RT fields specified */
2741#define XRT(op, xop, rt) (X ((op), (xop)) \
2742 | ((((unsigned long)(rt)) & 0x1f) << 21))
2743
2744/* An X form instruction with RT and RA fields specified */
2745#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2746 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2747 | ((((unsigned long)(ra)) & 0x1f) << 16))
2748
1439/* The mask for an X form comparison instruction. */ 2749/* The mask for an X form comparison instruction. */
1440#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) 2750#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1441 2751
@@ -1457,6 +2767,9 @@ extract_tbr (unsigned long insn,
1457/* An X form sync instruction with everything filled in except the LS field. */ 2767/* An X form sync instruction with everything filled in except the LS field. */
1458#define XSYNC_MASK (0xff9fffff) 2768#define XSYNC_MASK (0xff9fffff)
1459 2769
2770/* An X form sync instruction with everything filled in except the L and E fields. */
2771#define XSYNCLE_MASK (0xff90ffff)
2772
1460/* An X_MASK, but with the EH bit clear. */ 2773/* An X_MASK, but with the EH bit clear. */
1461#define XEH_MASK (X_MASK & ~((unsigned long )1)) 2774#define XEH_MASK (X_MASK & ~((unsigned long )1))
1462 2775
@@ -1469,8 +2782,8 @@ extract_tbr (unsigned long insn,
1469#define XFL_MASK XFL (0x3f, 0x3ff, 1) 2782#define XFL_MASK XFL (0x3f, 0x3ff, 1)
1470 2783
1471/* An X form isel instruction. */ 2784/* An X form isel instruction. */
1472#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) 2785#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1473#define XISEL_MASK XISEL(0x3f, 0x1f) 2786#define XISEL_MASK XISEL(0x3f, 0x1f)
1474 2787
1475/* An XL form instruction with the LK field set to 0. */ 2788/* An XL form instruction with the LK field set to 0. */
1476#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 2789#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
@@ -1481,6 +2794,9 @@ extract_tbr (unsigned long insn,
1481/* The mask for an XL form instruction. */ 2794/* The mask for an XL form instruction. */
1482#define XL_MASK XLLK (0x3f, 0x3ff, 1) 2795#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1483 2796
2797/* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
2798#define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
2799
1484/* An XL form instruction which explicitly sets the BO field. */ 2800/* An XL form instruction which explicitly sets the BO field. */
1485#define XLO(op, bo, xop, lk) \ 2801#define XLO(op, bo, xop, lk) \
1486 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 2802 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
@@ -1511,6 +2827,9 @@ extract_tbr (unsigned long insn,
1511/* An XL_MASK with the BO, BI and BB fields fixed. */ 2827/* An XL_MASK with the BO, BI and BB fields fixed. */
1512#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) 2828#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1513 2829
2830/* An X form mbar instruction with MO field. */
2831#define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2832
1514/* An XO form instruction. */ 2833/* An XO form instruction. */
1515#define XO(op, xop, oe, rc) \ 2834#define XO(op, xop, oe, rc) \
1516 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) 2835 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
@@ -1519,6 +2838,12 @@ extract_tbr (unsigned long insn,
1519/* An XO_MASK with the RB field fixed. */ 2838/* An XO_MASK with the RB field fixed. */
1520#define XORB_MASK (XO_MASK | RB_MASK) 2839#define XORB_MASK (XO_MASK | RB_MASK)
1521 2840
2841/* An XOPS form instruction for paired singles. */
2842#define XOPS(op, xop, rc) \
2843 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2844#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2845
2846
1522/* An XS form instruction. */ 2847/* An XS form instruction. */
1523#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) 2848#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1524#define XS_MASK XS (0x3f, 0x1ff, 1) 2849#define XS_MASK XS (0x3f, 0x1ff, 1)
@@ -1551,6 +2876,19 @@ extract_tbr (unsigned long insn,
1551#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) 2876#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1552#define XUC_MASK XUC(0x3f, 0x1f) 2877#define XUC_MASK XUC(0x3f, 0x1f)
1553 2878
2879/* An XW form instruction. */
2880#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2881/* The mask for a G form instruction. rc not supported at present. */
2882#define XW_MASK XW (0x3f, 0x3f, 0)
2883
2884/* An APU form instruction. */
2885#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2886
2887/* The mask for an APU form instruction. */
2888#define APU_MASK APU (0x3f, 0x3ff, 1)
2889#define APU_RT_MASK (APU_MASK | RT_MASK)
2890#define APU_RA_MASK (APU_MASK | RA_MASK)
2891
1554/* The BO encodings used in extended conditional branch mnemonics. */ 2892/* The BO encodings used in extended conditional branch mnemonics. */
1555#define BODNZF (0x0) 2893#define BODNZF (0x0)
1556#define BODNZFP (0x1) 2894#define BODNZFP (0x1)
@@ -1581,6 +2919,16 @@ extract_tbr (unsigned long insn,
1581 2919
1582#define BOU (0x14) 2920#define BOU (0x14)
1583 2921
2922/* The BO16 encodings used in extended VLE conditional branch mnemonics. */
2923#define BO16F (0x0)
2924#define BO16T (0x1)
2925
2926/* The BO32 encodings used in extended VLE conditional branch mnemonics. */
2927#define BO32F (0x0)
2928#define BO32T (0x1)
2929#define BO32DNZ (0x2)
2930#define BO32DZ (0x3)
2931
1584/* The BI condition bit encodings used in extended conditional branch 2932/* The BI condition bit encodings used in extended conditional branch
1585 mnemonics. */ 2933 mnemonics. */
1586#define CBLT (0) 2934#define CBLT (0)
@@ -1608,3075 +2956,4268 @@ extract_tbr (unsigned long insn,
1608/* Smaller names for the flags so each entry in the opcodes table will 2956/* Smaller names for the flags so each entry in the opcodes table will
1609 fit on a single line. */ 2957 fit on a single line. */
1610#undef PPC 2958#undef PPC
1611#define PPC PPC_OPCODE_PPC 2959#define PPC PPC_OPCODE_PPC
1612#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON 2960#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1613#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1614#define POWER4 PPC_OPCODE_POWER4 2961#define POWER4 PPC_OPCODE_POWER4
1615#define POWER5 PPC_OPCODE_POWER5 2962#define POWER5 PPC_OPCODE_POWER5
1616#define POWER6 PPC_OPCODE_POWER6 2963#define POWER6 PPC_OPCODE_POWER6
2964#define POWER7 PPC_OPCODE_POWER7
2965#define POWER8 PPC_OPCODE_POWER8
2966#define POWER9 PPC_OPCODE_POWER9
1617#define CELL PPC_OPCODE_CELL 2967#define CELL PPC_OPCODE_CELL
1618#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC 2968#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
1619#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC 2969#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
2970 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1620#define PPC403 PPC_OPCODE_403 2971#define PPC403 PPC_OPCODE_403
1621#define PPC405 PPC403 2972#define PPC405 PPC_OPCODE_405
1622#define PPC440 PPC_OPCODE_440 2973#define PPC440 PPC_OPCODE_440
1623#define PPC750 PPC 2974#define PPC464 PPC440
1624#define PPC860 PPC 2975#define PPC476 PPC_OPCODE_476
2976#define PPC750 PPC_OPCODE_750
2977#define PPC7450 PPC_OPCODE_7450
2978#define PPC860 PPC_OPCODE_860
2979#define PPCPS PPC_OPCODE_PPCPS
1625#define PPCVEC PPC_OPCODE_ALTIVEC 2980#define PPCVEC PPC_OPCODE_ALTIVEC
1626#define POWER PPC_OPCODE_POWER 2981#define PPCVEC2 PPC_OPCODE_ALTIVEC2
1627#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 2982#define PPCVEC3 PPC_OPCODE_ALTIVEC2
1628#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 2983#define PPCVSX PPC_OPCODE_VSX
1629#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32 2984#define PPCVSX2 PPC_OPCODE_VSX
1630#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON 2985#define PPCVSX3 PPC_OPCODE_VSX3
1631#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32 2986#define POWER PPC_OPCODE_POWER
1632#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 2987#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
2988#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2989#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2990#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2991#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1633#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON 2992#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1634#define MFDEC1 PPC_OPCODE_POWER 2993#define MFDEC1 PPC_OPCODE_POWER
1635#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE 2994#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
1636#define BOOKE PPC_OPCODE_BOOKE 2995#define BOOKE PPC_OPCODE_BOOKE
1637#define BOOKE64 PPC_OPCODE_BOOKE64 2996#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
1638#define CLASSIC PPC_OPCODE_CLASSIC
1639#define PPCE300 PPC_OPCODE_E300 2997#define PPCE300 PPC_OPCODE_E300
1640#define PPCSPE PPC_OPCODE_SPE 2998#define PPCSPE PPC_OPCODE_SPE
1641#define PPCISEL PPC_OPCODE_ISEL 2999#define PPCISEL PPC_OPCODE_ISEL
1642#define PPCEFS PPC_OPCODE_EFS 3000#define PPCEFS PPC_OPCODE_EFS
1643#define PPCBRLK PPC_OPCODE_BRLOCK 3001#define PPCBRLK PPC_OPCODE_BRLOCK
1644#define PPCPMR PPC_OPCODE_PMR 3002#define PPCPMR PPC_OPCODE_PMR
1645#define PPCCHLK PPC_OPCODE_CACHELCK 3003#define PPCTMR PPC_OPCODE_TMR
1646#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64 3004#define PPCCHLK PPC_OPCODE_CACHELCK
1647#define PPCRFMCI PPC_OPCODE_RFMCI 3005#define PPCRFMCI PPC_OPCODE_RFMCI
3006#define E500MC PPC_OPCODE_E500MC
3007#define PPCA2 PPC_OPCODE_A2
3008#define TITAN PPC_OPCODE_TITAN
3009#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
3010#define E500 PPC_OPCODE_E500
3011#define E6500 PPC_OPCODE_E6500
3012#define PPCVLE PPC_OPCODE_VLE
3013#define PPCHTM PPC_OPCODE_HTM
3014#define E200Z4 PPC_OPCODE_E200Z4
3015/* The list of embedded processors that use the embedded operand ordering
3016 for the 3 operand dcbt and dcbtst instructions. */
3017#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
3018 | PPC_OPCODE_A2)
3019
3020
1648 3021
1649/* The opcode table. 3022/* The opcode table.
1650 3023
1651 The format of the opcode table is: 3024 The format of the opcode table is:
1652 3025
1653 NAME OPCODE MASK FLAGS { OPERANDS } 3026 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
1654 3027
1655 NAME is the name of the instruction. 3028 NAME is the name of the instruction.
1656 OPCODE is the instruction opcode. 3029 OPCODE is the instruction opcode.
1657 MASK is the opcode mask; this is used to tell the disassembler 3030 MASK is the opcode mask; this is used to tell the disassembler
1658 which bits in the actual opcode must match OPCODE. 3031 which bits in the actual opcode must match OPCODE.
1659 FLAGS are flags indicated what processors support the instruction. 3032 FLAGS are flags indicating which processors support the instruction.
3033 ANTI indicates which processors don't support the instruction.
1660 OPERANDS is the list of operands. 3034 OPERANDS is the list of operands.
1661 3035
1662 The disassembler reads the table in order and prints the first 3036 The disassembler reads the table in order and prints the first
1663 instruction which matches, so this table is sorted to put more 3037 instruction which matches, so this table is sorted to put more
1664 specific instructions before more general instructions. It is also 3038 specific instructions before more general instructions.
1665 sorted by major opcode. */ 3039
3040 This table must be sorted by major opcode. Please try to keep it
3041 vaguely sorted within major opcode too, except of course where
3042 constrained otherwise by disassembler operation. */
1666 3043
1667const struct powerpc_opcode powerpc_opcodes[] = { 3044const struct powerpc_opcode powerpc_opcodes[] = {
1668{ "attn", X(0,256), X_MASK, POWER4, { 0 } }, 3045{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
1669{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } }, 3046{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1670{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } }, 3047{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1671{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } }, 3048{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1672{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } }, 3049{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1673{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } }, 3050{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1674{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } }, 3051{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1675{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } }, 3052{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1676{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } }, 3053{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1677{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } }, 3054{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1678{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } }, 3055{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1679{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } }, 3056{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1680{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } }, 3057{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1681{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } }, 3058{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1682{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } }, 3059{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1683{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } }, 3060{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1684 3061{"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
1685{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } }, 3062
1686{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } }, 3063{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1687{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } }, 3064{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1688{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } }, 3065{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1689{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } }, 3066{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1690{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } }, 3067{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1691{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } }, 3068{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1692{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } }, 3069{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1693{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } }, 3070{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1694{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } }, 3071{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1695{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } }, 3072{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1696{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } }, 3073{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1697{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } }, 3074{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1698{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } }, 3075{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1699{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } }, 3076{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1700{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } }, 3077{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1701{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } }, 3078{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1702{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } }, 3079{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1703{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } }, 3080{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1704{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } }, 3081{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1705{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } }, 3082{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1706{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } }, 3083{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1707{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } }, 3084{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1708{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } }, 3085{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1709{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } }, 3086{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1710{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } }, 3087{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1711{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } }, 3088{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1712{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } }, 3089{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1713{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 3090{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1714{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } }, 3091{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1715 3092{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1716{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3093{"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
1717{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3094{"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
1718{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3095
1719{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3096{"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
1720{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3097{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1721{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3098{"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
1722{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3099{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1723{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3100{"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1724{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3101{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
1725{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3102{"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
1726{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3103{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1727{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3104{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1728{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3105{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
1729{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3106{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1730{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3107{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
1731{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3108{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1732{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3109{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
1733{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3110{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
1734{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3111{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1735{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3112{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1736{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3113{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1737{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3114{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1738{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3115{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
1739{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3116{"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
1740{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3117{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
1741{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3118{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
1742{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3119{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
1743{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3120{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
1744{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3121{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1745{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3122{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1746{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3123{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1747{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3124{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1748{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3125{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
1749{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3126{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
1750{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3127{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
1751{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3128{"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
1752{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3129{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
1753{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3130{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
1754{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3131{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
1755{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3132{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
1756{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3133{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
1757{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3134{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
1758{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3135{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
1759{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3136{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
1760{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3137{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
1761{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3138{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
1762{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3139{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
1763{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3140{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
1764{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3141{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
1765{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3142{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
1766{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3143{"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
1767{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3144{"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
1768{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3145{"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1769{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3146{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
1770{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3147{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1771{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3148{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
1772{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3149{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
1773{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3150{"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
1774{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3151{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
1775{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3152{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
1776{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3153{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
1777{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3154{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
1778{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3155{"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
1779{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3156{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
1780{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3157{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
1781{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3158{"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1782{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3159{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1783{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3160{"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1784{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3161{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1785{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3162{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
1786{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3163{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1787{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3164{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
1788{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3165{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1789{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3166{"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
1790{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3167{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1791{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3168{"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
1792{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3169{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
1793{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3170{"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
1794{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3171{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
1795{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3172{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1796{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3173{"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
1797{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3174{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1798{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3175{"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1799{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3176{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
1800{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, 3177{"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
1801{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } }, 3178{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1802 3179{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1803 /* Double-precision opcodes. */ 3180{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
1804 /* Some of these conflict with AltiVec, so move them before, since 3181{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1805 PPCVEC includes the PPC_OPCODE_PPC set. */ 3182{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
1806{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } }, 3183{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1807{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } }, 3184{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
1808{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } }, 3185{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
1809{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } }, 3186{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
1810{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } }, 3187{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
1811{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } }, 3188{"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
1812{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } }, 3189{"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
1813{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } }, 3190{"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
1814{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3191{"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
1815{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3192{"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
1816{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3193{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1817{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3194{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1818{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3195{"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1819{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3196{"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
1820{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } }, 3197{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
1821{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } }, 3198{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
1822{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } }, 3199{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
1823{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } }, 3200{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
1824{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } }, 3201{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1825{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } }, 3202{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1826{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } }, 3203{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
1827{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } }, 3204{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
1828{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } }, 3205{"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
1829{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } }, 3206{"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
1830{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } }, 3207{"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
1831{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } }, 3208{"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
1832{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } }, 3209{"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
1833{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } }, 3210{"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
1834{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } }, 3211{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
1835 /* End of double-precision opcodes. */ 3212{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
1836 3213{"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
1837{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, 3214{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1838{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } }, 3215{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
1839{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } }, 3216{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
1840{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } }, 3217{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
1841{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } }, 3218{"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
1842{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } }, 3219{"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
1843{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } }, 3220{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1844{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } }, 3221{"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1845{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } }, 3222{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
1846{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } }, 3223{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1847{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } }, 3224{"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
1848{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } }, 3225{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1849{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } }, 3226{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1850{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } }, 3227{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
1851{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } }, 3228{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
1852{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } }, 3229{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
1853{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } }, 3230{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
1854{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } }, 3231{"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
1855{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } }, 3232{"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
1856{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 3233{"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
1857{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 3234{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1858{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3235{"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1859{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3236{"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
1860{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3237{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1861{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3238{"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
1862{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3239{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1863{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3240{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1864{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3241{"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
1865{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3242{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
1866{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3243{"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
1867{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3244{"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
1868{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3245{"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
1869{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3246{"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
1870{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3247{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1871{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3248{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1872{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3249{"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1873{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3250{"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
1874{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3251{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
1875{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3252{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
1876{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3253{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
1877{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3254{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1878{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3255{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1879{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3256{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
1880{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3257{"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
1881{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3258{"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
1882{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3259{"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1883{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3260{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
1884{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 3261{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
1885{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 3262{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
1886{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } }, 3263{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1887{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } }, 3264{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
1888{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, 3265{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
1889{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } }, 3266{"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
1890{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } }, 3267{"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
1891{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } }, 3268{"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1892{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } }, 3269{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1893{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } }, 3270{"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
1894{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } }, 3271{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
1895{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } }, 3272{"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1896{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3273{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1897{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3274{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
1898{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } }, 3275{"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1899{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } }, 3276{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
1900{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } }, 3277{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
1901{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } }, 3278{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
1902{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } }, 3279{"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
1903{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } }, 3280{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1904{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } }, 3281{"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
1905{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3282{"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
1906{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } }, 3283{"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
1907{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } }, 3284{"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
1908{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } }, 3285{"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
1909{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } }, 3286{"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
1910{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } }, 3287{"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
1911{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } }, 3288{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
1912{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3289{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
1913{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3290{"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
1914{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3291{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1915{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3292{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
1916{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3293{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
1917{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3294{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1918{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } }, 3295{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1919{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } }, 3296{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1920{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } }, 3297{"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
1921{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } }, 3298{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1922{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } }, 3299{"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1923{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } }, 3300{"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
1924{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } }, 3301{"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
1925{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } }, 3302{"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1926{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, 3303{"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1927{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } }, 3304{"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1928{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } }, 3305{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1929{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3306{"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1930{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } }, 3307{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
1931{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } }, 3308{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
1932{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } }, 3309{"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1933{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } }, 3310{"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
1934{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } }, 3311{"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1935{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } }, 3312{"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
1936{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } }, 3313{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
1937{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } }, 3314{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
1938{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } }, 3315{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1939{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } }, 3316{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1940{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } }, 3317{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1941{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } }, 3318{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1942{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } }, 3319{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
1943{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } }, 3320{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
1944{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } }, 3321{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
1945{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } }, 3322{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
1946{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } }, 3323{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
1947{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } }, 3324{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
1948{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3325{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1949{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } }, 3326{"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
1950{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } }, 3327{"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1951{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } }, 3328{"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1952{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } }, 3329{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
1953{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } }, 3330{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1954{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } }, 3331{"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
1955{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 3332{"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
1956{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 3333{"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
1957{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } }, 3334{"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
1958{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } }, 3335{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
1959{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } }, 3336{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
1960{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 3337{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
1961{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } }, 3338{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1962{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } }, 3339{"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1963{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } }, 3340{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1964{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } }, 3341{"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1965{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } }, 3342{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
1966{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } }, 3343{"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1967{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } }, 3344{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
1968{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } }, 3345{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
1969{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } }, 3346{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
1970{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } }, 3347{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
1971{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } }, 3348{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1972{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } }, 3349{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
1973{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } }, 3350{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
1974{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } }, 3351{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
1975{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } }, 3352{"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
1976{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } }, 3353{"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
1977{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } }, 3354{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
1978{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } }, 3355{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
1979{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } }, 3356{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
1980{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } }, 3357{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
1981{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } }, 3358{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
1982{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } }, 3359{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
1983{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } }, 3360{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
1984{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } }, 3361{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
1985{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } }, 3362{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
1986{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } }, 3363{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
1987{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } }, 3364{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
1988{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } }, 3365{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
1989{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } }, 3366{"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
1990{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } }, 3367{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
1991{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } }, 3368{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
1992 3369{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
1993{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } }, 3370{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
1994{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } }, 3371{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
1995{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } }, 3372{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
1996{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } }, 3373{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
1997{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } }, 3374{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
1998{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } }, 3375{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
1999{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } }, 3376{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2000{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } }, 3377{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
2001{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } }, 3378{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
2002{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } }, 3379{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2003{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } }, 3380{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
2004{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } }, 3381{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
2005{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } }, 3382{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
2006 3383{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2007{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } }, 3384{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2008 3385{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
2009{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } }, 3386{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2010{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } }, 3387{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2011{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } }, 3388{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2012{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } }, 3389{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
2013{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } }, 3390{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
2014{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } }, 3391{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
2015{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } }, 3392{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
2016{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } }, 3393{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
2017{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } }, 3394{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
2018{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } }, 3395{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
2019 3396{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
2020{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } }, 3397{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
2021{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 3398{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
2022{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } }, 3399{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
2023{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 3400{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
2024{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } }, 3401{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2025{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } }, 3402{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2026{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 3403{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2027{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 3404{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
2028{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } }, 3405{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
2029{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } }, 3406{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
2030{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } }, 3407{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
2031{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } }, 3408{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
2032{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } }, 3409{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
2033{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } }, 3410{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
2034 3411{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
2035{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3412{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
2036{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3413{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
2037{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3414{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
2038{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3415{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2039{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3416{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2040{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } }, 3417{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2041 3418{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
2042{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 3419{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
2043{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } }, 3420{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
2044{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 3421{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
2045{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } }, 3422{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
2046{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 3423{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
2047{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } }, 3424{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
2048{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3425{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
2049{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } }, 3426{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
2050{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3427{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
2051{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } }, 3428{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
2052{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3429{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
2053{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } }, 3430{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2054{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3431{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2055{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } }, 3432{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2056{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3433{"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2057{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } }, 3434{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2058{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, 3435{"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
2059{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } }, 3436{"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2060{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, 3437{"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2061{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } }, 3438{"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
2062{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, 3439{"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2063{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } }, 3440{"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2064 3441{"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
2065{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 3442{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2066{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } }, 3443{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2067{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 3444{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2068{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } }, 3445{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
2069{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 3446{"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2070{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } }, 3447{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2071{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3448{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2072{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } }, 3449{"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
2073{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3450{"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
2074{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } }, 3451{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
2075{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3452{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2076{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } }, 3453{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2077{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3454{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
2078{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } }, 3455{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
2079 3456{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2080{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } }, 3457{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
2081{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } }, 3458{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2082{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } }, 3459{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2083{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } }, 3460{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2084{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } }, 3461{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2085{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } }, 3462{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2086{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } }, 3463{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
2087{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3464{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2088{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3465{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
2089{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3466{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2090{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3467{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2091{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3468{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2092{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3469{"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2093{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } }, 3470{"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
2094{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } }, 3471{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2095{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } }, 3472{"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
2096{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } }, 3473{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2097{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } }, 3474{"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
2098{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } }, 3475{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2099{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } }, 3476{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2100{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } }, 3477{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2101{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } }, 3478{"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2102{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } }, 3479{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2103 3480{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2104{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } }, 3481{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2105{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } }, 3482{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2106{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } }, 3483{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2107{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } }, 3484{"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2108{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } }, 3485{"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2109{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } }, 3486{"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2110{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } }, 3487{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2111{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3488{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2112{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3489{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2113{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3490{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2114{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3491{"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
2115{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3492{"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
2116{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3493{"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2117{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } }, 3494{"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
2118{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } }, 3495{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
2119{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } }, 3496{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
2120{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } }, 3497{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
2121{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } }, 3498{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
2122{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } }, 3499{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
2123{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } }, 3500{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2124{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } }, 3501{"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2125{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } }, 3502{"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2126{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } }, 3503{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2127 3504{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2128{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } }, 3505{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2129{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } }, 3506{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2130{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } }, 3507{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
2131{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } }, 3508{"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
2132{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } }, 3509{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2133{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } }, 3510{"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2134{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } }, 3511{"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2135{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } }, 3512{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2136{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } }, 3513{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2137{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } }, 3514{"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
2138{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } }, 3515{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2139{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } }, 3516{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2140{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } }, 3517{"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
2141{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } }, 3518{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2142{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } }, 3519{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2143{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } }, 3520{"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2144 3521{"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2145{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } }, 3522{"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2146{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } }, 3523{"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2147{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } }, 3524{"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
2148{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } }, 3525{"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2149{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } }, 3526{"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2150{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } }, 3527{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2151{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } }, 3528{"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2152{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } }, 3529{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2153{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } }, 3530{"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2154{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } }, 3531{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2155{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } }, 3532{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2156{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } }, 3533{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2157 3534{"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2158{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } }, 3535{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2159{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } }, 3536{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2160{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } }, 3537{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2161{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } }, 3538{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2162{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } }, 3539{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2163{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } }, 3540{"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2164{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } }, 3541{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2165{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } }, 3542{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2166{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } }, 3543{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2167{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } }, 3544{"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2168{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } }, 3545{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2169{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } }, 3546{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2170 3547{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2171{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } }, 3548{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2172{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } }, 3549{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2173{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } }, 3550{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2174{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } }, 3551{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2175{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } }, 3552{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2176{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } }, 3553{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2177 3554{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2178{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } }, 3555{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2179{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } }, 3556{"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
2180{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } }, 3557{"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2181{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } }, 3558{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2182{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } }, 3559{"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2183{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } }, 3560{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2184 3561{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2185{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } }, 3562{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2186{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } }, 3563{"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2187{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } }, 3564{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2188{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } }, 3565{"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2189{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } }, 3566{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2190{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } }, 3567{"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2191{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } }, 3568{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2192{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } }, 3569{"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2193 3570{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2194{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } }, 3571{"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2195{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } }, 3572{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2196 3573{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2197{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } }, 3574{"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2198{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } }, 3575{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2199{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } }, 3576{"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2200{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } }, 3577{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2201 3578{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2202{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } }, 3579{"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2203{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } }, 3580{"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2204{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } }, 3581{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2205{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } }, 3582{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2206 3583{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2207{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } }, 3584{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2208{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } }, 3585{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2209{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } }, 3586{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2210{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } }, 3587{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2211{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } }, 3588{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2212{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } }, 3589{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2213{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } }, 3590{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2214{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } }, 3591{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2215 3592{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2216{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } }, 3593{"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2217{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } }, 3594{"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2218{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } }, 3595{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2219{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } }, 3596{"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
2220 3597{"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2221{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } }, 3598{"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2222{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } }, 3599{"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2223{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } }, 3600{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2224{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } }, 3601{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2225 3602{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2226{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } }, 3603{"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2227{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } }, 3604{"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2228{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } }, 3605{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2229{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } }, 3606{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2230 3607{"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2231{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } }, 3608{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
2232{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } }, 3609{"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
2233{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } }, 3610{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
2234{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } }, 3611{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
2235 3612{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
2236{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } }, 3613{"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
2237 3614{"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2238{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } }, 3615{"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2239{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } }, 3616{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2240 3617{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2241{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 3618{"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
2242{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } }, 3619{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2243 3620{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2244{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 3621{"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2245{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } }, 3622{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
2246 3623{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
2247{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } }, 3624{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
2248 3625{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
2249{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } }, 3626{"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2250{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } }, 3627{"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2251{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } }, 3628{"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2252{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } }, 3629{"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2253 3630{"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2254{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 3631{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2255{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 3632{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2256{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } }, 3633{"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2257{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } }, 3634{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2258 3635{"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
2259{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 3636{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2260{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } }, 3637{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2261{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } }, 3638{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2262{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } }, 3639{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2263 3640{"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
2264{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, 3641{"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2265{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } }, 3642{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2266{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } }, 3643{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2267 3644{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2268{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, 3645{"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2269{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } }, 3646{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2270{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } }, 3647{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2271 3648{"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2272{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 3649{"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2273{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } }, 3650{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2274{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } }, 3651{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2275{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } }, 3652{"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2276{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } }, 3653{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2277{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } }, 3654{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2278 3655{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2279{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } }, 3656{"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2280{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } }, 3657{"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2281{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } }, 3658{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2282{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } }, 3659{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2283{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } }, 3660{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2284 3661{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2285{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, 3662{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2286{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, 3663{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2287{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } }, 3664{"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2288{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } }, 3665{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2289{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, 3666{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2290{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, 3667{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2291{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } }, 3668{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2292{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } }, 3669{"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2293{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, 3670{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2294{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, 3671{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2295{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } }, 3672{"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2296{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } }, 3673{"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2297{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, 3674{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2298{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, 3675{"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2299{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } }, 3676{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2300{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } }, 3677{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2301{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, 3678{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2302{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, 3679{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2303{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } }, 3680{"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2304{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, 3681{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2305{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, 3682{"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2306{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } }, 3683{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2307{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, 3684{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2308{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, 3685{"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2309{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } }, 3686{"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2310{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, 3687{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2311{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, 3688{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2312{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } }, 3689{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2313{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3690{"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2314{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3691{"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
2315{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3692{"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
2316{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3693{"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2317{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3694{"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
2318{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3695{"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
2319{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3696{"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
2320{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3697{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2321{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3698{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2322{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3699{"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2323{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3700{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2324{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3701{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2325{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3702{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2326{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3703{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2327{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3704{"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2328{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3705{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2329{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3706{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2330{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3707{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2331{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3708{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2332{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3709{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2333{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3710{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2334{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3711{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2335{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3712{"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2336{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3713{"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2337{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3714{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2338{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3715{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2339{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3716{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2340{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3717{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2341{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3718{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2342{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3719{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2343{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3720{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2344{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3721{"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
2345{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3722{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2346{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3723{"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2347{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3724{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2348{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3725{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2349{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3726{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2350{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3727{"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
2351{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3728{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2352{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3729{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2353{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3730{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2354{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3731{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2355{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3732{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2356{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3733{"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2357{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3734{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2358{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3735{"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2359{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3736{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2360{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3737{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2361{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3738{"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2362{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3739{"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2363{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, 3740{"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2364{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3741{"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
2365{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3742{"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
2366{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, 3743{"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2367{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3744{"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2368{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3745{"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2369{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 3746{"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2370{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3747{"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2371{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3748{"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2372{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 3749{"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2373{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3750{"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2374{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3751{"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2375{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3752{"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2376{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3753{"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2377{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3754{"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2378{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3755{"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2379{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3756{"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2380{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3757{"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
2381{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3758{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2382{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3759{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2383{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3760{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2384{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3761{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2385{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3762{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
2386{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3763{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2387{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3764{"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
2388{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3765{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2389{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3766{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2390{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3767{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2391{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3768{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2392{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3769{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
2393{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3770{"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2394{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3771{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2395{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3772{"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
2396{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3773{"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2397{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3774{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2398{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3775{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2399{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3776{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2400{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3777{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2401{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3778{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2402{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3779{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
2403{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3780{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
2404{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3781{"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2405{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3782{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2406{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3783{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2407{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3784{"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
2408{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3785{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2409{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3786{"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2410{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3787{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2411{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3788{"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2412{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3789{"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2413{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3790{"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2414{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3791{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2415{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3792{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2416{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3793{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2417{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3794{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2418{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3795{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
2419{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3796{"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2420{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3797{"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2421{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3798{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2422{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3799{"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2423{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3800{"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2424{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3801{"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2425{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3802{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2426{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3803{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
2427{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3804{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2428{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3805{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2429{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3806{"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2430{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3807{"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2431{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3808{"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2432{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3809{"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2433{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3810{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2434{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3811{"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2435{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3812{"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2436{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3813{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2437{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3814{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2438{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3815{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2439{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3816{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2440{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3817{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2441{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3818{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
2442{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3819{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2443{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3820{"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2444{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3821{"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2445{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3822{"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2446{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3823{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2447{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, 3824{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2448{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3825{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
2449{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3826{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2450{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, 3827{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2451{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3828{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2452{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3829{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2453{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 3830{"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2454{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3831{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
2455{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3832
2456{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 3833{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
2457{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3834{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
2458{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3835
2459{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 3836{"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
2460{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3837{"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
2461{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3838
2462{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 3839{"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
2463{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3840
2464{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3841{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
2465{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 3842{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
2466{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3843{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
2467{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3844{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
2468{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 3845
2469{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3846{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
2470{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3847{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
2471{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 3848{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
2472{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3849{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
2473{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3850
2474{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 3851{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
2475{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3852{"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
2476{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3853{"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
2477{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 3854
2478{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3855{"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
2479{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3856{"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
2480{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 3857{"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
2481{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, 3858
2482{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, 3859{"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
2483{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, 3860{"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
2484{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, 3861{"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
2485{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, 3862{"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
2486{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, 3863{"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
2487{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, 3864{"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
2488{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, 3865
2489{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 3866{"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}},
2490{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 3867{"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}},
2491{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, 3868{"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
2492{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, 3869{"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
2493{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 3870{"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
2494{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 3871
2495{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, 3872{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
2496{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, 3873{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
2497{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, 3874{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
2498{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, 3875{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
2499{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, 3876{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
2500{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, 3877{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
2501{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, 3878{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
2502{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, 3879{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
2503{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, 3880{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
2504{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, 3881{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
2505{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 3882{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
2506{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 3883{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
2507{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, 3884{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
2508{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, 3885{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
2509{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 3886{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
2510{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 3887{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
2511{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, 3888{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
2512{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, 3889{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
2513{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3890{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}},
2514{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3891{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
2515{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 3892{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
2516{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3893{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}},
2517{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3894{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
2518{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 3895{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
2519{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3896{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}},
2520{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3897{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
2521{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 3898{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
2522{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3899{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}},
2523{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3900
2524{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 3901{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2525{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3902{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2526{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3903{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2527{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 3904{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2528{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3905{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2529{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3906{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2530{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 3907{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2531{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3908{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2532{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3909{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2533{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 3910{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2534{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3911{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2535{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3912{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2536{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 3913{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2537{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } }, 3914{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2538{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } }, 3915{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2539{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } }, 3916{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2540{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } }, 3917{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2541{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } }, 3918{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2542{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } }, 3919{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2543{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } }, 3920{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2544{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } }, 3921{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2545{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } }, 3922{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2546{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } }, 3923{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2547{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } }, 3924{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2548{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } }, 3925{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2549 3926{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2550{ "sc", SC(17,1,0), SC_MASK, PPC, { LEV } }, 3927{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2551{ "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } }, 3928{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2552{ "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } }, 3929{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2553{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } }, 3930{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2554{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, 3931{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2555 3932{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2556{ "b", B(18,0,0), B_MASK, COM, { LI } }, 3933{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2557{ "bl", B(18,0,1), B_MASK, COM, { LI } }, 3934{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2558{ "ba", B(18,1,0), B_MASK, COM, { LIA } }, 3935{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2559{ "bla", B(18,1,1), B_MASK, COM, { LIA } }, 3936{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2560 3937{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2561{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } }, 3938{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2562 3939{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2563{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, 3940{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2564{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } }, 3941{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2565{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, 3942{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2566{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } }, 3943{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2567{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, 3944{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2568{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3945{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2569{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 3946{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2570{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3947{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2571{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 3948{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2572{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, 3949{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2573{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3950{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2574{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 3951{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2575{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3952{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2576{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 3953{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2577{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, 3954{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2578{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3955{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2579{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 3956{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2580{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3957{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2581{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 3958{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2582{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, 3959{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2583{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3960{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2584{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 3961{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2585{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3962{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2586{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 3963{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2587{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3964{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2588{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3965{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2589{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3966{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
2590{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3967{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2591{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3968{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2592{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 3969{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2593{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3970{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2594{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3971{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2595{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3972{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
2596{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3973{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2597{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3974{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2598{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 3975{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2599{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3976{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2600{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3977{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2601{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3978{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
2602{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3979{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2603{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3980{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2604{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 3981{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2605{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3982{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2606{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3983{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2607{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3984{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
2608{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3985
2609{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3986{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2610{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 3987{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2611{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3988{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2612{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3989{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2613{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3990{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2614{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3991{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2615{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3992{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2616{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 3993{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2617{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3994{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2618{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3995{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2619{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3996{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2620{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3997{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2621{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3998{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2622{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 3999{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2623{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4000{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2624{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4001{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2625{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4002{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2626{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4003{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2627{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4004{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2628{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 4005{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2629{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4006{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2630{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4007{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2631{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4008{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2632{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4009{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2633{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4010{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2634{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 4011{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2635{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4012{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2636{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4013{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2637{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4014{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2638{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4015{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2639{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4016{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2640{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4017{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2641{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4018{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2642{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4019{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2643{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4020{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2644{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4021{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2645{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4022{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2646{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4023{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2647{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4024{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2648{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4025{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2649{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4026{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2650{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 4027{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
2651{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4028{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2652{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4029{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2653{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4030{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2654{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4031{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2655{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4032{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2656{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 4033{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
2657{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4034{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2658{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4035{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2659{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4036{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2660{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4037{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2661{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4038{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2662{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 4039{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
2663{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4040{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2664{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4041{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2665{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4042{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2666{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4043{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2667{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4044{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2668{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 4045{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
2669{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4046
2670{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4047{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2671{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4048{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2672{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4049{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2673{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4050{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2674{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 4051{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2675{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4052{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2676{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4053{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
2677{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4054{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
2678{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4055{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2679{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4056{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
2680{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 4057{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
2681{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4058{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2682{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4059{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2683{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4060{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2684{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4061{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2685{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4062{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2686{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 4063{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2687{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4064{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2688{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4065{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
2689{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4066{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
2690{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4067{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2691{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4068{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
2692{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 4069{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
2693{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4070{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2694{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4071
2695{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4072{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
2696{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4073{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
2697{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4074{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
2698{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 4075{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
2699{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4076{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
2700{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4077{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
2701{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4078{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
2702{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4079{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
2703{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4080{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
2704{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 4081{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
2705{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4082{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2706{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4083{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
2707{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4084{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
2708{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4085{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
2709{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4086{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2710{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 4087{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
2711{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4088
2712{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4089{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2713{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4090{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2714{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4091{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2715{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4092{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2716{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 4093{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2717{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4094{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2718{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4095{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
2719{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4096{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
2720{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4097{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2721{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4098{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
2722{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4099{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
2723{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4100{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2724{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4101{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2725{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4102{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2726{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4103{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2727{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 4104{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2728{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4105{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2729{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } }, 4106{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2730{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4107{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
2731{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } }, 4108{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
2732{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, 4109{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2733{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 4110{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
2734{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4111{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
2735{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } }, 4112{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2736{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4113
2737{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } }, 4114{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
2738{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, 4115{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
2739{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 4116{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
2740{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4117{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
2741{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } }, 4118{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
2742{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4119{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
2743{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } }, 4120{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
2744{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } }, 4121{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
2745{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 4122{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
2746{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4123{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
2747{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } }, 4124{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2748{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4125{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
2749{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } }, 4126{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
2750{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } }, 4127{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
2751{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 4128{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2752{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4129{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
2753{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4130
2754{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 4131{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
2755{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4132{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
2756{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4133{"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}},
2757{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 4134{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
2758{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4135{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
2759{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4136{"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}},
2760{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 4137{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
2761{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4138{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
2762{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4139{"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
2763{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 4140{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
2764{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4141{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
2765{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4142{"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
2766{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 4143
2767{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4144{"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
2768{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4145{"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
2769{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 4146{"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
2770{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4147{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
2771{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4148{"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
2772{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 4149
2773{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4150{"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}},
2774{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4151{"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}},
2775{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4152{"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}},
2776{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4153{"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}},
2777{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4154
2778{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4155{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
2779{ "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 4156
2780{ "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 4157{"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
2781{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } }, 4158{"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
2782{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } }, 4159
2783{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } }, 4160{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
2784{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } }, 4161{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
2785 4162{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
2786{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } }, 4163{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
2787 4164{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
2788{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } }, 4165{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
2789{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } }, 4166{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
2790{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 4167{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
2791 4168{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
2792{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, 4169{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
2793{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } }, 4170{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
2794 4171{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
2795{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, 4172{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
2796 4173{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
2797{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } }, 4174{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
2798 4175{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
2799{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 4176{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
2800{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } }, 4177{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
2801 4178{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
2802{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } }, 4179{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
2803{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } }, 4180{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
2804 4181{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
2805{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } }, 4182{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
2806 4183{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
2807{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, 4184
2808 4185{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2809{ "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } }, 4186{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2810 4187{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2811{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, 4188{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2812{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, 4189{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2813 4190{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2814{ "doze", XL(19,402), 0xffffffff, POWER6, { 0 } }, 4191{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2815 4192{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2816{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } }, 4193{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2817 4194{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2818{ "nap", XL(19,434), 0xffffffff, POWER6, { 0 } }, 4195{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2819 4196{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2820{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, 4197{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2821{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } }, 4198{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2822 4199{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2823{ "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } }, 4200{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2824{ "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } }, 4201{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2825 4202{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2826{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, 4203{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2827{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, 4204{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2828{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4205{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2829{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4206{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2830{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4207{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2831{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4208{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2832{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4209{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2833{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4210{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2834{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4211{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2835{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4212{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2836{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4213{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2837{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4214{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2838{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4215{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2839{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4216{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2840{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4217{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2841{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4218{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2842{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4219{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2843{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4220{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2844{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4221{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2845{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4222{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2846{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4223{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2847{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4224{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2848{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4225{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2849{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4226{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2850{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4227{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2851{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4228{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2852{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4229{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2853{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4230{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2854{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4231{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2855{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4232{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2856{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4233{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2857{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4234{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2858{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4235{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2859{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4236{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2860{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4237{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2861{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4238{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2862{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4239{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2863{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4240{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2864{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4241{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2865{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4242{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2866{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4243{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2867{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4244{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2868{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4245{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2869{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4246{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2870{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4247{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2871{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4248{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2872{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4249{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2873{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4250{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2874{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4251{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2875{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4252{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2876{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4253{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2877{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4254{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2878{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4255{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2879{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4256{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2880{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4257{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2881{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4258{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2882{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4259{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2883{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4260{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2884{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4261{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2885{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4262{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2886{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4263{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2887{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4264{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2888{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4265{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2889{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4266{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2890{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4267{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2891{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4268{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2892{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4269{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2893{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4270{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2894{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4271{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2895{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4272{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2896{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4273{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2897{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4274{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2898{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4275{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2899{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4276{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2900{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4277{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2901{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4278{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2902{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4279{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2903{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4280{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2904{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4281{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2905{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4282{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2906{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4283{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2907{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4284{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2908{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4285{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2909{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4286{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2910{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4287{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2911{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4288{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2912{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4289{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2913{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4290{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2914{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4291{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2915{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4292{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
2916{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4293{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
2917{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4294{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2918{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4295{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2919{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4296{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2920{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4297{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2921{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4298{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2922{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4299{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2923{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4300{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2924{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4301{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2925{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4302{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2926{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4303{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2927{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4304{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
2928{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4305{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2929{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4306{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2930{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4307{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2931{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4308{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2932{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4309{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2933{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4310{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2934{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4311{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2935{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4312{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2936{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4313{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2937{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4314{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2938{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4315{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2939{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4316{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2940{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4317{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2941{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4318{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2942{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4319{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2943{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4320{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2944{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4321{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2945{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4322{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2946{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4323{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2947{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4324{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
2948{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, 4325
2949{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4326{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
2950{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } }, 4327{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2951{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4328{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
2952{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } }, 4329{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2953{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, 4330{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2954{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4331{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2955{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } }, 4332{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
2956{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4333{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2957{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } }, 4334{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
2958{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, 4335{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2959{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4336{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2960{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } }, 4337{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2961{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4338{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
2962{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } }, 4339{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2963{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, 4340{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
2964{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4341{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
2965{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } }, 4342{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2966{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4343{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
2967{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } }, 4344{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2968{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4345{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2969{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4346{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
2970{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4347{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
2971{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4348{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
2972{ "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 4349{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
2973{ "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 4350{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
2974{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, 4351{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2975{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, 4352{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
2976{ "bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, { BO, BI } }, 4353{"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2977{ "bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, { BO, BI } }, 4354{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2978 4355{"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2979{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 4356{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
2980{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 4357{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2981 4358{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
2982{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 4359{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2983{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 4360{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2984 4361{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2985{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } }, 4362{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
2986{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 4363{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2987{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 4364{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
2988{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 4365{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
2989{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } }, 4366{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2990{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 4367{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
2991{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 4368{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2992{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 4369{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
2993 4370{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
2994{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } }, 4371{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
2995{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } }, 4372{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
2996 4373{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
2997{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } }, 4374
2998{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } }, 4375{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
2999{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } }, 4376{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
3000{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } }, 4377{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
3001 4378{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
3002{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } }, 4379{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
3003{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, 4380{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
3004{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, 4381{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
3005{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } }, 4382{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
3006{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, 4383
3007{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, 4384{"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}},
3008 4385
3009{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, 4386{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
3010{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } }, 4387{"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3011{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } }, 4388{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}},
3012 4389
3013{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } }, 4390{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}},
3014{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } }, 4391{"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
3015 4392{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
3016{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } }, 4393
3017{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } }, 4394{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
3018 4395
3019{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } }, 4396{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
3020{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } }, 4397
3021 4398{"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3022{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } }, 4399
3023{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } }, 4400{"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}},
3024 4401
3025{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } }, 4402{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}},
3026{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } }, 4403{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
3027 4404
3028{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } }, 4405{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
3029{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } }, 4406{"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3030{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 4407
3031{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } }, 4408{"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
3032{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } }, 4409
3033{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 4410{"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3034 4411
3035{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, 4412{"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3036{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, 4413
3037 4414{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}},
3038{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 4415
3039{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 4416{"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
3040 4417{"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3041{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 4418
3042{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 4419{"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}},
3043 4420{"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}},
3044{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } }, 4421
3045{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, 4422{"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
3046{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } }, 4423
3047{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, 4424{"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3048 4425
3049{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, 4426{"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
3050{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, 4427
3051 4428{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
3052{ "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, 4429{"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3053{ "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, 4430
3054{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, 4431{"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
3055{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, 4432{"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
3056 4433
3057{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, 4434{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}},
3058{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } }, 4435{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}},
3059{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } }, 4436
3060{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } }, 4437{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3061{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } }, 4438{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3062{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } }, 4439{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3063{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } }, 4440{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3064{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } }, 4441{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3065{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } }, 4442{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3066{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } }, 4443{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3067{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } }, 4444{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3068{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } }, 4445{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3069{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } }, 4446{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3070{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } }, 4447{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3071{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } }, 4448{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3072{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } }, 4449{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3073{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } }, 4450{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3074{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } }, 4451{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3075{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } }, 4452{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3076{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } }, 4453{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3077{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } }, 4454{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3078{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } }, 4455{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3079{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } }, 4456{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3080{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } }, 4457{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3081{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } }, 4458{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3082{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } }, 4459{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3083{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } }, 4460{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3084{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } }, 4461{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3085{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } }, 4462{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3086{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } }, 4463{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3087{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } }, 4464{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3088 4465{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3089{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 4466{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3090{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 4467{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3091{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, 4468{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3092{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 4469{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3093{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 4470{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3094{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } }, 4471{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3095{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 4472{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3096{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 4473{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3097{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, 4474{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3098{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 4475{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3099{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 4476{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3100{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, 4477{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3101 4478{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3102{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 4479{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3103{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 4480{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3104 4481{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3105{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 4482{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3106{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 4483{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3107{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 4484{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3108{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 4485{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3109{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 4486{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3110{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 4487{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3111{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 4488{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3112{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 4489{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3113 4490{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3114{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, 4491{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3115{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, 4492{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3116 4493{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3117{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } }, 4494{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3118{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } }, 4495{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3119{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } }, 4496{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3120{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } }, 4497{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3121 4498{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3122{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } }, 4499{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3123{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } }, 4500{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3124{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } }, 4501{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3125 4502{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3126{ "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } }, 4503{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3127 4504{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3128{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } }, 4505{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3129 4506{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3130{ "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } }, 4507{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3131{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, 4508{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3132 4509{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3133{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } }, 4510{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3134{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, 4511{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3135 4512{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3136{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } }, 4513{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3137{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } }, 4514{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3138{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } }, 4515{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3139{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } }, 4516{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3140 4517{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3141{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } }, 4518{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3142{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } }, 4519{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3143{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } }, 4520{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3144{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } }, 4521{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3145 4522{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3146{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } }, 4523{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3147{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } }, 4524{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3148 4525{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3149{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } }, 4526{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3150{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } }, 4527{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3151 4528{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3152{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } }, 4529{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3153{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } }, 4530{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3154 4531{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3155{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } }, 4532{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3156 4533{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3157{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } }, 4534{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3158 4535{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3159{ "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, 4536{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3160{ "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, 4537{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3161{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, 4538{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3162{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, 4539{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3163 4540{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3164{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, 4541{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3165{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, 4542{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3166{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, 4543{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3167{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, 4544{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3168{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, 4545{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3169{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, 4546{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3170{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, 4547{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3171{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, 4548{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4549{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4550{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4551{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4552{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4553{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4554{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4555{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4556{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4557
4558{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4559{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4560{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4561{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4562{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4563{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4564{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4565{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4566{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4567{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4568{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4569{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4570{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4571{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4572{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4573{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4574{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4575{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4576{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4577{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4578
4579{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4580{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4581{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4582{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4583{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4584{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4585{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4586{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4587
4588{"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4589{"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4590{"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4591{"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4592{"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4593{"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4594
4595{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4596{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4597
4598{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4599{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4600
4601{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4602{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4603{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4604{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4605{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4606{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4607{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4608{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4609
4610{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4611{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4612
4613{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4614{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4615{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4616{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4617{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4618{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4619
4620{"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}},
4621{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4622{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4623
4624{"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4625{"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4626
4627{"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}},
4628{"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4629{"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4630
4631{"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4632{"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4633
4634{"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4635{"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4636
4637{"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4638{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4639
4640{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4641{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4642{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4643{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4644{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4645{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4646
4647{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4648{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4649
4650{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4651{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4652
4653{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4654{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4655
4656{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4657{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4658{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4659{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4660
4661{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4662{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4663
4664{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4665{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4666{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
4667{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4668
4669{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4670{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4671{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4672{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4673{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
4674{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
4675{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4676{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4677{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4678{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4679{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4680{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4681{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4682{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4683{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4684{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4685{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4686{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4687{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4688{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4689{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4690{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4691{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4692{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4693{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4694{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4695{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4696{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4697{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}},
4698{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
4699{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4700{"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
4701{"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4702
4703{"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4704{"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4705{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4706
4707{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4708{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4709{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4710{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4711{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4712{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4713
4714{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4715{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4716
4717{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4718{"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4719{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4720{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4721
4722{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4723{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4724
4725{"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4726
4727{"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4728
4729{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}},
4730{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}},
4731{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4732{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
4733
4734{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
4735{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
4736
4737{"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
4738
4739{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
4740
4741{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
4742
4743{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
4744{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4745
4746{"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4747{"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4748{"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4749{"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4750
4751{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
4752{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
4753{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
4754{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
4755
4756{"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
4757{"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4758
4759{"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
4760{"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
4761
4762{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
4763{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
4764
4765{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4766
4767{"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
4768{"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}},
4769
4770{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4771
4772{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4773{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4774{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
4775{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4776
4777{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4778{"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4779{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4780
4781{"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
4782
4783{"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4784
4785{"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4786
4787{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
4788
4789{"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4790
4791{"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4792
4793{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
4794
4795{"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4796{"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
4797{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4798{"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
4799
4800{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4801{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4802{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4803{"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
4804
4805{"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4806
4807{"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
4808
4809{"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
4810
4811{"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
4812{"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4813
4814{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
4815{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
4816
4817{"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
4818{"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
4819
4820{"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4821{"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4822{"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
4823
4824{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4825
4826{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
4827{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
4828{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
4829{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
4830{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
4831{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
4832{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
4833{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
4834{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
4835{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
4836{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
4837{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
4838{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
4839{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
4840{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
4841{"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
4842
4843{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4844{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4845{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4846
4847{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4848{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4849
4850{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4851{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4852
4853{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},
4854
4855{"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
4856
4857{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
4858
4859{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
4860{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
4861
4862{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
4863
4864{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4865
4866{"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}},
4867
4868{"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4869{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4870
4871{"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
4872{"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
4873
4874{"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
4875{"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
4876
4877{"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
4878
4879{"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
4880
4881{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4882{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4883{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4884
4885{"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4886
4887{"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
4888
4889{"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
4890
4891{"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
4892
4893{"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},
4894{"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
4895{"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},
4896{"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
4897
4898{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4899
4900{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
4901
4902{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
4903
4904{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
4905
4906{"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4907{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4908
4909{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4910{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4911{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4912{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4913
4914{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4915{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4916{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4917{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4918
4919{"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
4920
4921{"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4922{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
4923
4924{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}},
4925{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
4926{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},
4927
4928{"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},
4929
4930{"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}},
4931
4932{"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4933{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4934
4935{"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
4936
4937{"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
4938
4939{"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
4940{"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
4941
4942{"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
4943{"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
3172 4944
3173{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } }, 4945{"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
4946{"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
3174 4947
3175{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, 4948{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
3176 4949
3177{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } }, 4950{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
3178{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3179 4951
3180{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } }, 4952{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
3181 4953
3182{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } }, 4954{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
3183 4955
3184{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } }, 4956{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
3185{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3186 4957
3187{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } }, 4958{"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
3188{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } }, 4959{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
3189 4960
3190{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } }, 4961{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
3191{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3192{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3193{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3194{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3195{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3196{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3197{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3198{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3199{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3200{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3201{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3202{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3203{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3204{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3205 4962
3206{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 4963{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
3207{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 4964{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
3208 4965
3209{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, 4966{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
3210{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3211 4967
3212{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } }, 4968{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
3213{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } }, 4969{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
4970{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
4971{"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
3214 4972
3215{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } }, 4973{"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
3216 4974
3217{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, 4975{"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}},
4976{"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
3218 4977
3219{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } }, 4978{"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
4979{"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
3220 4980
3221{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } }, 4981{"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
3222{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } }, 4982{"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
3223 4983
3224{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } }, 4984{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
3225 4985
3226{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } }, 4986{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
3227 4987
3228{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } }, 4988{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
3229 4989
3230{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, 4990{"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
3231{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, 4991{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
3232{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3233{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3234 4992
3235{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } }, 4993{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
3236{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } }, 4994{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
3237{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } }, 4995{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
3238{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } }, 4996{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
3239 4997
3240{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } }, 4998{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
4999{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5000{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5001{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
3241 5002
3242{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } }, 5003{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
3243 5004
3244{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } }, 5005{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
3245 5006
3246{ "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } }, 5007{"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5008{"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5009{"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5010{"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
3247 5011
3248{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } }, 5012{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
3249{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3250{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3251{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3252 5013
3253{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } }, 5014{"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
3254 5015
3255{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } }, 5016{"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
3256 5017
3257{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } }, 5018{"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
5019{"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
3258 5020
3259{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }}, 5021{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
5022{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
3260 5023
3261{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 5024{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
3262{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3263{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3264{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3265{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3266{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3267{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3268{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3269 5025
3270{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 5026{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
3271{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3272{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3273{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3274{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3275{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3276{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3277{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3278 5027
3279{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }}, 5028{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
3280 5029
3281{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } }, 5030{"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
3282{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }}, 5031{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
3283{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3284 5032
3285{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } }, 5033{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5034{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5035{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5036{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
3286 5037
3287{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } }, 5038{"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5039{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
3288 5040
3289{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } }, 5041{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5042{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5043{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5044{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
3290 5045
3291{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } }, 5046{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
3292{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } }, 5047{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5048{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5049{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
3293 5050
3294{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } }, 5051{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
5052{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5053{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
5054{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
3295 5055
3296{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } }, 5056{"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5057{"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5058{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
3297 5059
3298{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } }, 5060{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
3299{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } }, 5061{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5062{"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5063{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
3300 5064
3301{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, 5065{"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
3302{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3303 5066
3304{ "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } }, 5067{"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
5068{"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
3305 5069
3306{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } }, 5070{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
3307 5071
3308{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }}, 5072{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
3309{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3310 5073
3311{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } }, 5074{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
5075{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
3312 5076
3313{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, 5077{"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
3314 5078
3315{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } }, 5079{"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
3316{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3317 5080
3318{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, 5081{"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
3319{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3320 5082
3321{ "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } }, 5083{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5084{"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5085{"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
3322 5086
3323{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } }, 5087{"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
3324 5088
3325{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 5089{"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
3326{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } }, 5090{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
3327{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } }, 5091{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
3328{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } }, 5092{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
3329{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3330{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3331{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3332{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3333 5093
3334{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 5094{"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
3335{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3336{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3337{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3338{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3339{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3340{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3341{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3342 5095
3343{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } }, 5096{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
5097{"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
3344 5098
3345{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } }, 5099{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
3346 5100
3347{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } }, 5101{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
5102{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
3348 5103
3349{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } }, 5104{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
3350{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3351 5105
3352{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } }, 5106{"lqarx", X(31,276), XEH_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}},
3353{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3354 5107
3355{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } }, 5108{"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
5109{"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
3356 5110
3357{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }}, 5111{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5112{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5113{"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5114{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
3358 5115
3359{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 5116{"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
3360{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3361{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3362{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3363{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3364{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3365{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3366{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3367 5117
3368{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 5118{"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
3369{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3370{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3371{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3372 5119
3373{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 5120{"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
3374{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } }, 5121{"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
3375{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3376{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3377{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3378{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3379{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3380{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3381 5122
3382{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 5123{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
3383{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3384{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3385{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3386{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3387{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3388{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3389{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3390 5124
3391{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }}, 5125{"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}},
3392{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3393{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3394 5126
3395{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } }, 5127{"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5128{"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
3396 5129
3397{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, 5130{"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
3398
3399{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3400{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3401
3402{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3403
3404{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3405
3406{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3407
3408{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3409{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3410{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3411{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3412
3413{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3414{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3415{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3416{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3417{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3418{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3419{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3420{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3421
3422{ "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
3423
3424{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3425
3426{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3427{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3428
3429{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3430
3431{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3432
3433{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3434{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3435
3436{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3437
3438{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3439
3440{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3441{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3442
3443{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3444
3445{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3446
3447{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3448{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3449
3450{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3451
3452{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3453{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3454{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3455{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3456{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3457{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3458{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3459{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3460{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3461{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3462{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3463{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3464{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3465{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3466{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3467{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3468{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3469{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3470{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3471{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3472{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3473{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3474{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3475{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3476{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3477{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3478{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3479{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3480{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3481{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3482{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3483{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3484{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3485{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3486{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3487
3488{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3489{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3490{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3491{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3492
3493{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3494
3495{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3496{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3497{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3498{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3499{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3500{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3501{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3502{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3503{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3504{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3505{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3506{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3507{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3508{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3509{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3510{ "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
3511{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3512{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3513{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3514{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3515{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3516{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3517{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3518{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3519{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3520{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3521{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3522{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3523{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3524{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3525{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3526{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3527{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3528{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3529{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3530{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3531{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3532{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3533{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3534{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3535{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3536{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3537{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3538{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3539{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3540{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3541{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3542{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3543{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3544{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
3545{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3546{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3547{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3548{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3549{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
3550{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
3551{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
3552{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
3553{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3554{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3555{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3556{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3557{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3558{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3559{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3560{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3561{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3562{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3563{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3564{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3565{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3566{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3567{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3568{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3569{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3570{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3571{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3572{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3573{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3574{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3575{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3576{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3577{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3578{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3579{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3580{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3581{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3582{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3583{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3584{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3585{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3586{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3587{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3588{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3589{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3590{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3591{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3592{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3593{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3594{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3595{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3596{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3597{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3598{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3599{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3600{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3601{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3602{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3603{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3604{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3605{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
3606{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
3607{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3608{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3609{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3610{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3611{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3612{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3613{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3614{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3615{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3616{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3617{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3618{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3619{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3620{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
3621{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3622{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3623{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3624{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3625{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3626{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3627{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3628{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3629{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3630{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3631{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3632{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3633{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3634{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3635{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3636{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3637{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3638{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3639{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3640{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3641{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3642{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3643{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3644{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3645{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3646{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3647{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3648{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3649{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3650{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3651{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3652{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3653{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3654{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3655{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3656{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3657{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3658{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3659{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3660{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3661{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3662{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3663{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3664{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3665{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3666{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3667{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3668{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3669{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3670{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3671{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3672{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3673{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3674{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3675{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3676{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3677{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3678{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3679{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3680{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3681{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3682{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3683
3684{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3685
3686{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3687{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3688
3689{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3690
3691{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3692
3693{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3694{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3695
3696{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3697
3698{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3699{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3700{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3701{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3702
3703{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3704{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3705{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3706{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3707
3708{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3709
3710{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3711
3712{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3713
3714{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3715
3716{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3717
3718{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3719
3720{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3721{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3722
3723{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3724{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3725
3726{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3727
3728{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3729
3730{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
3731
3732{ "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
3733
3734{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3735
3736{ "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
3737
3738{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3739
3740{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3741
3742{ "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
3743
3744{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3745
3746{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3747{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3748
3749{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3750{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3751
3752{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
3753
3754{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3755
3756{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3757
3758{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3759
3760{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3761
3762{ "cctpl", 0x7c210b78, 0xffffffff, CELL, { 0 }},
3763{ "cctpm", 0x7c421378, 0xffffffff, CELL, { 0 }},
3764{ "cctph", 0x7c631b78, 0xffffffff, CELL, { 0 }},
3765{ "db8cyc", 0x7f9ce378, 0xffffffff, CELL, { 0 }},
3766{ "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, { 0 }},
3767{ "db12cyc", 0x7fdef378, 0xffffffff, CELL, { 0 }},
3768{ "db16cyc", 0x7ffffb78, 0xffffffff, CELL, { 0 }},
3769{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3770{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3771{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3772{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3773
3774{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
3775{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
3776{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
3777{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
3778{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
3779{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
3780{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
3781{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
3782{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
3783{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
3784{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
3785{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
3786{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
3787{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
3788{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
3789{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
3790{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
3791{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
3792{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
3793{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
3794{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
3795{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
3796{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
3797{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
3798{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
3799{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
3800{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
3801{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
3802{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
3803{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
3804{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
3805{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
3806{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
3807{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
3808{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
3809
3810{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3811{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3812
3813{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3814{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3815{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3816{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3817
3818{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3819{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3820
3821{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3822{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3823{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3824{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3825
3826{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3827{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3828{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3829{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3830{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3831{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3832{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3833{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3834{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3835{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3836{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3837{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3838{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3839{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3840{ "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
3841{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3842{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
3843{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3844{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3845{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3846{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3847{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
3848{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3849{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
3850{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3851{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
3852{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
3853{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
3854{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
3855{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
3856{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
3857{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
3858{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
3859{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
3860{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
3861{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
3862{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
3863{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
3864{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
3865{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
3866{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
3867{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
3868{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
3869{ "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
3870{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
3871{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
3872{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
3873{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
3874{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
3875{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
3876{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
3877{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
3878{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3879{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3880{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3881{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3882{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
3883{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
3884{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
3885{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
3886{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
3887{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
3888{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
3889{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
3890{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
3891{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
3892{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
3893{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
3894{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
3895{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
3896{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
3897{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
3898{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
3899{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
3900{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
3901{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
3902{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
3903{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
3904{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
3905{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
3906{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
3907{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
3908{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
3909{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
3910{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
3911{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
3912{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
3913{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
3914{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
3915{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
3916{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
3917{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
3918{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
3919{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
3920{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
3921{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
3922{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
3923{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
3924{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
3925{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
3926{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
3927{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
3928{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
3929{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
3930{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
3931{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
3932{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3933{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3934{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3935{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3936{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
3937{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
3938{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
3939{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
3940{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
3941{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
3942{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
3943{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
3944{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
3945{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
3946{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
3947{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
3948{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
3949{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
3950{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
3951{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
3952{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
3953{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
3954{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
3955{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
3956{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
3957{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
3958{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
3959{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
3960{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
3961{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
3962{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
3963{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
3964{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
3965{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
3966{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
3967{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
3968{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
3969{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
3970{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
3971{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
3972{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
3973{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
3974{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
3975{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
3976{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
3977{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
3978{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
3979
3980{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
3981
3982{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
3983{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
3984
3985{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
3986
3987{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
3988
3989{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
3990
3991{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
3992
3993{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
3994{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3995{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
3996{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
3997{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3998{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
3999
4000{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4001{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4002{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4003{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4004
4005{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4006{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4007
4008{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4009{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4010{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4011{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4012 5131
4013{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }}, 5132{"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
5133
5134{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
5135{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
5136{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
5137{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
5138
5139{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
5140
5141{"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
5142
5143{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5144
5145{"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
5146
5147{"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
5148
5149{"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
5150{"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
5151
5152{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5153
5154{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
5155{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
5156{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
5157{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
5158{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
5159{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
5160{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
5161{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
5162{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
5163{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
5164{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
5165{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
5166{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
5167{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
5168{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
5169{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
5170{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
5171{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
5172{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
5173{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
5174{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
5175{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
5176{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
5177{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
5178{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
5179{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
5180{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
5181{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
5182{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
5183{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
5184{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
5185{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
5186{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
5187{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
5188{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
5189{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
5190
5191{"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5192
5193{"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
5194
5195{"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5196{"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5197
5198{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
5199
5200{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5201{"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}},
5202
5203{"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}},
5204
5205{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
5206{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
5207{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
5208{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
5209{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
5210{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
5211{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
5212{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
5213{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
5214{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
5215{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
5216{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
5217{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
5218{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
5219{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
5220{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
5221{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
5222{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
5223{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
5224{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
5225{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
5226{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
5227{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
5228{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
5229{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
5230{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
5231{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
5232{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
5233{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
5234{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
5235{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
5236{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
5237{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
5238{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
5239{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
5240{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
5241{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
5242{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
5243{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
5244{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
5245{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
5246{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
5247{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
5248{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5249{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5250{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5251{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5252{"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5253{"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
5254{"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5255{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
5256{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
5257{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
5258{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
5259{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
5260{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
5261{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
5262{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
5263{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
5264{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
5265{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
5266{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
5267{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
5268{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
5269{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
5270{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
5271{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
5272{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
5273{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
5274{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
5275{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
5276{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
5277{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
5278{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
5279{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
5280{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
5281{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
5282{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
5283{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
5284{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
5285{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
5286{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
5287{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
5288{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
5289{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
5290{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
5291{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
5292{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
5293{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
5294{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
5295{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
5296{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}},
5297{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5298{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}},
5299{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5300{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
5301{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5302{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5303{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5304{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
5305{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
5306{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
5307{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
5308{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
5309{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
5310{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
5311{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
5312{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
5313{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
5314{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
5315{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
5316{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
5317{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
5318{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
5319{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
5320{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
5321{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
5322{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
5323{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
5324{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
5325{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
5326{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
5327{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
5328{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
5329{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
5330{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
5331{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
5332{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
5333{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
5334{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
5335{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
5336{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
5337{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
5338{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
5339{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
5340{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
5341{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
5342{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
5343{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
5344{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
5345{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
5346{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
5347{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
5348{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
5349{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
5350{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
5351{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
5352{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
5353{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
5354{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
5355{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
5356{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
5357{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
5358{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
5359{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
5360{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
5361{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
5362{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
5363{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
5364{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
5365{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
5366{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
5367{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
5368{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
5369{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
5370{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
5371{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
5372{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
5373{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
5374{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
5375{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
5376{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
5377{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
5378{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
5379{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
5380{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
5381{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
5382{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
5383{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
5384{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
5385{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
5386{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
5387{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
5388{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
5389{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
5390{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
5391{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
5392{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
5393{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
5394{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
5395{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
5396{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
5397{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
5398{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
5399{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
5400{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
5401{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
5402{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
5403{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
5404{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
5405{"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
5406
5407{"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
5408
5409{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5410
5411{"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
5412
5413{"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5414
5415{"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
5416{"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
5417
5418{"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5419{"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5420
5421{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5422
5423{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
5424
5425{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5426{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
5427{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5428
5429{"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
5430
5431{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5432
5433{"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
5434
5435{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
5436
5437{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
5438{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
5439
5440{"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5441
5442{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5443{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5444
5445{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5446{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5447{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5448{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5449
5450{"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5451{"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5452
5453{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5454
5455{"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
5456
5457{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
5458
5459{"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
5460
5461{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5462{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5463
5464{"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
5465
5466{"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
5467{"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
5468
5469{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5470
5471{"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}},
5472
5473{"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5474
5475{"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
5476
5477{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5478{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5479{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5480{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5481
5482{"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5483
5484{"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}},
5485
5486{"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
5487
5488{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5489
5490{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5491
5492{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
5493
5494{"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
5495
5496{"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}},
5497
5498/* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
5499 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
5500{"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}},
5501{"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
5502{"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
5503{"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},
5504{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
5505{"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},
5506{"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
5507
5508{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
5509{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
5510{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
5511{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
5512{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
5513{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
5514{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
5515{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
5516{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
5517{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
5518{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
5519{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
5520{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
5521{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
5522{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
5523{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
5524{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
5525{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
5526{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
5527{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
5528{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
5529{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
5530{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
5531{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
5532{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
5533{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
5534{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
5535{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
5536{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
5537{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
5538{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
5539{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
5540{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
5541{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
5542{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
5543{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
5544
5545{"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5546
5547{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
5548{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
5549
5550{"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5551{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5552
5553{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5554{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5555
5556{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
5557{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}},
5558
5559{"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
5560
5561{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
5562{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
5563{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
5564{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
5565{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
5566{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
5567{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
5568{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
5569{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
5570{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
5571{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}},
5572{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}},
5573{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
5574{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
5575{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
5576{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
5577{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
5578{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
5579{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
5580{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
5581{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
5582{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
5583{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
5584{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
5585{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
5586{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
5587{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}},
5588{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}},
5589{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}},
5590{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}},
5591{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
5592{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
5593{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
5594{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
5595{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
5596{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
5597{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
5598{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
5599{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
5600{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
5601{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
5602{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
5603{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
5604{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},
5605{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},
5606{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},
5607{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},
5608{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5609{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5610{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5611{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5612{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}},
5613{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
5614{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
5615{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
5616{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
5617{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
5618{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
5619{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
5620{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
5621{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
5622{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
5623{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
5624{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
5625{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
5626{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
5627{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
5628{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
5629{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
5630{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
5631{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
5632{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
5633{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}},
5634{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}},
5635{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}},
5636{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}},
5637{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}},
5638{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}},
5639{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}},
5640{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}},
5641{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}},
5642{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}},
5643{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
5644{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
5645{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
5646{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
5647{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
5648{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
5649{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}},
5650{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5651{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}},
5652{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5653{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},
5654{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
5655{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5656{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5657{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
5658{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
5659{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
5660{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
5661{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
5662{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
5663{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}},
5664{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}},
5665{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},
5666{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},
5667{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},
5668{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},
5669{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},
5670{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},
5671{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}},
5672{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}},
5673{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}},
5674{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}},
5675{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}},
5676{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}},
5677{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}},
5678{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}},
5679{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}},
5680{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}},
5681{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}},
5682{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}},
5683{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}},
5684{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}},
5685{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}},
5686{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}},
5687{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}},
5688{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}},
5689{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}},
5690{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}},
5691{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}},
5692{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}},
5693{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}},
5694{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}},
5695{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}},
5696{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}},
5697{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}},
5698{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}},
5699{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}},
5700{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}},
5701{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}},
5702{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}},
5703{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}},
5704{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}},
5705{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},
5706{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},
5707{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},
5708{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
5709{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},
5710{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},
5711{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},
5712{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},
5713{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},
5714{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},
5715{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}},
5716{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}},
5717{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}},
5718{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}},
5719{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}},
5720{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}},
5721{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}},
5722{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}},
5723{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}},
5724{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}},
5725{"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
5726
5727{"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
5728
5729{"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
5730{"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
5731
5732{"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
5733
5734{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
5735
5736{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5737
5738{"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5739
5740{"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
5741{"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
5742
5743{"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5744{"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5745
5746{"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5747{"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5748
5749{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5750
5751{"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}},
5752{"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
5753
5754{"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
5755
5756{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
5757
5758{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
5759
5760{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
5761
5762{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
5763{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
4014 5764
4015{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } }, 5765{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
4016 5766
4017{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, 5767{"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
5768{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4018 5769
4019{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } }, 5770{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5771{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5772{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5773{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5774{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5775{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4020 5776
4021{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, 5777{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5778{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5779{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5780{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4022 5781
4023{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }}, 5782{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4024{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4025 5783
4026{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, 5784{"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
4027 5785
4028{ "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } }, 5786{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
4029 5787
4030{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } }, 5788{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
4031{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, 5789{"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4032 5790
4033{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } }, 5791{"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
4034{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } }, 5792{"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4035 5793
4036{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, 5794{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
4037 5795
4038{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } }, 5796{"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4039{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } }, 5797{"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4040{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } }, 5798{"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4041{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } }, 5799{"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4042 5800
4043{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } }, 5801{"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
4044{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } }, 5802{"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
4045 5803
4046{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } }, 5804{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
4047{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } }, 5805{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
4048 5806
4049{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } }, 5807{"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
4050{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } }, 5808{"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4051 5809
4052{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } }, 5810{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
5811{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
4053 5812
4054{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } }, 5813{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
5814{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
4055 5815
4056{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }}, 5816{"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
4057 5817
4058{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, 5818{"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
4059 5819
4060{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, 5820{"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
5821{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4061 5822
4062{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } }, 5823{"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5824{"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
5825{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5826{"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
4063 5827
4064{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, 5828{"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
4065 5829
4066{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } }, 5830{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
4067{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4068 5831
4069{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } }, 5832{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
4070{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } }, 5833{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
4071{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4072{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4073{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4074 5834
4075{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } }, 5835{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
4076 5836
4077{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } }, 5837{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
5838{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
4078 5839
4079{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } }, 5840{"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
4080 5841
4081{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, 5842{"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
4082 5843
4083{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } }, 5844{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4084 5845
4085{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } }, 5846{"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
4086 5847
4087{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } }, 5848{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
4088 5849
4089{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, 5850{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
5851{"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
4090 5852
4091{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } }, 5853{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
5854{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
5855{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
5856{"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
5857{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
5858{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
5859{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
5860{"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
5861{"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
4092 5862
4093{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } }, 5863{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
4094{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4095 5864
4096{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } }, 5865{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
4097{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } }, 5866{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
4098 5867
4099{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } }, 5868{"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
4100 5869
4101{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } }, 5870{"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
4102{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4103 5871
4104{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } }, 5872{"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
4105{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4106 5873
4107{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } }, 5874{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4108 5875
4109{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } }, 5876{"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
5877{"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
4110 5878
4111{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } }, 5879{"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
5880{"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
4112 5881
4113{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } }, 5882{"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
4114{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4115 5883
4116{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } }, 5884{"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
4117 5885
4118{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } }, 5886{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
4119{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4120 5887
4121{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } }, 5888{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
5889{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
4122 5890
4123{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } }, 5891{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
4124{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } }, 5892{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4125 5893
4126{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } }, 5894{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
4127{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4128 5895
4129{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } }, 5896{"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
4130 5897
4131{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } }, 5898{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5899{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5900{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5901{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4132 5902
4133{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } }, 5903{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5904{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5905{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5906{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4134 5907
4135{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, 5908{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
4136 5909
4137{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } }, 5910{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
4138{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4139 5911
4140{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } }, 5912{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
5913{"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
4141 5914
4142{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } }, 5915{"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
5916{"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
4143 5917
4144{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } }, 5918{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
4145{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4146 5919
4147{ "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } }, 5920{"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
5921{"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
4148 5922
4149{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } }, 5923{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
5924{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
4150 5925
4151{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, 5926{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
4152{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } }, 5927{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
4153{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4154{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4155 5928
4156{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } }, 5929{"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
4157{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4158 5930
4159{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } }, 5931{"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
5932{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4160 5933
4161{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } }, 5934{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
4162{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } }, 5935{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
4163 5936
4164{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, 5937{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
4165 5938
4166{ "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } }, 5939{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
4167 5940
4168{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, 5941{"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
4169{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } }, 5942{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
4170 5943
4171{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, 5944{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
4172{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } }, 5945{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
4173{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4174{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4175 5946
4176{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } }, 5947{"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
4177 5948
4178{ "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } }, 5949{"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
4179 5950
4180{ "mbar", X(31,854), X_MASK, BOOKE, { MO } }, 5951{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4181{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4182 5952
4183{ "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } }, 5953{"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
4184 5954
4185{ "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } }, 5955{"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
4186 5956
4187{ "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, 5957{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
4188{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, 5958{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
4189{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } }, 5959{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
4190{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } }, 5960{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
4191 5961
4192{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, 5962{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5963{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5964{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5965{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
4193 5966
4194{ "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } }, 5967{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
5968{"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
4195 5969
4196{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } }, 5970{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
4197 5971
4198{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, 5972{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
4199{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4200 5973
4201{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } }, 5974{"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
4202{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } }, 5975{"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
4203 5976
4204{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } }, 5977{"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
4205{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } }, 5978{"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
4206{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4207{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4208 5979
4209{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } }, 5980{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
5981{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
4210 5982
4211{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } }, 5983{"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
4212 5984
4213{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } }, 5985{"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
4214{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4215{ "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4216 5986
4217{ "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } }, 5987{"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
4218 5988
4219{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, 5989{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4220{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4221 5990
4222{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, 5991{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
4223{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, 5992{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5993{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5994{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
4224 5995
4225{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } }, 5996{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5997{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4226 5998
4227{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } }, 5999{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6000{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6001{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6002{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
4228 6003
4229{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } }, 6004{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4230{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } }, 6005{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4231{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, 6006{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4232{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, 6007{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4233 6008
4234{ "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } }, 6009{"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6010{"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6011{"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
4235 6012
4236{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, 6013{"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
4237 6014
4238{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } }, 6015{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6016{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
4239 6017
4240{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } }, 6018{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
4241{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4242 6019
4243{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } }, 6020{"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
6021{"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
4244 6022
4245{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } }, 6023{"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
4246{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4247 6024
4248{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, 6025{"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
4249 6026
4250{ "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } }, 6027{"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6028{"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
6029{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4251 6030
4252{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } }, 6031{"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
4253{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, 6032{"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
4254{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4255 6033
4256{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } }, 6034{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6035{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6036{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6037{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4257 6038
4258{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } }, 6039{"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
4259{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } }, 6040{"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
4260{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4261{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4262{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4263{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4264{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4265{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4266{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4267{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4268{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4269{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4270 6041
4271/* New load/store left/right index vector instructions that are in the Cell only. */ 6042{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
4272{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } }, 6043{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
4273{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4274{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4275{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4276{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4277{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4278{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4279{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
4280 6044
4281{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } }, 6045{"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
4282{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4283 6046
4284{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } }, 6047{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
4285{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4286 6048
4287{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } }, 6049{"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
4288 6050
4289{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } }, 6051{"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
4290 6052
4291{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } }, 6053{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
4292{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } }, 6054{"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
4293 6055
4294{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } }, 6056{"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4295{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } }, 6057{"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6058{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6059{"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4296 6060
4297{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } }, 6061{"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6062{"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4298 6063
4299{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } }, 6064{"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
4300 6065
4301{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } }, 6066{"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6067{"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6068{"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
4302 6069
4303{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } }, 6070{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6071{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
4304 6072
4305{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } }, 6073{"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
4306 6074
4307{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } }, 6075{"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
4308 6076
4309{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } }, 6077{"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
4310 6078
4311{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } }, 6079{"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
4312 6080
4313{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } }, 6081{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}},
4314{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4315 6082
4316{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } }, 6083{"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
4317{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4318 6084
4319{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, 6085{"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6086{"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6087{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6088{"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
4320 6089
4321{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, 6090{"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6091{"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
4322 6092
4323{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, 6093{"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
4324 6094
4325{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, 6095{"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
4326 6096
4327{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } }, 6097{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6098{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
4328 6099
4329{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } }, 6100{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6101{"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
4330 6102
4331{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } }, 6103{"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
4332 6104
4333{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, 6105{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
4334 6106
4335{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } }, 6107{"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}},
6108{"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6109{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
4336 6110
4337{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } }, 6111{"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
4338 6112
4339{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, 6113{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
6114{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
6115{"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}},
6116{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}},
4340 6117
4341{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } }, 6118{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
4342 6119
4343{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 6120{"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
4344{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4345{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4346{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4347{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4348{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4349{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4350{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4351{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4352{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4353{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4354{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4355{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4356{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4357 6121
4358{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } }, 6122{"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
6123{"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
4359 6124
4360{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } }, 6125{"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6126{"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
4361 6127
4362{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } }, 6128{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
4363 6129
4364{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6130{"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
4365{ "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4366 6131
4367{ "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 6132{"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
4368{ "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4369 6133
4370{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 6134{"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
4371{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4372 6135
4373{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 6136{"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}},
4374{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4375 6137
4376{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 6138{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
4377{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4378 6139
4379{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, 6140{"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
4380{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, 6141{"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
4381 6142
4382{ "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, 6143{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
4383{ "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4384 6144
4385{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 6145{"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
4386{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 6146{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4387 6147
4388{ "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } }, 6148{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
4389{ "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } }, 6149{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6150{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6151{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
4390 6152
4391{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6153{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
4392{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6154{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
4393 6155
4394{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6156{"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
4395{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4396 6157
4397{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6158{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
4398{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6159{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
4399 6160
4400{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6161{"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
4401{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6162{"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
4402 6163
4403{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6164{"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
4404{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4405 6165
4406{ "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 6166{"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
4407{ "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4408 6167
4409{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 6168{"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
4410{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 6169{"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
4411 6170
4412{ "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, 6171{"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
4413{ "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, 6172{"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
4414 6173
4415{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 6174{"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
4416{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 6175{"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
4417 6176
4418{ "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 6177{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
4419{ "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 6178{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
6179{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
6180{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
4420 6181
4421{ "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } }, 6182{"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
4422 6183
4423{ "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } }, 6184{"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
4424{ "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4425{ "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4426 6185
4427{ "drintn", ZRC(59,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 6186{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
4428{ "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 6187{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
6188{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
4429 6189
4430{ "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } }, 6190{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
4431{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } },
4432 6191
4433{ "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } }, 6192{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
4434{ "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } }, 6193{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6194{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6195{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
4435 6196
4436{ "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, 6197{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
4437{ "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } }, 6198{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
4438 6199
4439{ "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } }, 6200{"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
4440{ "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } },
4441 6201
4442{ "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6202{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
4443{ "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 6203{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6204{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
4444 6205
4445{ "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6206{"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
4446{ "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4447 6207
4448{ "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } }, 6208{"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
6209{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
4449 6210
4450{ "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } }, 6211{"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
4451 6212
4452{ "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } }, 6213{"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
4453{ "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } }, 6214{"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
4454 6215
4455{ "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } }, 6216{"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
4456{ "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } }, 6217{"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
4457 6218
4458{ "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } }, 6219{"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
4459{ "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4460 6220
4461{ "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6221{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
4462{ "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 6222{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
4463 6223
4464{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, 6224{"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6225{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4465 6226
4466{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, 6227{"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6228{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4467 6229
4468{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } }, 6230{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6231{"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
4469 6232
4470{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } }, 6233{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
4471{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } }, 6234{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
4472{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, 6235{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
4473{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } }, 6236{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
4474{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4475{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4476{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4477{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4478{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4479{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4480{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4481{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4482 6237
4483{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } }, 6238{"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
4484 6239
4485{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, 6240{"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
4486 6241
4487{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } }, 6242{"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
4488 6243
4489{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, 6244{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
4490 6245
4491{ "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6246{"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
4492{ "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 6247{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
4493 6248
4494{ "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 6249{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4495{ "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4496 6250
4497{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6251{"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
4498{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4499 6252
4500{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, 6253{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
4501{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4502 6254
4503{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } }, 6255{"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
4504{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } }, 6256{"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
4505{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4506{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4507 6257
4508{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, 6258{"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4509{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, 6259{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4510{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4511{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4512 6260
4513{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 6261{"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4514{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 6262{"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4515{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4516{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4517 6263
4518{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 6264{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
4519{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4520{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4521{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4522 6265
4523{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 6266{"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}},
4524{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4525{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4526{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4527 6267
4528{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, 6268{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
4529{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4530 6269
4531{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6270{"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
4532{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4533 6271
4534{ "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, 6272{"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
4535{ "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, 6273{"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
4536 6274
4537{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, 6275{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4538{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4539{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4540{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4541 6276
4542{ "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, 6277{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
4543{ "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4544 6278
4545{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 6279{"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}},
4546{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 6280{"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}},
4547{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 6281{"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}},
4548{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4549 6282
4550{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 6283{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
4551{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 6284{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
4552{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 6285{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},
4553{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4554 6286
4555{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 6287{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}},
4556{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 6288{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}},
4557{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 6289{"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}},
4558{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 6290{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}},
4559 6291
4560{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 6292{"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
4561{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 6293{"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
4562{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4563{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4564 6294
4565{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, 6295{"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
6296{"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
4566 6297
4567{ "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6298{"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
4568{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4569 6299
4570{ "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 6300{"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
4571{ "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4572 6301
4573{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, 6302{"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
4574{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, 6303{"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
4575 6304
4576{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } }, 6305{"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},
4577{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } }, 6306{"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
4578 6307
4579{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, 6308{"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
4580 6309
4581{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 6310{"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
4582{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4583 6311
4584{ "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, 6312{"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
4585{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4586 6313
4587{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } }, 6314{"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
4588{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4589 6315
4590{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, 6316{"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
4591{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4592 6317
4593{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 6318{"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
4594{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4595 6319
4596{ "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 6320{"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
4597{ "drintxq.",ZRC(63,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4598 6321
4599{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } }, 6322{"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
4600 6323
4601{ "mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } }, 6324{"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
4602{ "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } }, 6325{"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
4603 6326
4604{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, 6327{"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
4605{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } }, 6328{"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
4606 6329
4607{ "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } }, 6330{"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
4608{ "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4609{ "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4610 6331
4611{ "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 6332{"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
4612{ "drintnq.",ZRC(63,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4613 6333
4614{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } }, 6334{"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
4615{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
4616 6335
4617{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, 6336{"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
4618{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4619 6337
4620{ "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } }, 6338{"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
4621{ "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } },
4622 6339
4623{ "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, 6340{"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
4624{ "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4625 6341
4626{ "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } }, 6342{"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
4627{ "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } },
4628 6343
4629{ "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } }, 6344{"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
4630{ "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } },
4631{ "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } },
4632{ "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } },
4633{ "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } },
4634{ "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } },
4635{ "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } },
4636{ "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } },
4637 6345
4638{ "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6346{"lq", OP(56), OP_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},
4639{ "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 6347{"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6348{"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
4640 6349
4641{ "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6350{"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
4642{ "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 6351{"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6352{"lfdp", OP(57), OP_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},
6353{"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6354{"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
4643 6355
4644{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, 6356{"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
4645{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } }, 6357{"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
6358{"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
4646 6359
4647{ "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } }, 6360{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6361{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
4648 6362
4649{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } }, 6363{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6364{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
4650 6365
4651{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W } }, 6366{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
4652{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W } }, 6367{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
4653 6368
4654{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } }, 6369{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
4655{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } }, 6370{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
4656 6371
4657{ "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } }, 6372{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
4658{ "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } }, 6373{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
4659 6374
4660{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } }, 6375{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
4661{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } }, 6376{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
4662 6377
4663{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } }, 6378{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
4664{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } }, 6379{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6380{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6381{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
4665 6382
4666{ "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } }, 6383{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
4667{ "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } }, 6384{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
4668 6385
4669{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } }, 6386{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
4670{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } }, 6387{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6388{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6389{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
4671 6390
4672{ "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6391{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
4673{ "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 6392{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
4674 6393
6394{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6395{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6396
6397{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6398{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6399
6400{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6401{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6402
6403{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6404{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6405
6406{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6407{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6408
6409{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6410{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6411
6412{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6413{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6414
6415{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6416{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6417
6418{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6419{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6420
6421{"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6422
6423{"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6424{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}},
6425{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}},
6426
6427{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6428{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6429
6430{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6431{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6432
6433{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6434{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6435
6436{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6437{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6438
6439{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6440{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6441
6442{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6443{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6444
6445{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6446{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6447
6448{"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6449
6450{"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6451{"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
6452
6453{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6454{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6455
6456{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6457{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6458
6459{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6460{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6461
6462{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6463{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6464
6465{"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6466{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6467
6468{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6469{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6470
6471{"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6472{"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6473{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}},
6474{"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6475{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6476{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6477{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
6478{"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6479{"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6480{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}},
6481{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6482{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6483{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6484{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}},
6485{"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6486{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6487{"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6488{"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6489{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6490{"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6491{"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6492{"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6493{"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6494{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6495{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6496{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6497{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6498{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6499{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6500{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6501{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6502{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6503{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6504{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6505{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6506{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6507{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6508{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6509{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6510{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6511{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6512{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6513{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6514{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6515{"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6516{"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}},
6517{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6518{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6519{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6520{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6521{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6522{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6523{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6524{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6525{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6526{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6527{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6528{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6529{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6530{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6531{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6532{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6533{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6534{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6535{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6536{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}},
6537{"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6538{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6539{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6540{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6541{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6542{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6543{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6544{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6545{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6546{"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}},
6547{"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6548{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6549{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6550{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6551{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6552{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6553{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6554{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6555{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6556{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6557{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6558{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6559{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6560{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6561{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6562{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6563{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6564{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6565{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6566{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6567{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6568{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6569{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6570{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6571{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6572{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6573{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6574{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6575{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6576{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6577{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6578{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6579{"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6580{"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6581{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6582{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6583{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6584{"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6585{"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6586{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6587{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6588{"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6589{"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6590{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6591{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6592{"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6593{"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6594{"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6595{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6596{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6597{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6598{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6599{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6600{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6601{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6602{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6603{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6604{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6605{"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6606{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6607{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6608{"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6609{"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6610{"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6611{"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6612{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6613{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6614{"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6615{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6616{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6617{"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6618{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6619{"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6620{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6621{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6622{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6623{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6624{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6625{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6626{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6627{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6628{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6629{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6630{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6631{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6632{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6633{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6634{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6635{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6636{"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6637{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6638{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6639{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6640{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6641{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6642{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6643{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6644{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
6645{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6646{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6647{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6648{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6649{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6650{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6651{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6652{"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6653{"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6654{"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6655{"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6656{"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6657{"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6658{"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6659{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6660{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6661{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6662{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6663{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6664{"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6665{"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6666{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6667{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6668{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6669
6670{"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6671{"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6672
6673{"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}},
6674{"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}},
6675{"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6676{"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6677{"stfdp", OP(61), OP_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},
6678{"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6679{"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6680
6681{"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},
6682{"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}},
6683{"stq", DSO(62,2), DS_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},
6684
6685{"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6686
6687{"daddq", XRC(63,2,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6688{"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6689
6690{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6691{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6692
6693{"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6694{"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6695
6696{"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6697{"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6698
6699{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6700{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6701
6702{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6703{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6704
6705{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6706{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6707{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6708{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6709
6710{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6711{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6712{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6713{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6714
6715{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6716{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6717{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6718{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6719
6720{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6721{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6722{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6723{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6724
6725{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6726{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6727{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6728{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6729
6730{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6731{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6732
6733{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6734{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6735
6736{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6737{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6738{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6739{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6740
6741{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6742{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6743{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6744{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6745
6746{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6747{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6748{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6749{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6750
6751{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6752{"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6753{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6754{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6755
6756{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6757{"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6758{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6759{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6760
6761{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6762{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6763{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6764{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6765
6766{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6767{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6768{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6769{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6770
6771{"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6772
6773{"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6774{"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6775
6776{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6777{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6778
6779{"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6780{"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6781
6782{"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6783
6784{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}},
6785{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}},
6786
6787{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6788{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6789
6790{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
6791
6792{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6793{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6794
6795{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6796{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6797
6798{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}},
6799{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}},
6800
6801{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6802{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6803
6804{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6805{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6806
6807{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6808{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6809
6810{"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6811
6812{"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}},
6813
6814{"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6815
6816{"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6817
6818{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6819{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6820{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6821{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6822
6823{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6824{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6825
6826{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6827{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6828{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6829{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6830
6831{"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}},
6832
6833{"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6834
6835{"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6836
6837{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}},
6838{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}},
6839
6840{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6841{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6842
6843{"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6844{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6845
6846{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6847{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6848
6849{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6850{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6851
6852{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6853{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6854
6855{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6856{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6857
6858{"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6859{"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6860
6861{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6862{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6863
6864{"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6865{"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6866
6867{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6868{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6869
6870{"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6871{"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6872
6873{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6874{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6875
6876{"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6877{"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6878
6879{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6880{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6881
6882{"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6883{"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6884
6885{"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6886{"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6887
6888{"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6889{"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6890
6891{"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6892{"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6893
6894{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
6895{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
6896
6897{"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
6898{"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
6899{"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}},
6900{"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
6901{"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}},
6902{"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
6903
6904{"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6905
6906{"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6907
6908{"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
6909{"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
6910
6911{"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
6912
6913{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6914{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
6915{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6916{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
6917
6918{"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
6919{"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
6920
6921{"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6922{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6923
6924{"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6925{"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6926{"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6927{"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6928{"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6929{"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6930{"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6931
6932{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6933{"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6934{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6935{"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6936
6937{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6938{"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6939{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6940{"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6941
6942{"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
6943{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
6944
6945{"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6946{"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6947{"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6948{"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6949{"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6950{"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6951{"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6952{"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6953{"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6954
6955{"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
6956
6957{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6958{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6959{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6960{"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6961
6962{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
6963{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
6964
6965{"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6966
6967{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6968{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6969
6970{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6971{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6972
6973{"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
6974
6975{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6976{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
4675}; 6977};
4676 6978
4677const int powerpc_num_opcodes = 6979const int powerpc_num_opcodes =
4678 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); 6980 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4679 6981
6982/* The VLE opcode table.
6983
6984 The format of this opcode table is the same as the main opcode table. */
6985
6986const struct powerpc_opcode vle_opcodes[] = {
6987{"se_illegal", C(0), C_MASK, PPCVLE, 0, {}},
6988{"se_isync", C(1), C_MASK, PPCVLE, 0, {}},
6989{"se_sc", C(2), C_MASK, PPCVLE, 0, {}},
6990{"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}},
6991{"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}},
6992{"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}},
6993{"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}},
6994{"se_rfi", C(8), C_MASK, PPCVLE, 0, {}},
6995{"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
6996{"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
6997{"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
6998{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
6999{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
7000{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
7001{"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}},
7002{"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}},
7003{"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}},
7004{"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}},
7005{"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}},
7006{"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}},
7007{"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}},
7008{"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7009{"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
7010{"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}},
7011{"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7012{"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7013{"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7014{"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7015{"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7016{"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7017{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7018{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7019
7020{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7021{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7022{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7023{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7024{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7025{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7026{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7027{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7028{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7029{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7030{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7031{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7032{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7033{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7034{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7035{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7036{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}},
7037{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7038{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7039{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7040{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7041{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7042{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7043{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7044{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7045{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7046{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7047{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7048{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7049{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7050{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7051{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7052{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7053{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7054{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7055{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7056{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7057{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7058{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7059{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7060{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
7061{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7062{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
7063
7064{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7065{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7066{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7067{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7068{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7069{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7070{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7071
7072{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7073{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7074{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7075
7076{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7077{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7078{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7079{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}},
7080{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7081{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7082{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7083{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7084{"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
7085
7086{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7087{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7088{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7089{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7090
7091{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7092{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7093{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7094{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7095{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7096{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7097{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7098
7099{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7100{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7101{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7102{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7103{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7104{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7105{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7106{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7107{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7108{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7109{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7110{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7111{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7112{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7113{"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
7114{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
7115{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
7116{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
7117{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
7118{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7119{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7120{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7121{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7122{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7123{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7124{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7125{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7126{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7127{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7128{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7129{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7130{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7131{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7132{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7133{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7134{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7135{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7136{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7137{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7138{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7139{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7140{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7141{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7142{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7143{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7144{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7145{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7146{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7147{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7148
7149{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7150{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7151{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7152{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7153
7154{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7155{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7156{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7157{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7158{"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7159{"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7160{"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7161{"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7162{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
7163{"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7164{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7165
7166{"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7167
7168{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7169{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7170
7171{"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7172{"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7173
7174{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7175{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7176
7177{"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7178
7179{"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7180{"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7181
7182{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}},
7183
7184{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7185{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7186
7187{"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7188
7189{"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7190
7191{"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7192
7193{"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7194
7195{"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7196
7197{"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7198
7199{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7200{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7201{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7202{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7203{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7204{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7205{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7206{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7207{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7208{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7209{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7210{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7211{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7212{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7213{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
7214{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
7215{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
7216};
7217
7218const int vle_num_opcodes =
7219 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
7220
4680/* The macro table. This is only used by the assembler. */ 7221/* The macro table. This is only used by the assembler. */
4681 7222
4682/* The expressions of the form (-x ! 31) & (x | 31) have the value 0 7223/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
@@ -4690,45 +7231,57 @@ const int powerpc_num_opcodes =
4690 support extracting the whole word (32 bits in this case). */ 7231 support extracting the whole word (32 bits in this case). */
4691 7232
4692const struct powerpc_macro powerpc_macros[] = { 7233const struct powerpc_macro powerpc_macros[] = {
4693{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" }, 7234{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
4694{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" }, 7235{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
4695{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, 7236{"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
4696{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, 7237{"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
4697{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, 7238{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
4698{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, 7239{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
4699{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" }, 7240{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
4700{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" }, 7241{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
4701{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" }, 7242{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
4702{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" }, 7243{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
4703{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" }, 7244{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
4704{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" }, 7245{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
4705{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" }, 7246{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
4706{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" }, 7247{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
4707{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" }, 7248{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
4708{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" }, 7249{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
4709 7250
4710{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, 7251{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
4711{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" }, 7252{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
4712{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, 7253{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
4713{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, 7254{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
4714{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, 7255{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4715{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 7256{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4716{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, 7257{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4717{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 7258{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4718{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" }, 7259{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
4719{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" }, 7260{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
4720{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" }, 7261{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
4721{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" }, 7262{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
4722{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" }, 7263{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
4723{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" }, 7264{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
4724{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 7265{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4725{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 7266{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4726{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 7267{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4727{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 7268{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4728{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" }, 7269{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
4729{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" }, 7270{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
4730{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, 7271{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
4731{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, 7272{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
7273
7274{"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
7275{"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7276{"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7277{"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7278{"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
7279{"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7280{"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
7281{"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7282{"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
7283{"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
7284{"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
4732}; 7285};
4733 7286
4734const int powerpc_num_macros = 7287const int powerpc_num_macros =
diff --git a/arch/powerpc/xmon/ppc.h b/arch/powerpc/xmon/ppc.h
index 6771856fd5f8..29c385f8e115 100644
--- a/arch/powerpc/xmon/ppc.h
+++ b/arch/powerpc/xmon/ppc.h
@@ -1,6 +1,5 @@
1/* ppc.h -- Header file for PowerPC opcode table 1/* ppc.h -- Header file for PowerPC opcode table
2 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 2007 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support 3 Written by Ian Lance Taylor, Cygnus Support
5 4
6This file is part of GDB, GAS, and the GNU binutils. 5This file is part of GDB, GAS, and the GNU binutils.
@@ -22,6 +21,14 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
22#ifndef PPC_H 21#ifndef PPC_H
23#define PPC_H 22#define PPC_H
24 23
24#include "bfd_stdint.h"
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30typedef uint64_t ppc_cpu_t;
31
25/* The opcode table is an array of struct powerpc_opcode. */ 32/* The opcode table is an array of struct powerpc_opcode. */
26 33
27struct powerpc_opcode 34struct powerpc_opcode
@@ -42,7 +49,12 @@ struct powerpc_opcode
42 /* One bit flags for the opcode. These are used to indicate which 49 /* One bit flags for the opcode. These are used to indicate which
43 specific processors support the instructions. The defined values 50 specific processors support the instructions. The defined values
44 are listed below. */ 51 are listed below. */
45 unsigned long flags; 52 ppc_cpu_t flags;
53
54 /* One bit flags for the opcode. These are used to indicate which
55 specific processors no longer support the instructions. The defined
56 values are listed below. */
57 ppc_cpu_t deprecated;
46 58
47 /* An array of operand codes. Each code is an index into the 59 /* An array of operand codes. Each code is an index into the
48 operand table. They appear in the order which the operands must 60 operand table. They appear in the order which the operands must
@@ -55,6 +67,8 @@ struct powerpc_opcode
55 instructions. */ 67 instructions. */
56extern const struct powerpc_opcode powerpc_opcodes[]; 68extern const struct powerpc_opcode powerpc_opcodes[];
57extern const int powerpc_num_opcodes; 69extern const int powerpc_num_opcodes;
70extern const struct powerpc_opcode vle_opcodes[];
71extern const int vle_num_opcodes;
58 72
59/* Values defined for the flags field of a struct powerpc_opcode. */ 73/* Values defined for the flags field of a struct powerpc_opcode. */
60 74
@@ -67,87 +81,152 @@ extern const int powerpc_num_opcodes;
67/* Opcode is defined for the POWER2 (Rios 2) architecture. */ 81/* Opcode is defined for the POWER2 (Rios 2) architecture. */
68#define PPC_OPCODE_POWER2 4 82#define PPC_OPCODE_POWER2 4
69 83
70/* Opcode is only defined on 32 bit architectures. */
71#define PPC_OPCODE_32 8
72
73/* Opcode is only defined on 64 bit architectures. */
74#define PPC_OPCODE_64 0x10
75
76/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 84/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
77 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, 85 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
78 but it also supports many additional POWER instructions. */ 86 but it also supports many additional POWER instructions. */
79#define PPC_OPCODE_601 0x20 87#define PPC_OPCODE_601 8
80 88
81/* Opcode is supported in both the Power and PowerPC architectures 89/* Opcode is supported in both the Power and PowerPC architectures
82 (ie, compiler's -mcpu=common or assembler's -mcom). */ 90 (ie, compiler's -mcpu=common or assembler's -mcom). More than just
83#define PPC_OPCODE_COMMON 0x40 91 the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
92 and PPC_OPCODE_POWER2 because many instructions changed mnemonics
93 between POWER and POWERPC. */
94#define PPC_OPCODE_COMMON 0x10
84 95
85/* Opcode is supported for any Power or PowerPC platform (this is 96/* Opcode is supported for any Power or PowerPC platform (this is
86 for the assembler's -many option, and it eliminates duplicates). */ 97 for the assembler's -many option, and it eliminates duplicates). */
87#define PPC_OPCODE_ANY 0x80 98#define PPC_OPCODE_ANY 0x20
99
100/* Opcode is only defined on 64 bit architectures. */
101#define PPC_OPCODE_64 0x40
88 102
89/* Opcode is supported as part of the 64-bit bridge. */ 103/* Opcode is supported as part of the 64-bit bridge. */
90#define PPC_OPCODE_64_BRIDGE 0x100 104#define PPC_OPCODE_64_BRIDGE 0x80
91 105
92/* Opcode is supported by Altivec Vector Unit */ 106/* Opcode is supported by Altivec Vector Unit */
93#define PPC_OPCODE_ALTIVEC 0x200 107#define PPC_OPCODE_ALTIVEC 0x100
94 108
95/* Opcode is supported by PowerPC 403 processor. */ 109/* Opcode is supported by PowerPC 403 processor. */
96#define PPC_OPCODE_403 0x400 110#define PPC_OPCODE_403 0x200
97 111
98/* Opcode is supported by PowerPC BookE processor. */ 112/* Opcode is supported by PowerPC BookE processor. */
99#define PPC_OPCODE_BOOKE 0x800 113#define PPC_OPCODE_BOOKE 0x400
100
101/* Opcode is only supported by 64-bit PowerPC BookE processor. */
102#define PPC_OPCODE_BOOKE64 0x1000
103 114
104/* Opcode is supported by PowerPC 440 processor. */ 115/* Opcode is supported by PowerPC 440 processor. */
105#define PPC_OPCODE_440 0x2000 116#define PPC_OPCODE_440 0x800
106 117
107/* Opcode is only supported by Power4 architecture. */ 118/* Opcode is only supported by Power4 architecture. */
108#define PPC_OPCODE_POWER4 0x4000 119#define PPC_OPCODE_POWER4 0x1000
109 120
110/* Opcode isn't supported by Power4 architecture. */ 121/* Opcode is only supported by Power7 architecture. */
111#define PPC_OPCODE_NOPOWER4 0x8000 122#define PPC_OPCODE_POWER7 0x2000
112
113/* Opcode is only supported by POWERPC Classic architecture. */
114#define PPC_OPCODE_CLASSIC 0x10000
115 123
116/* Opcode is only supported by e500x2 Core. */ 124/* Opcode is only supported by e500x2 Core. */
117#define PPC_OPCODE_SPE 0x20000 125#define PPC_OPCODE_SPE 0x4000
118 126
119/* Opcode is supported by e500x2 Integer select APU. */ 127/* Opcode is supported by e500x2 Integer select APU. */
120#define PPC_OPCODE_ISEL 0x40000 128#define PPC_OPCODE_ISEL 0x8000
121 129
122/* Opcode is an e500 SPE floating point instruction. */ 130/* Opcode is an e500 SPE floating point instruction. */
123#define PPC_OPCODE_EFS 0x80000 131#define PPC_OPCODE_EFS 0x10000
124 132
125/* Opcode is supported by branch locking APU. */ 133/* Opcode is supported by branch locking APU. */
126#define PPC_OPCODE_BRLOCK 0x100000 134#define PPC_OPCODE_BRLOCK 0x20000
127 135
128/* Opcode is supported by performance monitor APU. */ 136/* Opcode is supported by performance monitor APU. */
129#define PPC_OPCODE_PMR 0x200000 137#define PPC_OPCODE_PMR 0x40000
130 138
131/* Opcode is supported by cache locking APU. */ 139/* Opcode is supported by cache locking APU. */
132#define PPC_OPCODE_CACHELCK 0x400000 140#define PPC_OPCODE_CACHELCK 0x80000
133 141
134/* Opcode is supported by machine check APU. */ 142/* Opcode is supported by machine check APU. */
135#define PPC_OPCODE_RFMCI 0x800000 143#define PPC_OPCODE_RFMCI 0x100000
136 144
137/* Opcode is only supported by Power5 architecture. */ 145/* Opcode is only supported by Power5 architecture. */
138#define PPC_OPCODE_POWER5 0x1000000 146#define PPC_OPCODE_POWER5 0x200000
139 147
140/* Opcode is supported by PowerPC e300 family. */ 148/* Opcode is supported by PowerPC e300 family. */
141#define PPC_OPCODE_E300 0x2000000 149#define PPC_OPCODE_E300 0x400000
142 150
143/* Opcode is only supported by Power6 architecture. */ 151/* Opcode is only supported by Power6 architecture. */
144#define PPC_OPCODE_POWER6 0x4000000 152#define PPC_OPCODE_POWER6 0x800000
145 153
146/* Opcode is only supported by PowerPC Cell family. */ 154/* Opcode is only supported by PowerPC Cell family. */
147#define PPC_OPCODE_CELL 0x8000000 155#define PPC_OPCODE_CELL 0x1000000
156
157/* Opcode is supported by CPUs with paired singles support. */
158#define PPC_OPCODE_PPCPS 0x2000000
159
160/* Opcode is supported by Power E500MC */
161#define PPC_OPCODE_E500MC 0x4000000
162
163/* Opcode is supported by PowerPC 405 processor. */
164#define PPC_OPCODE_405 0x8000000
165
166/* Opcode is supported by Vector-Scalar (VSX) Unit */
167#define PPC_OPCODE_VSX 0x10000000
168
169/* Opcode is supported by A2. */
170#define PPC_OPCODE_A2 0x20000000
171
172/* Opcode is supported by PowerPC 476 processor. */
173#define PPC_OPCODE_476 0x40000000
174
175/* Opcode is supported by AppliedMicro Titan core */
176#define PPC_OPCODE_TITAN 0x80000000
177
178/* Opcode which is supported by the e500 family */
179#define PPC_OPCODE_E500 0x100000000ull
180
181/* Opcode is supported by Extended Altivec Vector Unit */
182#define PPC_OPCODE_ALTIVEC2 0x200000000ull
183
184/* Opcode is supported by Power E6500 */
185#define PPC_OPCODE_E6500 0x400000000ull
186
187/* Opcode is supported by Thread management APU */
188#define PPC_OPCODE_TMR 0x800000000ull
189
190/* Opcode which is supported by the VLE extension. */
191#define PPC_OPCODE_VLE 0x1000000000ull
192
193/* Opcode is only supported by Power8 architecture. */
194#define PPC_OPCODE_POWER8 0x2000000000ull
195
196/* Opcode which is supported by the Hardware Transactional Memory extension. */
197/* Currently, this is the same as the POWER8 mask. If another cpu comes out
198 that isn't a superset of POWER8, we can define this to its own mask. */
199#define PPC_OPCODE_HTM PPC_OPCODE_POWER8
200
201/* Opcode is supported by ppc750cl. */
202#define PPC_OPCODE_750 0x4000000000ull
203
204/* Opcode is supported by ppc7450. */
205#define PPC_OPCODE_7450 0x8000000000ull
206
207/* Opcode is supported by ppc821/850/860. */
208#define PPC_OPCODE_860 0x10000000000ull
209
210/* Opcode is only supported by Power9 architecture. */
211#define PPC_OPCODE_POWER9 0x20000000000ull
212
213/* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
214#define PPC_OPCODE_VSX3 0x40000000000ull
215
216 /* Opcode is supported by e200z4. */
217#define PPC_OPCODE_E200Z4 0x80000000000ull
148 218
149/* A macro to extract the major opcode from an instruction. */ 219/* A macro to extract the major opcode from an instruction. */
150#define PPC_OP(i) (((i) >> 26) & 0x3f) 220#define PPC_OP(i) (((i) >> 26) & 0x3f)
221
222/* A macro to determine if the instruction is a 2-byte VLE insn. */
223#define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
224
225/* A macro to extract the major opcode from a VLE instruction. */
226#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
227
228/* A macro to convert a VLE opcode to a VLE opcode segment. */
229#define VLE_OP_TO_SEG(i) ((i) >> 1)
151 230
152/* The operands table is an array of struct powerpc_operand. */ 231/* The operands table is an array of struct powerpc_operand. */
153 232
@@ -156,16 +235,22 @@ struct powerpc_operand
156 /* A bitmask of bits in the operand. */ 235 /* A bitmask of bits in the operand. */
157 unsigned int bitm; 236 unsigned int bitm;
158 237
159 /* How far the operand is left shifted in the instruction. 238 /* The shift operation to be applied to the operand. No shift
160 -1 to indicate that BITM and SHIFT cannot be used to determine 239 is made if this is zero. For positive values, the operand
161 where the operand goes in the insn. */ 240 is shifted left by SHIFT. For negative values, the operand
241 is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
242 that BITM and SHIFT cannot be used to determine where the
243 operand goes in the insn. */
162 int shift; 244 int shift;
163 245
164 /* Insertion function. This is used by the assembler. To insert an 246 /* Insertion function. This is used by the assembler. To insert an
165 operand value into an instruction, check this field. 247 operand value into an instruction, check this field.
166 248
167 If it is NULL, execute 249 If it is NULL, execute
168 i |= (op & o->bitm) << o->shift; 250 if (o->shift >= 0)
251 i |= (op & o->bitm) << o->shift;
252 else
253 i |= (op & o->bitm) >> -o->shift;
169 (i is the instruction which we are filling in, o is a pointer to 254 (i is the instruction which we are filling in, o is a pointer to
170 this structure, and op is the operand value). 255 this structure, and op is the operand value).
171 256
@@ -177,13 +262,16 @@ struct powerpc_operand
177 operand value is legal, *ERRMSG will be unchanged (most operands 262 operand value is legal, *ERRMSG will be unchanged (most operands
178 can accept any value). */ 263 can accept any value). */
179 unsigned long (*insert) 264 unsigned long (*insert)
180 (unsigned long instruction, long op, int dialect, const char **errmsg); 265 (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
181 266
182 /* Extraction function. This is used by the disassembler. To 267 /* Extraction function. This is used by the disassembler. To
183 extract this operand type from an instruction, check this field. 268 extract this operand type from an instruction, check this field.
184 269
185 If it is NULL, compute 270 If it is NULL, compute
186 op = (i >> o->shift) & o->bitm; 271 if (o->shift >= 0)
272 op = (i >> o->shift) & o->bitm;
273 else
274 op = (i << -o->shift) & o->bitm;
187 if ((o->flags & PPC_OPERAND_SIGNED) != 0) 275 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
188 sign_extend (op); 276 sign_extend (op);
189 (i is the instruction, o is a pointer to this structure, and op 277 (i is the instruction, o is a pointer to this structure, and op
@@ -195,7 +283,7 @@ struct powerpc_operand
195 non-zero if this operand type can not actually be extracted from 283 non-zero if this operand type can not actually be extracted from
196 this operand (i.e., the instruction does not match). If the 284 this operand (i.e., the instruction does not match). If the
197 operand is valid, *INVALID will not be changed. */ 285 operand is valid, *INVALID will not be changed. */
198 long (*extract) (unsigned long instruction, int dialect, int *invalid); 286 long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
199 287
200 /* One bit syntax flags. */ 288 /* One bit syntax flags. */
201 unsigned long flags; 289 unsigned long flags;
@@ -207,6 +295,11 @@ struct powerpc_operand
207extern const struct powerpc_operand powerpc_operands[]; 295extern const struct powerpc_operand powerpc_operands[];
208extern const unsigned int num_powerpc_operands; 296extern const unsigned int num_powerpc_operands;
209 297
298/* Use with the shift field of a struct powerpc_operand to indicate
299 that BITM and SHIFT cannot be used to determine where the operand
300 goes in the insn. */
301#define PPC_OPSHIFT_INV (-1U << 31)
302
210/* Values defined for the flags field of a struct powerpc_operand. */ 303/* Values defined for the flags field of a struct powerpc_operand. */
211 304
212/* This operand takes signed values. */ 305/* This operand takes signed values. */
@@ -240,7 +333,7 @@ extern const unsigned int num_powerpc_operands;
240 cr4 4 cr5 5 cr6 6 cr7 7 333 cr4 4 cr5 5 cr6 6 cr7 7
241 These may be combined arithmetically, as in cr2*4+gt. These are 334 These may be combined arithmetically, as in cr2*4+gt. These are
242 only supported on the PowerPC, not the POWER. */ 335 only supported on the PowerPC, not the POWER. */
243#define PPC_OPERAND_CR (0x10) 336#define PPC_OPERAND_CR_BIT (0x10)
244 337
245/* This operand names a register. The disassembler uses this to print 338/* This operand names a register. The disassembler uses this to print
246 register names with a leading 'r'. */ 339 register names with a leading 'r'. */
@@ -296,6 +389,27 @@ extern const unsigned int num_powerpc_operands;
296 389
297/* Valid range of operand is 0..n rather than 0..n-1. */ 390/* Valid range of operand is 0..n rather than 0..n-1. */
298#define PPC_OPERAND_PLUS1 (0x10000) 391#define PPC_OPERAND_PLUS1 (0x10000)
392
393/* Xilinx APU and FSL related operands */
394#define PPC_OPERAND_FSL (0x20000)
395#define PPC_OPERAND_FCR (0x40000)
396#define PPC_OPERAND_UDI (0x80000)
397
398/* This operand names a vector-scalar unit register. The disassembler
399 prints these with a leading 'vs'. */
400#define PPC_OPERAND_VSR (0x100000)
401
402/* This is a CR FIELD that does not use symbolic names. */
403#define PPC_OPERAND_CR_REG (0x200000)
404
405/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
406 is omitted, then the value it should use for the operand is stored
407 in the SHIFT field of the immediatly following operand field. */
408#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
409
410/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
411 only optional when generating 32-bit code. */
412#define PPC_OPERAND_OPTIONAL32 (0x800000)
299 413
300/* The POWER and PowerPC assemblers use a few macros. We keep them 414/* The POWER and PowerPC assemblers use a few macros. We keep them
301 with the operands table for simplicity. The macro table is an 415 with the operands table for simplicity. The macro table is an
@@ -312,7 +426,7 @@ struct powerpc_macro
312 /* One bit flags for the opcode. These are used to indicate which 426 /* One bit flags for the opcode. These are used to indicate which
313 specific processors support the instructions. The values are the 427 specific processors support the instructions. The values are the
314 same as those for the struct powerpc_opcode flags field. */ 428 same as those for the struct powerpc_opcode flags field. */
315 unsigned long flags; 429 ppc_cpu_t flags;
316 430
317 /* A format string to turn the macro into a normal instruction. 431 /* A format string to turn the macro into a normal instruction.
318 Each %N in the string is replaced with operand number N (zero 432 Each %N in the string is replaced with operand number N (zero
@@ -323,4 +437,18 @@ struct powerpc_macro
323extern const struct powerpc_macro powerpc_macros[]; 437extern const struct powerpc_macro powerpc_macros[];
324extern const int powerpc_num_macros; 438extern const int powerpc_num_macros;
325 439
440extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
441
442static inline long
443ppc_optional_operand_value (const struct powerpc_operand *operand)
444{
445 if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
446 return (operand+1)->shift;
447 return 0;
448}
449
450#ifdef __cplusplus
451}
452#endif
453
326#endif /* PPC_H */ 454#endif /* PPC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 10:17:46 -0400