Merge tag 'v4.7-rockchip-clk-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes

A bunch of fixes. Some for the newly added rk3399 clock tree, some
concerning error handling and initialization and a revert of the
mmc-phase clock initialization, as this could conflict with the
bootloader setting of this clock and a real solution to initing
the phase correctly from dw_mmc went in as fix for 4.7 through
the mmc tree.

* tag 'v4.7-rockchip-clk-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: release io resource when failing to init clk on rk3399
  clk: rockchip: fix cpuclk registration error handling
  clk: rockchip: Revert "clk: rockchip: reset init state before mmc card initialization"
  clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src
  clk: rockchip: mark rk3399 GIC clocks as critical
  clk: rockchip: initialize flags of clk_init_data in mmc-phase clock

3 files changed, 9 insertions, 15 deletions

diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index 4bb130cd0062..05b3d73bfefa 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -321,9 +321,9 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
         }
 
         cclk = clk_register(NULL, &cpuclk->hw);
-        if (IS_ERR(clk)) {
+        if (IS_ERR(cclk)) {
                 pr_err("%s: could not register cpuclk %s\n", __func__,  name);
-                ret = PTR_ERR(clk);
+                ret = PTR_ERR(cclk);
                 goto free_rate_table;
         }
 
diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c
index bc856f21f6b2..077fcdc7908b 100644
--- a/drivers/clk/rockchip/clk-mmc-phase.c
+++ b/drivers/clk/rockchip/clk-mmc-phase.c
@@ -41,8 +41,6 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
 #define ROCKCHIP_MMC_DEGREE_MASK 0x3
 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
-#define ROCKCHIP_MMC_INIT_STATE_RESET 0x1
-#define ROCKCHIP_MMC_INIT_STATE_SHIFT 1
 
 #define PSECS_PER_SEC 1000000000000LL
 
@@ -154,6 +152,7 @@ struct clk *rockchip_clk_register_mmc(const char *name,
                 return ERR_PTR(-ENOMEM);
 
         init.name = name;
+        init.flags = 0;
         init.num_parents = num_parents;
         init.parent_names = parent_names;
         init.ops = &rockchip_mmc_clk_ops;
@@ -162,15 +161,6 @@ struct clk *rockchip_clk_register_mmc(const char *name,
         mmc_clock->reg = reg;
         mmc_clock->shift = shift;
 
-        /*
-         * Assert init_state to soft reset the CLKGEN
-         * for mmc tuning phase and degree
-         */
-        if (mmc_clock->shift == ROCKCHIP_MMC_INIT_STATE_SHIFT)
-                writel(HIWORD_UPDATE(ROCKCHIP_MMC_INIT_STATE_RESET,
-                                     ROCKCHIP_MMC_INIT_STATE_RESET,
-                                     mmc_clock->shift), mmc_clock->reg);
-
         clk = clk_register(NULL, &mmc_clock->hw);
         if (IS_ERR(clk))
                 kfree(mmc_clock);
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 291543f52caa..8059a8d3ea36 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -832,9 +832,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                         RK3399_CLKGATE_CON(13), 1, GFLAGS),
 
         /* perihp */
-        GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
+        GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
                         RK3399_CLKGATE_CON(5), 0, GFLAGS),
-        GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
+        GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
                         RK3399_CLKGATE_CON(5), 1, GFLAGS),
         COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
                         RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
@@ -1466,6 +1466,8 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
 
 static const char *const rk3399_cru_critical_clocks[] __initconst = {
         "aclk_cci_pre",
+        "aclk_gic",
+        "aclk_gic_noc",
         "pclk_perilp0",
         "pclk_perilp0",
         "hclk_perilp0",
@@ -1508,6 +1510,7 @@ static void __init rk3399_clk_init(struct device_node *np)
         ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
         if (IS_ERR(ctx)) {
                 pr_err("%s: rockchip clk init failed\n", __func__);
+                iounmap(reg_base);
                 return;
         }
 
@@ -1553,6 +1556,7 @@ static void __init rk3399_pmu_clk_init(struct device_node *np)
         ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
         if (IS_ERR(ctx)) {
                 pr_err("%s: rockchip pmu clk init failed\n", __func__);
+                iounmap(reg_base);
                 return;
         }