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authorLinus Torvalds <torvalds@linux-foundation.org>2016-07-31 21:36:58 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-07-31 21:36:58 -0400
commit07f00f06ba9a5533d6650d46d3e938f6cbeee97e (patch)
tree854142fbef263efe8c5b3e9d7450cb44b7fb84c6
parent27acbec338113a75b9d72aeb53149a3538031dda (diff)
parent6ea6257945188ff7f5d1670d5adc964ac78c590c (diff)
Merge tag 'mmc-v4.8' of git://git.linaro.org/people/ulf.hansson/mmc
Pull MMC updates from Ulf Hansson: "MMC core: - A couple of changes to improve the support for erase/discard/trim cmds - Add eMMC HS400 enhanced strobe support - Show OCR and DSR registers in SYSFS for MMC/SD cards - Correct and improve busy detection logic for MMC switch (CMD6) cmds - Disable HPI cmds for certain broken Hynix eMMC cards - Allow MMC hosts to specify non-support for SD and MMC cmds - Some minor additional fixes MMC host: - sdhci: Re-works, fixes and clean-ups - sdhci: Add HW auto re-tuning support - sdhci: Re-factor code to prepare for adding support for eMMC CMDQ - sdhci-esdhc-imx: Fixes and clean-ups - sdhci-esdhc-imx: Update system PM support - sdhci-esdhc-imx: Enable HW auto re-tuning - sdhci-bcm2835: Remove driver as sdhci-iproc is used instead - sdhci-brcmstb: Add new driver for Broadcom BRCMSTB SoCs - sdhci-msm: Add support for UHS cards - sdhci-tegra: Improve support for UHS cards - sdhci-of-arasan: Update phy support for Rockchip SoCs - sdhci-of-arasan: Deploy enhanced strobe support - dw_mmc: Some fixes and clean-ups - dw_mmc: Enable support for erase/discard/trim cmds - dw_mmc: Enable CMD23 support - mediatek: Some fixes related to the eMMC HS400 support - sh_mmcif: Improve support for HW busy detection - rtsx_pci: Enable support for erase/discard/trim cmds" * tag 'mmc-v4.8' of git://git.linaro.org/people/ulf.hansson/mmc: (135 commits) mmc: rtsx_pci: Remove deprecated create_singlethread_workqueue mmc: rtsx_pci: Enable MMC_CAP_ERASE to allow erase/discard/trim requests mmc: rtsx_pci: Use the provided busy timeout from the mmc core mmc: sdhci-pltfm: Drop define for SDHCI_PLTFM_PMOPS mmc: sdhci-pltfm: Convert to use the SET_SYSTEM_SLEEP_PM_OPS mmc: sdhci-pltfm: Make sdhci_pltfm_suspend|resume() static mmc: sdhci-esdhc-imx: Use common sdhci_suspend|resume_host() mmc: sdhci-esdhc-imx: Assign system PM ops within #ifdef CONFIG_PM_SLEEP mmc: sdhci-sirf: Remove non needed #ifdef CONFIG_PM* for dev_pm_ops mmc: sdhci-s3c: Remove non needed #ifdef CONFIG_PM for dev_pm_ops mmc: sdhci-pxav3: Remove non needed #ifdef CONFIG_PM for dev_pm_ops mmc: sdhci-of-esdhc: Simplify code by using SIMPLE_DEV_PM_OPS mmc: sdhci-acpi: Simplify code by using SET_SYSTEM_SLEEP_PM_OPS mmc: sdhci-pci-core: Simplify code by using SET_SYSTEM_SLEEP_PM_OPS mmc: Change the max discard sectors and erase response when HW busy detect phy: rockchip-emmc: Wait even longer for the DLL to lock phy: rockchip-emmc: Be tolerant to card clock of 0 in power on mmc: sdhci-of-arasan: Revert: Always power the PHY off/on when clock changes mmc: sdhci-msm: Add support for UHS cards mmc: sdhci-msm: Add set_uhs_signaling() implementation ...
-rw-r--r--Documentation/devicetree/bindings/mmc/arasan,sdhci.txt35
-rw-r--r--Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhci.txt18
-rw-r--r--Documentation/devicetree/bindings/mmc/brcm,bcm7425-sdhci.txt36
-rw-r--r--Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt2
-rw-r--r--Documentation/devicetree/bindings/mmc/mmc.txt4
-rw-r--r--Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt9
-rw-r--r--Documentation/mmc/mmc-dev-attrs.txt2
-rw-r--r--MAINTAINERS8
-rw-r--r--drivers/mmc/card/block.c13
-rw-r--r--drivers/mmc/core/bus.c3
-rw-r--r--drivers/mmc/core/core.c95
-rw-r--r--drivers/mmc/core/debugfs.c3
-rw-r--r--drivers/mmc/core/host.c8
-rw-r--r--drivers/mmc/core/mmc.c253
-rw-r--r--drivers/mmc/core/mmc_ops.c27
-rw-r--r--drivers/mmc/core/quirks.c2
-rw-r--r--drivers/mmc/core/sd.c19
-rw-r--r--drivers/mmc/host/Kconfig22
-rw-r--r--drivers/mmc/host/Makefile2
-rw-r--r--drivers/mmc/host/dw_mmc-exynos.c2
-rw-r--r--drivers/mmc/host/dw_mmc-k3.c7
-rw-r--r--drivers/mmc/host/dw_mmc-rockchip.c11
-rw-r--r--drivers/mmc/host/dw_mmc.c126
-rw-r--r--drivers/mmc/host/dw_mmc.h10
-rw-r--r--drivers/mmc/host/mtk-sd.c70
-rw-r--r--drivers/mmc/host/mxcmmc.c2
-rw-r--r--drivers/mmc/host/rtsx_pci_sdmmc.c16
-rw-r--r--drivers/mmc/host/s3cmci.c2
-rw-r--r--drivers/mmc/host/s3cmci.h2
-rw-r--r--drivers/mmc/host/sdhci-acpi.c8
-rw-r--r--drivers/mmc/host/sdhci-bcm-kona.c8
-rw-r--r--drivers/mmc/host/sdhci-bcm2835.c204
-rw-r--r--drivers/mmc/host/sdhci-brcmstb.c143
-rw-r--r--drivers/mmc/host/sdhci-cns3xxx.c2
-rw-r--r--drivers/mmc/host/sdhci-dove.c2
-rw-r--r--drivers/mmc/host/sdhci-esdhc-imx.c153
-rw-r--r--drivers/mmc/host/sdhci-iproc.c15
-rw-r--r--drivers/mmc/host/sdhci-msm.c117
-rw-r--r--drivers/mmc/host/sdhci-of-arasan.c332
-rw-r--r--drivers/mmc/host/sdhci-of-at91.c2
-rw-r--r--drivers/mmc/host/sdhci-of-esdhc.c16
-rw-r--r--drivers/mmc/host/sdhci-of-hlwd.c2
-rw-r--r--drivers/mmc/host/sdhci-pci-core.c83
-rw-r--r--drivers/mmc/host/sdhci-pci.h2
-rw-r--r--drivers/mmc/host/sdhci-pltfm.c13
-rw-r--r--drivers/mmc/host/sdhci-pltfm.h7
-rw-r--r--drivers/mmc/host/sdhci-pxav2.c2
-rw-r--r--drivers/mmc/host/sdhci-pxav3.c9
-rw-r--r--drivers/mmc/host/sdhci-s3c.c9
-rw-r--r--drivers/mmc/host/sdhci-sirf.c4
-rw-r--r--drivers/mmc/host/sdhci-st.c2
-rw-r--r--drivers/mmc/host/sdhci-tegra.c51
-rw-r--r--drivers/mmc/host/sdhci.c745
-rw-r--r--drivers/mmc/host/sdhci.h30
-rw-r--r--drivers/mmc/host/sdhci_f_sdh30.c2
-rw-r--r--drivers/mmc/host/sh_mmcif.c53
-rw-r--r--drivers/mmc/host/sh_mobile_sdhi.c14
-rw-r--r--drivers/mmc/host/tmio_mmc.h2
-rw-r--r--drivers/mmc/host/tmio_mmc_pio.c2
-rw-r--r--drivers/phy/phy-rockchip-emmc.c241
-rw-r--r--include/linux/mmc/card.h36
-rw-r--r--include/linux/mmc/dw_mmc.h9
-rw-r--r--include/linux/mmc/host.h14
-rw-r--r--include/linux/mmc/mmc.h3
-rw-r--r--include/linux/platform_data/mmc-esdhc-imx.h1
65 files changed, 2127 insertions, 1020 deletions
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 31b35c3a5e47..3404afa9b938 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -9,8 +9,12 @@ Device Tree Bindings for the Arasan SDHCI Controller
9 [4] Documentation/devicetree/bindings/phy/phy-bindings.txt 9 [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
10 10
11Required Properties: 11Required Properties:
12 - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or 12 - compatible: Compatibility string. One of:
13 'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1' 13 - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
14 - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
15 - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
16 - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
17 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
14 - reg: From mmc bindings: Register location and length. 18 - reg: From mmc bindings: Register location and length.
15 - clocks: From clock bindings: Handles to clock inputs. 19 - clocks: From clock bindings: Handles to clock inputs.
16 - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" 20 - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
@@ -22,6 +26,17 @@ Required Properties for "arasan,sdhci-5.1":
22 - phys: From PHY bindings: Phandle for the Generic PHY for arasan. 26 - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
23 - phy-names: MUST be "phy_arasan". 27 - phy-names: MUST be "phy_arasan".
24 28
29Optional Properties:
30 - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
31 used to access core corecfg registers. Offsets of registers in this
32 syscon are determined based on the main compatible string for the device.
33 - clock-output-names: If specified, this will be the name of the card clock
34 which will be exposed by this device. Required if #clock-cells is
35 specified.
36 - #clock-cells: If specified this should be the value <0>. With this property
37 in place we will export a clock representing the Card Clock. This clock
38 is expected to be consumed by our PHY. You must also specify
39
25Example: 40Example:
26 sdhci@e0100000 { 41 sdhci@e0100000 {
27 compatible = "arasan,sdhci-8.9a"; 42 compatible = "arasan,sdhci-8.9a";
@@ -42,3 +57,19 @@ Example:
42 phys = <&emmc_phy>; 57 phys = <&emmc_phy>;
43 phy-names = "phy_arasan"; 58 phy-names = "phy_arasan";
44 } ; 59 } ;
60
61 sdhci: sdhci@fe330000 {
62 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
63 reg = <0x0 0xfe330000 0x0 0x10000>;
64 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
65 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
66 clock-names = "clk_xin", "clk_ahb";
67 arasan,soc-ctl-syscon = <&grf>;
68 assigned-clocks = <&cru SCLK_EMMC>;
69 assigned-clock-rates = <200000000>;
70 clock-output-names = "emmc_cardclock";
71 phys = <&emmc_phy>;
72 phy-names = "phy_arasan";
73 #clock-cells = <0>;
74 status = "disabled";
75 };
diff --git a/Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhci.txt b/Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhci.txt
deleted file mode 100644
index 59476fbdbfa1..000000000000
--- a/Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhci.txt
+++ /dev/null
@@ -1,18 +0,0 @@
1Broadcom BCM2835 SDHCI controller
2
3This file documents differences between the core properties described
4by mmc.txt and the properties that represent the BCM2835 controller.
5
6Required properties:
7- compatible : Should be "brcm,bcm2835-sdhci".
8- clocks : The clock feeding the SDHCI controller.
9
10Example:
11
12sdhci: sdhci {
13 compatible = "brcm,bcm2835-sdhci";
14 reg = <0x7e300000 0x100>;
15 interrupts = <2 30>;
16 clocks = <&clk_mmc>;
17 bus-width = <4>;
18};
diff --git a/Documentation/devicetree/bindings/mmc/brcm,bcm7425-sdhci.txt b/Documentation/devicetree/bindings/mmc/brcm,bcm7425-sdhci.txt
new file mode 100644
index 000000000000..82847174c37d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/brcm,bcm7425-sdhci.txt
@@ -0,0 +1,36 @@
1* BROADCOM BRCMSTB/BMIPS SDHCI Controller
2
3This file documents differences between the core properties in mmc.txt
4and the properties used by the sdhci-brcmstb driver.
5
6NOTE: The driver disables all UHS speed modes by default and depends
7on Device Tree properties to enable them for SoC/Board combinations
8that support them.
9
10Required properties:
11- compatible: "brcm,bcm7425-sdhci"
12
13Refer to clocks/clock-bindings.txt for generic clock consumer properties.
14
15Example:
16
17 sdhci@f03e0100 {
18 compatible = "brcm,bcm7425-sdhci";
19 reg = <0xf03e0000 0x100>;
20 interrupts = <0x0 0x26 0x0>;
21 sdhci,auto-cmd12;
22 clocks = <&sw_sdio>;
23 sd-uhs-sdr50;
24 sd-uhs-ddr50;
25 };
26
27 sdhci@f03e0300 {
28 non-removable;
29 bus-width = <0x8>;
30 compatible = "brcm,bcm7425-sdhci";
31 reg = <0xf03e0200 0x100>;
32 interrupts = <0x0 0x27 0x0>;
33 sdhci,auto-cmd12;
34 clocks = <sw_sdio>;
35 mmc-hs200-1_8v;
36 };
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
index dca56d6248f5..3e29050ec769 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
@@ -28,6 +28,8 @@ Optional properties:
28 transparent level shifters on the outputs of the controller. Two cells are 28 transparent level shifters on the outputs of the controller. Two cells are
29 required, first cell specifies minimum slot voltage (mV), second cell 29 required, first cell specifies minimum slot voltage (mV), second cell
30 specifies maximum slot voltage (mV). Several ranges could be specified. 30 specifies maximum slot voltage (mV). Several ranges could be specified.
31- fsl,tuning-start-tap: Specify the start dealy cell point when send first CMD19
32 in tuning procedure.
31- fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure. 33- fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure.
32 The uSDHC use one delay cell as default increasing step to do tuning process. 34 The uSDHC use one delay cell as default increasing step to do tuning process.
33 This property allows user to change the tuning step to more than one delay 35 This property allows user to change the tuning step to more than one delay
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt
index ed23b9bedfdc..22d1e1f3f38b 100644
--- a/Documentation/devicetree/bindings/mmc/mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/mmc.txt
@@ -46,8 +46,12 @@ Optional properties:
46- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported 46- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported
47- mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported 47- mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported
48- mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported 48- mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported
49- mmc-hs400-enhanced-strobe: eMMC HS400 enhanced strobe mode is supported
49- dsr: Value the card's (optional) Driver Stage Register (DSR) should be 50- dsr: Value the card's (optional) Driver Stage Register (DSR) should be
50 programmed with. Valid range: [0 .. 0xffff]. 51 programmed with. Valid range: [0 .. 0xffff].
52- no-sdio: controller is limited to send sdio cmd during initialization
53- no-sd: controller is limited to send sd cmd during initialization
54- no-mmc: controller is limited to send mmc cmd during initialization
51 55
52*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line 56*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
53polarity properties, we have to fix the meaning of the "normal" and "inverted" 57polarity properties, we have to fix the meaning of the "normal" and "inverted"
diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
index 555cb0f40690..e3ea55763b0a 100644
--- a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
@@ -7,6 +7,13 @@ Required properties:
7 - reg: PHY register address offset and length in "general 7 - reg: PHY register address offset and length in "general
8 register files" 8 register files"
9 9
10Optional clocks using the clock bindings (see ../clock/clock-bindings.txt),
11specified by name:
12 - clock-names: Should contain "emmcclk". Although this is listed as optional
13 (because most boards can get basic functionality without having
14 access to it), it is strongly suggested.
15 - clocks: Should have a phandle to the card clock exported by the SDHCI driver.
16
10Example: 17Example:
11 18
12 19
@@ -20,6 +27,8 @@ grf: syscon@ff770000 {
20 emmcphy: phy@f780 { 27 emmcphy: phy@f780 {
21 compatible = "rockchip,rk3399-emmc-phy"; 28 compatible = "rockchip,rk3399-emmc-phy";
22 reg = <0xf780 0x20>; 29 reg = <0xf780 0x20>;
30 clocks = <&sdhci>;
31 clock-names = "emmcclk";
23 #phy-cells = <0>; 32 #phy-cells = <0>;
24 }; 33 };
25}; 34};
diff --git a/Documentation/mmc/mmc-dev-attrs.txt b/Documentation/mmc/mmc-dev-attrs.txt
index caa555706f89..404a0e9e92b0 100644
--- a/Documentation/mmc/mmc-dev-attrs.txt
+++ b/Documentation/mmc/mmc-dev-attrs.txt
@@ -28,6 +28,8 @@ All attributes are read-only.
28 preferred_erase_size Preferred erase size 28 preferred_erase_size Preferred erase size
29 raw_rpmb_size_mult RPMB partition size 29 raw_rpmb_size_mult RPMB partition size
30 rel_sectors Reliable write sector count 30 rel_sectors Reliable write sector count
31 ocr Operation Conditions Register
32 dsr Driver Stage Register
31 33
32Note on Erase Size and Preferred Erase Size: 34Note on Erase Size and Preferred Erase Size:
33 35
diff --git a/MAINTAINERS b/MAINTAINERS
index 0868ea5de465..72f77035c562 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7863,6 +7863,7 @@ M: Ulf Hansson <ulf.hansson@linaro.org>
7863L: linux-mmc@vger.kernel.org 7863L: linux-mmc@vger.kernel.org
7864T: git git://git.linaro.org/people/ulf.hansson/mmc.git 7864T: git git://git.linaro.org/people/ulf.hansson/mmc.git
7865S: Maintained 7865S: Maintained
7866F: Documentation/devicetree/bindings/mmc/
7866F: drivers/mmc/ 7867F: drivers/mmc/
7867F: include/linux/mmc/ 7868F: include/linux/mmc/
7868F: include/uapi/linux/mmc/ 7869F: include/uapi/linux/mmc/
@@ -10355,6 +10356,13 @@ F: tools/testing/selftests/seccomp/*
10355K: \bsecure_computing 10356K: \bsecure_computing
10356K: \bTIF_SECCOMP\b 10357K: \bTIF_SECCOMP\b
10357 10358
10359SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) Broadcom BRCMSTB DRIVER
10360M: Al Cooper <alcooperx@gmail.com>
10361L: linux-mmc@vger.kernel.org
10362L: bcm-kernel-feedback-list@broadcom.com
10363S: Maintained
10364F: drivers/mmc/host/sdhci-brcmstb*
10365
10358SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) SAMSUNG DRIVER 10366SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) SAMSUNG DRIVER
10359M: Ben Dooks <ben-linux@fluff.org> 10367M: Ben Dooks <ben-linux@fluff.org>
10360M: Jaehoon Chung <jh80.chung@samsung.com> 10368M: Jaehoon Chung <jh80.chung@samsung.com>
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index 10b553765ee7..48a5dd740f3b 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -1801,8 +1801,7 @@ static void mmc_blk_packed_hdr_wrq_prep(struct mmc_queue_req *mqrq,
1801 do_data_tag = (card->ext_csd.data_tag_unit_size) && 1801 do_data_tag = (card->ext_csd.data_tag_unit_size) &&
1802 (prq->cmd_flags & REQ_META) && 1802 (prq->cmd_flags & REQ_META) &&
1803 (rq_data_dir(prq) == WRITE) && 1803 (rq_data_dir(prq) == WRITE) &&
1804 ((brq->data.blocks * brq->data.blksz) >= 1804 blk_rq_bytes(prq) >= card->ext_csd.data_tag_unit_size;
1805 card->ext_csd.data_tag_unit_size);
1806 /* Argument of CMD23 */ 1805 /* Argument of CMD23 */
1807 packed_cmd_hdr[(i * 2)] = cpu_to_le32( 1806 packed_cmd_hdr[(i * 2)] = cpu_to_le32(
1808 (do_rel_wr ? MMC_CMD23_ARG_REL_WR : 0) | 1807 (do_rel_wr ? MMC_CMD23_ARG_REL_WR : 0) |
@@ -1977,8 +1976,8 @@ static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *rqc)
1977 * When 4KB native sector is enabled, only 8 blocks 1976 * When 4KB native sector is enabled, only 8 blocks
1978 * multiple read or write is allowed 1977 * multiple read or write is allowed
1979 */ 1978 */
1980 if ((brq->data.blocks & 0x07) && 1979 if (mmc_large_sector(card) &&
1981 (card->ext_csd.data_sector_size == 4096)) { 1980 !IS_ALIGNED(blk_rq_sectors(rqc), 8)) {
1982 pr_err("%s: Transfer size is not 4KB sector size aligned\n", 1981 pr_err("%s: Transfer size is not 4KB sector size aligned\n",
1983 req->rq_disk->disk_name); 1982 req->rq_disk->disk_name);
1984 mq_rq = mq->mqrq_cur; 1983 mq_rq = mq->mqrq_cur;
@@ -2501,12 +2500,6 @@ force_ro_fail:
2501 return ret; 2500 return ret;
2502} 2501}
2503 2502
2504#define CID_MANFID_SANDISK 0x2
2505#define CID_MANFID_TOSHIBA 0x11
2506#define CID_MANFID_MICRON 0x13
2507#define CID_MANFID_SAMSUNG 0x15
2508#define CID_MANFID_KINGSTON 0x70
2509
2510static const struct mmc_fixup blk_fixups[] = 2503static const struct mmc_fixup blk_fixups[] =
2511{ 2504{
2512 MMC_FIXUP("SEM02G", CID_MANFID_SANDISK, 0x100, add_quirk, 2505 MMC_FIXUP("SEM02G", CID_MANFID_SANDISK, 0x100, add_quirk,
diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c
index 4bc48f10452f..c64266f5a399 100644
--- a/drivers/mmc/core/bus.c
+++ b/drivers/mmc/core/bus.c
@@ -332,12 +332,13 @@ int mmc_add_card(struct mmc_card *card)
332 mmc_card_ddr52(card) ? "DDR " : "", 332 mmc_card_ddr52(card) ? "DDR " : "",
333 type); 333 type);
334 } else { 334 } else {
335 pr_info("%s: new %s%s%s%s%s card at address %04x\n", 335 pr_info("%s: new %s%s%s%s%s%s card at address %04x\n",
336 mmc_hostname(card->host), 336 mmc_hostname(card->host),
337 mmc_card_uhs(card) ? "ultra high speed " : 337 mmc_card_uhs(card) ? "ultra high speed " :
338 (mmc_card_hs(card) ? "high speed " : ""), 338 (mmc_card_hs(card) ? "high speed " : ""),
339 mmc_card_hs400(card) ? "HS400 " : 339 mmc_card_hs400(card) ? "HS400 " :
340 (mmc_card_hs200(card) ? "HS200 " : ""), 340 (mmc_card_hs200(card) ? "HS200 " : ""),
341 mmc_card_hs400es(card) ? "Enhanced strobe " : "",
341 mmc_card_ddr52(card) ? "DDR " : "", 342 mmc_card_ddr52(card) ? "DDR " : "",
342 uhs_bus_speed_mode, type, card->rca); 343 uhs_bus_speed_mode, type, card->rca);
343 } 344 }
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 8b4dfd45433b..e55cde6d436d 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -1127,6 +1127,15 @@ void mmc_set_initial_state(struct mmc_host *host)
1127 host->ios.bus_width = MMC_BUS_WIDTH_1; 1127 host->ios.bus_width = MMC_BUS_WIDTH_1;
1128 host->ios.timing = MMC_TIMING_LEGACY; 1128 host->ios.timing = MMC_TIMING_LEGACY;
1129 host->ios.drv_type = 0; 1129 host->ios.drv_type = 0;
1130 host->ios.enhanced_strobe = false;
1131
1132 /*
1133 * Make sure we are in non-enhanced strobe mode before we
1134 * actually enable it in ext_csd.
1135 */
1136 if ((host->caps2 & MMC_CAP2_HS400_ES) &&
1137 host->ops->hs400_enhanced_strobe)
1138 host->ops->hs400_enhanced_strobe(host, &host->ios);
1130 1139
1131 mmc_set_ios(host); 1140 mmc_set_ios(host);
1132} 1141}
@@ -1925,17 +1934,15 @@ void mmc_init_erase(struct mmc_card *card)
1925 * to that size and alignment. 1934 * to that size and alignment.
1926 * 1935 *
1927 * For SD cards that define Allocation Unit size, limit erases to one 1936 * For SD cards that define Allocation Unit size, limit erases to one
1928 * Allocation Unit at a time. For MMC cards that define High Capacity 1937 * Allocation Unit at a time.
1929 * Erase Size, whether it is switched on or not, limit to that size. 1938 * For MMC, have a stab at ai good value and for modern cards it will
1930 * Otherwise just have a stab at a good value. For modern cards it 1939 * end up being 4MiB. Note that if the value is too small, it can end
1931 * will end up being 4MiB. Note that if the value is too small, it 1940 * up taking longer to erase. Also note, erase_size is already set to
1932 * can end up taking longer to erase. 1941 * High Capacity Erase Size if available when this function is called.
1933 */ 1942 */
1934 if (mmc_card_sd(card) && card->ssr.au) { 1943 if (mmc_card_sd(card) && card->ssr.au) {
1935 card->pref_erase = card->ssr.au; 1944 card->pref_erase = card->ssr.au;
1936 card->erase_shift = ffs(card->ssr.au) - 1; 1945 card->erase_shift = ffs(card->ssr.au) - 1;
1937 } else if (card->ext_csd.hc_erase_size) {
1938 card->pref_erase = card->ext_csd.hc_erase_size;
1939 } else if (card->erase_size) { 1946 } else if (card->erase_size) {
1940 sz = (card->csd.capacity << (card->csd.read_blkbits - 9)) >> 11; 1947 sz = (card->csd.capacity << (card->csd.read_blkbits - 9)) >> 11;
1941 if (sz < 128) 1948 if (sz < 128)
@@ -2060,7 +2067,8 @@ static int mmc_do_erase(struct mmc_card *card, unsigned int from,
2060 unsigned int to, unsigned int arg) 2067 unsigned int to, unsigned int arg)
2061{ 2068{
2062 struct mmc_command cmd = {0}; 2069 struct mmc_command cmd = {0};
2063 unsigned int qty = 0; 2070 unsigned int qty = 0, busy_timeout = 0;
2071 bool use_r1b_resp = false;
2064 unsigned long timeout; 2072 unsigned long timeout;
2065 int err; 2073 int err;
2066 2074
@@ -2128,8 +2136,22 @@ static int mmc_do_erase(struct mmc_card *card, unsigned int from,
2128 memset(&cmd, 0, sizeof(struct mmc_command)); 2136 memset(&cmd, 0, sizeof(struct mmc_command));
2129 cmd.opcode = MMC_ERASE; 2137 cmd.opcode = MMC_ERASE;
2130 cmd.arg = arg; 2138 cmd.arg = arg;
2131 cmd.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC; 2139 busy_timeout = mmc_erase_timeout(card, arg, qty);
2132 cmd.busy_timeout = mmc_erase_timeout(card, arg, qty); 2140 /*
2141 * If the host controller supports busy signalling and the timeout for
2142 * the erase operation does not exceed the max_busy_timeout, we should
2143 * use R1B response. Or we need to prevent the host from doing hw busy
2144 * detection, which is done by converting to a R1 response instead.
2145 */
2146 if (card->host->max_busy_timeout &&
2147 busy_timeout > card->host->max_busy_timeout) {
2148 cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
2149 } else {
2150 cmd.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
2151 cmd.busy_timeout = busy_timeout;
2152 use_r1b_resp = true;
2153 }
2154
2133 err = mmc_wait_for_cmd(card->host, &cmd, 0); 2155 err = mmc_wait_for_cmd(card->host, &cmd, 0);
2134 if (err) { 2156 if (err) {
2135 pr_err("mmc_erase: erase error %d, status %#x\n", 2157 pr_err("mmc_erase: erase error %d, status %#x\n",
@@ -2141,7 +2163,14 @@ static int mmc_do_erase(struct mmc_card *card, unsigned int from,
2141 if (mmc_host_is_spi(card->host)) 2163 if (mmc_host_is_spi(card->host))
2142 goto out; 2164 goto out;
2143 2165
2144 timeout = jiffies + msecs_to_jiffies(MMC_CORE_TIMEOUT_MS); 2166 /*
2167 * In case of when R1B + MMC_CAP_WAIT_WHILE_BUSY is used, the polling
2168 * shall be avoided.
2169 */
2170 if ((card->host->caps & MMC_CAP_WAIT_WHILE_BUSY) && use_r1b_resp)
2171 goto out;
2172
2173 timeout = jiffies + msecs_to_jiffies(busy_timeout);
2145 do { 2174 do {
2146 memset(&cmd, 0, sizeof(struct mmc_command)); 2175 memset(&cmd, 0, sizeof(struct mmc_command));
2147 cmd.opcode = MMC_SEND_STATUS; 2176 cmd.opcode = MMC_SEND_STATUS;
@@ -2321,23 +2350,41 @@ static unsigned int mmc_do_calc_max_discard(struct mmc_card *card,
2321 unsigned int arg) 2350 unsigned int arg)
2322{ 2351{
2323 struct mmc_host *host = card->host; 2352 struct mmc_host *host = card->host;
2324 unsigned int max_discard, x, y, qty = 0, max_qty, timeout; 2353 unsigned int max_discard, x, y, qty = 0, max_qty, min_qty, timeout;
2325 unsigned int last_timeout = 0; 2354 unsigned int last_timeout = 0;
2326 2355
2327 if (card->erase_shift) 2356 if (card->erase_shift) {
2328 max_qty = UINT_MAX >> card->erase_shift; 2357 max_qty = UINT_MAX >> card->erase_shift;
2329 else if (mmc_card_sd(card)) 2358 min_qty = card->pref_erase >> card->erase_shift;
2359 } else if (mmc_card_sd(card)) {
2330 max_qty = UINT_MAX; 2360 max_qty = UINT_MAX;
2331 else 2361 min_qty = card->pref_erase;
2362 } else {
2332 max_qty = UINT_MAX / card->erase_size; 2363 max_qty = UINT_MAX / card->erase_size;
2364 min_qty = card->pref_erase / card->erase_size;
2365 }
2333 2366
2334 /* Find the largest qty with an OK timeout */ 2367 /*
2368 * We should not only use 'host->max_busy_timeout' as the limitation
2369 * when deciding the max discard sectors. We should set a balance value
2370 * to improve the erase speed, and it can not get too long timeout at
2371 * the same time.
2372 *
2373 * Here we set 'card->pref_erase' as the minimal discard sectors no
2374 * matter what size of 'host->max_busy_timeout', but if the
2375 * 'host->max_busy_timeout' is large enough for more discard sectors,
2376 * then we can continue to increase the max discard sectors until we
2377 * get a balance value.
2378 */
2335 do { 2379 do {
2336 y = 0; 2380 y = 0;
2337 for (x = 1; x && x <= max_qty && max_qty - x >= qty; x <<= 1) { 2381 for (x = 1; x && x <= max_qty && max_qty - x >= qty; x <<= 1) {
2338 timeout = mmc_erase_timeout(card, arg, qty + x); 2382 timeout = mmc_erase_timeout(card, arg, qty + x);
2339 if (timeout > host->max_busy_timeout) 2383
2384 if (qty + x > min_qty &&
2385 timeout > host->max_busy_timeout)
2340 break; 2386 break;
2387
2341 if (timeout < last_timeout) 2388 if (timeout < last_timeout)
2342 break; 2389 break;
2343 last_timeout = timeout; 2390 last_timeout = timeout;
@@ -2491,17 +2538,21 @@ static int mmc_rescan_try_freq(struct mmc_host *host, unsigned freq)
2491 2538
2492 mmc_go_idle(host); 2539 mmc_go_idle(host);
2493 2540
2494 mmc_send_if_cond(host, host->ocr_avail); 2541 if (!(host->caps2 & MMC_CAP2_NO_SD))
2542 mmc_send_if_cond(host, host->ocr_avail);
2495 2543
2496 /* Order's important: probe SDIO, then SD, then MMC */ 2544 /* Order's important: probe SDIO, then SD, then MMC */
2497 if (!(host->caps2 & MMC_CAP2_NO_SDIO)) 2545 if (!(host->caps2 & MMC_CAP2_NO_SDIO))
2498 if (!mmc_attach_sdio(host)) 2546 if (!mmc_attach_sdio(host))
2499 return 0; 2547 return 0;
2500 2548
2501 if (!mmc_attach_sd(host)) 2549 if (!(host->caps2 & MMC_CAP2_NO_SD))
2502 return 0; 2550 if (!mmc_attach_sd(host))
2503 if (!mmc_attach_mmc(host)) 2551 return 0;
2504 return 0; 2552
2553 if (!(host->caps2 & MMC_CAP2_NO_MMC))
2554 if (!mmc_attach_mmc(host))
2555 return 0;
2505 2556
2506 mmc_power_off(host); 2557 mmc_power_off(host);
2507 return -EIO; 2558 return -EIO;
diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c
index 9382a57a5aa4..c8451ce557ae 100644
--- a/drivers/mmc/core/debugfs.c
+++ b/drivers/mmc/core/debugfs.c
@@ -148,7 +148,8 @@ static int mmc_ios_show(struct seq_file *s, void *data)
148 str = "mmc HS200"; 148 str = "mmc HS200";
149 break; 149 break;
150 case MMC_TIMING_MMC_HS400: 150 case MMC_TIMING_MMC_HS400:
151 str = "mmc HS400"; 151 str = mmc_card_hs400es(host->card) ?
152 "mmc HS400 enhanced strobe" : "mmc HS400";
152 break; 153 break;
153 default: 154 default:
154 str = "invalid"; 155 str = "invalid";
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index 1be42fab1a30..98f25ffb4258 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -313,6 +313,14 @@ int mmc_of_parse(struct mmc_host *host)
313 host->caps2 |= MMC_CAP2_HS400_1_8V | MMC_CAP2_HS200_1_8V_SDR; 313 host->caps2 |= MMC_CAP2_HS400_1_8V | MMC_CAP2_HS200_1_8V_SDR;
314 if (of_property_read_bool(np, "mmc-hs400-1_2v")) 314 if (of_property_read_bool(np, "mmc-hs400-1_2v"))
315 host->caps2 |= MMC_CAP2_HS400_1_2V | MMC_CAP2_HS200_1_2V_SDR; 315 host->caps2 |= MMC_CAP2_HS400_1_2V | MMC_CAP2_HS200_1_2V_SDR;
316 if (of_property_read_bool(np, "mmc-hs400-enhanced-strobe"))
317 host->caps2 |= MMC_CAP2_HS400_ES;
318 if (of_property_read_bool(np, "no-sdio"))
319 host->caps2 |= MMC_CAP2_NO_SDIO;
320 if (of_property_read_bool(np, "no-sd"))
321 host->caps2 |= MMC_CAP2_NO_SD;
322 if (of_property_read_bool(np, "no-mmc"))
323 host->caps2 |= MMC_CAP2_NO_MMC;
316 324
317 host->dsr_req = !of_property_read_u32(np, "dsr", &host->dsr); 325 host->dsr_req = !of_property_read_u32(np, "dsr", &host->dsr);
318 if (host->dsr_req && (host->dsr & ~0xffff)) { 326 if (host->dsr_req && (host->dsr & ~0xffff)) {
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 5d438ad3ee32..f2d185cf8a8b 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -45,6 +45,17 @@ static const unsigned int tacc_mant[] = {
45 35, 40, 45, 50, 55, 60, 70, 80, 45 35, 40, 45, 50, 55, 60, 70, 80,
46}; 46};
47 47
48static const struct mmc_fixup mmc_ext_csd_fixups[] = {
49 /*
50 * Certain Hynix eMMC 4.41 cards might get broken when HPI feature
51 * is used so disable the HPI feature for such buggy cards.
52 */
53 MMC_FIXUP_EXT_CSD_REV(CID_NAME_ANY, CID_MANFID_HYNIX,
54 0x014a, add_quirk, MMC_QUIRK_BROKEN_HPI, 5),
55
56 END_FIXUP
57};
58
48#define UNSTUFF_BITS(resp,start,size) \ 59#define UNSTUFF_BITS(resp,start,size) \
49 ({ \ 60 ({ \
50 const int __size = size; \ 61 const int __size = size; \
@@ -235,6 +246,11 @@ static void mmc_select_card_type(struct mmc_card *card)
235 avail_type |= EXT_CSD_CARD_TYPE_HS400_1_2V; 246 avail_type |= EXT_CSD_CARD_TYPE_HS400_1_2V;
236 } 247 }
237 248
249 if ((caps2 & MMC_CAP2_HS400_ES) &&
250 card->ext_csd.strobe_support &&
251 (avail_type & EXT_CSD_CARD_TYPE_HS400))
252 avail_type |= EXT_CSD_CARD_TYPE_HS400ES;
253
238 card->ext_csd.hs_max_dtr = hs_max_dtr; 254 card->ext_csd.hs_max_dtr = hs_max_dtr;
239 card->ext_csd.hs200_max_dtr = hs200_max_dtr; 255 card->ext_csd.hs200_max_dtr = hs200_max_dtr;
240 card->mmc_avail_type = avail_type; 256 card->mmc_avail_type = avail_type;
@@ -370,6 +386,9 @@ static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd)
370 */ 386 */
371 card->ext_csd.rev = ext_csd[EXT_CSD_REV]; 387 card->ext_csd.rev = ext_csd[EXT_CSD_REV];
372 388
389 /* fixup device after ext_csd revision field is updated */
390 mmc_fixup_device(card, mmc_ext_csd_fixups);
391
373 card->ext_csd.raw_sectors[0] = ext_csd[EXT_CSD_SEC_CNT + 0]; 392 card->ext_csd.raw_sectors[0] = ext_csd[EXT_CSD_SEC_CNT + 0];
374 card->ext_csd.raw_sectors[1] = ext_csd[EXT_CSD_SEC_CNT + 1]; 393 card->ext_csd.raw_sectors[1] = ext_csd[EXT_CSD_SEC_CNT + 1];
375 card->ext_csd.raw_sectors[2] = ext_csd[EXT_CSD_SEC_CNT + 2]; 394 card->ext_csd.raw_sectors[2] = ext_csd[EXT_CSD_SEC_CNT + 2];
@@ -386,6 +405,7 @@ static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd)
386 mmc_card_set_blockaddr(card); 405 mmc_card_set_blockaddr(card);
387 } 406 }
388 407
408 card->ext_csd.strobe_support = ext_csd[EXT_CSD_STROBE_SUPPORT];
389 card->ext_csd.raw_card_type = ext_csd[EXT_CSD_CARD_TYPE]; 409 card->ext_csd.raw_card_type = ext_csd[EXT_CSD_CARD_TYPE];
390 mmc_select_card_type(card); 410 mmc_select_card_type(card);
391 411
@@ -500,7 +520,8 @@ static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd)
500 card->cid.year += 16; 520 card->cid.year += 16;
501 521
502 /* check whether the eMMC card supports BKOPS */ 522 /* check whether the eMMC card supports BKOPS */
503 if (ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1) { 523 if (!mmc_card_broken_hpi(card) &&
524 ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1) {
504 card->ext_csd.bkops = 1; 525 card->ext_csd.bkops = 1;
505 card->ext_csd.man_bkops_en = 526 card->ext_csd.man_bkops_en =
506 (ext_csd[EXT_CSD_BKOPS_EN] & 527 (ext_csd[EXT_CSD_BKOPS_EN] &
@@ -513,7 +534,8 @@ static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd)
513 } 534 }
514 535
515 /* check whether the eMMC card supports HPI */ 536 /* check whether the eMMC card supports HPI */
516 if (!broken_hpi && (ext_csd[EXT_CSD_HPI_FEATURES] & 0x1)) { 537 if (!mmc_card_broken_hpi(card) &&
538 !broken_hpi && (ext_csd[EXT_CSD_HPI_FEATURES] & 0x1)) {
517 card->ext_csd.hpi = 1; 539 card->ext_csd.hpi = 1;
518 if (ext_csd[EXT_CSD_HPI_FEATURES] & 0x2) 540 if (ext_csd[EXT_CSD_HPI_FEATURES] & 0x2)
519 card->ext_csd.hpi_cmd = MMC_STOP_TRANSMISSION; 541 card->ext_csd.hpi_cmd = MMC_STOP_TRANSMISSION;
@@ -727,6 +749,7 @@ MMC_DEV_ATTR(enhanced_area_offset, "%llu\n",
727MMC_DEV_ATTR(enhanced_area_size, "%u\n", card->ext_csd.enhanced_area_size); 749MMC_DEV_ATTR(enhanced_area_size, "%u\n", card->ext_csd.enhanced_area_size);
728MMC_DEV_ATTR(raw_rpmb_size_mult, "%#x\n", card->ext_csd.raw_rpmb_size_mult); 750MMC_DEV_ATTR(raw_rpmb_size_mult, "%#x\n", card->ext_csd.raw_rpmb_size_mult);
729MMC_DEV_ATTR(rel_sectors, "%#x\n", card->ext_csd.rel_sectors); 751MMC_DEV_ATTR(rel_sectors, "%#x\n", card->ext_csd.rel_sectors);
752MMC_DEV_ATTR(ocr, "%08x\n", card->ocr);
730 753
731static ssize_t mmc_fwrev_show(struct device *dev, 754static ssize_t mmc_fwrev_show(struct device *dev,
732 struct device_attribute *attr, 755 struct device_attribute *attr,
@@ -744,6 +767,22 @@ static ssize_t mmc_fwrev_show(struct device *dev,
744 767
745static DEVICE_ATTR(fwrev, S_IRUGO, mmc_fwrev_show, NULL); 768static DEVICE_ATTR(fwrev, S_IRUGO, mmc_fwrev_show, NULL);
746 769
770static ssize_t mmc_dsr_show(struct device *dev,
771 struct device_attribute *attr,
772 char *buf)
773{
774 struct mmc_card *card = mmc_dev_to_card(dev);
775 struct mmc_host *host = card->host;
776
777 if (card->csd.dsr_imp && host->dsr_req)
778 return sprintf(buf, "0x%x\n", host->dsr);
779 else
780 /* return default DSR value */
781 return sprintf(buf, "0x%x\n", 0x404);
782}
783
784static DEVICE_ATTR(dsr, S_IRUGO, mmc_dsr_show, NULL);
785
747static struct attribute *mmc_std_attrs[] = { 786static struct attribute *mmc_std_attrs[] = {
748 &dev_attr_cid.attr, 787 &dev_attr_cid.attr,
749 &dev_attr_csd.attr, 788 &dev_attr_csd.attr,
@@ -762,6 +801,8 @@ static struct attribute *mmc_std_attrs[] = {
762 &dev_attr_enhanced_area_size.attr, 801 &dev_attr_enhanced_area_size.attr,
763 &dev_attr_raw_rpmb_size_mult.attr, 802 &dev_attr_raw_rpmb_size_mult.attr,
764 &dev_attr_rel_sectors.attr, 803 &dev_attr_rel_sectors.attr,
804 &dev_attr_ocr.attr,
805 &dev_attr_dsr.attr,
765 NULL, 806 NULL,
766}; 807};
767ATTRIBUTE_GROUPS(mmc_std); 808ATTRIBUTE_GROUPS(mmc_std);
@@ -959,6 +1000,19 @@ static int mmc_select_bus_width(struct mmc_card *card)
959 return err; 1000 return err;
960} 1001}
961 1002
1003/* Caller must hold re-tuning */
1004static int mmc_switch_status(struct mmc_card *card)
1005{
1006 u32 status;
1007 int err;
1008
1009 err = mmc_send_status(card, &status);
1010 if (err)
1011 return err;
1012
1013 return mmc_switch_status_error(card->host, status);
1014}
1015
962/* 1016/*
963 * Switch to the high-speed mode 1017 * Switch to the high-speed mode
964 */ 1018 */
@@ -969,9 +1023,11 @@ static int mmc_select_hs(struct mmc_card *card)
969 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, 1023 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
970 EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS, 1024 EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS,
971 card->ext_csd.generic_cmd6_time, 1025 card->ext_csd.generic_cmd6_time,
972 true, true, true); 1026 true, false, true);
973 if (!err) 1027 if (!err) {
974 mmc_set_timing(card->host, MMC_TIMING_MMC_HS); 1028 mmc_set_timing(card->host, MMC_TIMING_MMC_HS);
1029 err = mmc_switch_status(card);
1030 }
975 1031
976 return err; 1032 return err;
977} 1033}
@@ -1047,23 +1103,9 @@ static int mmc_select_hs_ddr(struct mmc_card *card)
1047 return err; 1103 return err;
1048} 1104}
1049 1105
1050/* Caller must hold re-tuning */
1051static int mmc_switch_status(struct mmc_card *card)
1052{
1053 u32 status;
1054 int err;
1055
1056 err = mmc_send_status(card, &status);
1057 if (err)
1058 return err;
1059
1060 return mmc_switch_status_error(card->host, status);
1061}
1062
1063static int mmc_select_hs400(struct mmc_card *card) 1106static int mmc_select_hs400(struct mmc_card *card)
1064{ 1107{
1065 struct mmc_host *host = card->host; 1108 struct mmc_host *host = card->host;
1066 bool send_status = true;
1067 unsigned int max_dtr; 1109 unsigned int max_dtr;
1068 int err = 0; 1110 int err = 0;
1069 u8 val; 1111 u8 val;
@@ -1075,19 +1117,12 @@ static int mmc_select_hs400(struct mmc_card *card)
1075 host->ios.bus_width == MMC_BUS_WIDTH_8)) 1117 host->ios.bus_width == MMC_BUS_WIDTH_8))
1076 return 0; 1118 return 0;
1077 1119
1078 if (host->caps & MMC_CAP_WAIT_WHILE_BUSY)
1079 send_status = false;
1080
1081 /* Reduce frequency to HS frequency */
1082 max_dtr = card->ext_csd.hs_max_dtr;
1083 mmc_set_clock(host, max_dtr);
1084
1085 /* Switch card to HS mode */ 1120 /* Switch card to HS mode */
1086 val = EXT_CSD_TIMING_HS; 1121 val = EXT_CSD_TIMING_HS;
1087 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, 1122 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
1088 EXT_CSD_HS_TIMING, val, 1123 EXT_CSD_HS_TIMING, val,
1089 card->ext_csd.generic_cmd6_time, 1124 card->ext_csd.generic_cmd6_time,
1090 true, send_status, true); 1125 true, false, true);
1091 if (err) { 1126 if (err) {
1092 pr_err("%s: switch to high-speed from hs200 failed, err:%d\n", 1127 pr_err("%s: switch to high-speed from hs200 failed, err:%d\n",
1093 mmc_hostname(host), err); 1128 mmc_hostname(host), err);
@@ -1097,11 +1132,13 @@ static int mmc_select_hs400(struct mmc_card *card)
1097 /* Set host controller to HS timing */ 1132 /* Set host controller to HS timing */
1098 mmc_set_timing(card->host, MMC_TIMING_MMC_HS); 1133 mmc_set_timing(card->host, MMC_TIMING_MMC_HS);
1099 1134
1100 if (!send_status) { 1135 /* Reduce frequency to HS frequency */
1101 err = mmc_switch_status(card); 1136 max_dtr = card->ext_csd.hs_max_dtr;
1102 if (err) 1137 mmc_set_clock(host, max_dtr);
1103 goto out_err; 1138
1104 } 1139 err = mmc_switch_status(card);
1140 if (err)
1141 goto out_err;
1105 1142
1106 /* Switch card to DDR */ 1143 /* Switch card to DDR */
1107 err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, 1144 err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
@@ -1120,7 +1157,7 @@ static int mmc_select_hs400(struct mmc_card *card)
1120 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, 1157 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
1121 EXT_CSD_HS_TIMING, val, 1158 EXT_CSD_HS_TIMING, val,
1122 card->ext_csd.generic_cmd6_time, 1159 card->ext_csd.generic_cmd6_time,
1123 true, send_status, true); 1160 true, false, true);
1124 if (err) { 1161 if (err) {
1125 pr_err("%s: switch to hs400 failed, err:%d\n", 1162 pr_err("%s: switch to hs400 failed, err:%d\n",
1126 mmc_hostname(host), err); 1163 mmc_hostname(host), err);
@@ -1131,11 +1168,9 @@ static int mmc_select_hs400(struct mmc_card *card)
1131 mmc_set_timing(host, MMC_TIMING_MMC_HS400); 1168 mmc_set_timing(host, MMC_TIMING_MMC_HS400);
1132 mmc_set_bus_speed(card); 1169 mmc_set_bus_speed(card);
1133 1170
1134 if (!send_status) { 1171 err = mmc_switch_status(card);
1135 err = mmc_switch_status(card); 1172 if (err)
1136 if (err) 1173 goto out_err;
1137 goto out_err;
1138 }
1139 1174
1140 return 0; 1175 return 0;
1141 1176
@@ -1153,14 +1188,10 @@ int mmc_hs200_to_hs400(struct mmc_card *card)
1153int mmc_hs400_to_hs200(struct mmc_card *card) 1188int mmc_hs400_to_hs200(struct mmc_card *card)
1154{ 1189{
1155 struct mmc_host *host = card->host; 1190 struct mmc_host *host = card->host;
1156 bool send_status = true;
1157 unsigned int max_dtr; 1191 unsigned int max_dtr;
1158 int err; 1192 int err;
1159 u8 val; 1193 u8 val;
1160 1194
1161 if (host->caps & MMC_CAP_WAIT_WHILE_BUSY)
1162 send_status = false;
1163
1164 /* Reduce frequency to HS */ 1195 /* Reduce frequency to HS */
1165 max_dtr = card->ext_csd.hs_max_dtr; 1196 max_dtr = card->ext_csd.hs_max_dtr;
1166 mmc_set_clock(host, max_dtr); 1197 mmc_set_clock(host, max_dtr);
@@ -1169,49 +1200,43 @@ int mmc_hs400_to_hs200(struct mmc_card *card)
1169 val = EXT_CSD_TIMING_HS; 1200 val = EXT_CSD_TIMING_HS;
1170 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1201 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
1171 val, card->ext_csd.generic_cmd6_time, 1202 val, card->ext_csd.generic_cmd6_time,
1172 true, send_status, true); 1203 true, false, true);
1173 if (err) 1204 if (err)
1174 goto out_err; 1205 goto out_err;
1175 1206
1176 mmc_set_timing(host, MMC_TIMING_MMC_DDR52); 1207 mmc_set_timing(host, MMC_TIMING_MMC_DDR52);
1177 1208
1178 if (!send_status) { 1209 err = mmc_switch_status(card);
1179 err = mmc_switch_status(card); 1210 if (err)
1180 if (err) 1211 goto out_err;
1181 goto out_err;
1182 }
1183 1212
1184 /* Switch HS DDR to HS */ 1213 /* Switch HS DDR to HS */
1185 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, 1214 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1186 EXT_CSD_BUS_WIDTH_8, card->ext_csd.generic_cmd6_time, 1215 EXT_CSD_BUS_WIDTH_8, card->ext_csd.generic_cmd6_time,
1187 true, send_status, true); 1216 true, false, true);
1188 if (err) 1217 if (err)
1189 goto out_err; 1218 goto out_err;
1190 1219
1191 mmc_set_timing(host, MMC_TIMING_MMC_HS); 1220 mmc_set_timing(host, MMC_TIMING_MMC_HS);
1192 1221
1193 if (!send_status) { 1222 err = mmc_switch_status(card);
1194 err = mmc_switch_status(card); 1223 if (err)
1195 if (err) 1224 goto out_err;
1196 goto out_err;
1197 }
1198 1225
1199 /* Switch HS to HS200 */ 1226 /* Switch HS to HS200 */
1200 val = EXT_CSD_TIMING_HS200 | 1227 val = EXT_CSD_TIMING_HS200 |
1201 card->drive_strength << EXT_CSD_DRV_STR_SHIFT; 1228 card->drive_strength << EXT_CSD_DRV_STR_SHIFT;
1202 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1229 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
1203 val, card->ext_csd.generic_cmd6_time, true, 1230 val, card->ext_csd.generic_cmd6_time,
1204 send_status, true); 1231 true, false, true);
1205 if (err) 1232 if (err)
1206 goto out_err; 1233 goto out_err;
1207 1234
1208 mmc_set_timing(host, MMC_TIMING_MMC_HS200); 1235 mmc_set_timing(host, MMC_TIMING_MMC_HS200);
1209 1236
1210 if (!send_status) { 1237 err = mmc_switch_status(card);
1211 err = mmc_switch_status(card); 1238 if (err)
1212 if (err) 1239 goto out_err;
1213 goto out_err;
1214 }
1215 1240
1216 mmc_set_bus_speed(card); 1241 mmc_set_bus_speed(card);
1217 1242
@@ -1223,6 +1248,78 @@ out_err:
1223 return err; 1248 return err;
1224} 1249}
1225 1250
1251static int mmc_select_hs400es(struct mmc_card *card)
1252{
1253 struct mmc_host *host = card->host;
1254 int err = 0;
1255 u8 val;
1256
1257 if (!(host->caps & MMC_CAP_8_BIT_DATA)) {
1258 err = -ENOTSUPP;
1259 goto out_err;
1260 }
1261
1262 err = mmc_select_bus_width(card);
1263 if (err < 0)
1264 goto out_err;
1265
1266 /* Switch card to HS mode */
1267 err = mmc_select_hs(card);
1268 if (err) {
1269 pr_err("%s: switch to high-speed failed, err:%d\n",
1270 mmc_hostname(host), err);
1271 goto out_err;
1272 }
1273
1274 err = mmc_switch_status(card);
1275 if (err)
1276 goto out_err;
1277
1278 /* Switch card to DDR with strobe bit */
1279 val = EXT_CSD_DDR_BUS_WIDTH_8 | EXT_CSD_BUS_WIDTH_STROBE;
1280 err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
1281 EXT_CSD_BUS_WIDTH,
1282 val,
1283 card->ext_csd.generic_cmd6_time);
1284 if (err) {
1285 pr_err("%s: switch to bus width for hs400es failed, err:%d\n",
1286 mmc_hostname(host), err);
1287 goto out_err;
1288 }
1289
1290 /* Switch card to HS400 */
1291 val = EXT_CSD_TIMING_HS400 |
1292 card->drive_strength << EXT_CSD_DRV_STR_SHIFT;
1293 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
1294 EXT_CSD_HS_TIMING, val,
1295 card->ext_csd.generic_cmd6_time,
1296 true, false, true);
1297 if (err) {
1298 pr_err("%s: switch to hs400es failed, err:%d\n",
1299 mmc_hostname(host), err);
1300 goto out_err;
1301 }
1302
1303 /* Set host controller to HS400 timing and frequency */
1304 mmc_set_timing(host, MMC_TIMING_MMC_HS400);
1305
1306 /* Controller enable enhanced strobe function */
1307 host->ios.enhanced_strobe = true;
1308 if (host->ops->hs400_enhanced_strobe)
1309 host->ops->hs400_enhanced_strobe(host, &host->ios);
1310
1311 err = mmc_switch_status(card);
1312 if (err)
1313 goto out_err;
1314
1315 return 0;
1316
1317out_err:
1318 pr_err("%s: %s failed, error %d\n", mmc_hostname(card->host),
1319 __func__, err);
1320 return err;
1321}
1322
1226static void mmc_select_driver_type(struct mmc_card *card) 1323static void mmc_select_driver_type(struct mmc_card *card)
1227{ 1324{
1228 int card_drv_type, drive_strength, drv_type; 1325 int card_drv_type, drive_strength, drv_type;
@@ -1250,7 +1347,6 @@ static void mmc_select_driver_type(struct mmc_card *card)
1250static int mmc_select_hs200(struct mmc_card *card) 1347static int mmc_select_hs200(struct mmc_card *card)
1251{ 1348{
1252 struct mmc_host *host = card->host; 1349 struct mmc_host *host = card->host;
1253 bool send_status = true;
1254 unsigned int old_timing, old_signal_voltage; 1350 unsigned int old_timing, old_signal_voltage;
1255 int err = -EINVAL; 1351 int err = -EINVAL;
1256 u8 val; 1352 u8 val;
@@ -1268,34 +1364,30 @@ static int mmc_select_hs200(struct mmc_card *card)
1268 1364
1269 mmc_select_driver_type(card); 1365 mmc_select_driver_type(card);
1270 1366
1271 if (host->caps & MMC_CAP_WAIT_WHILE_BUSY)
1272 send_status = false;
1273
1274 /* 1367 /*
1275 * Set the bus width(4 or 8) with host's support and 1368 * Set the bus width(4 or 8) with host's support and
1276 * switch to HS200 mode if bus width is set successfully. 1369 * switch to HS200 mode if bus width is set successfully.
1277 */ 1370 */
1278 err = mmc_select_bus_width(card); 1371 err = mmc_select_bus_width(card);
1279 if (err >= 0) { 1372 if (err > 0) {
1280 val = EXT_CSD_TIMING_HS200 | 1373 val = EXT_CSD_TIMING_HS200 |
1281 card->drive_strength << EXT_CSD_DRV_STR_SHIFT; 1374 card->drive_strength << EXT_CSD_DRV_STR_SHIFT;
1282 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, 1375 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
1283 EXT_CSD_HS_TIMING, val, 1376 EXT_CSD_HS_TIMING, val,
1284 card->ext_csd.generic_cmd6_time, 1377 card->ext_csd.generic_cmd6_time,
1285 true, send_status, true); 1378 true, false, true);
1286 if (err) 1379 if (err)
1287 goto err; 1380 goto err;
1288 old_timing = host->ios.timing; 1381 old_timing = host->ios.timing;
1289 mmc_set_timing(host, MMC_TIMING_MMC_HS200); 1382 mmc_set_timing(host, MMC_TIMING_MMC_HS200);
1290 if (!send_status) { 1383
1291 err = mmc_switch_status(card); 1384 err = mmc_switch_status(card);
1292 /* 1385 /*
1293 * mmc_select_timing() assumes timing has not changed if 1386 * mmc_select_timing() assumes timing has not changed if
1294 * it is a switch error. 1387 * it is a switch error.
1295 */ 1388 */
1296 if (err == -EBADMSG) 1389 if (err == -EBADMSG)
1297 mmc_set_timing(host, old_timing); 1390 mmc_set_timing(host, old_timing);
1298 }
1299 } 1391 }
1300err: 1392err:
1301 if (err) { 1393 if (err) {
@@ -1310,7 +1402,7 @@ err:
1310} 1402}
1311 1403
1312/* 1404/*
1313 * Activate High Speed or HS200 mode if supported. 1405 * Activate High Speed, HS200 or HS400ES mode if supported.
1314 */ 1406 */
1315static int mmc_select_timing(struct mmc_card *card) 1407static int mmc_select_timing(struct mmc_card *card)
1316{ 1408{
@@ -1319,7 +1411,9 @@ static int mmc_select_timing(struct mmc_card *card)
1319 if (!mmc_can_ext_csd(card)) 1411 if (!mmc_can_ext_csd(card))
1320 goto bus_speed; 1412 goto bus_speed;
1321 1413
1322 if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200) 1414 if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400ES)
1415 err = mmc_select_hs400es(card);
1416 else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200)
1323 err = mmc_select_hs200(card); 1417 err = mmc_select_hs200(card);
1324 else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS) 1418 else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS)
1325 err = mmc_select_hs(card); 1419 err = mmc_select_hs(card);
@@ -1583,7 +1677,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
1583 } else if (mmc_card_hs(card)) { 1677 } else if (mmc_card_hs(card)) {
1584 /* Select the desired bus width optionally */ 1678 /* Select the desired bus width optionally */
1585 err = mmc_select_bus_width(card); 1679 err = mmc_select_bus_width(card);
1586 if (err >= 0) { 1680 if (err > 0) {
1587 err = mmc_select_hs_ddr(card); 1681 err = mmc_select_hs_ddr(card);
1588 if (err) 1682 if (err)
1589 goto free_card; 1683 goto free_card;
@@ -1616,7 +1710,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
1616 * If cache size is higher than 0, this indicates 1710 * If cache size is higher than 0, this indicates
1617 * the existence of cache and it can be turned on. 1711 * the existence of cache and it can be turned on.
1618 */ 1712 */
1619 if (card->ext_csd.cache_size > 0) { 1713 if (!mmc_card_broken_hpi(card) &&
1714 card->ext_csd.cache_size > 0) {
1620 err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, 1715 err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
1621 EXT_CSD_CACHE_CTRL, 1, 1716 EXT_CSD_CACHE_CTRL, 1,
1622 card->ext_csd.generic_cmd6_time); 1717 card->ext_csd.generic_cmd6_time);
diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c
index 62355bda608f..ad6e9798e949 100644
--- a/drivers/mmc/core/mmc_ops.c
+++ b/drivers/mmc/core/mmc_ops.c
@@ -480,6 +480,7 @@ int __mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value,
480 u32 status = 0; 480 u32 status = 0;
481 bool use_r1b_resp = use_busy_signal; 481 bool use_r1b_resp = use_busy_signal;
482 bool expired = false; 482 bool expired = false;
483 bool busy = false;
483 484
484 mmc_retune_hold(host); 485 mmc_retune_hold(host);
485 486
@@ -533,21 +534,26 @@ int __mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value,
533 timeout_ms = MMC_OPS_TIMEOUT_MS; 534 timeout_ms = MMC_OPS_TIMEOUT_MS;
534 535
535 /* Must check status to be sure of no errors. */ 536 /* Must check status to be sure of no errors. */
536 timeout = jiffies + msecs_to_jiffies(timeout_ms); 537 timeout = jiffies + msecs_to_jiffies(timeout_ms) + 1;
537 do { 538 do {
539 /*
540 * Due to the possibility of being preempted after
541 * sending the status command, check the expiration
542 * time first.
543 */
544 expired = time_after(jiffies, timeout);
538 if (send_status) { 545 if (send_status) {
539 /*
540 * Due to the possibility of being preempted after
541 * sending the status command, check the expiration
542 * time first.
543 */
544 expired = time_after(jiffies, timeout);
545 err = __mmc_send_status(card, &status, ignore_crc); 546 err = __mmc_send_status(card, &status, ignore_crc);
546 if (err) 547 if (err)
547 goto out; 548 goto out;
548 } 549 }
549 if ((host->caps & MMC_CAP_WAIT_WHILE_BUSY) && use_r1b_resp) 550 if ((host->caps & MMC_CAP_WAIT_WHILE_BUSY) && use_r1b_resp)
550 break; 551 break;
552 if (host->ops->card_busy) {
553 if (!host->ops->card_busy(host))
554 break;
555 busy = true;
556 }
551 if (mmc_host_is_spi(host)) 557 if (mmc_host_is_spi(host))
552 break; 558 break;
553 559
@@ -556,19 +562,20 @@ int __mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value,
556 * does'nt support MMC_CAP_WAIT_WHILE_BUSY, then we can only 562 * does'nt support MMC_CAP_WAIT_WHILE_BUSY, then we can only
557 * rely on waiting for the stated timeout to be sufficient. 563 * rely on waiting for the stated timeout to be sufficient.
558 */ 564 */
559 if (!send_status) { 565 if (!send_status && !host->ops->card_busy) {
560 mmc_delay(timeout_ms); 566 mmc_delay(timeout_ms);
561 goto out; 567 goto out;
562 } 568 }
563 569
564 /* Timeout if the device never leaves the program state. */ 570 /* Timeout if the device never leaves the program state. */
565 if (expired && R1_CURRENT_STATE(status) == R1_STATE_PRG) { 571 if (expired &&
572 (R1_CURRENT_STATE(status) == R1_STATE_PRG || busy)) {
566 pr_err("%s: Card stuck in programming state! %s\n", 573 pr_err("%s: Card stuck in programming state! %s\n",
567 mmc_hostname(host), __func__); 574 mmc_hostname(host), __func__);
568 err = -ETIMEDOUT; 575 err = -ETIMEDOUT;
569 goto out; 576 goto out;
570 } 577 }
571 } while (R1_CURRENT_STATE(status) == R1_STATE_PRG); 578 } while (R1_CURRENT_STATE(status) == R1_STATE_PRG || busy);
572 579
573 err = mmc_switch_status_error(host, status); 580 err = mmc_switch_status_error(host, status);
574out: 581out:
diff --git a/drivers/mmc/core/quirks.c b/drivers/mmc/core/quirks.c
index fad660b95809..ca9cade317c7 100644
--- a/drivers/mmc/core/quirks.c
+++ b/drivers/mmc/core/quirks.c
@@ -72,6 +72,8 @@ void mmc_fixup_device(struct mmc_card *card, const struct mmc_fixup *table)
72 f->cis_vendor == (u16) SDIO_ANY_ID) && 72 f->cis_vendor == (u16) SDIO_ANY_ID) &&
73 (f->cis_device == card->cis.device || 73 (f->cis_device == card->cis.device ||
74 f->cis_device == (u16) SDIO_ANY_ID) && 74 f->cis_device == (u16) SDIO_ANY_ID) &&
75 (f->ext_csd_rev == EXT_CSD_REV_ANY ||
76 f->ext_csd_rev == card->ext_csd.rev) &&
75 rev >= f->rev_start && rev <= f->rev_end) { 77 rev >= f->rev_start && rev <= f->rev_end) {
76 dev_dbg(&card->dev, "calling %pf\n", f->vendor_fixup); 78 dev_dbg(&card->dev, "calling %pf\n", f->vendor_fixup);
77 f->vendor_fixup(card, f->data); 79 f->vendor_fixup(card, f->data);
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
index b95bd24d92f4..0123936241b0 100644
--- a/drivers/mmc/core/sd.c
+++ b/drivers/mmc/core/sd.c
@@ -675,8 +675,25 @@ MMC_DEV_ATTR(manfid, "0x%06x\n", card->cid.manfid);
675MMC_DEV_ATTR(name, "%s\n", card->cid.prod_name); 675MMC_DEV_ATTR(name, "%s\n", card->cid.prod_name);
676MMC_DEV_ATTR(oemid, "0x%04x\n", card->cid.oemid); 676MMC_DEV_ATTR(oemid, "0x%04x\n", card->cid.oemid);
677MMC_DEV_ATTR(serial, "0x%08x\n", card->cid.serial); 677MMC_DEV_ATTR(serial, "0x%08x\n", card->cid.serial);
678MMC_DEV_ATTR(ocr, "%08x\n", card->ocr);
678 679
679 680
681static ssize_t mmc_dsr_show(struct device *dev,
682 struct device_attribute *attr,
683 char *buf)
684{
685 struct mmc_card *card = mmc_dev_to_card(dev);
686 struct mmc_host *host = card->host;
687
688 if (card->csd.dsr_imp && host->dsr_req)
689 return sprintf(buf, "0x%x\n", host->dsr);
690 else
691 /* return default DSR value */
692 return sprintf(buf, "0x%x\n", 0x404);
693}
694
695static DEVICE_ATTR(dsr, S_IRUGO, mmc_dsr_show, NULL);
696
680static struct attribute *sd_std_attrs[] = { 697static struct attribute *sd_std_attrs[] = {
681 &dev_attr_cid.attr, 698 &dev_attr_cid.attr,
682 &dev_attr_csd.attr, 699 &dev_attr_csd.attr,
@@ -690,6 +707,8 @@ static struct attribute *sd_std_attrs[] = {
690 &dev_attr_name.attr, 707 &dev_attr_name.attr,
691 &dev_attr_oemid.attr, 708 &dev_attr_oemid.attr,
692 &dev_attr_serial.attr, 709 &dev_attr_serial.attr,
710 &dev_attr_ocr.attr,
711 &dev_attr_dsr.attr,
693 NULL, 712 NULL,
694}; 713};
695ATTRIBUTE_GROUPS(sd_std); 714ATTRIBUTE_GROUPS(sd_std);
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 0aa484c10c0a..5274f503a39a 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -122,6 +122,7 @@ config MMC_SDHCI_OF_ARASAN
122 tristate "SDHCI OF support for the Arasan SDHCI controllers" 122 tristate "SDHCI OF support for the Arasan SDHCI controllers"
123 depends on MMC_SDHCI_PLTFM 123 depends on MMC_SDHCI_PLTFM
124 depends on OF 124 depends on OF
125 depends on COMMON_CLK
125 help 126 help
126 This selects the Arasan Secure Digital Host Controller Interface 127 This selects the Arasan Secure Digital Host Controller Interface
127 (SDHCI). This hardware is found e.g. in Xilinx' Zynq SoC. 128 (SDHCI). This hardware is found e.g. in Xilinx' Zynq SoC.
@@ -296,17 +297,6 @@ config MMC_SDHCI_BCM_KONA
296 297
297 If you have a controller with this interface, say Y or M here. 298 If you have a controller with this interface, say Y or M here.
298 299
299config MMC_SDHCI_BCM2835
300 tristate "SDHCI platform support for the BCM2835 SD/MMC Controller"
301 depends on ARCH_BCM2835
302 depends on MMC_SDHCI_PLTFM
303 select MMC_SDHCI_IO_ACCESSORS
304 help
305 This selects the BCM2835 SD/MMC controller. If you have a BCM2835
306 platform with SD or MMC devices, say Y or M here.
307
308 If unsure, say N.
309
310config MMC_SDHCI_F_SDH30 300config MMC_SDHCI_F_SDH30
311 tristate "SDHCI support for Fujitsu Semiconductor F_SDH30" 301 tristate "SDHCI support for Fujitsu Semiconductor F_SDH30"
312 depends on MMC_SDHCI_PLTFM 302 depends on MMC_SDHCI_PLTFM
@@ -798,3 +788,13 @@ config MMC_SDHCI_MICROCHIP_PIC32
798 If you have a controller with this interface, say Y or M here. 788 If you have a controller with this interface, say Y or M here.
799 789
800 If unsure, say N. 790 If unsure, say N.
791config MMC_SDHCI_BRCMSTB
792 tristate "Broadcom SDIO/SD/MMC support"
793 depends on ARCH_BRCMSTB || BMIPS_GENERIC
794 depends on MMC_SDHCI_PLTFM
795 default y
796 help
797 This selects support for the SDIO/SD/MMC Host Controller on
798 Broadcom STB SoCs.
799
800 If unsure, say Y.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index af918d261ff9..e2bdaaf43184 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -71,11 +71,11 @@ obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o
71obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o 71obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
72obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o 72obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
73obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o 73obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
74obj-$(CONFIG_MMC_SDHCI_BCM2835) += sdhci-bcm2835.o
75obj-$(CONFIG_MMC_SDHCI_IPROC) += sdhci-iproc.o 74obj-$(CONFIG_MMC_SDHCI_IPROC) += sdhci-iproc.o
76obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o 75obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
77obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o 76obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o
78obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) += sdhci-pic32.o 77obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) += sdhci-pic32.o
78obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o
79 79
80ifeq ($(CONFIG_CB710_DEBUG),y) 80ifeq ($(CONFIG_CB710_DEBUG),y)
81 CFLAGS-cb710-mmc += -DDEBUG 81 CFLAGS-cb710-mmc += -DDEBUG
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 7e3a3247b852..da0ef1765735 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -157,7 +157,7 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
157 * HOLD register should be bypassed in case there is no phase shift 157 * HOLD register should be bypassed in case there is no phase shift
158 * applied on CMD/DATA that is sent to the card. 158 * applied on CMD/DATA that is sent to the card.
159 */ 159 */
160 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel)) 160 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->cur_slot)
161 set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags); 161 set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags);
162} 162}
163 163
diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c
index 63c2e2ed1288..8e9d886bfcda 100644
--- a/drivers/mmc/host/dw_mmc-k3.c
+++ b/drivers/mmc/host/dw_mmc-k3.c
@@ -32,6 +32,12 @@ struct k3_priv {
32 struct regmap *reg; 32 struct regmap *reg;
33}; 33};
34 34
35static unsigned long dw_mci_hi6220_caps[] = {
36 MMC_CAP_CMD23,
37 MMC_CAP_CMD23,
38 0
39};
40
35static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios) 41static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
36{ 42{
37 int ret; 43 int ret;
@@ -126,6 +132,7 @@ static void dw_mci_hi6220_set_ios(struct dw_mci *host, struct mmc_ios *ios)
126} 132}
127 133
128static const struct dw_mci_drv_data hi6220_data = { 134static const struct dw_mci_drv_data hi6220_data = {
135 .caps = dw_mci_hi6220_caps,
129 .switch_voltage = dw_mci_hi6220_switch_voltage, 136 .switch_voltage = dw_mci_hi6220_switch_voltage,
130 .set_ios = dw_mci_hi6220_set_ios, 137 .set_ios = dw_mci_hi6220_set_ios,
131 .parse_dt = dw_mci_hi6220_parse_dt, 138 .parse_dt = dw_mci_hi6220_parse_dt,
diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
index 358b0dc853b0..25eae359a5ea 100644
--- a/drivers/mmc/host/dw_mmc-rockchip.c
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
@@ -285,9 +285,6 @@ static int dw_mci_rockchip_init(struct dw_mci *host)
285 /* It is slot 8 on Rockchip SoCs */ 285 /* It is slot 8 on Rockchip SoCs */
286 host->sdio_id0 = 8; 286 host->sdio_id0 = 8;
287 287
288 /* It needs this quirk on all Rockchip SoCs */
289 host->pdata->quirks |= DW_MCI_QUIRK_BROKEN_DTO;
290
291 if (of_device_is_compatible(host->dev->of_node, 288 if (of_device_is_compatible(host->dev->of_node,
292 "rockchip,rk3288-dw-mshc")) 289 "rockchip,rk3288-dw-mshc"))
293 host->bus_hz /= RK3288_CLKGEN_DIV; 290 host->bus_hz /= RK3288_CLKGEN_DIV;
@@ -297,10 +294,10 @@ static int dw_mci_rockchip_init(struct dw_mci *host)
297 294
298/* Common capabilities of RK3288 SoC */ 295/* Common capabilities of RK3288 SoC */
299static unsigned long dw_mci_rk3288_dwmmc_caps[4] = { 296static unsigned long dw_mci_rk3288_dwmmc_caps[4] = {
300 MMC_CAP_ERASE | MMC_CAP_CMD23, 297 MMC_CAP_CMD23,
301 MMC_CAP_ERASE | MMC_CAP_CMD23, 298 MMC_CAP_CMD23,
302 MMC_CAP_ERASE | MMC_CAP_CMD23, 299 MMC_CAP_CMD23,
303 MMC_CAP_ERASE | MMC_CAP_CMD23, 300 MMC_CAP_CMD23,
304}; 301};
305 302
306static const struct dw_mci_drv_data rk2928_drv_data = { 303static const struct dw_mci_drv_data rk2928_drv_data = {
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 2cc6123b1df9..32380d5d4f6b 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -44,11 +44,11 @@
44/* Common flag combinations */ 44/* Common flag combinations */
45#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 45#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \ 46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE) 47 SDMMC_INT_EBE | SDMMC_INT_HLE)
48#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 48#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR) 49 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
50#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 50#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) 51 DW_MCI_CMD_ERROR_FLAGS)
52#define DW_MCI_SEND_STATUS 1 52#define DW_MCI_SEND_STATUS 1
53#define DW_MCI_RECV_STATUS 2 53#define DW_MCI_RECV_STATUS 2
54#define DW_MCI_DMA_THRESHOLD 16 54#define DW_MCI_DMA_THRESHOLD 16
@@ -92,7 +92,7 @@ struct idmac_desc {
92 92
93 __le32 des1; /* Buffer sizes */ 93 __le32 des1; /* Buffer sizes */
94#define IDMAC_SET_BUFFER1_SIZE(d, s) \ 94#define IDMAC_SET_BUFFER1_SIZE(d, s) \
95 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) 95 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
96 96
97 __le32 des2; /* buffer 1 physical address */ 97 __le32 des2; /* buffer 1 physical address */
98 98
@@ -105,6 +105,7 @@ struct idmac_desc {
105static bool dw_mci_reset(struct dw_mci *host); 105static bool dw_mci_reset(struct dw_mci *host);
106static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset); 106static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
107static int dw_mci_card_busy(struct mmc_host *mmc); 107static int dw_mci_card_busy(struct mmc_host *mmc);
108static int dw_mci_get_cd(struct mmc_host *mmc);
108 109
109#if defined(CONFIG_DEBUG_FS) 110#if defined(CONFIG_DEBUG_FS)
110static int dw_mci_req_show(struct seq_file *s, void *v) 111static int dw_mci_req_show(struct seq_file *s, void *v)
@@ -898,23 +899,35 @@ done:
898 mci_writel(host, FIFOTH, fifoth_val); 899 mci_writel(host, FIFOTH, fifoth_val);
899} 900}
900 901
901static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data) 902static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
902{ 903{
903 unsigned int blksz = data->blksz; 904 unsigned int blksz = data->blksz;
904 u32 blksz_depth, fifo_depth; 905 u32 blksz_depth, fifo_depth;
905 u16 thld_size; 906 u16 thld_size;
906 907 u8 enable;
907 WARN_ON(!(data->flags & MMC_DATA_READ));
908 908
909 /* 909 /*
910 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 910 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
911 * in the FIFO region, so we really shouldn't access it). 911 * in the FIFO region, so we really shouldn't access it).
912 */ 912 */
913 if (host->verid < DW_MMC_240A) 913 if (host->verid < DW_MMC_240A ||
914 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
915 return;
916
917 /*
918 * Card write Threshold is introduced since 2.80a
919 * It's used when HS400 mode is enabled.
920 */
921 if (data->flags & MMC_DATA_WRITE &&
922 !(host->timing != MMC_TIMING_MMC_HS400))
914 return; 923 return;
915 924
925 if (data->flags & MMC_DATA_WRITE)
926 enable = SDMMC_CARD_WR_THR_EN;
927 else
928 enable = SDMMC_CARD_RD_THR_EN;
929
916 if (host->timing != MMC_TIMING_MMC_HS200 && 930 if (host->timing != MMC_TIMING_MMC_HS200 &&
917 host->timing != MMC_TIMING_MMC_HS400 &&
918 host->timing != MMC_TIMING_UHS_SDR104) 931 host->timing != MMC_TIMING_UHS_SDR104)
919 goto disable; 932 goto disable;
920 933
@@ -930,11 +943,11 @@ static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
930 * Currently just choose blksz. 943 * Currently just choose blksz.
931 */ 944 */
932 thld_size = blksz; 945 thld_size = blksz;
933 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1)); 946 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
934 return; 947 return;
935 948
936disable: 949disable:
937 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0)); 950 mci_writel(host, CDTHRCTL, 0);
938} 951}
939 952
940static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 953static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
@@ -1005,12 +1018,12 @@ static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1005 host->sg = NULL; 1018 host->sg = NULL;
1006 host->data = data; 1019 host->data = data;
1007 1020
1008 if (data->flags & MMC_DATA_READ) { 1021 if (data->flags & MMC_DATA_READ)
1009 host->dir_status = DW_MCI_RECV_STATUS; 1022 host->dir_status = DW_MCI_RECV_STATUS;
1010 dw_mci_ctrl_rd_thld(host, data); 1023 else
1011 } else {
1012 host->dir_status = DW_MCI_SEND_STATUS; 1024 host->dir_status = DW_MCI_SEND_STATUS;
1013 } 1025
1026 dw_mci_ctrl_thld(host, data);
1014 1027
1015 if (dw_mci_submit_data_dma(host, data)) { 1028 if (dw_mci_submit_data_dma(host, data)) {
1016 if (host->data->flags & MMC_DATA_READ) 1029 if (host->data->flags & MMC_DATA_READ)
@@ -1099,12 +1112,11 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1099 1112
1100 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1113 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1101 1114
1102 if ((clock << div) != slot->__clk_old || force_clkinit) 1115 dev_info(&slot->mmc->class_dev,
1103 dev_info(&slot->mmc->class_dev, 1116 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1104 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1117 slot->id, host->bus_hz, clock,
1105 slot->id, host->bus_hz, clock, 1118 div ? ((host->bus_hz / div) >> 1) :
1106 div ? ((host->bus_hz / div) >> 1) : 1119 host->bus_hz, div);
1107 host->bus_hz, div);
1108 1120
1109 /* disable clock */ 1121 /* disable clock */
1110 mci_writel(host, CLKENA, 0); 1122 mci_writel(host, CLKENA, 0);
@@ -1127,9 +1139,6 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1127 1139
1128 /* inform CIU */ 1140 /* inform CIU */
1129 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1141 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1130
1131 /* keep the clock with reflecting clock dividor */
1132 slot->__clk_old = clock << div;
1133 } 1142 }
1134 1143
1135 host->current_speed = clock; 1144 host->current_speed = clock;
@@ -1253,15 +1262,15 @@ static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1253 * atomic, otherwise the card could be removed in between and the 1262 * atomic, otherwise the card could be removed in between and the
1254 * request wouldn't fail until another card was inserted. 1263 * request wouldn't fail until another card was inserted.
1255 */ 1264 */
1256 spin_lock_bh(&host->lock);
1257 1265
1258 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 1266 if (!dw_mci_get_cd(mmc)) {
1259 spin_unlock_bh(&host->lock);
1260 mrq->cmd->error = -ENOMEDIUM; 1267 mrq->cmd->error = -ENOMEDIUM;
1261 mmc_request_done(mmc, mrq); 1268 mmc_request_done(mmc, mrq);
1262 return; 1269 return;
1263 } 1270 }
1264 1271
1272 spin_lock_bh(&host->lock);
1273
1265 dw_mci_queue_request(host, slot, mrq); 1274 dw_mci_queue_request(host, slot, mrq);
1266 1275
1267 spin_unlock_bh(&host->lock); 1276 spin_unlock_bh(&host->lock);
@@ -1451,8 +1460,7 @@ static int dw_mci_get_cd(struct mmc_host *mmc)
1451 int gpio_cd = mmc_gpio_get_cd(mmc); 1460 int gpio_cd = mmc_gpio_get_cd(mmc);
1452 1461
1453 /* Use platform get_cd function, else try onboard card detect */ 1462 /* Use platform get_cd function, else try onboard card detect */
1454 if ((mmc->caps & MMC_CAP_NEEDS_POLL) || 1463 if ((mmc->caps & MMC_CAP_NEEDS_POLL) || !mmc_card_is_removable(mmc))
1455 (mmc->caps & MMC_CAP_NONREMOVABLE))
1456 present = 1; 1464 present = 1;
1457 else if (gpio_cd >= 0) 1465 else if (gpio_cd >= 0)
1458 present = gpio_cd; 1466 present = gpio_cd;
@@ -1761,6 +1769,33 @@ static void dw_mci_tasklet_func(unsigned long priv)
1761 } 1769 }
1762 1770
1763 if (cmd->data && err) { 1771 if (cmd->data && err) {
1772 /*
1773 * During UHS tuning sequence, sending the stop
1774 * command after the response CRC error would
1775 * throw the system into a confused state
1776 * causing all future tuning phases to report
1777 * failure.
1778 *
1779 * In such case controller will move into a data
1780 * transfer state after a response error or
1781 * response CRC error. Let's let that finish
1782 * before trying to send a stop, so we'll go to
1783 * STATE_SENDING_DATA.
1784 *
1785 * Although letting the data transfer take place
1786 * will waste a bit of time (we already know
1787 * the command was bad), it can't cause any
1788 * errors since it's possible it would have
1789 * taken place anyway if this tasklet got
1790 * delayed. Allowing the transfer to take place
1791 * avoids races and keeps things simple.
1792 */
1793 if ((err != -ETIMEDOUT) &&
1794 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
1795 state = STATE_SENDING_DATA;
1796 continue;
1797 }
1798
1764 dw_mci_stop_dma(host); 1799 dw_mci_stop_dma(host);
1765 send_stop_abort(host, data); 1800 send_stop_abort(host, data);
1766 state = STATE_SENDING_STOP; 1801 state = STATE_SENDING_STOP;
@@ -1801,8 +1836,7 @@ static void dw_mci_tasklet_func(unsigned long priv)
1801 * If all data-related interrupts don't come 1836 * If all data-related interrupts don't come
1802 * within the given time in reading data state. 1837 * within the given time in reading data state.
1803 */ 1838 */
1804 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) && 1839 if (host->dir_status == DW_MCI_RECV_STATUS)
1805 (host->dir_status == DW_MCI_RECV_STATUS))
1806 dw_mci_set_drto(host); 1840 dw_mci_set_drto(host);
1807 break; 1841 break;
1808 } 1842 }
@@ -1844,8 +1878,7 @@ static void dw_mci_tasklet_func(unsigned long priv)
1844 * interrupt doesn't come within the given time. 1878 * interrupt doesn't come within the given time.
1845 * in reading data state. 1879 * in reading data state.
1846 */ 1880 */
1847 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) && 1881 if (host->dir_status == DW_MCI_RECV_STATUS)
1848 (host->dir_status == DW_MCI_RECV_STATUS))
1849 dw_mci_set_drto(host); 1882 dw_mci_set_drto(host);
1850 break; 1883 break;
1851 } 1884 }
@@ -2411,8 +2444,7 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2411 } 2444 }
2412 2445
2413 if (pending & SDMMC_INT_DATA_OVER) { 2446 if (pending & SDMMC_INT_DATA_OVER) {
2414 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO) 2447 del_timer(&host->dto_timer);
2415 del_timer(&host->dto_timer);
2416 2448
2417 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2449 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2418 if (!host->data_status) 2450 if (!host->data_status)
@@ -2474,7 +2506,8 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2474 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 2506 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2475 SDMMC_IDMAC_INT_RI); 2507 SDMMC_IDMAC_INT_RI);
2476 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2508 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2477 host->dma_ops->complete((void *)host); 2509 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2510 host->dma_ops->complete((void *)host);
2478 } 2511 }
2479 } else { 2512 } else {
2480 pending = mci_readl(host, IDSTS); 2513 pending = mci_readl(host, IDSTS);
@@ -2482,7 +2515,8 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2482 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 2515 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2483 SDMMC_IDMAC_INT_RI); 2516 SDMMC_IDMAC_INT_RI);
2484 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2517 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2485 host->dma_ops->complete((void *)host); 2518 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2519 host->dma_ops->complete((void *)host);
2486 } 2520 }
2487 } 2521 }
2488 2522
@@ -2570,6 +2604,12 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2570 if (host->pdata->caps) 2604 if (host->pdata->caps)
2571 mmc->caps = host->pdata->caps; 2605 mmc->caps = host->pdata->caps;
2572 2606
2607 /*
2608 * Support MMC_CAP_ERASE by default.
2609 * It needs to use trim/discard/erase commands.
2610 */
2611 mmc->caps |= MMC_CAP_ERASE;
2612
2573 if (host->pdata->pm_caps) 2613 if (host->pdata->pm_caps)
2574 mmc->pm_caps = host->pdata->pm_caps; 2614 mmc->pm_caps = host->pdata->pm_caps;
2575 2615
@@ -2616,10 +2656,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2616 mmc->max_seg_size = mmc->max_req_size; 2656 mmc->max_seg_size = mmc->max_req_size;
2617 } 2657 }
2618 2658
2619 if (dw_mci_get_cd(mmc)) 2659 dw_mci_get_cd(mmc);
2620 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2621 else
2622 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2623 2660
2624 ret = mmc_add_host(mmc); 2661 ret = mmc_add_host(mmc);
2625 if (ret) 2662 if (ret)
@@ -3006,11 +3043,8 @@ int dw_mci_probe(struct dw_mci *host)
3006 setup_timer(&host->cmd11_timer, 3043 setup_timer(&host->cmd11_timer,
3007 dw_mci_cmd11_timer, (unsigned long)host); 3044 dw_mci_cmd11_timer, (unsigned long)host);
3008 3045
3009 host->quirks = host->pdata->quirks; 3046 setup_timer(&host->dto_timer,
3010 3047 dw_mci_dto_timer, (unsigned long)host);
3011 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
3012 setup_timer(&host->dto_timer,
3013 dw_mci_dto_timer, (unsigned long)host);
3014 3048
3015 spin_lock_init(&host->lock); 3049 spin_lock_init(&host->lock);
3016 spin_lock_init(&host->irq_lock); 3050 spin_lock_init(&host->irq_lock);
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 1e8d8380f9cf..9e740bc232a8 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -15,6 +15,7 @@
15#define _DW_MMC_H_ 15#define _DW_MMC_H_
16 16
17#define DW_MMC_240A 0x240a 17#define DW_MMC_240A 0x240a
18#define DW_MMC_280A 0x280a
18 19
19#define SDMMC_CTRL 0x000 20#define SDMMC_CTRL 0x000
20#define SDMMC_PWREN 0x004 21#define SDMMC_PWREN 0x004
@@ -175,7 +176,10 @@
175/* Version ID register define */ 176/* Version ID register define */
176#define SDMMC_GET_VERID(x) ((x) & 0xFFFF) 177#define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
177/* Card read threshold */ 178/* Card read threshold */
178#define SDMMC_SET_RD_THLD(v, x) (((v) & 0xFFF) << 16 | (x)) 179#define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
180#define SDMMC_CARD_WR_THR_EN BIT(2)
181#define SDMMC_CARD_RD_THR_EN BIT(0)
182/* UHS-1 register defines */
179#define SDMMC_UHS_18V BIT(0) 183#define SDMMC_UHS_18V BIT(0)
180/* All ctrl reset bits */ 184/* All ctrl reset bits */
181#define SDMMC_CTRL_ALL_RESET_FLAGS \ 185#define SDMMC_CTRL_ALL_RESET_FLAGS \
@@ -245,9 +249,6 @@ extern int dw_mci_resume(struct dw_mci *host);
245 * @queue_node: List node for placing this node in the @queue list of 249 * @queue_node: List node for placing this node in the @queue list of
246 * &struct dw_mci. 250 * &struct dw_mci.
247 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 251 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
248 * @__clk_old: The last updated clock with reflecting clock divider.
249 * Keeping track of this helps us to avoid spamming the console
250 * with CONFIG_MMC_CLKGATE.
251 * @flags: Random state bits associated with the slot. 252 * @flags: Random state bits associated with the slot.
252 * @id: Number of this slot. 253 * @id: Number of this slot.
253 * @sdio_id: Number of this slot in the SDIO interrupt registers. 254 * @sdio_id: Number of this slot in the SDIO interrupt registers.
@@ -262,7 +263,6 @@ struct dw_mci_slot {
262 struct list_head queue_node; 263 struct list_head queue_node;
263 264
264 unsigned int clock; 265 unsigned int clock;
265 unsigned int __clk_old;
266 266
267 unsigned long flags; 267 unsigned long flags;
268#define DW_MMC_CARD_PRESENT 0 268#define DW_MMC_CARD_PRESENT 0
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 5642f71f8bf0..84e9afcb5c09 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -287,6 +287,11 @@ struct msdc_save_para {
287 u32 emmc50_cfg0; 287 u32 emmc50_cfg0;
288}; 288};
289 289
290struct msdc_tune_para {
291 u32 iocon;
292 u32 pad_tune;
293};
294
290struct msdc_delay_phase { 295struct msdc_delay_phase {
291 u8 maxlen; 296 u8 maxlen;
292 u8 start; 297 u8 start;
@@ -326,7 +331,10 @@ struct msdc_host {
326 unsigned char timing; 331 unsigned char timing;
327 bool vqmmc_enabled; 332 bool vqmmc_enabled;
328 u32 hs400_ds_delay; 333 u32 hs400_ds_delay;
334 bool hs400_mode; /* current eMMC will run at hs400 mode */
329 struct msdc_save_para save_para; /* used when gate HCLK */ 335 struct msdc_save_para save_para; /* used when gate HCLK */
336 struct msdc_tune_para def_tune_para; /* default tune setting */
337 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
330}; 338};
331 339
332static void sdr_set_bits(void __iomem *reg, u32 bs) 340static void sdr_set_bits(void __iomem *reg, u32 bs)
@@ -582,6 +590,18 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
582 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 590 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
583 sdr_set_bits(host->base + MSDC_INTEN, flags); 591 sdr_set_bits(host->base + MSDC_INTEN, flags);
584 592
593 /*
594 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
595 * tune result of hs200/200Mhz is not suitable for 50Mhz
596 */
597 if (host->sclk <= 52000000) {
598 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
599 writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
600 } else {
601 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
602 writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
603 }
604
585 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing); 605 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing);
586} 606}
587 607
@@ -781,7 +801,13 @@ static bool msdc_cmd_done(struct msdc_host *host, int events,
781 } 801 }
782 802
783 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 803 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
784 msdc_reset_hw(host); 804 if (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
805 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
806 /*
807 * should not clear fifo/interrupt as the tune data
808 * may have alreay come.
809 */
810 msdc_reset_hw(host);
785 if (events & MSDC_INT_RSPCRCERR) { 811 if (events & MSDC_INT_RSPCRCERR) {
786 cmd->error = -EILSEQ; 812 cmd->error = -EILSEQ;
787 host->error |= REQ_CMD_EIO; 813 host->error |= REQ_CMD_EIO;
@@ -865,7 +891,11 @@ static void msdc_start_command(struct msdc_host *host,
865static void msdc_cmd_next(struct msdc_host *host, 891static void msdc_cmd_next(struct msdc_host *host,
866 struct mmc_request *mrq, struct mmc_command *cmd) 892 struct mmc_request *mrq, struct mmc_command *cmd)
867{ 893{
868 if (cmd->error || (mrq->sbc && mrq->sbc->error)) 894 if ((cmd->error &&
895 !(cmd->error == -EILSEQ &&
896 (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
897 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) ||
898 (mrq->sbc && mrq->sbc->error))
869 msdc_request_done(host, mrq); 899 msdc_request_done(host, mrq);
870 else if (cmd == mrq->sbc) 900 else if (cmd == mrq->sbc)
871 msdc_start_command(host, mrq, mrq->cmd); 901 msdc_start_command(host, mrq, mrq->cmd);
@@ -1158,6 +1188,8 @@ static void msdc_init_hw(struct msdc_host *host)
1158 /* Configure to default data timeout */ 1188 /* Configure to default data timeout */
1159 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1189 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1160 1190
1191 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1192 host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
1161 dev_dbg(host->dev, "init hardware done!"); 1193 dev_dbg(host->dev, "init hardware done!");
1162} 1194}
1163 1195
@@ -1296,7 +1328,7 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1296{ 1328{
1297 struct msdc_host *host = mmc_priv(mmc); 1329 struct msdc_host *host = mmc_priv(mmc);
1298 u32 rise_delay = 0, fall_delay = 0; 1330 u32 rise_delay = 0, fall_delay = 0;
1299 struct msdc_delay_phase final_rise_delay, final_fall_delay; 1331 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1300 u8 final_delay, final_maxlen; 1332 u8 final_delay, final_maxlen;
1301 int cmd_err; 1333 int cmd_err;
1302 int i; 1334 int i;
@@ -1309,6 +1341,11 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1309 if (!cmd_err) 1341 if (!cmd_err)
1310 rise_delay |= (1 << i); 1342 rise_delay |= (1 << i);
1311 } 1343 }
1344 final_rise_delay = get_best_delay(host, rise_delay);
1345 /* if rising edge has enough margin, then do not scan falling edge */
1346 if (final_rise_delay.maxlen >= 10 ||
1347 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1348 goto skip_fall;
1312 1349
1313 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1350 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1314 for (i = 0; i < PAD_DELAY_MAX; i++) { 1351 for (i = 0; i < PAD_DELAY_MAX; i++) {
@@ -1318,10 +1355,9 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1318 if (!cmd_err) 1355 if (!cmd_err)
1319 fall_delay |= (1 << i); 1356 fall_delay |= (1 << i);
1320 } 1357 }
1321
1322 final_rise_delay = get_best_delay(host, rise_delay);
1323 final_fall_delay = get_best_delay(host, fall_delay); 1358 final_fall_delay = get_best_delay(host, fall_delay);
1324 1359
1360skip_fall:
1325 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1361 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1326 if (final_maxlen == final_rise_delay.maxlen) { 1362 if (final_maxlen == final_rise_delay.maxlen) {
1327 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1363 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
@@ -1342,7 +1378,7 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
1342{ 1378{
1343 struct msdc_host *host = mmc_priv(mmc); 1379 struct msdc_host *host = mmc_priv(mmc);
1344 u32 rise_delay = 0, fall_delay = 0; 1380 u32 rise_delay = 0, fall_delay = 0;
1345 struct msdc_delay_phase final_rise_delay, final_fall_delay; 1381 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1346 u8 final_delay, final_maxlen; 1382 u8 final_delay, final_maxlen;
1347 int i, ret; 1383 int i, ret;
1348 1384
@@ -1355,6 +1391,11 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
1355 if (!ret) 1391 if (!ret)
1356 rise_delay |= (1 << i); 1392 rise_delay |= (1 << i);
1357 } 1393 }
1394 final_rise_delay = get_best_delay(host, rise_delay);
1395 /* if rising edge has enough margin, then do not scan falling edge */
1396 if (final_rise_delay.maxlen >= 10 ||
1397 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1398 goto skip_fall;
1358 1399
1359 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1400 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1360 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1401 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
@@ -1365,14 +1406,10 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
1365 if (!ret) 1406 if (!ret)
1366 fall_delay |= (1 << i); 1407 fall_delay |= (1 << i);
1367 } 1408 }
1368
1369 final_rise_delay = get_best_delay(host, rise_delay);
1370 final_fall_delay = get_best_delay(host, fall_delay); 1409 final_fall_delay = get_best_delay(host, fall_delay);
1371 1410
1411skip_fall:
1372 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1412 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1373 /* Rising edge is more stable, prefer to use it */
1374 if (final_rise_delay.maxlen >= 10)
1375 final_maxlen = final_rise_delay.maxlen;
1376 if (final_maxlen == final_rise_delay.maxlen) { 1413 if (final_maxlen == final_rise_delay.maxlen) {
1377 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1414 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1378 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1415 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
@@ -1402,16 +1439,21 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1402 dev_err(host->dev, "Tune response fail!\n"); 1439 dev_err(host->dev, "Tune response fail!\n");
1403 return ret; 1440 return ret;
1404 } 1441 }
1405 ret = msdc_tune_data(mmc, opcode); 1442 if (host->hs400_mode == false) {
1406 if (ret == -EIO) 1443 ret = msdc_tune_data(mmc, opcode);
1407 dev_err(host->dev, "Tune data fail!\n"); 1444 if (ret == -EIO)
1445 dev_err(host->dev, "Tune data fail!\n");
1446 }
1408 1447
1448 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1449 host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
1409 return ret; 1450 return ret;
1410} 1451}
1411 1452
1412static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1453static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1413{ 1454{
1414 struct msdc_host *host = mmc_priv(mmc); 1455 struct msdc_host *host = mmc_priv(mmc);
1456 host->hs400_mode = true;
1415 1457
1416 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 1458 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
1417 return 0; 1459 return 0;
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index 3d1ea5e0e549..fb3ca8296273 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -1065,7 +1065,7 @@ static int mxcmci_probe(struct platform_device *pdev)
1065 1065
1066 if (pdata) 1066 if (pdata)
1067 dat3_card_detect = pdata->dat3_card_detect; 1067 dat3_card_detect = pdata->dat3_card_detect;
1068 else if (!(mmc->caps & MMC_CAP_NONREMOVABLE) 1068 else if (mmc_card_is_removable(mmc)
1069 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios")) 1069 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1070 dat3_card_detect = true; 1070 dat3_card_detect = true;
1071 1071
diff --git a/drivers/mmc/host/rtsx_pci_sdmmc.c b/drivers/mmc/host/rtsx_pci_sdmmc.c
index 93137483ecde..396c9b7e4121 100644
--- a/drivers/mmc/host/rtsx_pci_sdmmc.c
+++ b/drivers/mmc/host/rtsx_pci_sdmmc.c
@@ -38,7 +38,6 @@ struct realtek_pci_sdmmc {
38 struct rtsx_pcr *pcr; 38 struct rtsx_pcr *pcr;
39 struct mmc_host *mmc; 39 struct mmc_host *mmc;
40 struct mmc_request *mrq; 40 struct mmc_request *mrq;
41 struct workqueue_struct *workq;
42#define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq" 41#define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq"
43 42
44 struct work_struct work; 43 struct work_struct work;
@@ -244,7 +243,7 @@ static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
244 stat_idx = sd_status_index(rsp_type); 243 stat_idx = sd_status_index(rsp_type);
245 244
246 if (rsp_type == SD_RSP_TYPE_R1b) 245 if (rsp_type == SD_RSP_TYPE_R1b)
247 timeout = 3000; 246 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
248 247
249 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 248 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
250 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 249 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
@@ -885,7 +884,7 @@ static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
885 if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data)) 884 if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
886 host->using_cookie = sd_pre_dma_transfer(host, data, false); 885 host->using_cookie = sd_pre_dma_transfer(host, data, false);
887 886
888 queue_work(host->workq, &host->work); 887 schedule_work(&host->work);
889} 888}
890 889
891static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 890static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
@@ -1360,7 +1359,7 @@ static void realtek_init_host(struct realtek_pci_sdmmc *host)
1360 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1359 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1361 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1360 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1362 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 1361 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1363 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 1362 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_ERASE;
1364 mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE; 1363 mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1365 mmc->max_current_330 = 400; 1364 mmc->max_current_330 = 400;
1366 mmc->max_current_180 = 800; 1365 mmc->max_current_180 = 800;
@@ -1404,11 +1403,6 @@ static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1404 return -ENOMEM; 1403 return -ENOMEM;
1405 1404
1406 host = mmc_priv(mmc); 1405 host = mmc_priv(mmc);
1407 host->workq = create_singlethread_workqueue(SDMMC_WORKQ_NAME);
1408 if (!host->workq) {
1409 mmc_free_host(mmc);
1410 return -ENOMEM;
1411 }
1412 host->pcr = pcr; 1406 host->pcr = pcr;
1413 host->mmc = mmc; 1407 host->mmc = mmc;
1414 host->pdev = pdev; 1408 host->pdev = pdev;
@@ -1462,9 +1456,7 @@ static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1462 mmc_remove_host(mmc); 1456 mmc_remove_host(mmc);
1463 host->eject = true; 1457 host->eject = true;
1464 1458
1465 flush_workqueue(host->workq); 1459 flush_work(&host->work);
1466 destroy_workqueue(host->workq);
1467 host->workq = NULL;
1468 1460
1469 mmc_free_host(mmc); 1461 mmc_free_host(mmc);
1470 1462
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
index 39814f3dc96f..c531deef3258 100644
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -1365,7 +1365,7 @@ static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1365 .no_detect = 1, 1365 .no_detect = 1,
1366}; 1366};
1367 1367
1368#ifdef CONFIG_CPU_FREQ 1368#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1369 1369
1370static int s3cmci_cpufreq_transition(struct notifier_block *nb, 1370static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1371 unsigned long val, void *data) 1371 unsigned long val, void *data)
diff --git a/drivers/mmc/host/s3cmci.h b/drivers/mmc/host/s3cmci.h
index cc2e46cb5c64..30c2c0dd1bc8 100644
--- a/drivers/mmc/host/s3cmci.h
+++ b/drivers/mmc/host/s3cmci.h
@@ -74,7 +74,7 @@ struct s3cmci_host {
74 struct dentry *debug_regs; 74 struct dentry *debug_regs;
75#endif 75#endif
76 76
77#ifdef CONFIG_CPU_FREQ 77#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
78 struct notifier_block freq_transition; 78 struct notifier_block freq_transition;
79#endif 79#endif
80}; 80};
diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c
index 008709c5cb09..8fe0756c8e1e 100644
--- a/drivers/mmc/host/sdhci-acpi.c
+++ b/drivers/mmc/host/sdhci-acpi.c
@@ -532,11 +532,6 @@ static int sdhci_acpi_resume(struct device *dev)
532 return sdhci_resume_host(c->host); 532 return sdhci_resume_host(c->host);
533} 533}
534 534
535#else
536
537#define sdhci_acpi_suspend NULL
538#define sdhci_acpi_resume NULL
539
540#endif 535#endif
541 536
542#ifdef CONFIG_PM 537#ifdef CONFIG_PM
@@ -560,8 +555,7 @@ static int sdhci_acpi_runtime_resume(struct device *dev)
560#endif 555#endif
561 556
562static const struct dev_pm_ops sdhci_acpi_pm_ops = { 557static const struct dev_pm_ops sdhci_acpi_pm_ops = {
563 .suspend = sdhci_acpi_suspend, 558 SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume)
564 .resume = sdhci_acpi_resume,
565 SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend, 559 SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend,
566 sdhci_acpi_runtime_resume, NULL) 560 sdhci_acpi_runtime_resume, NULL)
567}; 561};
diff --git a/drivers/mmc/host/sdhci-bcm-kona.c b/drivers/mmc/host/sdhci-bcm-kona.c
index 00a8a40a3729..e5c634bdfdd9 100644
--- a/drivers/mmc/host/sdhci-bcm-kona.c
+++ b/drivers/mmc/host/sdhci-bcm-kona.c
@@ -264,12 +264,12 @@ static int sdhci_bcm_kona_probe(struct platform_device *pdev)
264 } 264 }
265 265
266 dev_dbg(dev, "non-removable=%c\n", 266 dev_dbg(dev, "non-removable=%c\n",
267 (host->mmc->caps & MMC_CAP_NONREMOVABLE) ? 'Y' : 'N'); 267 mmc_card_is_removable(host->mmc) ? 'N' : 'Y');
268 dev_dbg(dev, "cd_gpio %c, wp_gpio %c\n", 268 dev_dbg(dev, "cd_gpio %c, wp_gpio %c\n",
269 (mmc_gpio_get_cd(host->mmc) != -ENOSYS) ? 'Y' : 'N', 269 (mmc_gpio_get_cd(host->mmc) != -ENOSYS) ? 'Y' : 'N',
270 (mmc_gpio_get_ro(host->mmc) != -ENOSYS) ? 'Y' : 'N'); 270 (mmc_gpio_get_ro(host->mmc) != -ENOSYS) ? 'Y' : 'N');
271 271
272 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 272 if (!mmc_card_is_removable(host->mmc))
273 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 273 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
274 274
275 dev_dbg(dev, "is_8bit=%c\n", 275 dev_dbg(dev, "is_8bit=%c\n",
@@ -288,7 +288,7 @@ static int sdhci_bcm_kona_probe(struct platform_device *pdev)
288 } 288 }
289 289
290 /* if device is eMMC, emulate card insert right here */ 290 /* if device is eMMC, emulate card insert right here */
291 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) { 291 if (!mmc_card_is_removable(host->mmc)) {
292 ret = sdhci_bcm_kona_sd_card_emulate(host, 1); 292 ret = sdhci_bcm_kona_sd_card_emulate(host, 1);
293 if (ret) { 293 if (ret) {
294 dev_err(dev, 294 dev_err(dev,
@@ -326,7 +326,7 @@ err_pltfm_free:
326static struct platform_driver sdhci_bcm_kona_driver = { 326static struct platform_driver sdhci_bcm_kona_driver = {
327 .driver = { 327 .driver = {
328 .name = "sdhci-kona", 328 .name = "sdhci-kona",
329 .pm = SDHCI_PLTFM_PMOPS, 329 .pm = &sdhci_pltfm_pmops,
330 .of_match_table = sdhci_bcm_kona_of_match, 330 .of_match_table = sdhci_bcm_kona_of_match,
331 }, 331 },
332 .probe = sdhci_bcm_kona_probe, 332 .probe = sdhci_bcm_kona_probe,
diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c
deleted file mode 100644
index 4a6a1d1386cb..000000000000
--- a/drivers/mmc/host/sdhci-bcm2835.c
+++ /dev/null
@@ -1,204 +0,0 @@
1/*
2 * BCM2835 SDHCI
3 * Copyright (C) 2012 Stephen Warren
4 * Based on U-Boot's MMC driver for the BCM2835 by Oleksandr Tymoshenko & me
5 * Portions of the code there were obviously based on the Linux kernel at:
6 * git://github.com/raspberrypi/linux.git rpi-3.6.y
7 * commit f5b930b "Main bcm2708 linux port" signed-off-by Dom Cobley.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/delay.h>
23#include <linux/module.h>
24#include <linux/mmc/host.h>
25#include "sdhci-pltfm.h"
26
27/*
28 * 400KHz is max freq for card ID etc. Use that as min card clock. We need to
29 * know the min to enable static calculation of max BCM2835_SDHCI_WRITE_DELAY.
30 */
31#define MIN_FREQ 400000
32
33/*
34 * The Arasan has a bugette whereby it may lose the content of successive
35 * writes to registers that are within two SD-card clock cycles of each other
36 * (a clock domain crossing problem). It seems, however, that the data
37 * register does not have this problem, which is just as well - otherwise we'd
38 * have to nobble the DMA engine too.
39 *
40 * This should probably be dynamically calculated based on the actual card
41 * frequency. However, this is the longest we'll have to wait, and doesn't
42 * seem to slow access down too much, so the added complexity doesn't seem
43 * worth it for now.
44 *
45 * 1/MIN_FREQ is (max) time per tick of eMMC clock.
46 * 2/MIN_FREQ is time for two ticks.
47 * Multiply by 1000000 to get uS per two ticks.
48 * *1000000 for uSecs.
49 * +1 for hack rounding.
50 */
51#define BCM2835_SDHCI_WRITE_DELAY (((2 * 1000000) / MIN_FREQ) + 1)
52
53struct bcm2835_sdhci {
54 u32 shadow;
55};
56
57static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
58{
59 writel(val, host->ioaddr + reg);
60
61 udelay(BCM2835_SDHCI_WRITE_DELAY);
62}
63
64static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
65{
66 u32 val = readl(host->ioaddr + reg);
67
68 if (reg == SDHCI_CAPABILITIES)
69 val |= SDHCI_CAN_VDD_330;
70
71 return val;
72}
73
74static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
75{
76 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
77 struct bcm2835_sdhci *bcm2835_host = sdhci_pltfm_priv(pltfm_host);
78 u32 oldval = (reg == SDHCI_COMMAND) ? bcm2835_host->shadow :
79 bcm2835_sdhci_readl(host, reg & ~3);
80 u32 word_num = (reg >> 1) & 1;
81 u32 word_shift = word_num * 16;
82 u32 mask = 0xffff << word_shift;
83 u32 newval = (oldval & ~mask) | (val << word_shift);
84
85 if (reg == SDHCI_TRANSFER_MODE)
86 bcm2835_host->shadow = newval;
87 else
88 bcm2835_sdhci_writel(host, newval, reg & ~3);
89}
90
91static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg)
92{
93 u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
94 u32 word_num = (reg >> 1) & 1;
95 u32 word_shift = word_num * 16;
96 u32 word = (val >> word_shift) & 0xffff;
97
98 return word;
99}
100
101static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
102{
103 u32 oldval = bcm2835_sdhci_readl(host, reg & ~3);
104 u32 byte_num = reg & 3;
105 u32 byte_shift = byte_num * 8;
106 u32 mask = 0xff << byte_shift;
107 u32 newval = (oldval & ~mask) | (val << byte_shift);
108
109 bcm2835_sdhci_writel(host, newval, reg & ~3);
110}
111
112static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
113{
114 u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
115 u32 byte_num = reg & 3;
116 u32 byte_shift = byte_num * 8;
117 u32 byte = (val >> byte_shift) & 0xff;
118
119 return byte;
120}
121
122static unsigned int bcm2835_sdhci_get_min_clock(struct sdhci_host *host)
123{
124 return MIN_FREQ;
125}
126
127static const struct sdhci_ops bcm2835_sdhci_ops = {
128 .write_l = bcm2835_sdhci_writel,
129 .write_w = bcm2835_sdhci_writew,
130 .write_b = bcm2835_sdhci_writeb,
131 .read_l = bcm2835_sdhci_readl,
132 .read_w = bcm2835_sdhci_readw,
133 .read_b = bcm2835_sdhci_readb,
134 .set_clock = sdhci_set_clock,
135 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
136 .get_min_clock = bcm2835_sdhci_get_min_clock,
137 .set_bus_width = sdhci_set_bus_width,
138 .reset = sdhci_reset,
139 .set_uhs_signaling = sdhci_set_uhs_signaling,
140};
141
142static const struct sdhci_pltfm_data bcm2835_sdhci_pdata = {
143 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
144 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
145 .ops = &bcm2835_sdhci_ops,
146};
147
148static int bcm2835_sdhci_probe(struct platform_device *pdev)
149{
150 struct sdhci_host *host;
151 struct bcm2835_sdhci *bcm2835_host;
152 struct sdhci_pltfm_host *pltfm_host;
153 int ret;
154
155 host = sdhci_pltfm_init(pdev, &bcm2835_sdhci_pdata,
156 sizeof(*bcm2835_host));
157 if (IS_ERR(host))
158 return PTR_ERR(host);
159
160 pltfm_host = sdhci_priv(host);
161
162 pltfm_host->clk = devm_clk_get(&pdev->dev, NULL);
163 if (IS_ERR(pltfm_host->clk)) {
164 ret = PTR_ERR(pltfm_host->clk);
165 goto err;
166 }
167 ret = clk_prepare_enable(pltfm_host->clk);
168 if (ret) {
169 dev_err(&pdev->dev, "failed to enable host clk\n");
170 goto err;
171 }
172
173 ret = sdhci_add_host(host);
174 if (ret)
175 goto err_clk;
176
177 return 0;
178err_clk:
179 clk_disable_unprepare(pltfm_host->clk);
180err:
181 sdhci_pltfm_free(pdev);
182 return ret;
183}
184
185static const struct of_device_id bcm2835_sdhci_of_match[] = {
186 { .compatible = "brcm,bcm2835-sdhci" },
187 { }
188};
189MODULE_DEVICE_TABLE(of, bcm2835_sdhci_of_match);
190
191static struct platform_driver bcm2835_sdhci_driver = {
192 .driver = {
193 .name = "sdhci-bcm2835",
194 .of_match_table = bcm2835_sdhci_of_match,
195 .pm = SDHCI_PLTFM_PMOPS,
196 },
197 .probe = bcm2835_sdhci_probe,
198 .remove = sdhci_pltfm_unregister,
199};
200module_platform_driver(bcm2835_sdhci_driver);
201
202MODULE_DESCRIPTION("BCM2835 SDHCI driver");
203MODULE_AUTHOR("Stephen Warren");
204MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
new file mode 100644
index 000000000000..cce10fe3e19e
--- /dev/null
+++ b/drivers/mmc/host/sdhci-brcmstb.c
@@ -0,0 +1,143 @@
1/*
2 * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's
3 *
4 * Copyright (C) 2015 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/io.h>
18#include <linux/mmc/host.h>
19#include <linux/module.h>
20#include <linux/of.h>
21
22#include "sdhci-pltfm.h"
23
24#ifdef CONFIG_PM_SLEEP
25
26static int sdhci_brcmstb_suspend(struct device *dev)
27{
28 struct sdhci_host *host = dev_get_drvdata(dev);
29 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
30 int res;
31
32 res = sdhci_suspend_host(host);
33 if (res)
34 return res;
35 clk_disable_unprepare(pltfm_host->clk);
36 return res;
37}
38
39static int sdhci_brcmstb_resume(struct device *dev)
40{
41 struct sdhci_host *host = dev_get_drvdata(dev);
42 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
43 int err;
44
45 err = clk_prepare_enable(pltfm_host->clk);
46 if (err)
47 return err;
48 return sdhci_resume_host(host);
49}
50
51#endif /* CONFIG_PM_SLEEP */
52
53static SIMPLE_DEV_PM_OPS(sdhci_brcmstb_pmops, sdhci_brcmstb_suspend,
54 sdhci_brcmstb_resume);
55
56static const struct sdhci_ops sdhci_brcmstb_ops = {
57 .set_clock = sdhci_set_clock,
58 .set_bus_width = sdhci_set_bus_width,
59 .reset = sdhci_reset,
60 .set_uhs_signaling = sdhci_set_uhs_signaling,
61};
62
63static struct sdhci_pltfm_data sdhci_brcmstb_pdata = {
64 .ops = &sdhci_brcmstb_ops,
65};
66
67static int sdhci_brcmstb_probe(struct platform_device *pdev)
68{
69 struct sdhci_host *host;
70 struct sdhci_pltfm_host *pltfm_host;
71 struct clk *clk;
72 int res;
73
74 clk = devm_clk_get(&pdev->dev, NULL);
75 if (IS_ERR(clk)) {
76 dev_err(&pdev->dev, "Clock not found in Device Tree\n");
77 clk = NULL;
78 }
79 res = clk_prepare_enable(clk);
80 if (res)
81 return res;
82
83 host = sdhci_pltfm_init(pdev, &sdhci_brcmstb_pdata, 0);
84 if (IS_ERR(host)) {
85 res = PTR_ERR(host);
86 goto err_clk;
87 }
88
89 /* Enable MMC_CAP2_HC_ERASE_SZ for better max discard calculations */
90 host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
91
92 sdhci_get_of_property(pdev);
93 mmc_of_parse(host->mmc);
94
95 /*
96 * Supply the existing CAPS, but clear the UHS modes. This
97 * will allow these modes to be specified by device tree
98 * properties through mmc_of_parse().
99 */
100 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
101 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
102 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
103 SDHCI_SUPPORT_DDR50);
104 host->quirks |= SDHCI_QUIRK_MISSING_CAPS |
105 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
106
107 res = sdhci_add_host(host);
108 if (res)
109 goto err;
110
111 pltfm_host = sdhci_priv(host);
112 pltfm_host->clk = clk;
113 return res;
114
115err:
116 sdhci_pltfm_free(pdev);
117err_clk:
118 clk_disable_unprepare(clk);
119 return res;
120}
121
122static const struct of_device_id sdhci_brcm_of_match[] = {
123 { .compatible = "brcm,bcm7425-sdhci" },
124 {},
125};
126MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match);
127
128static struct platform_driver sdhci_brcmstb_driver = {
129 .driver = {
130 .name = "sdhci-brcmstb",
131 .owner = THIS_MODULE,
132 .pm = &sdhci_brcmstb_pmops,
133 .of_match_table = of_match_ptr(sdhci_brcm_of_match),
134 },
135 .probe = sdhci_brcmstb_probe,
136 .remove = sdhci_pltfm_unregister,
137};
138
139module_platform_driver(sdhci_brcmstb_driver);
140
141MODULE_DESCRIPTION("SDHCI driver for Broadcom BRCMSTB SoCs");
142MODULE_AUTHOR("Broadcom");
143MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/sdhci-cns3xxx.c b/drivers/mmc/host/sdhci-cns3xxx.c
index 59f2923f8054..bd286db7f9af 100644
--- a/drivers/mmc/host/sdhci-cns3xxx.c
+++ b/drivers/mmc/host/sdhci-cns3xxx.c
@@ -101,7 +101,7 @@ static int sdhci_cns3xxx_probe(struct platform_device *pdev)
101static struct platform_driver sdhci_cns3xxx_driver = { 101static struct platform_driver sdhci_cns3xxx_driver = {
102 .driver = { 102 .driver = {
103 .name = "sdhci-cns3xxx", 103 .name = "sdhci-cns3xxx",
104 .pm = SDHCI_PLTFM_PMOPS, 104 .pm = &sdhci_pltfm_pmops,
105 }, 105 },
106 .probe = sdhci_cns3xxx_probe, 106 .probe = sdhci_cns3xxx_probe,
107 .remove = sdhci_pltfm_unregister, 107 .remove = sdhci_pltfm_unregister,
diff --git a/drivers/mmc/host/sdhci-dove.c b/drivers/mmc/host/sdhci-dove.c
index 407c21f152b2..de9f9603dbdc 100644
--- a/drivers/mmc/host/sdhci-dove.c
+++ b/drivers/mmc/host/sdhci-dove.c
@@ -117,7 +117,7 @@ MODULE_DEVICE_TABLE(of, sdhci_dove_of_match_table);
117static struct platform_driver sdhci_dove_driver = { 117static struct platform_driver sdhci_dove_driver = {
118 .driver = { 118 .driver = {
119 .name = "sdhci-dove", 119 .name = "sdhci-dove",
120 .pm = SDHCI_PLTFM_PMOPS, 120 .pm = &sdhci_pltfm_pmops,
121 .of_match_table = sdhci_dove_of_match_table, 121 .of_match_table = sdhci_dove_of_match_table,
122 }, 122 },
123 .probe = sdhci_dove_probe, 123 .probe = sdhci_dove_probe,
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 9d3ae1f4bd3c..99e0b334f9df 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -39,11 +39,13 @@
39#define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 39#define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
40#define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 40#define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
41#define ESDHC_WTMK_LVL 0x44 41#define ESDHC_WTMK_LVL 0x44
42#define ESDHC_WTMK_DEFAULT_VAL 0x10401040
42#define ESDHC_MIX_CTRL 0x48 43#define ESDHC_MIX_CTRL 0x48
43#define ESDHC_MIX_CTRL_DDREN (1 << 3) 44#define ESDHC_MIX_CTRL_DDREN (1 << 3)
44#define ESDHC_MIX_CTRL_AC23EN (1 << 7) 45#define ESDHC_MIX_CTRL_AC23EN (1 << 7)
45#define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 46#define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
46#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 47#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
48#define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
47#define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 49#define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
48#define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 50#define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
49/* Bits 3 and 6 are not SDHCI standard definitions */ 51/* Bits 3 and 6 are not SDHCI standard definitions */
@@ -75,7 +77,8 @@
75#define ESDHC_TUNING_CTRL 0xcc 77#define ESDHC_TUNING_CTRL 0xcc
76#define ESDHC_STD_TUNING_EN (1 << 24) 78#define ESDHC_STD_TUNING_EN (1 << 24)
77/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 79/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
78#define ESDHC_TUNING_START_TAP 0x1 80#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
81#define ESDHC_TUNING_START_TAP_MASK 0xff
79#define ESDHC_TUNING_STEP_MASK 0x00070000 82#define ESDHC_TUNING_STEP_MASK 0x00070000
80#define ESDHC_TUNING_STEP_SHIFT 16 83#define ESDHC_TUNING_STEP_SHIFT 16
81 84
@@ -299,7 +302,8 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
299 /* imx6q/dl does not have cap_1 register, fake one */ 302 /* imx6q/dl does not have cap_1 register, fake one */
300 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 303 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
301 | SDHCI_SUPPORT_SDR50 304 | SDHCI_SUPPORT_SDR50
302 | SDHCI_USE_SDR50_TUNING; 305 | SDHCI_USE_SDR50_TUNING
306 | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
303 307
304 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 308 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
305 val |= SDHCI_SUPPORT_HS400; 309 val |= SDHCI_SUPPORT_HS400;
@@ -469,32 +473,29 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
469 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 473 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
470 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 474 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
471 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 475 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
472 if (val & SDHCI_CTRL_TUNED_CLK) 476 if (val & SDHCI_CTRL_TUNED_CLK) {
473 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 477 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
474 else 478 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
479 } else {
475 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 480 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
481 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
482 }
476 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 483 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
477 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 484 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
478 u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); 485 u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
479 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 486 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
480 u32 tuning_ctrl;
481 if (val & SDHCI_CTRL_TUNED_CLK) { 487 if (val & SDHCI_CTRL_TUNED_CLK) {
482 v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 488 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
483 } else { 489 } else {
484 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 490 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
485 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 491 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
492 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
486 } 493 }
487 494
488 if (val & SDHCI_CTRL_EXEC_TUNING) { 495 if (val & SDHCI_CTRL_EXEC_TUNING) {
489 v |= ESDHC_MIX_CTRL_EXE_TUNE; 496 v |= ESDHC_MIX_CTRL_EXE_TUNE;
490 m |= ESDHC_MIX_CTRL_FBCLK_SEL; 497 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
491 tuning_ctrl = readl(host->ioaddr + ESDHC_TUNING_CTRL); 498 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
492 tuning_ctrl |= ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP;
493 if (imx_data->boarddata.tuning_step) {
494 tuning_ctrl &= ~ESDHC_TUNING_STEP_MASK;
495 tuning_ctrl |= imx_data->boarddata.tuning_step << ESDHC_TUNING_STEP_SHIFT;
496 }
497 writel(tuning_ctrl, host->ioaddr + ESDHC_TUNING_CTRL);
498 } else { 499 } else {
499 v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 500 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
500 } 501 }
@@ -751,6 +752,7 @@ static void esdhc_post_tuning(struct sdhci_host *host)
751 752
752 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 753 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
753 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 754 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
755 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
754 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 756 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
755} 757}
756 758
@@ -838,6 +840,11 @@ static void esdhc_set_strobe_dll(struct sdhci_host *host)
838 u32 v; 840 u32 v;
839 841
840 if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) { 842 if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
843 /* disable clock before enabling strobe dll */
844 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
845 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
846 host->ioaddr + ESDHC_VENDOR_SPEC);
847
841 /* force a reset on strobe dll */ 848 /* force a reset on strobe dll */
842 writel(ESDHC_STROBE_DLL_CTRL_RESET, 849 writel(ESDHC_STROBE_DLL_CTRL_RESET,
843 host->ioaddr + ESDHC_STROBE_DLL_CTRL); 850 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
@@ -899,6 +906,8 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
899 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 906 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
900 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 907 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
901 imx_data->is_ddr = 1; 908 imx_data->is_ddr = 1;
909 /* update clock after enable DDR for strobe DLL lock */
910 host->ops->set_clock(host, host->clock);
902 esdhc_set_strobe_dll(host); 911 esdhc_set_strobe_dll(host);
903 break; 912 break;
904 } 913 }
@@ -957,6 +966,62 @@ static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
957 .ops = &sdhci_esdhc_ops, 966 .ops = &sdhci_esdhc_ops,
958}; 967};
959 968
969static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
970{
971 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
972 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
973 int tmp;
974
975 if (esdhc_is_usdhc(imx_data)) {
976 /*
977 * The imx6q ROM code will change the default watermark
978 * level setting to something insane. Change it back here.
979 */
980 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
981
982 /*
983 * ROM code will change the bit burst_length_enable setting
984 * to zero if this usdhc is choosed to boot system. Change
985 * it back here, otherwise it will impact the performance a
986 * lot. This bit is used to enable/disable the burst length
987 * for the external AHB2AXI bridge, it's usefully especially
988 * for INCR transfer because without burst length indicator,
989 * the AHB2AXI bridge does not know the burst length in
990 * advance. And without burst length indicator, AHB INCR
991 * transfer can only be converted to singles on the AXI side.
992 */
993 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
994 | ESDHC_BURST_LEN_EN_INCR,
995 host->ioaddr + SDHCI_HOST_CONTROL);
996 /*
997 * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
998 * TO1.1, it's harmless for MX6SL
999 */
1000 writel(readl(host->ioaddr + 0x6c) | BIT(7),
1001 host->ioaddr + 0x6c);
1002
1003 /* disable DLL_CTRL delay line settings */
1004 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1005
1006 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1007 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1008 tmp |= ESDHC_STD_TUNING_EN |
1009 ESDHC_TUNING_START_TAP_DEFAULT;
1010 if (imx_data->boarddata.tuning_start_tap) {
1011 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1012 tmp |= imx_data->boarddata.tuning_start_tap;
1013 }
1014
1015 if (imx_data->boarddata.tuning_step) {
1016 tmp &= ~ESDHC_TUNING_STEP_MASK;
1017 tmp |= imx_data->boarddata.tuning_step
1018 << ESDHC_TUNING_STEP_SHIFT;
1019 }
1020 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1021 }
1022 }
1023}
1024
960#ifdef CONFIG_OF 1025#ifdef CONFIG_OF
961static int 1026static int
962sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 1027sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
@@ -975,6 +1040,8 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
975 boarddata->wp_type = ESDHC_WP_GPIO; 1040 boarddata->wp_type = ESDHC_WP_GPIO;
976 1041
977 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1042 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1043 of_property_read_u32(np, "fsl,tuning-start-tap",
1044 &boarddata->tuning_start_tap);
978 1045
979 if (of_find_property(np, "no-1-8-v", NULL)) 1046 if (of_find_property(np, "no-1-8-v", NULL))
980 boarddata->support_vsel = false; 1047 boarddata->support_vsel = false;
@@ -1147,58 +1214,27 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1147 if (IS_ERR(imx_data->pins_default)) 1214 if (IS_ERR(imx_data->pins_default))
1148 dev_warn(mmc_dev(host->mmc), "could not get default state\n"); 1215 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1149 1216
1150 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1151
1152 if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) 1217 if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
1153 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 1218 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
1154 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 1219 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1155 | SDHCI_QUIRK_BROKEN_ADMA; 1220 | SDHCI_QUIRK_BROKEN_ADMA;
1156 1221
1157 /*
1158 * The imx6q ROM code will change the default watermark level setting
1159 * to something insane. Change it back here.
1160 */
1161 if (esdhc_is_usdhc(imx_data)) { 1222 if (esdhc_is_usdhc(imx_data)) {
1162 writel(0x10401040, host->ioaddr + ESDHC_WTMK_LVL);
1163
1164 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1223 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1165 host->mmc->caps |= MMC_CAP_1_8V_DDR; 1224 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1166
1167 /*
1168 * ROM code will change the bit burst_length_enable setting
1169 * to zero if this usdhc is choosed to boot system. Change
1170 * it back here, otherwise it will impact the performance a
1171 * lot. This bit is used to enable/disable the burst length
1172 * for the external AHB2AXI bridge, it's usefully especially
1173 * for INCR transfer because without burst length indicator,
1174 * the AHB2AXI bridge does not know the burst length in
1175 * advance. And without burst length indicator, AHB INCR
1176 * transfer can only be converted to singles on the AXI side.
1177 */
1178 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1179 | ESDHC_BURST_LEN_EN_INCR,
1180 host->ioaddr + SDHCI_HOST_CONTROL);
1181
1182 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 1225 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1183 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1226 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1184 1227
1185 /* 1228 /* clear tuning bits in case ROM has set it already */
1186 * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1229 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1187 * TO1.1, it's harmless for MX6SL 1230 writel(0x0, host->ioaddr + SDHCI_ACMD12_ERR);
1188 */ 1231 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1189 writel(readl(host->ioaddr + 0x6c) | BIT(7),
1190 host->ioaddr + 0x6c);
1191 } 1232 }
1192 1233
1193 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 1234 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1194 sdhci_esdhc_ops.platform_execute_tuning = 1235 sdhci_esdhc_ops.platform_execute_tuning =
1195 esdhc_executing_tuning; 1236 esdhc_executing_tuning;
1196 1237
1197 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
1198 writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
1199 ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
1200 host->ioaddr + ESDHC_TUNING_CTRL);
1201
1202 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 1238 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1203 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1239 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1204 1240
@@ -1212,6 +1248,8 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1212 if (err) 1248 if (err)
1213 goto disable_clk; 1249 goto disable_clk;
1214 1250
1251 sdhci_esdhc_imx_hwinit(host);
1252
1215 err = sdhci_add_host(host); 1253 err = sdhci_add_host(host);
1216 if (err) 1254 if (err)
1217 goto disable_clk; 1255 goto disable_clk;
@@ -1255,6 +1293,25 @@ static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1255 return 0; 1293 return 0;
1256} 1294}
1257 1295
1296#ifdef CONFIG_PM_SLEEP
1297static int sdhci_esdhc_suspend(struct device *dev)
1298{
1299 struct sdhci_host *host = dev_get_drvdata(dev);
1300
1301 return sdhci_suspend_host(host);
1302}
1303
1304static int sdhci_esdhc_resume(struct device *dev)
1305{
1306 struct sdhci_host *host = dev_get_drvdata(dev);
1307
1308 /* re-initialize hw state in case it's lost in low power mode */
1309 sdhci_esdhc_imx_hwinit(host);
1310
1311 return sdhci_resume_host(host);
1312}
1313#endif
1314
1258#ifdef CONFIG_PM 1315#ifdef CONFIG_PM
1259static int sdhci_esdhc_runtime_suspend(struct device *dev) 1316static int sdhci_esdhc_runtime_suspend(struct device *dev)
1260{ 1317{
@@ -1291,7 +1348,7 @@ static int sdhci_esdhc_runtime_resume(struct device *dev)
1291#endif 1348#endif
1292 1349
1293static const struct dev_pm_ops sdhci_esdhc_pmops = { 1350static const struct dev_pm_ops sdhci_esdhc_pmops = {
1294 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume) 1351 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1295 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 1352 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1296 sdhci_esdhc_runtime_resume, NULL) 1353 sdhci_esdhc_runtime_resume, NULL)
1297}; 1354};
diff --git a/drivers/mmc/host/sdhci-iproc.c b/drivers/mmc/host/sdhci-iproc.c
index 1110f73b08aa..726246665850 100644
--- a/drivers/mmc/host/sdhci-iproc.c
+++ b/drivers/mmc/host/sdhci-iproc.c
@@ -164,8 +164,17 @@ static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
164 164
165static const struct sdhci_iproc_data iproc_data = { 165static const struct sdhci_iproc_data iproc_data = {
166 .pdata = &sdhci_iproc_pltfm_data, 166 .pdata = &sdhci_iproc_pltfm_data,
167 .caps = 0x05E90000, 167 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
168 .caps1 = 0x00000064, 168 & SDHCI_MAX_BLOCK_MASK) |
169 SDHCI_CAN_VDD_330 |
170 SDHCI_CAN_VDD_180 |
171 SDHCI_CAN_DO_SUSPEND |
172 SDHCI_CAN_DO_HISPD |
173 SDHCI_CAN_DO_ADMA2 |
174 SDHCI_CAN_DO_SDMA,
175 .caps1 = SDHCI_DRIVER_TYPE_C |
176 SDHCI_DRIVER_TYPE_D |
177 SDHCI_SUPPORT_DDR50,
169 .mmc_caps = MMC_CAP_1_8V_DDR, 178 .mmc_caps = MMC_CAP_1_8V_DDR,
170}; 179};
171 180
@@ -251,7 +260,7 @@ static struct platform_driver sdhci_iproc_driver = {
251 .driver = { 260 .driver = {
252 .name = "sdhci-iproc", 261 .name = "sdhci-iproc",
253 .of_match_table = sdhci_iproc_of_match, 262 .of_match_table = sdhci_iproc_of_match,
254 .pm = SDHCI_PLTFM_PMOPS, 263 .pm = &sdhci_pltfm_pmops,
255 }, 264 },
256 .probe = sdhci_iproc_probe, 265 .probe = sdhci_iproc_probe,
257 .remove = sdhci_pltfm_unregister, 266 .remove = sdhci_pltfm_unregister,
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 0653fe730150..8ef44a2a2fd9 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -32,6 +32,21 @@
32#define CORE_POWER 0x0 32#define CORE_POWER 0x0
33#define CORE_SW_RST BIT(7) 33#define CORE_SW_RST BIT(7)
34 34
35#define CORE_PWRCTL_STATUS 0xdc
36#define CORE_PWRCTL_MASK 0xe0
37#define CORE_PWRCTL_CLEAR 0xe4
38#define CORE_PWRCTL_CTL 0xe8
39#define CORE_PWRCTL_BUS_OFF BIT(0)
40#define CORE_PWRCTL_BUS_ON BIT(1)
41#define CORE_PWRCTL_IO_LOW BIT(2)
42#define CORE_PWRCTL_IO_HIGH BIT(3)
43#define CORE_PWRCTL_BUS_SUCCESS BIT(0)
44#define CORE_PWRCTL_IO_SUCCESS BIT(2)
45#define REQ_BUS_OFF BIT(0)
46#define REQ_BUS_ON BIT(1)
47#define REQ_IO_LOW BIT(2)
48#define REQ_IO_HIGH BIT(3)
49#define INT_MASK 0xf
35#define MAX_PHASES 16 50#define MAX_PHASES 16
36#define CORE_DLL_LOCK BIT(7) 51#define CORE_DLL_LOCK BIT(7)
37#define CORE_DLL_EN BIT(16) 52#define CORE_DLL_EN BIT(16)
@@ -56,6 +71,7 @@
56struct sdhci_msm_host { 71struct sdhci_msm_host {
57 struct platform_device *pdev; 72 struct platform_device *pdev;
58 void __iomem *core_mem; /* MSM SDCC mapped address */ 73 void __iomem *core_mem; /* MSM SDCC mapped address */
74 int pwr_irq; /* power irq */
59 struct clk *clk; /* main SD/MMC bus clock */ 75 struct clk *clk; /* main SD/MMC bus clock */
60 struct clk *pclk; /* SDHC peripheral bus clock */ 76 struct clk *pclk; /* SDHC peripheral bus clock */
61 struct clk *bus_clk; /* SDHC bus voter clock */ 77 struct clk *bus_clk; /* SDHC bus voter clock */
@@ -410,6 +426,85 @@ retry:
410 return rc; 426 return rc;
411} 427}
412 428
429static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
430 unsigned int uhs)
431{
432 struct mmc_host *mmc = host->mmc;
433 u16 ctrl_2;
434
435 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
436 /* Select Bus Speed Mode for host */
437 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
438 switch (uhs) {
439 case MMC_TIMING_UHS_SDR12:
440 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
441 break;
442 case MMC_TIMING_UHS_SDR25:
443 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
444 break;
445 case MMC_TIMING_UHS_SDR50:
446 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
447 break;
448 case MMC_TIMING_MMC_HS200:
449 case MMC_TIMING_UHS_SDR104:
450 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
451 break;
452 case MMC_TIMING_UHS_DDR50:
453 case MMC_TIMING_MMC_DDR52:
454 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
455 break;
456 }
457
458 /*
459 * When clock frequency is less than 100MHz, the feedback clock must be
460 * provided and DLL must not be used so that tuning can be skipped. To
461 * provide feedback clock, the mode selection can be any value less
462 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
463 */
464 if (host->clock <= 100000000 &&
465 (uhs == MMC_TIMING_MMC_HS400 ||
466 uhs == MMC_TIMING_MMC_HS200 ||
467 uhs == MMC_TIMING_UHS_SDR104))
468 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
469
470 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
471 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
472 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
473}
474
475static void sdhci_msm_voltage_switch(struct sdhci_host *host)
476{
477 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
478 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
479 u32 irq_status, irq_ack = 0;
480
481 irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);
482 irq_status &= INT_MASK;
483
484 writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR);
485
486 if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF))
487 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
488 if (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH))
489 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
490
491 /*
492 * The driver has to acknowledge the interrupt, switch voltages and
493 * report back if it succeded or not to this register. The voltage
494 * switches are handled by the sdhci core, so just report success.
495 */
496 writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);
497}
498
499static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
500{
501 struct sdhci_host *host = (struct sdhci_host *)data;
502
503 sdhci_msm_voltage_switch(host);
504
505 return IRQ_HANDLED;
506}
507
413static const struct of_device_id sdhci_msm_dt_match[] = { 508static const struct of_device_id sdhci_msm_dt_match[] = {
414 { .compatible = "qcom,sdhci-msm-v4" }, 509 { .compatible = "qcom,sdhci-msm-v4" },
415 {}, 510 {},
@@ -422,11 +517,13 @@ static const struct sdhci_ops sdhci_msm_ops = {
422 .reset = sdhci_reset, 517 .reset = sdhci_reset,
423 .set_clock = sdhci_set_clock, 518 .set_clock = sdhci_set_clock,
424 .set_bus_width = sdhci_set_bus_width, 519 .set_bus_width = sdhci_set_bus_width,
425 .set_uhs_signaling = sdhci_set_uhs_signaling, 520 .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
521 .voltage_switch = sdhci_msm_voltage_switch,
426}; 522};
427 523
428static const struct sdhci_pltfm_data sdhci_msm_pdata = { 524static const struct sdhci_pltfm_data sdhci_msm_pdata = {
429 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 525 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
526 SDHCI_QUIRK_NO_CARD_NO_RESET |
430 SDHCI_QUIRK_SINGLE_POWER_WRITE, 527 SDHCI_QUIRK_SINGLE_POWER_WRITE,
431 .ops = &sdhci_msm_ops, 528 .ops = &sdhci_msm_ops,
432}; 529};
@@ -473,7 +570,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
473 msm_host->pclk = devm_clk_get(&pdev->dev, "iface"); 570 msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
474 if (IS_ERR(msm_host->pclk)) { 571 if (IS_ERR(msm_host->pclk)) {
475 ret = PTR_ERR(msm_host->pclk); 572 ret = PTR_ERR(msm_host->pclk);
476 dev_err(&pdev->dev, "Perpheral clk setup failed (%d)\n", ret); 573 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
477 goto bus_clk_disable; 574 goto bus_clk_disable;
478 } 575 }
479 576
@@ -545,6 +642,22 @@ static int sdhci_msm_probe(struct platform_device *pdev)
545 CORE_VENDOR_SPEC_CAPABILITIES0); 642 CORE_VENDOR_SPEC_CAPABILITIES0);
546 } 643 }
547 644
645 /* Setup IRQ for handling power/voltage tasks with PMIC */
646 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
647 if (msm_host->pwr_irq < 0) {
648 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n",
649 msm_host->pwr_irq);
650 goto clk_disable;
651 }
652
653 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
654 sdhci_msm_pwr_irq, IRQF_ONESHOT,
655 dev_name(&pdev->dev), host);
656 if (ret) {
657 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
658 goto clk_disable;
659 }
660
548 ret = sdhci_add_host(host); 661 ret = sdhci_add_host(host);
549 if (ret) 662 if (ret)
550 goto clk_disable; 663 goto clk_disable;
diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index b6f4c1d41636..e0f193f7e3e5 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -19,27 +19,136 @@
19 * your option) any later version. 19 * your option) any later version.
20 */ 20 */
21 21
22#include <linux/clk-provider.h>
23#include <linux/mfd/syscon.h>
22#include <linux/module.h> 24#include <linux/module.h>
23#include <linux/of_device.h> 25#include <linux/of_device.h>
24#include <linux/phy/phy.h> 26#include <linux/phy/phy.h>
27#include <linux/regmap.h>
25#include "sdhci-pltfm.h" 28#include "sdhci-pltfm.h"
26 29
27#define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c 30#define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c
31#define SDHCI_ARASAN_VENDOR_REGISTER 0x78
28 32
33#define VENDOR_ENHANCED_STROBE BIT(0)
29#define CLK_CTRL_TIMEOUT_SHIFT 16 34#define CLK_CTRL_TIMEOUT_SHIFT 16
30#define CLK_CTRL_TIMEOUT_MASK (0xf << CLK_CTRL_TIMEOUT_SHIFT) 35#define CLK_CTRL_TIMEOUT_MASK (0xf << CLK_CTRL_TIMEOUT_SHIFT)
31#define CLK_CTRL_TIMEOUT_MIN_EXP 13 36#define CLK_CTRL_TIMEOUT_MIN_EXP 13
32 37
38/*
39 * On some SoCs the syscon area has a feature where the upper 16-bits of
40 * each 32-bit register act as a write mask for the lower 16-bits. This allows
41 * atomic updates of the register without locking. This macro is used on SoCs
42 * that have that feature.
43 */
44#define HIWORD_UPDATE(val, mask, shift) \
45 ((val) << (shift) | (mask) << ((shift) + 16))
46
47/**
48 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
49 *
50 * @reg: Offset within the syscon of the register containing this field
51 * @width: Number of bits for this field
52 * @shift: Bit offset within @reg of this field (or -1 if not avail)
53 */
54struct sdhci_arasan_soc_ctl_field {
55 u32 reg;
56 u16 width;
57 s16 shift;
58};
59
60/**
61 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
62 *
63 * It's up to the licensee of the Arsan IP block to make these available
64 * somewhere if needed. Presumably these will be scattered somewhere that's
65 * accessible via the syscon API.
66 *
67 * @baseclkfreq: Where to find corecfg_baseclkfreq
68 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
69 */
70struct sdhci_arasan_soc_ctl_map {
71 struct sdhci_arasan_soc_ctl_field baseclkfreq;
72 bool hiword_update;
73};
74
33/** 75/**
34 * struct sdhci_arasan_data 76 * struct sdhci_arasan_data
35 * @clk_ahb: Pointer to the AHB clock 77 * @host: Pointer to the main SDHCI host structure.
36 * @phy: Pointer to the generic phy 78 * @clk_ahb: Pointer to the AHB clock
79 * @phy: Pointer to the generic phy
80 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
81 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
82 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
83 * @soc_ctl_map: Map to get offsets into soc_ctl registers.
37 */ 84 */
38struct sdhci_arasan_data { 85struct sdhci_arasan_data {
86 struct sdhci_host *host;
39 struct clk *clk_ahb; 87 struct clk *clk_ahb;
40 struct phy *phy; 88 struct phy *phy;
89
90 struct clk_hw sdcardclk_hw;
91 struct clk *sdcardclk;
92
93 struct regmap *soc_ctl_base;
94 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
95};
96
97static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
98 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
99 .hiword_update = true,
41}; 100};
42 101
102/**
103 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
104 *
105 * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
106 * Note that if a field is specified as not available (shift < 0) then
107 * this function will silently return an error code. It will be noisy
108 * and print errors for any other (unexpected) errors.
109 *
110 * @host: The sdhci_host
111 * @fld: The field to write to
112 * @val: The value to write
113 */
114static int sdhci_arasan_syscon_write(struct sdhci_host *host,
115 const struct sdhci_arasan_soc_ctl_field *fld,
116 u32 val)
117{
118 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
119 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
120 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
121 u32 reg = fld->reg;
122 u16 width = fld->width;
123 s16 shift = fld->shift;
124 int ret;
125
126 /*
127 * Silently return errors for shift < 0 so caller doesn't have
128 * to check for fields which are optional. For fields that
129 * are required then caller needs to do something special
130 * anyway.
131 */
132 if (shift < 0)
133 return -EINVAL;
134
135 if (sdhci_arasan->soc_ctl_map->hiword_update)
136 ret = regmap_write(soc_ctl_base, reg,
137 HIWORD_UPDATE(val, GENMASK(width, 0),
138 shift));
139 else
140 ret = regmap_update_bits(soc_ctl_base, reg,
141 GENMASK(shift + width, shift),
142 val << shift);
143
144 /* Yell about (unexpected) regmap errors */
145 if (ret)
146 pr_warn("%s: Regmap write fail: %d\n",
147 mmc_hostname(host->mmc), ret);
148
149 return ret;
150}
151
43static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host) 152static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
44{ 153{
45 u32 div; 154 u32 div;
@@ -79,6 +188,21 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
79 } 188 }
80} 189}
81 190
191static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
192 struct mmc_ios *ios)
193{
194 u32 vendor;
195 struct sdhci_host *host = mmc_priv(mmc);
196
197 vendor = readl(host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
198 if (ios->enhanced_strobe)
199 vendor |= VENDOR_ENHANCED_STROBE;
200 else
201 vendor &= ~VENDOR_ENHANCED_STROBE;
202
203 writel(vendor, host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
204}
205
82static struct sdhci_ops sdhci_arasan_ops = { 206static struct sdhci_ops sdhci_arasan_ops = {
83 .set_clock = sdhci_arasan_set_clock, 207 .set_clock = sdhci_arasan_set_clock,
84 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 208 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
@@ -172,9 +296,168 @@ static int sdhci_arasan_resume(struct device *dev)
172static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, 296static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
173 sdhci_arasan_resume); 297 sdhci_arasan_resume);
174 298
299static const struct of_device_id sdhci_arasan_of_match[] = {
300 /* SoC-specific compatible strings w/ soc_ctl_map */
301 {
302 .compatible = "rockchip,rk3399-sdhci-5.1",
303 .data = &rk3399_soc_ctl_map,
304 },
305
306 /* Generic compatible below here */
307 { .compatible = "arasan,sdhci-8.9a" },
308 { .compatible = "arasan,sdhci-5.1" },
309 { .compatible = "arasan,sdhci-4.9a" },
310
311 { /* sentinel */ }
312};
313MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
314
315/**
316 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
317 *
318 * Return the current actual rate of the SD card clock. This can be used
319 * to communicate with out PHY.
320 *
321 * @hw: Pointer to the hardware clock structure.
322 * @parent_rate The parent rate (should be rate of clk_xin).
323 * Returns the card clock rate.
324 */
325static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
326 unsigned long parent_rate)
327
328{
329 struct sdhci_arasan_data *sdhci_arasan =
330 container_of(hw, struct sdhci_arasan_data, sdcardclk_hw);
331 struct sdhci_host *host = sdhci_arasan->host;
332
333 return host->mmc->actual_clock;
334}
335
336static const struct clk_ops arasan_sdcardclk_ops = {
337 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
338};
339
340/**
341 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
342 *
343 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
344 * function can be used to make that happen.
345 *
346 * NOTES:
347 * - Many existing devices don't seem to do this and work fine. To keep
348 * compatibility for old hardware where the device tree doesn't provide a
349 * register map, this function is a noop if a soc_ctl_map hasn't been provided
350 * for this platform.
351 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
352 * to achieve lower clock rates. That means that this function is called once
353 * at probe time and never called again.
354 *
355 * @host: The sdhci_host
356 */
357static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
358{
359 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
360 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
361 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
362 sdhci_arasan->soc_ctl_map;
363 u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
364
365 /* Having a map is optional */
366 if (!soc_ctl_map)
367 return;
368
369 /* If we have a map, we expect to have a syscon */
370 if (!sdhci_arasan->soc_ctl_base) {
371 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
372 mmc_hostname(host->mmc));
373 return;
374 }
375
376 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
377}
378
379/**
380 * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use
381 *
382 * Some PHY devices need to know what the actual card clock is. In order for
383 * them to find out, we'll provide a clock through the common clock framework
384 * for them to query.
385 *
386 * Note: without seriously re-architecting SDHCI's clock code and testing on
387 * all platforms, there's no way to create a totally beautiful clock here
388 * with all clock ops implemented. Instead, we'll just create a clock that can
389 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
390 * framework that we're doing things behind its back. This should be sufficient
391 * to create nice clean device tree bindings and later (if needed) we can try
392 * re-architecting SDHCI if we see some benefit to it.
393 *
394 * @sdhci_arasan: Our private data structure.
395 * @clk_xin: Pointer to the functional clock
396 * @dev: Pointer to our struct device.
397 * Returns 0 on success and error value on error
398 */
399static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
400 struct clk *clk_xin,
401 struct device *dev)
402{
403 struct device_node *np = dev->of_node;
404 struct clk_init_data sdcardclk_init;
405 const char *parent_clk_name;
406 int ret;
407
408 /* Providing a clock to the PHY is optional; no error if missing */
409 if (!of_find_property(np, "#clock-cells", NULL))
410 return 0;
411
412 ret = of_property_read_string_index(np, "clock-output-names", 0,
413 &sdcardclk_init.name);
414 if (ret) {
415 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
416 return ret;
417 }
418
419 parent_clk_name = __clk_get_name(clk_xin);
420 sdcardclk_init.parent_names = &parent_clk_name;
421 sdcardclk_init.num_parents = 1;
422 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
423 sdcardclk_init.ops = &arasan_sdcardclk_ops;
424
425 sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init;
426 sdhci_arasan->sdcardclk =
427 devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw);
428 sdhci_arasan->sdcardclk_hw.init = NULL;
429
430 ret = of_clk_add_provider(np, of_clk_src_simple_get,
431 sdhci_arasan->sdcardclk);
432 if (ret)
433 dev_err(dev, "Failed to add clock provider\n");
434
435 return ret;
436}
437
438/**
439 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
440 *
441 * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
442 * returned success.
443 *
444 * @dev: Pointer to our struct device.
445 */
446static void sdhci_arasan_unregister_sdclk(struct device *dev)
447{
448 struct device_node *np = dev->of_node;
449
450 if (!of_find_property(np, "#clock-cells", NULL))
451 return;
452
453 of_clk_del_provider(dev->of_node);
454}
455
175static int sdhci_arasan_probe(struct platform_device *pdev) 456static int sdhci_arasan_probe(struct platform_device *pdev)
176{ 457{
177 int ret; 458 int ret;
459 const struct of_device_id *match;
460 struct device_node *node;
178 struct clk *clk_xin; 461 struct clk *clk_xin;
179 struct sdhci_host *host; 462 struct sdhci_host *host;
180 struct sdhci_pltfm_host *pltfm_host; 463 struct sdhci_pltfm_host *pltfm_host;
@@ -187,6 +470,24 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
187 470
188 pltfm_host = sdhci_priv(host); 471 pltfm_host = sdhci_priv(host);
189 sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 472 sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
473 sdhci_arasan->host = host;
474
475 match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
476 sdhci_arasan->soc_ctl_map = match->data;
477
478 node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
479 if (node) {
480 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
481 of_node_put(node);
482
483 if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
484 ret = PTR_ERR(sdhci_arasan->soc_ctl_base);
485 if (ret != -EPROBE_DEFER)
486 dev_err(&pdev->dev, "Can't get syscon: %d\n",
487 ret);
488 goto err_pltfm_free;
489 }
490 }
190 491
191 sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); 492 sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
192 if (IS_ERR(sdhci_arasan->clk_ahb)) { 493 if (IS_ERR(sdhci_arasan->clk_ahb)) {
@@ -217,10 +518,16 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
217 sdhci_get_of_property(pdev); 518 sdhci_get_of_property(pdev);
218 pltfm_host->clk = clk_xin; 519 pltfm_host->clk = clk_xin;
219 520
521 sdhci_arasan_update_baseclkfreq(host);
522
523 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
524 if (ret)
525 goto clk_disable_all;
526
220 ret = mmc_of_parse(host->mmc); 527 ret = mmc_of_parse(host->mmc);
221 if (ret) { 528 if (ret) {
222 dev_err(&pdev->dev, "parsing dt failed (%u)\n", ret); 529 dev_err(&pdev->dev, "parsing dt failed (%u)\n", ret);
223 goto clk_disable_all; 530 goto unreg_clk;
224 } 531 }
225 532
226 sdhci_arasan->phy = ERR_PTR(-ENODEV); 533 sdhci_arasan->phy = ERR_PTR(-ENODEV);
@@ -231,13 +538,13 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
231 if (IS_ERR(sdhci_arasan->phy)) { 538 if (IS_ERR(sdhci_arasan->phy)) {
232 ret = PTR_ERR(sdhci_arasan->phy); 539 ret = PTR_ERR(sdhci_arasan->phy);
233 dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); 540 dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
234 goto clk_disable_all; 541 goto unreg_clk;
235 } 542 }
236 543
237 ret = phy_init(sdhci_arasan->phy); 544 ret = phy_init(sdhci_arasan->phy);
238 if (ret < 0) { 545 if (ret < 0) {
239 dev_err(&pdev->dev, "phy_init err.\n"); 546 dev_err(&pdev->dev, "phy_init err.\n");
240 goto clk_disable_all; 547 goto unreg_clk;
241 } 548 }
242 549
243 ret = phy_power_on(sdhci_arasan->phy); 550 ret = phy_power_on(sdhci_arasan->phy);
@@ -245,6 +552,9 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
245 dev_err(&pdev->dev, "phy_power_on err.\n"); 552 dev_err(&pdev->dev, "phy_power_on err.\n");
246 goto err_phy_power; 553 goto err_phy_power;
247 } 554 }
555
556 host->mmc_host_ops.hs400_enhanced_strobe =
557 sdhci_arasan_hs400_enhanced_strobe;
248 } 558 }
249 559
250 ret = sdhci_add_host(host); 560 ret = sdhci_add_host(host);
@@ -259,6 +569,8 @@ err_add_host:
259err_phy_power: 569err_phy_power:
260 if (!IS_ERR(sdhci_arasan->phy)) 570 if (!IS_ERR(sdhci_arasan->phy))
261 phy_exit(sdhci_arasan->phy); 571 phy_exit(sdhci_arasan->phy);
572unreg_clk:
573 sdhci_arasan_unregister_sdclk(&pdev->dev);
262clk_disable_all: 574clk_disable_all:
263 clk_disable_unprepare(clk_xin); 575 clk_disable_unprepare(clk_xin);
264clk_dis_ahb: 576clk_dis_ahb:
@@ -281,6 +593,8 @@ static int sdhci_arasan_remove(struct platform_device *pdev)
281 phy_exit(sdhci_arasan->phy); 593 phy_exit(sdhci_arasan->phy);
282 } 594 }
283 595
596 sdhci_arasan_unregister_sdclk(&pdev->dev);
597
284 ret = sdhci_pltfm_unregister(pdev); 598 ret = sdhci_pltfm_unregister(pdev);
285 599
286 clk_disable_unprepare(clk_ahb); 600 clk_disable_unprepare(clk_ahb);
@@ -288,14 +602,6 @@ static int sdhci_arasan_remove(struct platform_device *pdev)
288 return ret; 602 return ret;
289} 603}
290 604
291static const struct of_device_id sdhci_arasan_of_match[] = {
292 { .compatible = "arasan,sdhci-8.9a" },
293 { .compatible = "arasan,sdhci-5.1" },
294 { .compatible = "arasan,sdhci-4.9a" },
295 { }
296};
297MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
298
299static struct platform_driver sdhci_arasan_driver = { 605static struct platform_driver sdhci_arasan_driver = {
300 .driver = { 606 .driver = {
301 .name = "sdhci-arasan", 607 .name = "sdhci-arasan",
diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c
index d4cef713d246..a9b7fc06c434 100644
--- a/drivers/mmc/host/sdhci-of-at91.c
+++ b/drivers/mmc/host/sdhci-of-at91.c
@@ -288,7 +288,7 @@ static int sdhci_at91_probe(struct platform_device *pdev)
288 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries 288 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
289 * to enable polling via device tree with broken-cd property. 289 * to enable polling via device tree with broken-cd property.
290 */ 290 */
291 if (!(host->mmc->caps & MMC_CAP_NONREMOVABLE) && 291 if (mmc_card_is_removable(host->mmc) &&
292 mmc_gpio_get_cd(host->mmc) < 0) { 292 mmc_gpio_get_cd(host->mmc) < 0) {
293 host->mmc->caps |= MMC_CAP_NEEDS_POLL; 293 host->mmc->caps |= MMC_CAP_NEEDS_POLL;
294 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 294 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index 3f34d354f1fc..239be2fde242 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -481,7 +481,7 @@ static void esdhc_reset(struct sdhci_host *host, u8 mask)
481 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 481 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
482} 482}
483 483
484#ifdef CONFIG_PM 484#ifdef CONFIG_PM_SLEEP
485static u32 esdhc_proctl; 485static u32 esdhc_proctl;
486static int esdhc_of_suspend(struct device *dev) 486static int esdhc_of_suspend(struct device *dev)
487{ 487{
@@ -504,16 +504,12 @@ static int esdhc_of_resume(struct device *dev)
504 } 504 }
505 return ret; 505 return ret;
506} 506}
507
508static const struct dev_pm_ops esdhc_pmops = {
509 .suspend = esdhc_of_suspend,
510 .resume = esdhc_of_resume,
511};
512#define ESDHC_PMOPS (&esdhc_pmops)
513#else
514#define ESDHC_PMOPS NULL
515#endif 507#endif
516 508
509static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops,
510 esdhc_of_suspend,
511 esdhc_of_resume);
512
517static const struct sdhci_ops sdhci_esdhc_be_ops = { 513static const struct sdhci_ops sdhci_esdhc_be_ops = {
518 .read_l = esdhc_be_readl, 514 .read_l = esdhc_be_readl,
519 .read_w = esdhc_be_readw, 515 .read_w = esdhc_be_readw,
@@ -657,7 +653,7 @@ static struct platform_driver sdhci_esdhc_driver = {
657 .driver = { 653 .driver = {
658 .name = "sdhci-esdhc", 654 .name = "sdhci-esdhc",
659 .of_match_table = sdhci_esdhc_of_match, 655 .of_match_table = sdhci_esdhc_of_match,
660 .pm = ESDHC_PMOPS, 656 .pm = &esdhc_of_dev_pm_ops,
661 }, 657 },
662 .probe = sdhci_esdhc_probe, 658 .probe = sdhci_esdhc_probe,
663 .remove = sdhci_pltfm_unregister, 659 .remove = sdhci_pltfm_unregister,
diff --git a/drivers/mmc/host/sdhci-of-hlwd.c b/drivers/mmc/host/sdhci-of-hlwd.c
index 4079a96ad37e..ac00c5efb2a3 100644
--- a/drivers/mmc/host/sdhci-of-hlwd.c
+++ b/drivers/mmc/host/sdhci-of-hlwd.c
@@ -85,7 +85,7 @@ static struct platform_driver sdhci_hlwd_driver = {
85 .driver = { 85 .driver = {
86 .name = "sdhci-hlwd", 86 .name = "sdhci-hlwd",
87 .of_match_table = sdhci_hlwd_of_match, 87 .of_match_table = sdhci_hlwd_of_match,
88 .pm = SDHCI_PLTFM_PMOPS, 88 .pm = &sdhci_pltfm_pmops,
89 }, 89 },
90 .probe = sdhci_hlwd_probe, 90 .probe = sdhci_hlwd_probe,
91 .remove = sdhci_pltfm_unregister, 91 .remove = sdhci_pltfm_unregister,
diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
index a4dbf7421edc..897cfd24ca2e 100644
--- a/drivers/mmc/host/sdhci-pci-core.c
+++ b/drivers/mmc/host/sdhci-pci-core.c
@@ -419,13 +419,13 @@ static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
419}; 419};
420 420
421/* Define Host controllers for Intel Merrifield platform */ 421/* Define Host controllers for Intel Merrifield platform */
422#define INTEL_MRFL_EMMC_0 0 422#define INTEL_MRFLD_EMMC_0 0
423#define INTEL_MRFL_EMMC_1 1 423#define INTEL_MRFLD_EMMC_1 1
424 424
425static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot) 425static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
426{ 426{
427 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) && 427 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFLD_EMMC_0) &&
428 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1)) 428 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFLD_EMMC_1))
429 /* SD support is not ready yet */ 429 /* SD support is not ready yet */
430 return -ENODEV; 430 return -ENODEV;
431 431
@@ -435,12 +435,12 @@ static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
435 return 0; 435 return 0;
436} 436}
437 437
438static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = { 438static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
439 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 439 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
440 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 440 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
441 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 441 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
442 .allow_runtime_pm = true, 442 .allow_runtime_pm = true,
443 .probe_slot = intel_mrfl_mmc_probe_slot, 443 .probe_slot = intel_mrfld_mmc_probe_slot,
444}; 444};
445 445
446/* O2Micro extra registers */ 446/* O2Micro extra registers */
@@ -1104,10 +1104,10 @@ static const struct pci_device_id pci_ids[] = {
1104 1104
1105 { 1105 {
1106 .vendor = PCI_VENDOR_ID_INTEL, 1106 .vendor = PCI_VENDOR_ID_INTEL,
1107 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC, 1107 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC,
1108 .subvendor = PCI_ANY_ID, 1108 .subvendor = PCI_ANY_ID,
1109 .subdevice = PCI_ANY_ID, 1109 .subdevice = PCI_ANY_ID,
1110 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc, 1110 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc,
1111 }, 1111 },
1112 1112
1113 { 1113 {
@@ -1413,8 +1413,7 @@ static const struct sdhci_ops sdhci_pci_ops = {
1413 * * 1413 * *
1414\*****************************************************************************/ 1414\*****************************************************************************/
1415 1415
1416#ifdef CONFIG_PM 1416#ifdef CONFIG_PM_SLEEP
1417
1418static int sdhci_pci_suspend(struct device *dev) 1417static int sdhci_pci_suspend(struct device *dev)
1419{ 1418{
1420 struct pci_dev *pdev = to_pci_dev(dev); 1419 struct pci_dev *pdev = to_pci_dev(dev);
@@ -1496,7 +1495,9 @@ static int sdhci_pci_resume(struct device *dev)
1496 1495
1497 return 0; 1496 return 0;
1498} 1497}
1498#endif
1499 1499
1500#ifdef CONFIG_PM
1500static int sdhci_pci_runtime_suspend(struct device *dev) 1501static int sdhci_pci_runtime_suspend(struct device *dev)
1501{ 1502{
1502 struct pci_dev *pdev = to_pci_dev(dev); 1503 struct pci_dev *pdev = to_pci_dev(dev);
@@ -1562,17 +1563,10 @@ static int sdhci_pci_runtime_resume(struct device *dev)
1562 1563
1563 return 0; 1564 return 0;
1564} 1565}
1565 1566#endif
1566#else /* CONFIG_PM */
1567
1568#define sdhci_pci_suspend NULL
1569#define sdhci_pci_resume NULL
1570
1571#endif /* CONFIG_PM */
1572 1567
1573static const struct dev_pm_ops sdhci_pci_pm_ops = { 1568static const struct dev_pm_ops sdhci_pci_pm_ops = {
1574 .suspend = sdhci_pci_suspend, 1569 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1575 .resume = sdhci_pci_resume,
1576 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1570 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1577 sdhci_pci_runtime_resume, NULL) 1571 sdhci_pci_runtime_resume, NULL)
1578}; 1572};
@@ -1760,11 +1754,12 @@ static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1760 1754
1761static void sdhci_pci_runtime_pm_allow(struct device *dev) 1755static void sdhci_pci_runtime_pm_allow(struct device *dev)
1762{ 1756{
1763 pm_runtime_put_noidle(dev); 1757 pm_suspend_ignore_children(dev, 1);
1764 pm_runtime_allow(dev);
1765 pm_runtime_set_autosuspend_delay(dev, 50); 1758 pm_runtime_set_autosuspend_delay(dev, 50);
1766 pm_runtime_use_autosuspend(dev); 1759 pm_runtime_use_autosuspend(dev);
1767 pm_suspend_ignore_children(dev, 1); 1760 pm_runtime_allow(dev);
1761 /* Stay active until mmc core scans for a card */
1762 pm_runtime_put_noidle(dev);
1768} 1763}
1769 1764
1770static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1765static void sdhci_pci_runtime_pm_forbid(struct device *dev)
@@ -1810,15 +1805,13 @@ static int sdhci_pci_probe(struct pci_dev *pdev,
1810 return -ENODEV; 1805 return -ENODEV;
1811 } 1806 }
1812 1807
1813 ret = pci_enable_device(pdev); 1808 ret = pcim_enable_device(pdev);
1814 if (ret) 1809 if (ret)
1815 return ret; 1810 return ret;
1816 1811
1817 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL); 1812 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1818 if (!chip) { 1813 if (!chip)
1819 ret = -ENOMEM; 1814 return -ENOMEM;
1820 goto err;
1821 }
1822 1815
1823 chip->pdev = pdev; 1816 chip->pdev = pdev;
1824 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1817 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
@@ -1834,7 +1827,7 @@ static int sdhci_pci_probe(struct pci_dev *pdev,
1834 if (chip->fixes && chip->fixes->probe) { 1827 if (chip->fixes && chip->fixes->probe) {
1835 ret = chip->fixes->probe(chip); 1828 ret = chip->fixes->probe(chip);
1836 if (ret) 1829 if (ret)
1837 goto free; 1830 return ret;
1838 } 1831 }
1839 1832
1840 slots = chip->num_slots; /* Quirk may have changed this */ 1833 slots = chip->num_slots; /* Quirk may have changed this */
@@ -1844,8 +1837,7 @@ static int sdhci_pci_probe(struct pci_dev *pdev,
1844 if (IS_ERR(slot)) { 1837 if (IS_ERR(slot)) {
1845 for (i--; i >= 0; i--) 1838 for (i--; i >= 0; i--)
1846 sdhci_pci_remove_slot(chip->slots[i]); 1839 sdhci_pci_remove_slot(chip->slots[i]);
1847 ret = PTR_ERR(slot); 1840 return PTR_ERR(slot);
1848 goto free;
1849 } 1841 }
1850 1842
1851 chip->slots[i] = slot; 1843 chip->slots[i] = slot;
@@ -1855,35 +1847,18 @@ static int sdhci_pci_probe(struct pci_dev *pdev,
1855 sdhci_pci_runtime_pm_allow(&pdev->dev); 1847 sdhci_pci_runtime_pm_allow(&pdev->dev);
1856 1848
1857 return 0; 1849 return 0;
1858
1859free:
1860 pci_set_drvdata(pdev, NULL);
1861 kfree(chip);
1862
1863err:
1864 pci_disable_device(pdev);
1865 return ret;
1866} 1850}
1867 1851
1868static void sdhci_pci_remove(struct pci_dev *pdev) 1852static void sdhci_pci_remove(struct pci_dev *pdev)
1869{ 1853{
1870 int i; 1854 int i;
1871 struct sdhci_pci_chip *chip; 1855 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1872 1856
1873 chip = pci_get_drvdata(pdev); 1857 if (chip->allow_runtime_pm)
1874 1858 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1875 if (chip) {
1876 if (chip->allow_runtime_pm)
1877 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1878
1879 for (i = 0; i < chip->num_slots; i++)
1880 sdhci_pci_remove_slot(chip->slots[i]);
1881
1882 pci_set_drvdata(pdev, NULL);
1883 kfree(chip);
1884 }
1885 1859
1886 pci_disable_device(pdev); 1860 for (i = 0; i < chip->num_slots; i++)
1861 sdhci_pci_remove_slot(chip->slots[i]);
1887} 1862}
1888 1863
1889static struct pci_driver sdhci_driver = { 1864static struct pci_driver sdhci_driver = {
diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h
index 89e7151684a1..7e0788712e1a 100644
--- a/drivers/mmc/host/sdhci-pci.h
+++ b/drivers/mmc/host/sdhci-pci.h
@@ -14,7 +14,7 @@
14#define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294 14#define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294
15#define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295 15#define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295
16#define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296 16#define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296
17#define PCI_DEVICE_ID_INTEL_MRFL_MMC 0x1190 17#define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190
18#define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9 18#define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9
19#define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa 19#define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa
20#define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb 20#define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index 64f287a03cd3..1d17dcfc3ffb 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -215,29 +215,26 @@ int sdhci_pltfm_unregister(struct platform_device *pdev)
215} 215}
216EXPORT_SYMBOL_GPL(sdhci_pltfm_unregister); 216EXPORT_SYMBOL_GPL(sdhci_pltfm_unregister);
217 217
218#ifdef CONFIG_PM 218#ifdef CONFIG_PM_SLEEP
219int sdhci_pltfm_suspend(struct device *dev) 219static int sdhci_pltfm_suspend(struct device *dev)
220{ 220{
221 struct sdhci_host *host = dev_get_drvdata(dev); 221 struct sdhci_host *host = dev_get_drvdata(dev);
222 222
223 return sdhci_suspend_host(host); 223 return sdhci_suspend_host(host);
224} 224}
225EXPORT_SYMBOL_GPL(sdhci_pltfm_suspend);
226 225
227int sdhci_pltfm_resume(struct device *dev) 226static int sdhci_pltfm_resume(struct device *dev)
228{ 227{
229 struct sdhci_host *host = dev_get_drvdata(dev); 228 struct sdhci_host *host = dev_get_drvdata(dev);
230 229
231 return sdhci_resume_host(host); 230 return sdhci_resume_host(host);
232} 231}
233EXPORT_SYMBOL_GPL(sdhci_pltfm_resume); 232#endif
234 233
235const struct dev_pm_ops sdhci_pltfm_pmops = { 234const struct dev_pm_ops sdhci_pltfm_pmops = {
236 .suspend = sdhci_pltfm_suspend, 235 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume)
237 .resume = sdhci_pltfm_resume,
238}; 236};
239EXPORT_SYMBOL_GPL(sdhci_pltfm_pmops); 237EXPORT_SYMBOL_GPL(sdhci_pltfm_pmops);
240#endif /* CONFIG_PM */
241 238
242static int __init sdhci_pltfm_drv_init(void) 239static int __init sdhci_pltfm_drv_init(void)
243{ 240{
diff --git a/drivers/mmc/host/sdhci-pltfm.h b/drivers/mmc/host/sdhci-pltfm.h
index d38053bf9e4d..3280f2077959 100644
--- a/drivers/mmc/host/sdhci-pltfm.h
+++ b/drivers/mmc/host/sdhci-pltfm.h
@@ -109,13 +109,6 @@ static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host)
109 return (void *)host->private; 109 return (void *)host->private;
110} 110}
111 111
112#ifdef CONFIG_PM
113extern int sdhci_pltfm_suspend(struct device *dev);
114extern int sdhci_pltfm_resume(struct device *dev);
115extern const struct dev_pm_ops sdhci_pltfm_pmops; 112extern const struct dev_pm_ops sdhci_pltfm_pmops;
116#define SDHCI_PLTFM_PMOPS (&sdhci_pltfm_pmops)
117#else
118#define SDHCI_PLTFM_PMOPS NULL
119#endif
120 113
121#endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */ 114#endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */
diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c
index 1d8dd3540636..347eae2d7b6a 100644
--- a/drivers/mmc/host/sdhci-pxav2.c
+++ b/drivers/mmc/host/sdhci-pxav2.c
@@ -252,7 +252,7 @@ static struct platform_driver sdhci_pxav2_driver = {
252 .driver = { 252 .driver = {
253 .name = "sdhci-pxav2", 253 .name = "sdhci-pxav2",
254 .of_match_table = of_match_ptr(sdhci_pxav2_of_match), 254 .of_match_table = of_match_ptr(sdhci_pxav2_of_match),
255 .pm = SDHCI_PLTFM_PMOPS, 255 .pm = &sdhci_pltfm_pmops,
256 }, 256 },
257 .probe = sdhci_pxav2_probe, 257 .probe = sdhci_pxav2_probe,
258 .remove = sdhci_pxav2_remove, 258 .remove = sdhci_pxav2_remove,
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 30132500aa1c..dd1938d341f7 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -583,24 +583,17 @@ static int sdhci_pxav3_runtime_resume(struct device *dev)
583} 583}
584#endif 584#endif
585 585
586#ifdef CONFIG_PM
587static const struct dev_pm_ops sdhci_pxav3_pmops = { 586static const struct dev_pm_ops sdhci_pxav3_pmops = {
588 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume) 587 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
589 SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend, 588 SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
590 sdhci_pxav3_runtime_resume, NULL) 589 sdhci_pxav3_runtime_resume, NULL)
591}; 590};
592 591
593#define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
594
595#else
596#define SDHCI_PXAV3_PMOPS NULL
597#endif
598
599static struct platform_driver sdhci_pxav3_driver = { 592static struct platform_driver sdhci_pxav3_driver = {
600 .driver = { 593 .driver = {
601 .name = "sdhci-pxav3", 594 .name = "sdhci-pxav3",
602 .of_match_table = of_match_ptr(sdhci_pxav3_of_match), 595 .of_match_table = of_match_ptr(sdhci_pxav3_of_match),
603 .pm = SDHCI_PXAV3_PMOPS, 596 .pm = &sdhci_pxav3_pmops,
604 }, 597 },
605 .probe = sdhci_pxav3_probe, 598 .probe = sdhci_pxav3_probe,
606 .remove = sdhci_pxav3_remove, 599 .remove = sdhci_pxav3_remove,
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 70c724bc6fc7..784c5a848fb4 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -714,19 +714,12 @@ static int sdhci_s3c_runtime_resume(struct device *dev)
714} 714}
715#endif 715#endif
716 716
717#ifdef CONFIG_PM
718static const struct dev_pm_ops sdhci_s3c_pmops = { 717static const struct dev_pm_ops sdhci_s3c_pmops = {
719 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume) 718 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
720 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume, 719 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
721 NULL) 720 NULL)
722}; 721};
723 722
724#define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
725
726#else
727#define SDHCI_S3C_PMOPS NULL
728#endif
729
730#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) 723#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
731static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = { 724static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
732 .no_divider = true, 725 .no_divider = true,
@@ -765,7 +758,7 @@ static struct platform_driver sdhci_s3c_driver = {
765 .driver = { 758 .driver = {
766 .name = "s3c-sdhci", 759 .name = "s3c-sdhci",
767 .of_match_table = of_match_ptr(sdhci_s3c_dt_match), 760 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
768 .pm = SDHCI_S3C_PMOPS, 761 .pm = &sdhci_s3c_pmops,
769 }, 762 },
770}; 763};
771 764
diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c
index 34866f668dd7..5d068639dd3f 100644
--- a/drivers/mmc/host/sdhci-sirf.c
+++ b/drivers/mmc/host/sdhci-sirf.c
@@ -260,9 +260,9 @@ static int sdhci_sirf_resume(struct device *dev)
260 260
261 return sdhci_resume_host(host); 261 return sdhci_resume_host(host);
262} 262}
263#endif
263 264
264static SIMPLE_DEV_PM_OPS(sdhci_sirf_pm_ops, sdhci_sirf_suspend, sdhci_sirf_resume); 265static SIMPLE_DEV_PM_OPS(sdhci_sirf_pm_ops, sdhci_sirf_suspend, sdhci_sirf_resume);
265#endif
266 266
267static const struct of_device_id sdhci_sirf_of_match[] = { 267static const struct of_device_id sdhci_sirf_of_match[] = {
268 { .compatible = "sirf,prima2-sdhc" }, 268 { .compatible = "sirf,prima2-sdhc" },
@@ -274,9 +274,7 @@ static struct platform_driver sdhci_sirf_driver = {
274 .driver = { 274 .driver = {
275 .name = "sdhci-sirf", 275 .name = "sdhci-sirf",
276 .of_match_table = sdhci_sirf_of_match, 276 .of_match_table = sdhci_sirf_of_match,
277#ifdef CONFIG_PM_SLEEP
278 .pm = &sdhci_sirf_pm_ops, 277 .pm = &sdhci_sirf_pm_ops,
279#endif
280 }, 278 },
281 .probe = sdhci_sirf_probe, 279 .probe = sdhci_sirf_probe,
282 .remove = sdhci_pltfm_unregister, 280 .remove = sdhci_pltfm_unregister,
diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index 320e1c2f8853..c95ba83366a0 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -183,7 +183,7 @@ static void st_mmcss_cconfig(struct device_node *np, struct sdhci_host *host)
183 183
184 writel_relaxed(cconf2, host->ioaddr + ST_MMC_CCONFIG_REG_2); 184 writel_relaxed(cconf2, host->ioaddr + ST_MMC_CCONFIG_REG_2);
185 185
186 if (mhost->caps & MMC_CAP_NONREMOVABLE) 186 if (!mmc_card_is_removable(mhost))
187 cconf3 |= ST_MMC_CCONFIG_EMMC_SLOT_TYPE; 187 cconf3 |= ST_MMC_CCONFIG_EMMC_SLOT_TYPE;
188 else 188 else
189 /* CARD _D ET_CTRL */ 189 /* CARD _D ET_CTRL */
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index bcc0de47fe7e..1e93dc4e303e 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -148,28 +148,37 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
148 return; 148 return;
149 149
150 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 150 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
151 /* Erratum: Enable SDHCI spec v3.00 support */
152 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
153 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
154 /* Advertise UHS modes as supported by host */
155 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
156 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
157 else
158 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50;
159 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
160 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
161 else
162 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50;
163 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
164 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
165 else
166 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104;
167 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
168
169 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 151 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
152
153 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 |
154 SDHCI_MISC_CTRL_ENABLE_SDR50 |
155 SDHCI_MISC_CTRL_ENABLE_DDR50 |
156 SDHCI_MISC_CTRL_ENABLE_SDR104);
157
170 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; 158 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
171 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 159
172 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 160 /*
161 * If the board does not define a regulator for the SDHCI
162 * IO voltage, then don't advertise support for UHS modes
163 * even if the device supports it because the IO voltage
164 * cannot be configured.
165 */
166 if (!IS_ERR(host->mmc->supply.vqmmc)) {
167 /* Erratum: Enable SDHCI spec v3.00 support */
168 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
169 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
170 /* Advertise UHS modes as supported by host */
171 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
172 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
173 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
174 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
175 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
176 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
177 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50)
178 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
179 }
180
181 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
173 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 182 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
174 183
175 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 184 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
@@ -474,7 +483,7 @@ static struct platform_driver sdhci_tegra_driver = {
474 .driver = { 483 .driver = {
475 .name = "sdhci-tegra", 484 .name = "sdhci-tegra",
476 .of_match_table = sdhci_tegra_dt_match, 485 .of_match_table = sdhci_tegra_dt_match,
477 .pm = SDHCI_PLTFM_PMOPS, 486 .pm = &sdhci_pltfm_pmops,
478 }, 487 },
479 .probe = sdhci_tegra_probe, 488 .probe = sdhci_tegra_probe,
480 .remove = sdhci_pltfm_unregister, 489 .remove = sdhci_pltfm_unregister,
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 0e3d7c056cb1..cd65d474afa2 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -45,65 +45,62 @@ static unsigned int debug_quirks2;
45 45
46static void sdhci_finish_data(struct sdhci_host *); 46static void sdhci_finish_data(struct sdhci_host *);
47 47
48static void sdhci_finish_command(struct sdhci_host *);
49static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
50static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 48static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
51static int sdhci_get_cd(struct mmc_host *mmc);
52 49
53static void sdhci_dumpregs(struct sdhci_host *host) 50static void sdhci_dumpregs(struct sdhci_host *host)
54{ 51{
55 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 52 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
56 mmc_hostname(host->mmc)); 53 mmc_hostname(host->mmc));
57 54
58 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 55 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
59 sdhci_readl(host, SDHCI_DMA_ADDRESS), 56 sdhci_readl(host, SDHCI_DMA_ADDRESS),
60 sdhci_readw(host, SDHCI_HOST_VERSION)); 57 sdhci_readw(host, SDHCI_HOST_VERSION));
61 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 58 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
62 sdhci_readw(host, SDHCI_BLOCK_SIZE), 59 sdhci_readw(host, SDHCI_BLOCK_SIZE),
63 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 60 sdhci_readw(host, SDHCI_BLOCK_COUNT));
64 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 61 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
65 sdhci_readl(host, SDHCI_ARGUMENT), 62 sdhci_readl(host, SDHCI_ARGUMENT),
66 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 63 sdhci_readw(host, SDHCI_TRANSFER_MODE));
67 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 64 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
68 sdhci_readl(host, SDHCI_PRESENT_STATE), 65 sdhci_readl(host, SDHCI_PRESENT_STATE),
69 sdhci_readb(host, SDHCI_HOST_CONTROL)); 66 sdhci_readb(host, SDHCI_HOST_CONTROL));
70 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 67 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
71 sdhci_readb(host, SDHCI_POWER_CONTROL), 68 sdhci_readb(host, SDHCI_POWER_CONTROL),
72 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 69 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
73 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 70 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
74 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 71 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
75 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 72 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
76 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 73 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
77 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 74 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
78 sdhci_readl(host, SDHCI_INT_STATUS)); 75 sdhci_readl(host, SDHCI_INT_STATUS));
79 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 76 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
80 sdhci_readl(host, SDHCI_INT_ENABLE), 77 sdhci_readl(host, SDHCI_INT_ENABLE),
81 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 78 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
82 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 79 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
83 sdhci_readw(host, SDHCI_ACMD12_ERR), 80 sdhci_readw(host, SDHCI_ACMD12_ERR),
84 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 81 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
85 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 82 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
86 sdhci_readl(host, SDHCI_CAPABILITIES), 83 sdhci_readl(host, SDHCI_CAPABILITIES),
87 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 84 sdhci_readl(host, SDHCI_CAPABILITIES_1));
88 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 85 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
89 sdhci_readw(host, SDHCI_COMMAND), 86 sdhci_readw(host, SDHCI_COMMAND),
90 sdhci_readl(host, SDHCI_MAX_CURRENT)); 87 sdhci_readl(host, SDHCI_MAX_CURRENT));
91 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", 88 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
92 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 89 sdhci_readw(host, SDHCI_HOST_CONTROL2));
93 90
94 if (host->flags & SDHCI_USE_ADMA) { 91 if (host->flags & SDHCI_USE_ADMA) {
95 if (host->flags & SDHCI_USE_64_BIT_DMA) 92 if (host->flags & SDHCI_USE_64_BIT_DMA)
96 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", 93 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
97 readl(host->ioaddr + SDHCI_ADMA_ERROR), 94 readl(host->ioaddr + SDHCI_ADMA_ERROR),
98 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI), 95 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
99 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
100 else 97 else
101 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 98 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
102 readl(host->ioaddr + SDHCI_ADMA_ERROR), 99 readl(host->ioaddr + SDHCI_ADMA_ERROR),
103 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 100 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
104 } 101 }
105 102
106 pr_debug(DRIVER_NAME ": ===========================================\n"); 103 pr_err(DRIVER_NAME ": ===========================================\n");
107} 104}
108 105
109/*****************************************************************************\ 106/*****************************************************************************\
@@ -112,12 +109,17 @@ static void sdhci_dumpregs(struct sdhci_host *host)
112 * * 109 * *
113\*****************************************************************************/ 110\*****************************************************************************/
114 111
112static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
113{
114 return cmd->data || cmd->flags & MMC_RSP_BUSY;
115}
116
115static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 117static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
116{ 118{
117 u32 present; 119 u32 present;
118 120
119 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 121 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
120 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 122 !mmc_card_is_removable(host->mmc))
121 return; 123 return;
122 124
123 if (enable) { 125 if (enable) {
@@ -193,7 +195,9 @@ EXPORT_SYMBOL_GPL(sdhci_reset);
193static void sdhci_do_reset(struct sdhci_host *host, u8 mask) 195static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
194{ 196{
195 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 197 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
196 if (!sdhci_get_cd(host->mmc)) 198 struct mmc_host *mmc = host->mmc;
199
200 if (!mmc->ops->get_cd(mmc))
197 return; 201 return;
198 } 202 }
199 203
@@ -210,10 +214,10 @@ static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
210 } 214 }
211} 215}
212 216
213static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
214
215static void sdhci_init(struct sdhci_host *host, int soft) 217static void sdhci_init(struct sdhci_host *host, int soft)
216{ 218{
219 struct mmc_host *mmc = host->mmc;
220
217 if (soft) 221 if (soft)
218 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 222 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
219 else 223 else
@@ -225,13 +229,17 @@ static void sdhci_init(struct sdhci_host *host, int soft)
225 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | 229 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
226 SDHCI_INT_RESPONSE; 230 SDHCI_INT_RESPONSE;
227 231
232 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
233 host->tuning_mode == SDHCI_TUNING_MODE_3)
234 host->ier |= SDHCI_INT_RETUNE;
235
228 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 236 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
229 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 237 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
230 238
231 if (soft) { 239 if (soft) {
232 /* force clock reconfiguration */ 240 /* force clock reconfiguration */
233 host->clock = 0; 241 host->clock = 0;
234 sdhci_set_ios(host->mmc, &host->mmc->ios); 242 mmc->ops->set_ios(mmc, &mmc->ios);
235 } 243 }
236} 244}
237 245
@@ -429,8 +437,6 @@ static void sdhci_transfer_pio(struct sdhci_host *host)
429{ 437{
430 u32 mask; 438 u32 mask;
431 439
432 BUG_ON(!host->data);
433
434 if (host->blocks == 0) 440 if (host->blocks == 0)
435 return; 441 return;
436 442
@@ -747,14 +753,14 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
747 u8 ctrl; 753 u8 ctrl;
748 struct mmc_data *data = cmd->data; 754 struct mmc_data *data = cmd->data;
749 755
750 WARN_ON(host->data); 756 if (sdhci_data_line_cmd(cmd))
751
752 if (data || (cmd->flags & MMC_RSP_BUSY))
753 sdhci_set_timeout(host, cmd); 757 sdhci_set_timeout(host, cmd);
754 758
755 if (!data) 759 if (!data)
756 return; 760 return;
757 761
762 WARN_ON(host->data);
763
758 /* Sanity checks */ 764 /* Sanity checks */
759 BUG_ON(data->blksz * data->blocks > 524288); 765 BUG_ON(data->blksz * data->blocks > 524288);
760 BUG_ON(data->blksz > host->mmc->max_blk_size); 766 BUG_ON(data->blksz > host->mmc->max_blk_size);
@@ -879,6 +885,12 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
879 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 885 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
880} 886}
881 887
888static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
889 struct mmc_request *mrq)
890{
891 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12);
892}
893
882static void sdhci_set_transfer_mode(struct sdhci_host *host, 894static void sdhci_set_transfer_mode(struct sdhci_host *host,
883 struct mmc_command *cmd) 895 struct mmc_command *cmd)
884{ 896{
@@ -909,12 +921,12 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
909 * If we are sending CMD23, CMD12 never gets sent 921 * If we are sending CMD23, CMD12 never gets sent
910 * on successful completion (so no Auto-CMD12). 922 * on successful completion (so no Auto-CMD12).
911 */ 923 */
912 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && 924 if (sdhci_auto_cmd12(host, cmd->mrq) &&
913 (cmd->opcode != SD_IO_RW_EXTENDED)) 925 (cmd->opcode != SD_IO_RW_EXTENDED))
914 mode |= SDHCI_TRNS_AUTO_CMD12; 926 mode |= SDHCI_TRNS_AUTO_CMD12;
915 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 927 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
916 mode |= SDHCI_TRNS_AUTO_CMD23; 928 mode |= SDHCI_TRNS_AUTO_CMD23;
917 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); 929 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
918 } 930 }
919 } 931 }
920 932
@@ -926,14 +938,63 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
926 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 938 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
927} 939}
928 940
929static void sdhci_finish_data(struct sdhci_host *host) 941static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
942{
943 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
944 ((mrq->cmd && mrq->cmd->error) ||
945 (mrq->sbc && mrq->sbc->error) ||
946 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
947 (mrq->data->stop && mrq->data->stop->error))) ||
948 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
949}
950
951static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
952{
953 int i;
954
955 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
956 if (host->mrqs_done[i] == mrq) {
957 WARN_ON(1);
958 return;
959 }
960 }
961
962 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
963 if (!host->mrqs_done[i]) {
964 host->mrqs_done[i] = mrq;
965 break;
966 }
967 }
968
969 WARN_ON(i >= SDHCI_MAX_MRQS);
970
971 tasklet_schedule(&host->finish_tasklet);
972}
973
974static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
930{ 975{
931 struct mmc_data *data; 976 if (host->cmd && host->cmd->mrq == mrq)
977 host->cmd = NULL;
978
979 if (host->data_cmd && host->data_cmd->mrq == mrq)
980 host->data_cmd = NULL;
981
982 if (host->data && host->data->mrq == mrq)
983 host->data = NULL;
932 984
933 BUG_ON(!host->data); 985 if (sdhci_needs_reset(host, mrq))
986 host->pending_reset = true;
987
988 __sdhci_finish_mrq(host, mrq);
989}
990
991static void sdhci_finish_data(struct sdhci_host *host)
992{
993 struct mmc_command *data_cmd = host->data_cmd;
994 struct mmc_data *data = host->data;
934 995
935 data = host->data;
936 host->data = NULL; 996 host->data = NULL;
997 host->data_cmd = NULL;
937 998
938 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) == 999 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
939 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) 1000 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
@@ -958,20 +1019,41 @@ static void sdhci_finish_data(struct sdhci_host *host)
958 */ 1019 */
959 if (data->stop && 1020 if (data->stop &&
960 (data->error || 1021 (data->error ||
961 !host->mrq->sbc)) { 1022 !data->mrq->sbc)) {
962 1023
963 /* 1024 /*
964 * The controller needs a reset of internal state machines 1025 * The controller needs a reset of internal state machines
965 * upon error conditions. 1026 * upon error conditions.
966 */ 1027 */
967 if (data->error) { 1028 if (data->error) {
968 sdhci_do_reset(host, SDHCI_RESET_CMD); 1029 if (!host->cmd || host->cmd == data_cmd)
1030 sdhci_do_reset(host, SDHCI_RESET_CMD);
969 sdhci_do_reset(host, SDHCI_RESET_DATA); 1031 sdhci_do_reset(host, SDHCI_RESET_DATA);
970 } 1032 }
971 1033
1034 /* Avoid triggering warning in sdhci_send_command() */
1035 host->cmd = NULL;
972 sdhci_send_command(host, data->stop); 1036 sdhci_send_command(host, data->stop);
973 } else 1037 } else {
974 tasklet_schedule(&host->finish_tasklet); 1038 sdhci_finish_mrq(host, data->mrq);
1039 }
1040}
1041
1042static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1043 unsigned long timeout)
1044{
1045 if (sdhci_data_line_cmd(mrq->cmd))
1046 mod_timer(&host->data_timer, timeout);
1047 else
1048 mod_timer(&host->timer, timeout);
1049}
1050
1051static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1052{
1053 if (sdhci_data_line_cmd(mrq->cmd))
1054 del_timer(&host->data_timer);
1055 else
1056 del_timer(&host->timer);
975} 1057}
976 1058
977void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 1059void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
@@ -989,12 +1071,12 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
989 timeout = 10; 1071 timeout = 10;
990 1072
991 mask = SDHCI_CMD_INHIBIT; 1073 mask = SDHCI_CMD_INHIBIT;
992 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 1074 if (sdhci_data_line_cmd(cmd))
993 mask |= SDHCI_DATA_INHIBIT; 1075 mask |= SDHCI_DATA_INHIBIT;
994 1076
995 /* We shouldn't wait for data inihibit for stop commands, even 1077 /* We shouldn't wait for data inihibit for stop commands, even
996 though they might use busy signaling */ 1078 though they might use busy signaling */
997 if (host->mrq->data && (cmd == host->mrq->data->stop)) 1079 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
998 mask &= ~SDHCI_DATA_INHIBIT; 1080 mask &= ~SDHCI_DATA_INHIBIT;
999 1081
1000 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 1082 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
@@ -1003,7 +1085,7 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1003 mmc_hostname(host->mmc)); 1085 mmc_hostname(host->mmc));
1004 sdhci_dumpregs(host); 1086 sdhci_dumpregs(host);
1005 cmd->error = -EIO; 1087 cmd->error = -EIO;
1006 tasklet_schedule(&host->finish_tasklet); 1088 sdhci_finish_mrq(host, cmd->mrq);
1007 return; 1089 return;
1008 } 1090 }
1009 timeout--; 1091 timeout--;
@@ -1015,10 +1097,13 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1015 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 1097 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1016 else 1098 else
1017 timeout += 10 * HZ; 1099 timeout += 10 * HZ;
1018 mod_timer(&host->timer, timeout); 1100 sdhci_mod_timer(host, cmd->mrq, timeout);
1019 1101
1020 host->cmd = cmd; 1102 host->cmd = cmd;
1021 host->busy_handle = 0; 1103 if (sdhci_data_line_cmd(cmd)) {
1104 WARN_ON(host->data_cmd);
1105 host->data_cmd = cmd;
1106 }
1022 1107
1023 sdhci_prepare_data(host, cmd); 1108 sdhci_prepare_data(host, cmd);
1024 1109
@@ -1030,7 +1115,7 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1030 pr_err("%s: Unsupported response type!\n", 1115 pr_err("%s: Unsupported response type!\n",
1031 mmc_hostname(host->mmc)); 1116 mmc_hostname(host->mmc));
1032 cmd->error = -EINVAL; 1117 cmd->error = -EINVAL;
1033 tasklet_schedule(&host->finish_tasklet); 1118 sdhci_finish_mrq(host, cmd->mrq);
1034 return; 1119 return;
1035 } 1120 }
1036 1121
@@ -1059,40 +1144,58 @@ EXPORT_SYMBOL_GPL(sdhci_send_command);
1059 1144
1060static void sdhci_finish_command(struct sdhci_host *host) 1145static void sdhci_finish_command(struct sdhci_host *host)
1061{ 1146{
1147 struct mmc_command *cmd = host->cmd;
1062 int i; 1148 int i;
1063 1149
1064 BUG_ON(host->cmd == NULL); 1150 host->cmd = NULL;
1065 1151
1066 if (host->cmd->flags & MMC_RSP_PRESENT) { 1152 if (cmd->flags & MMC_RSP_PRESENT) {
1067 if (host->cmd->flags & MMC_RSP_136) { 1153 if (cmd->flags & MMC_RSP_136) {
1068 /* CRC is stripped so we need to do some shifting. */ 1154 /* CRC is stripped so we need to do some shifting. */
1069 for (i = 0;i < 4;i++) { 1155 for (i = 0;i < 4;i++) {
1070 host->cmd->resp[i] = sdhci_readl(host, 1156 cmd->resp[i] = sdhci_readl(host,
1071 SDHCI_RESPONSE + (3-i)*4) << 8; 1157 SDHCI_RESPONSE + (3-i)*4) << 8;
1072 if (i != 3) 1158 if (i != 3)
1073 host->cmd->resp[i] |= 1159 cmd->resp[i] |=
1074 sdhci_readb(host, 1160 sdhci_readb(host,
1075 SDHCI_RESPONSE + (3-i)*4-1); 1161 SDHCI_RESPONSE + (3-i)*4-1);
1076 } 1162 }
1077 } else { 1163 } else {
1078 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1164 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1165 }
1166 }
1167
1168 /*
1169 * The host can send and interrupt when the busy state has
1170 * ended, allowing us to wait without wasting CPU cycles.
1171 * The busy signal uses DAT0 so this is similar to waiting
1172 * for data to complete.
1173 *
1174 * Note: The 1.0 specification is a bit ambiguous about this
1175 * feature so there might be some problems with older
1176 * controllers.
1177 */
1178 if (cmd->flags & MMC_RSP_BUSY) {
1179 if (cmd->data) {
1180 DBG("Cannot wait for busy signal when also doing a data transfer");
1181 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1182 cmd == host->data_cmd) {
1183 /* Command complete before busy is ended */
1184 return;
1079 } 1185 }
1080 } 1186 }
1081 1187
1082 /* Finished CMD23, now send actual command. */ 1188 /* Finished CMD23, now send actual command. */
1083 if (host->cmd == host->mrq->sbc) { 1189 if (cmd == cmd->mrq->sbc) {
1084 host->cmd = NULL; 1190 sdhci_send_command(host, cmd->mrq->cmd);
1085 sdhci_send_command(host, host->mrq->cmd);
1086 } else { 1191 } else {
1087 1192
1088 /* Processed actual command. */ 1193 /* Processed actual command. */
1089 if (host->data && host->data_early) 1194 if (host->data && host->data_early)
1090 sdhci_finish_data(host); 1195 sdhci_finish_data(host);
1091 1196
1092 if (!host->cmd->data) 1197 if (!cmd->data)
1093 tasklet_schedule(&host->finish_tasklet); 1198 sdhci_finish_mrq(host, cmd->mrq);
1094
1095 host->cmd = NULL;
1096 } 1199 }
1097} 1200}
1098 1201
@@ -1373,26 +1476,22 @@ static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1373 1476
1374 spin_lock_irqsave(&host->lock, flags); 1477 spin_lock_irqsave(&host->lock, flags);
1375 1478
1376 WARN_ON(host->mrq != NULL);
1377
1378 sdhci_led_activate(host); 1479 sdhci_led_activate(host);
1379 1480
1380 /* 1481 /*
1381 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1482 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1382 * requests if Auto-CMD12 is enabled. 1483 * requests if Auto-CMD12 is enabled.
1383 */ 1484 */
1384 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 1485 if (sdhci_auto_cmd12(host, mrq)) {
1385 if (mrq->stop) { 1486 if (mrq->stop) {
1386 mrq->data->stop = NULL; 1487 mrq->data->stop = NULL;
1387 mrq->stop = NULL; 1488 mrq->stop = NULL;
1388 } 1489 }
1389 } 1490 }
1390 1491
1391 host->mrq = mrq;
1392
1393 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1492 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1394 host->mrq->cmd->error = -ENOMEDIUM; 1493 mrq->cmd->error = -ENOMEDIUM;
1395 tasklet_schedule(&host->finish_tasklet); 1494 sdhci_finish_mrq(host, mrq);
1396 } else { 1495 } else {
1397 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1496 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1398 sdhci_send_command(host, mrq->sbc); 1497 sdhci_send_command(host, mrq->sbc);
@@ -1617,7 +1716,7 @@ static int sdhci_get_cd(struct mmc_host *mmc)
1617 return 0; 1716 return 0;
1618 1717
1619 /* If nonremovable, assume that the card is always present. */ 1718 /* If nonremovable, assume that the card is always present. */
1620 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 1719 if (!mmc_card_is_removable(host->mmc))
1621 return 1; 1720 return 1;
1622 1721
1623 /* 1722 /*
@@ -1733,13 +1832,14 @@ static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1733 1832
1734 switch (ios->signal_voltage) { 1833 switch (ios->signal_voltage) {
1735 case MMC_SIGNAL_VOLTAGE_330: 1834 case MMC_SIGNAL_VOLTAGE_330:
1835 if (!(host->flags & SDHCI_SIGNALING_330))
1836 return -EINVAL;
1736 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1837 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1737 ctrl &= ~SDHCI_CTRL_VDD_180; 1838 ctrl &= ~SDHCI_CTRL_VDD_180;
1738 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1839 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1739 1840
1740 if (!IS_ERR(mmc->supply.vqmmc)) { 1841 if (!IS_ERR(mmc->supply.vqmmc)) {
1741 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000, 1842 ret = mmc_regulator_set_vqmmc(mmc, ios);
1742 3600000);
1743 if (ret) { 1843 if (ret) {
1744 pr_warn("%s: Switching to 3.3V signalling voltage failed\n", 1844 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1745 mmc_hostname(mmc)); 1845 mmc_hostname(mmc));
@@ -1759,9 +1859,10 @@ static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1759 1859
1760 return -EAGAIN; 1860 return -EAGAIN;
1761 case MMC_SIGNAL_VOLTAGE_180: 1861 case MMC_SIGNAL_VOLTAGE_180:
1862 if (!(host->flags & SDHCI_SIGNALING_180))
1863 return -EINVAL;
1762 if (!IS_ERR(mmc->supply.vqmmc)) { 1864 if (!IS_ERR(mmc->supply.vqmmc)) {
1763 ret = regulator_set_voltage(mmc->supply.vqmmc, 1865 ret = mmc_regulator_set_vqmmc(mmc, ios);
1764 1700000, 1950000);
1765 if (ret) { 1866 if (ret) {
1766 pr_warn("%s: Switching to 1.8V signalling voltage failed\n", 1867 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1767 mmc_hostname(mmc)); 1868 mmc_hostname(mmc));
@@ -1790,9 +1891,10 @@ static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1790 1891
1791 return -EAGAIN; 1892 return -EAGAIN;
1792 case MMC_SIGNAL_VOLTAGE_120: 1893 case MMC_SIGNAL_VOLTAGE_120:
1894 if (!(host->flags & SDHCI_SIGNALING_120))
1895 return -EINVAL;
1793 if (!IS_ERR(mmc->supply.vqmmc)) { 1896 if (!IS_ERR(mmc->supply.vqmmc)) {
1794 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000, 1897 ret = mmc_regulator_set_vqmmc(mmc, ios);
1795 1300000);
1796 if (ret) { 1898 if (ret) {
1797 pr_warn("%s: Switching to 1.2V signalling voltage failed\n", 1899 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1798 mmc_hostname(mmc)); 1900 mmc_hostname(mmc));
@@ -1811,10 +1913,10 @@ static int sdhci_card_busy(struct mmc_host *mmc)
1811 struct sdhci_host *host = mmc_priv(mmc); 1913 struct sdhci_host *host = mmc_priv(mmc);
1812 u32 present_state; 1914 u32 present_state;
1813 1915
1814 /* Check whether DAT[3:0] is 0000 */ 1916 /* Check whether DAT[0] is 0 */
1815 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1917 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1816 1918
1817 return !(present_state & SDHCI_DATA_LVL_MASK); 1919 return !(present_state & SDHCI_DATA_0_LVL_MASK);
1818} 1920}
1819 1921
1820static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1922static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
@@ -1909,7 +2011,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1909 2011
1910 /* 2012 /*
1911 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 2013 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1912 * of loops reaches 40 times or a timeout of 150ms occurs. 2014 * of loops reaches 40 times.
1913 */ 2015 */
1914 do { 2016 do {
1915 struct mmc_command cmd = {0}; 2017 struct mmc_command cmd = {0};
@@ -1920,13 +2022,13 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1920 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 2022 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1921 cmd.retries = 0; 2023 cmd.retries = 0;
1922 cmd.data = NULL; 2024 cmd.data = NULL;
2025 cmd.mrq = &mrq;
1923 cmd.error = 0; 2026 cmd.error = 0;
1924 2027
1925 if (tuning_loop_counter-- == 0) 2028 if (tuning_loop_counter-- == 0)
1926 break; 2029 break;
1927 2030
1928 mrq.cmd = &cmd; 2031 mrq.cmd = &cmd;
1929 host->mrq = &mrq;
1930 2032
1931 /* 2033 /*
1932 * In response to CMD19, the card sends 64 bytes of tuning 2034 * In response to CMD19, the card sends 64 bytes of tuning
@@ -1956,7 +2058,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1956 sdhci_send_command(host, &cmd); 2058 sdhci_send_command(host, &cmd);
1957 2059
1958 host->cmd = NULL; 2060 host->cmd = NULL;
1959 host->mrq = NULL; 2061 sdhci_del_timer(host, &mrq);
1960 2062
1961 spin_unlock_irqrestore(&host->lock, flags); 2063 spin_unlock_irqrestore(&host->lock, flags);
1962 /* Wait for Buffer Read Ready interrupt */ 2064 /* Wait for Buffer Read Ready interrupt */
@@ -2086,6 +2188,24 @@ static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2086 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED); 2188 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2087} 2189}
2088 2190
2191static inline bool sdhci_has_requests(struct sdhci_host *host)
2192{
2193 return host->cmd || host->data_cmd;
2194}
2195
2196static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2197{
2198 if (host->data_cmd) {
2199 host->data_cmd->error = err;
2200 sdhci_finish_mrq(host, host->data_cmd->mrq);
2201 }
2202
2203 if (host->cmd) {
2204 host->cmd->error = err;
2205 sdhci_finish_mrq(host, host->cmd->mrq);
2206 }
2207}
2208
2089static void sdhci_card_event(struct mmc_host *mmc) 2209static void sdhci_card_event(struct mmc_host *mmc)
2090{ 2210{
2091 struct sdhci_host *host = mmc_priv(mmc); 2211 struct sdhci_host *host = mmc_priv(mmc);
@@ -2096,12 +2216,12 @@ static void sdhci_card_event(struct mmc_host *mmc)
2096 if (host->ops->card_event) 2216 if (host->ops->card_event)
2097 host->ops->card_event(host); 2217 host->ops->card_event(host);
2098 2218
2099 present = sdhci_get_cd(host->mmc); 2219 present = mmc->ops->get_cd(mmc);
2100 2220
2101 spin_lock_irqsave(&host->lock, flags); 2221 spin_lock_irqsave(&host->lock, flags);
2102 2222
2103 /* Check host->mrq first in case we are runtime suspended */ 2223 /* Check sdhci_has_requests() first in case we are runtime suspended */
2104 if (host->mrq && !present) { 2224 if (sdhci_has_requests(host) && !present) {
2105 pr_err("%s: Card removed during transfer!\n", 2225 pr_err("%s: Card removed during transfer!\n",
2106 mmc_hostname(host->mmc)); 2226 mmc_hostname(host->mmc));
2107 pr_err("%s: Resetting controller.\n", 2227 pr_err("%s: Resetting controller.\n",
@@ -2110,8 +2230,7 @@ static void sdhci_card_event(struct mmc_host *mmc)
2110 sdhci_do_reset(host, SDHCI_RESET_CMD); 2230 sdhci_do_reset(host, SDHCI_RESET_CMD);
2111 sdhci_do_reset(host, SDHCI_RESET_DATA); 2231 sdhci_do_reset(host, SDHCI_RESET_DATA);
2112 2232
2113 host->mrq->cmd->error = -ENOMEDIUM; 2233 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2114 tasklet_schedule(&host->finish_tasklet);
2115 } 2234 }
2116 2235
2117 spin_unlock_irqrestore(&host->lock, flags); 2236 spin_unlock_irqrestore(&host->lock, flags);
@@ -2140,28 +2259,28 @@ static const struct mmc_host_ops sdhci_ops = {
2140 * * 2259 * *
2141\*****************************************************************************/ 2260\*****************************************************************************/
2142 2261
2143static void sdhci_tasklet_finish(unsigned long param) 2262static bool sdhci_request_done(struct sdhci_host *host)
2144{ 2263{
2145 struct sdhci_host *host;
2146 unsigned long flags; 2264 unsigned long flags;
2147 struct mmc_request *mrq; 2265 struct mmc_request *mrq;
2148 2266 int i;
2149 host = (struct sdhci_host*)param;
2150 2267
2151 spin_lock_irqsave(&host->lock, flags); 2268 spin_lock_irqsave(&host->lock, flags);
2152 2269
2153 /* 2270 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2154 * If this tasklet gets rescheduled while running, it will 2271 mrq = host->mrqs_done[i];
2155 * be run again afterwards but without any active request. 2272 if (mrq) {
2156 */ 2273 host->mrqs_done[i] = NULL;
2157 if (!host->mrq) { 2274 break;
2158 spin_unlock_irqrestore(&host->lock, flags); 2275 }
2159 return;
2160 } 2276 }
2161 2277
2162 del_timer(&host->timer); 2278 if (!mrq) {
2279 spin_unlock_irqrestore(&host->lock, flags);
2280 return true;
2281 }
2163 2282
2164 mrq = host->mrq; 2283 sdhci_del_timer(host, mrq);
2165 2284
2166 /* 2285 /*
2167 * Always unmap the data buffers if they were mapped by 2286 * Always unmap the data buffers if they were mapped by
@@ -2183,13 +2302,7 @@ static void sdhci_tasklet_finish(unsigned long param)
2183 * The controller needs a reset of internal state machines 2302 * The controller needs a reset of internal state machines
2184 * upon error conditions. 2303 * upon error conditions.
2185 */ 2304 */
2186 if (!(host->flags & SDHCI_DEVICE_DEAD) && 2305 if (sdhci_needs_reset(host, mrq)) {
2187 ((mrq->cmd && mrq->cmd->error) ||
2188 (mrq->sbc && mrq->sbc->error) ||
2189 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2190 (mrq->data->stop && mrq->data->stop->error))) ||
2191 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2192
2193 /* Some controllers need this kick or reset won't work here */ 2306 /* Some controllers need this kick or reset won't work here */
2194 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 2307 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2195 /* This is to force an update */ 2308 /* This is to force an update */
@@ -2197,20 +2310,31 @@ static void sdhci_tasklet_finish(unsigned long param)
2197 2310
2198 /* Spec says we should do both at the same time, but Ricoh 2311 /* Spec says we should do both at the same time, but Ricoh
2199 controllers do not like that. */ 2312 controllers do not like that. */
2200 sdhci_do_reset(host, SDHCI_RESET_CMD); 2313 if (!host->cmd)
2201 sdhci_do_reset(host, SDHCI_RESET_DATA); 2314 sdhci_do_reset(host, SDHCI_RESET_CMD);
2202 } 2315 if (!host->data_cmd)
2316 sdhci_do_reset(host, SDHCI_RESET_DATA);
2203 2317
2204 host->mrq = NULL; 2318 host->pending_reset = false;
2205 host->cmd = NULL; 2319 }
2206 host->data = NULL;
2207 2320
2208 sdhci_led_deactivate(host); 2321 if (!sdhci_has_requests(host))
2322 sdhci_led_deactivate(host);
2209 2323
2210 mmiowb(); 2324 mmiowb();
2211 spin_unlock_irqrestore(&host->lock, flags); 2325 spin_unlock_irqrestore(&host->lock, flags);
2212 2326
2213 mmc_request_done(host->mmc, mrq); 2327 mmc_request_done(host->mmc, mrq);
2328
2329 return false;
2330}
2331
2332static void sdhci_tasklet_finish(unsigned long param)
2333{
2334 struct sdhci_host *host = (struct sdhci_host *)param;
2335
2336 while (!sdhci_request_done(host))
2337 ;
2214} 2338}
2215 2339
2216static void sdhci_timeout_timer(unsigned long data) 2340static void sdhci_timeout_timer(unsigned long data)
@@ -2222,7 +2346,30 @@ static void sdhci_timeout_timer(unsigned long data)
2222 2346
2223 spin_lock_irqsave(&host->lock, flags); 2347 spin_lock_irqsave(&host->lock, flags);
2224 2348
2225 if (host->mrq) { 2349 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2350 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2351 mmc_hostname(host->mmc));
2352 sdhci_dumpregs(host);
2353
2354 host->cmd->error = -ETIMEDOUT;
2355 sdhci_finish_mrq(host, host->cmd->mrq);
2356 }
2357
2358 mmiowb();
2359 spin_unlock_irqrestore(&host->lock, flags);
2360}
2361
2362static void sdhci_timeout_data_timer(unsigned long data)
2363{
2364 struct sdhci_host *host;
2365 unsigned long flags;
2366
2367 host = (struct sdhci_host *)data;
2368
2369 spin_lock_irqsave(&host->lock, flags);
2370
2371 if (host->data || host->data_cmd ||
2372 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2226 pr_err("%s: Timeout waiting for hardware interrupt.\n", 2373 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2227 mmc_hostname(host->mmc)); 2374 mmc_hostname(host->mmc));
2228 sdhci_dumpregs(host); 2375 sdhci_dumpregs(host);
@@ -2230,13 +2377,12 @@ static void sdhci_timeout_timer(unsigned long data)
2230 if (host->data) { 2377 if (host->data) {
2231 host->data->error = -ETIMEDOUT; 2378 host->data->error = -ETIMEDOUT;
2232 sdhci_finish_data(host); 2379 sdhci_finish_data(host);
2380 } else if (host->data_cmd) {
2381 host->data_cmd->error = -ETIMEDOUT;
2382 sdhci_finish_mrq(host, host->data_cmd->mrq);
2233 } else { 2383 } else {
2234 if (host->cmd) 2384 host->cmd->error = -ETIMEDOUT;
2235 host->cmd->error = -ETIMEDOUT; 2385 sdhci_finish_mrq(host, host->cmd->mrq);
2236 else
2237 host->mrq->cmd->error = -ETIMEDOUT;
2238
2239 tasklet_schedule(&host->finish_tasklet);
2240 } 2386 }
2241 } 2387 }
2242 2388
@@ -2252,9 +2398,14 @@ static void sdhci_timeout_timer(unsigned long data)
2252 2398
2253static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask) 2399static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2254{ 2400{
2255 BUG_ON(intmask == 0);
2256
2257 if (!host->cmd) { 2401 if (!host->cmd) {
2402 /*
2403 * SDHCI recovers from errors by resetting the cmd and data
2404 * circuits. Until that is done, there very well might be more
2405 * interrupts, so ignore them in that case.
2406 */
2407 if (host->pending_reset)
2408 return;
2258 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", 2409 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2259 mmc_hostname(host->mmc), (unsigned)intmask); 2410 mmc_hostname(host->mmc), (unsigned)intmask);
2260 sdhci_dumpregs(host); 2411 sdhci_dumpregs(host);
@@ -2285,37 +2436,14 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2285 return; 2436 return;
2286 } 2437 }
2287 2438
2288 tasklet_schedule(&host->finish_tasklet); 2439 sdhci_finish_mrq(host, host->cmd->mrq);
2289 return; 2440 return;
2290 } 2441 }
2291 2442
2292 /* 2443 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2293 * The host can send and interrupt when the busy state has 2444 !(host->cmd->flags & MMC_RSP_BUSY) && !host->data &&
2294 * ended, allowing us to wait without wasting CPU cycles. 2445 host->cmd->opcode == MMC_STOP_TRANSMISSION)
2295 * Unfortunately this is overloaded on the "data complete"
2296 * interrupt, so we need to take some care when handling
2297 * it.
2298 *
2299 * Note: The 1.0 specification is a bit ambiguous about this
2300 * feature so there might be some problems with older
2301 * controllers.
2302 */
2303 if (host->cmd->flags & MMC_RSP_BUSY) {
2304 if (host->cmd->data)
2305 DBG("Cannot wait for busy signal when also doing a data transfer");
2306 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2307 && !host->busy_handle) {
2308 /* Mark that command complete before busy is ended */
2309 host->busy_handle = 1;
2310 return;
2311 }
2312
2313 /* The controller does not support the end-of-busy IRQ,
2314 * fall through and take the SDHCI_INT_RESPONSE */
2315 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2316 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2317 *mask &= ~SDHCI_INT_DATA_END; 2446 *mask &= ~SDHCI_INT_DATA_END;
2318 }
2319 2447
2320 if (intmask & SDHCI_INT_RESPONSE) 2448 if (intmask & SDHCI_INT_RESPONSE)
2321 sdhci_finish_command(host); 2449 sdhci_finish_command(host);
@@ -2357,7 +2485,6 @@ static void sdhci_adma_show_error(struct sdhci_host *host) { }
2357static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2485static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2358{ 2486{
2359 u32 command; 2487 u32 command;
2360 BUG_ON(intmask == 0);
2361 2488
2362 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2489 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2363 if (intmask & SDHCI_INT_DATA_AVAIL) { 2490 if (intmask & SDHCI_INT_DATA_AVAIL) {
@@ -2371,15 +2498,20 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2371 } 2498 }
2372 2499
2373 if (!host->data) { 2500 if (!host->data) {
2501 struct mmc_command *data_cmd = host->data_cmd;
2502
2503 if (data_cmd)
2504 host->data_cmd = NULL;
2505
2374 /* 2506 /*
2375 * The "data complete" interrupt is also used to 2507 * The "data complete" interrupt is also used to
2376 * indicate that a busy state has ended. See comment 2508 * indicate that a busy state has ended. See comment
2377 * above in sdhci_cmd_irq(). 2509 * above in sdhci_cmd_irq().
2378 */ 2510 */
2379 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 2511 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2380 if (intmask & SDHCI_INT_DATA_TIMEOUT) { 2512 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2381 host->cmd->error = -ETIMEDOUT; 2513 data_cmd->error = -ETIMEDOUT;
2382 tasklet_schedule(&host->finish_tasklet); 2514 sdhci_finish_mrq(host, data_cmd->mrq);
2383 return; 2515 return;
2384 } 2516 }
2385 if (intmask & SDHCI_INT_DATA_END) { 2517 if (intmask & SDHCI_INT_DATA_END) {
@@ -2388,14 +2520,22 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2388 * before the command completed, so make 2520 * before the command completed, so make
2389 * sure we do things in the proper order. 2521 * sure we do things in the proper order.
2390 */ 2522 */
2391 if (host->busy_handle) 2523 if (host->cmd == data_cmd)
2392 sdhci_finish_command(host); 2524 return;
2393 else 2525
2394 host->busy_handle = 1; 2526 sdhci_finish_mrq(host, data_cmd->mrq);
2395 return; 2527 return;
2396 } 2528 }
2397 } 2529 }
2398 2530
2531 /*
2532 * SDHCI recovers from errors by resetting the cmd and data
2533 * circuits. Until that is done, there very well might be more
2534 * interrupts, so ignore them in that case.
2535 */
2536 if (host->pending_reset)
2537 return;
2538
2399 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", 2539 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2400 mmc_hostname(host->mmc), (unsigned)intmask); 2540 mmc_hostname(host->mmc), (unsigned)intmask);
2401 sdhci_dumpregs(host); 2541 sdhci_dumpregs(host);
@@ -2453,7 +2593,7 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2453 } 2593 }
2454 2594
2455 if (intmask & SDHCI_INT_DATA_END) { 2595 if (intmask & SDHCI_INT_DATA_END) {
2456 if (host->cmd) { 2596 if (host->cmd == host->data_cmd) {
2457 /* 2597 /*
2458 * Data managed to finish before the 2598 * Data managed to finish before the
2459 * command completed. Make sure we do 2599 * command completed. Make sure we do
@@ -2537,6 +2677,9 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id)
2537 pr_err("%s: Card is consuming too much power!\n", 2677 pr_err("%s: Card is consuming too much power!\n",
2538 mmc_hostname(host->mmc)); 2678 mmc_hostname(host->mmc));
2539 2679
2680 if (intmask & SDHCI_INT_RETUNE)
2681 mmc_retune_needed(host->mmc);
2682
2540 if (intmask & SDHCI_INT_CARD_INT) { 2683 if (intmask & SDHCI_INT_CARD_INT) {
2541 sdhci_enable_sdio_irq_nolock(host, false); 2684 sdhci_enable_sdio_irq_nolock(host, false);
2542 host->thread_isr |= SDHCI_INT_CARD_INT; 2685 host->thread_isr |= SDHCI_INT_CARD_INT;
@@ -2546,7 +2689,7 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id)
2546 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 2689 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2547 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2690 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2548 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 2691 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2549 SDHCI_INT_CARD_INT); 2692 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
2550 2693
2551 if (intmask) { 2694 if (intmask) {
2552 unexpected |= intmask; 2695 unexpected |= intmask;
@@ -2582,8 +2725,10 @@ static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2582 spin_unlock_irqrestore(&host->lock, flags); 2725 spin_unlock_irqrestore(&host->lock, flags);
2583 2726
2584 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2727 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2585 sdhci_card_event(host->mmc); 2728 struct mmc_host *mmc = host->mmc;
2586 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 2729
2730 mmc->ops->card_event(mmc);
2731 mmc_detect_change(mmc, msecs_to_jiffies(200));
2587 } 2732 }
2588 2733
2589 if (isr & SDHCI_INT_CARD_INT) { 2734 if (isr & SDHCI_INT_CARD_INT) {
@@ -2605,18 +2750,31 @@ static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2605\*****************************************************************************/ 2750\*****************************************************************************/
2606 2751
2607#ifdef CONFIG_PM 2752#ifdef CONFIG_PM
2753/*
2754 * To enable wakeup events, the corresponding events have to be enabled in
2755 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2756 * Table' in the SD Host Controller Standard Specification.
2757 * It is useless to restore SDHCI_INT_ENABLE state in
2758 * sdhci_disable_irq_wakeups() since it will be set by
2759 * sdhci_enable_card_detection() or sdhci_init().
2760 */
2608void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2761void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2609{ 2762{
2610 u8 val; 2763 u8 val;
2611 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2764 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2612 | SDHCI_WAKE_ON_INT; 2765 | SDHCI_WAKE_ON_INT;
2766 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2767 SDHCI_INT_CARD_INT;
2613 2768
2614 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2769 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2615 val |= mask ; 2770 val |= mask ;
2616 /* Avoid fake wake up */ 2771 /* Avoid fake wake up */
2617 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 2772 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
2618 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2773 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2774 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2775 }
2619 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2776 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2777 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
2620} 2778}
2621EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2779EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2622 2780
@@ -2636,7 +2794,8 @@ int sdhci_suspend_host(struct sdhci_host *host)
2636 sdhci_disable_card_detection(host); 2794 sdhci_disable_card_detection(host);
2637 2795
2638 mmc_retune_timer_stop(host->mmc); 2796 mmc_retune_timer_stop(host->mmc);
2639 mmc_retune_needed(host->mmc); 2797 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
2798 mmc_retune_needed(host->mmc);
2640 2799
2641 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2800 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2642 host->ier = 0; 2801 host->ier = 0;
@@ -2654,6 +2813,7 @@ EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2654 2813
2655int sdhci_resume_host(struct sdhci_host *host) 2814int sdhci_resume_host(struct sdhci_host *host)
2656{ 2815{
2816 struct mmc_host *mmc = host->mmc;
2657 int ret = 0; 2817 int ret = 0;
2658 2818
2659 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2819 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
@@ -2667,7 +2827,7 @@ int sdhci_resume_host(struct sdhci_host *host)
2667 sdhci_init(host, 0); 2827 sdhci_init(host, 0);
2668 host->pwr = 0; 2828 host->pwr = 0;
2669 host->clock = 0; 2829 host->clock = 0;
2670 sdhci_set_ios(host->mmc, &host->mmc->ios); 2830 mmc->ops->set_ios(mmc, &mmc->ios);
2671 } else { 2831 } else {
2672 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 2832 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2673 mmiowb(); 2833 mmiowb();
@@ -2696,7 +2856,8 @@ int sdhci_runtime_suspend_host(struct sdhci_host *host)
2696 unsigned long flags; 2856 unsigned long flags;
2697 2857
2698 mmc_retune_timer_stop(host->mmc); 2858 mmc_retune_timer_stop(host->mmc);
2699 mmc_retune_needed(host->mmc); 2859 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
2860 mmc_retune_needed(host->mmc);
2700 2861
2701 spin_lock_irqsave(&host->lock, flags); 2862 spin_lock_irqsave(&host->lock, flags);
2702 host->ier &= SDHCI_INT_CARD_INT; 2863 host->ier &= SDHCI_INT_CARD_INT;
@@ -2716,6 +2877,7 @@ EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2716 2877
2717int sdhci_runtime_resume_host(struct sdhci_host *host) 2878int sdhci_runtime_resume_host(struct sdhci_host *host)
2718{ 2879{
2880 struct mmc_host *mmc = host->mmc;
2719 unsigned long flags; 2881 unsigned long flags;
2720 int host_flags = host->flags; 2882 int host_flags = host->flags;
2721 2883
@@ -2729,8 +2891,8 @@ int sdhci_runtime_resume_host(struct sdhci_host *host)
2729 /* Force clock and power re-program */ 2891 /* Force clock and power re-program */
2730 host->pwr = 0; 2892 host->pwr = 0;
2731 host->clock = 0; 2893 host->clock = 0;
2732 sdhci_start_signal_voltage_switch(host->mmc, &host->mmc->ios); 2894 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2733 sdhci_set_ios(host->mmc, &host->mmc->ios); 2895 mmc->ops->set_ios(mmc, &mmc->ios);
2734 2896
2735 if ((host_flags & SDHCI_PV_ENABLED) && 2897 if ((host_flags & SDHCI_PV_ENABLED) &&
2736 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 2898 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
@@ -2781,6 +2943,8 @@ struct sdhci_host *sdhci_alloc_host(struct device *dev,
2781 host->mmc_host_ops = sdhci_ops; 2943 host->mmc_host_ops = sdhci_ops;
2782 mmc->ops = &host->mmc_host_ops; 2944 mmc->ops = &host->mmc_host_ops;
2783 2945
2946 host->flags = SDHCI_SIGNALING_330;
2947
2784 return host; 2948 return host;
2785} 2949}
2786 2950
@@ -2816,10 +2980,41 @@ static int sdhci_set_dma_mask(struct sdhci_host *host)
2816 return ret; 2980 return ret;
2817} 2981}
2818 2982
2819int sdhci_add_host(struct sdhci_host *host) 2983void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
2984{
2985 u16 v;
2986
2987 if (host->read_caps)
2988 return;
2989
2990 host->read_caps = true;
2991
2992 if (debug_quirks)
2993 host->quirks = debug_quirks;
2994
2995 if (debug_quirks2)
2996 host->quirks2 = debug_quirks2;
2997
2998 sdhci_do_reset(host, SDHCI_RESET_ALL);
2999
3000 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3001 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3002
3003 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3004 return;
3005
3006 host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES);
3007
3008 if (host->version < SDHCI_SPEC_300)
3009 return;
3010
3011 host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1);
3012}
3013EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3014
3015int sdhci_setup_host(struct sdhci_host *host)
2820{ 3016{
2821 struct mmc_host *mmc; 3017 struct mmc_host *mmc;
2822 u32 caps[2] = {0, 0};
2823 u32 max_current_caps; 3018 u32 max_current_caps;
2824 unsigned int ocr_avail; 3019 unsigned int ocr_avail;
2825 unsigned int override_timeout_clk; 3020 unsigned int override_timeout_clk;
@@ -2832,34 +3027,28 @@ int sdhci_add_host(struct sdhci_host *host)
2832 3027
2833 mmc = host->mmc; 3028 mmc = host->mmc;
2834 3029
2835 if (debug_quirks) 3030 /*
2836 host->quirks = debug_quirks; 3031 * If there are external regulators, get them. Note this must be done
2837 if (debug_quirks2) 3032 * early before resetting the host and reading the capabilities so that
2838 host->quirks2 = debug_quirks2; 3033 * the host can take the appropriate action if regulators are not
3034 * available.
3035 */
3036 ret = mmc_regulator_get_supply(mmc);
3037 if (ret == -EPROBE_DEFER)
3038 return ret;
2839 3039
2840 override_timeout_clk = host->timeout_clk; 3040 sdhci_read_caps(host);
2841 3041
2842 sdhci_do_reset(host, SDHCI_RESET_ALL); 3042 override_timeout_clk = host->timeout_clk;
2843 3043
2844 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2845 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2846 >> SDHCI_SPEC_VER_SHIFT;
2847 if (host->version > SDHCI_SPEC_300) { 3044 if (host->version > SDHCI_SPEC_300) {
2848 pr_err("%s: Unknown controller version (%d). You may experience problems.\n", 3045 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2849 mmc_hostname(mmc), host->version); 3046 mmc_hostname(mmc), host->version);
2850 } 3047 }
2851 3048
2852 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2853 sdhci_readl(host, SDHCI_CAPABILITIES);
2854
2855 if (host->version >= SDHCI_SPEC_300)
2856 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2857 host->caps1 :
2858 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2859
2860 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 3049 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2861 host->flags |= SDHCI_USE_SDMA; 3050 host->flags |= SDHCI_USE_SDMA;
2862 else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) 3051 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
2863 DBG("Controller doesn't have SDMA capability\n"); 3052 DBG("Controller doesn't have SDMA capability\n");
2864 else 3053 else
2865 host->flags |= SDHCI_USE_SDMA; 3054 host->flags |= SDHCI_USE_SDMA;
@@ -2871,7 +3060,7 @@ int sdhci_add_host(struct sdhci_host *host)
2871 } 3060 }
2872 3061
2873 if ((host->version >= SDHCI_SPEC_200) && 3062 if ((host->version >= SDHCI_SPEC_200) &&
2874 (caps[0] & SDHCI_CAN_DO_ADMA2)) 3063 (host->caps & SDHCI_CAN_DO_ADMA2))
2875 host->flags |= SDHCI_USE_ADMA; 3064 host->flags |= SDHCI_USE_ADMA;
2876 3065
2877 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 3066 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
@@ -2887,7 +3076,7 @@ int sdhci_add_host(struct sdhci_host *host)
2887 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to 3076 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2888 * implement. 3077 * implement.
2889 */ 3078 */
2890 if (caps[0] & SDHCI_CAN_64BIT) 3079 if (host->caps & SDHCI_CAN_64BIT)
2891 host->flags |= SDHCI_USE_64_BIT_DMA; 3080 host->flags |= SDHCI_USE_64_BIT_DMA;
2892 3081
2893 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 3082 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
@@ -2963,10 +3152,10 @@ int sdhci_add_host(struct sdhci_host *host)
2963 } 3152 }
2964 3153
2965 if (host->version >= SDHCI_SPEC_300) 3154 if (host->version >= SDHCI_SPEC_300)
2966 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) 3155 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
2967 >> SDHCI_CLOCK_BASE_SHIFT; 3156 >> SDHCI_CLOCK_BASE_SHIFT;
2968 else 3157 else
2969 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) 3158 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
2970 >> SDHCI_CLOCK_BASE_SHIFT; 3159 >> SDHCI_CLOCK_BASE_SHIFT;
2971 3160
2972 host->max_clk *= 1000000; 3161 host->max_clk *= 1000000;
@@ -2985,7 +3174,7 @@ int sdhci_add_host(struct sdhci_host *host)
2985 * In case of Host Controller v3.00, find out whether clock 3174 * In case of Host Controller v3.00, find out whether clock
2986 * multiplier is supported. 3175 * multiplier is supported.
2987 */ 3176 */
2988 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> 3177 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
2989 SDHCI_CLOCK_MUL_SHIFT; 3178 SDHCI_CLOCK_MUL_SHIFT;
2990 3179
2991 /* 3180 /*
@@ -3017,7 +3206,7 @@ int sdhci_add_host(struct sdhci_host *host)
3017 mmc->f_max = max_clk; 3206 mmc->f_max = max_clk;
3018 3207
3019 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 3208 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3020 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> 3209 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3021 SDHCI_TIMEOUT_CLK_SHIFT; 3210 SDHCI_TIMEOUT_CLK_SHIFT;
3022 if (host->timeout_clk == 0) { 3211 if (host->timeout_clk == 0) {
3023 if (host->ops->get_timeout_clock) { 3212 if (host->ops->get_timeout_clock) {
@@ -3031,7 +3220,7 @@ int sdhci_add_host(struct sdhci_host *host)
3031 } 3220 }
3032 } 3221 }
3033 3222
3034 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) 3223 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3035 host->timeout_clk *= 1000; 3224 host->timeout_clk *= 1000;
3036 3225
3037 if (override_timeout_clk) 3226 if (override_timeout_clk)
@@ -3072,27 +3261,22 @@ int sdhci_add_host(struct sdhci_host *host)
3072 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 3261 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3073 mmc->caps &= ~MMC_CAP_CMD23; 3262 mmc->caps &= ~MMC_CAP_CMD23;
3074 3263
3075 if (caps[0] & SDHCI_CAN_DO_HISPD) 3264 if (host->caps & SDHCI_CAN_DO_HISPD)
3076 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 3265 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3077 3266
3078 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 3267 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3079 !(mmc->caps & MMC_CAP_NONREMOVABLE) && 3268 mmc_card_is_removable(mmc) &&
3080 mmc_gpio_get_cd(host->mmc) < 0) 3269 mmc_gpio_get_cd(host->mmc) < 0)
3081 mmc->caps |= MMC_CAP_NEEDS_POLL; 3270 mmc->caps |= MMC_CAP_NEEDS_POLL;
3082 3271
3083 /* If there are external regulators, get them */
3084 ret = mmc_regulator_get_supply(mmc);
3085 if (ret == -EPROBE_DEFER)
3086 goto undma;
3087
3088 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 3272 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3089 if (!IS_ERR(mmc->supply.vqmmc)) { 3273 if (!IS_ERR(mmc->supply.vqmmc)) {
3090 ret = regulator_enable(mmc->supply.vqmmc); 3274 ret = regulator_enable(mmc->supply.vqmmc);
3091 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, 3275 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3092 1950000)) 3276 1950000))
3093 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | 3277 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3094 SDHCI_SUPPORT_SDR50 | 3278 SDHCI_SUPPORT_SDR50 |
3095 SDHCI_SUPPORT_DDR50); 3279 SDHCI_SUPPORT_DDR50);
3096 if (ret) { 3280 if (ret) {
3097 pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 3281 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3098 mmc_hostname(mmc), ret); 3282 mmc_hostname(mmc), ret);
@@ -3100,28 +3284,30 @@ int sdhci_add_host(struct sdhci_host *host)
3100 } 3284 }
3101 } 3285 }
3102 3286
3103 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) 3287 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3104 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3288 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3105 SDHCI_SUPPORT_DDR50); 3289 SDHCI_SUPPORT_DDR50);
3290 }
3106 3291
3107 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 3292 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3108 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3293 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3109 SDHCI_SUPPORT_DDR50)) 3294 SDHCI_SUPPORT_DDR50))
3110 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 3295 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3111 3296
3112 /* SDR104 supports also implies SDR50 support */ 3297 /* SDR104 supports also implies SDR50 support */
3113 if (caps[1] & SDHCI_SUPPORT_SDR104) { 3298 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3114 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 3299 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3115 /* SD3.0: SDR104 is supported so (for eMMC) the caps2 3300 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3116 * field can be promoted to support HS200. 3301 * field can be promoted to support HS200.
3117 */ 3302 */
3118 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) 3303 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3119 mmc->caps2 |= MMC_CAP2_HS200; 3304 mmc->caps2 |= MMC_CAP2_HS200;
3120 } else if (caps[1] & SDHCI_SUPPORT_SDR50) 3305 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3121 mmc->caps |= MMC_CAP_UHS_SDR50; 3306 mmc->caps |= MMC_CAP_UHS_SDR50;
3307 }
3122 3308
3123 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && 3309 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3124 (caps[1] & SDHCI_SUPPORT_HS400)) 3310 (host->caps1 & SDHCI_SUPPORT_HS400))
3125 mmc->caps2 |= MMC_CAP2_HS400; 3311 mmc->caps2 |= MMC_CAP2_HS400;
3126 3312
3127 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && 3313 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
@@ -3130,25 +3316,25 @@ int sdhci_add_host(struct sdhci_host *host)
3130 1300000))) 3316 1300000)))
3131 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; 3317 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3132 3318
3133 if ((caps[1] & SDHCI_SUPPORT_DDR50) && 3319 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3134 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 3320 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3135 mmc->caps |= MMC_CAP_UHS_DDR50; 3321 mmc->caps |= MMC_CAP_UHS_DDR50;
3136 3322
3137 /* Does the host need tuning for SDR50? */ 3323 /* Does the host need tuning for SDR50? */
3138 if (caps[1] & SDHCI_USE_SDR50_TUNING) 3324 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3139 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 3325 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3140 3326
3141 /* Driver Type(s) (A, C, D) supported by the host */ 3327 /* Driver Type(s) (A, C, D) supported by the host */
3142 if (caps[1] & SDHCI_DRIVER_TYPE_A) 3328 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3143 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 3329 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3144 if (caps[1] & SDHCI_DRIVER_TYPE_C) 3330 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3145 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 3331 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3146 if (caps[1] & SDHCI_DRIVER_TYPE_D) 3332 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3147 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 3333 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3148 3334
3149 /* Initial value for re-tuning timer count */ 3335 /* Initial value for re-tuning timer count */
3150 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 3336 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3151 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 3337 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3152 3338
3153 /* 3339 /*
3154 * In case Re-tuning Timer is not disabled, the actual value of 3340 * In case Re-tuning Timer is not disabled, the actual value of
@@ -3158,7 +3344,7 @@ int sdhci_add_host(struct sdhci_host *host)
3158 host->tuning_count = 1 << (host->tuning_count - 1); 3344 host->tuning_count = 1 << (host->tuning_count - 1);
3159 3345
3160 /* Re-tuning mode supported by the Host Controller */ 3346 /* Re-tuning mode supported by the Host Controller */
3161 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> 3347 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3162 SDHCI_RETUNING_MODE_SHIFT; 3348 SDHCI_RETUNING_MODE_SHIFT;
3163 3349
3164 ocr_avail = 0; 3350 ocr_avail = 0;
@@ -3187,7 +3373,7 @@ int sdhci_add_host(struct sdhci_host *host)
3187 } 3373 }
3188 } 3374 }
3189 3375
3190 if (caps[0] & SDHCI_CAN_VDD_330) { 3376 if (host->caps & SDHCI_CAN_VDD_330) {
3191 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 3377 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3192 3378
3193 mmc->max_current_330 = ((max_current_caps & 3379 mmc->max_current_330 = ((max_current_caps &
@@ -3195,7 +3381,7 @@ int sdhci_add_host(struct sdhci_host *host)
3195 SDHCI_MAX_CURRENT_330_SHIFT) * 3381 SDHCI_MAX_CURRENT_330_SHIFT) *
3196 SDHCI_MAX_CURRENT_MULTIPLIER; 3382 SDHCI_MAX_CURRENT_MULTIPLIER;
3197 } 3383 }
3198 if (caps[0] & SDHCI_CAN_VDD_300) { 3384 if (host->caps & SDHCI_CAN_VDD_300) {
3199 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 3385 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3200 3386
3201 mmc->max_current_300 = ((max_current_caps & 3387 mmc->max_current_300 = ((max_current_caps &
@@ -3203,7 +3389,7 @@ int sdhci_add_host(struct sdhci_host *host)
3203 SDHCI_MAX_CURRENT_300_SHIFT) * 3389 SDHCI_MAX_CURRENT_300_SHIFT) *
3204 SDHCI_MAX_CURRENT_MULTIPLIER; 3390 SDHCI_MAX_CURRENT_MULTIPLIER;
3205 } 3391 }
3206 if (caps[0] & SDHCI_CAN_VDD_180) { 3392 if (host->caps & SDHCI_CAN_VDD_180) {
3207 ocr_avail |= MMC_VDD_165_195; 3393 ocr_avail |= MMC_VDD_165_195;
3208 3394
3209 mmc->max_current_180 = ((max_current_caps & 3395 mmc->max_current_180 = ((max_current_caps &
@@ -3240,6 +3426,15 @@ int sdhci_add_host(struct sdhci_host *host)
3240 goto unreg; 3426 goto unreg;
3241 } 3427 }
3242 3428
3429 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3430 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3431 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3432 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3433 host->flags |= SDHCI_SIGNALING_180;
3434
3435 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3436 host->flags |= SDHCI_SIGNALING_120;
3437
3243 spin_lock_init(&host->lock); 3438 spin_lock_init(&host->lock);
3244 3439
3245 /* 3440 /*
@@ -3281,7 +3476,7 @@ int sdhci_add_host(struct sdhci_host *host)
3281 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 3476 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3282 mmc->max_blk_size = 2; 3477 mmc->max_blk_size = 2;
3283 } else { 3478 } else {
3284 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> 3479 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
3285 SDHCI_MAX_BLOCK_SHIFT; 3480 SDHCI_MAX_BLOCK_SHIFT;
3286 if (mmc->max_blk_size >= 3) { 3481 if (mmc->max_blk_size >= 3) {
3287 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", 3482 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
@@ -3297,6 +3492,28 @@ int sdhci_add_host(struct sdhci_host *host)
3297 */ 3492 */
3298 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 3493 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3299 3494
3495 return 0;
3496
3497unreg:
3498 if (!IS_ERR(mmc->supply.vqmmc))
3499 regulator_disable(mmc->supply.vqmmc);
3500undma:
3501 if (host->align_buffer)
3502 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3503 host->adma_table_sz, host->align_buffer,
3504 host->align_addr);
3505 host->adma_table = NULL;
3506 host->align_buffer = NULL;
3507
3508 return ret;
3509}
3510EXPORT_SYMBOL_GPL(sdhci_setup_host);
3511
3512int __sdhci_add_host(struct sdhci_host *host)
3513{
3514 struct mmc_host *mmc = host->mmc;
3515 int ret;
3516
3300 /* 3517 /*
3301 * Init tasklets. 3518 * Init tasklets.
3302 */ 3519 */
@@ -3304,6 +3521,8 @@ int sdhci_add_host(struct sdhci_host *host)
3304 sdhci_tasklet_finish, (unsigned long)host); 3521 sdhci_tasklet_finish, (unsigned long)host);
3305 3522
3306 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 3523 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3524 setup_timer(&host->data_timer, sdhci_timeout_data_timer,
3525 (unsigned long)host);
3307 3526
3308 init_waitqueue_head(&host->buf_ready_int); 3527 init_waitqueue_head(&host->buf_ready_int);
3309 3528
@@ -3353,10 +3572,10 @@ unirq:
3353 free_irq(host->irq, host); 3572 free_irq(host->irq, host);
3354untasklet: 3573untasklet:
3355 tasklet_kill(&host->finish_tasklet); 3574 tasklet_kill(&host->finish_tasklet);
3356unreg: 3575
3357 if (!IS_ERR(mmc->supply.vqmmc)) 3576 if (!IS_ERR(mmc->supply.vqmmc))
3358 regulator_disable(mmc->supply.vqmmc); 3577 regulator_disable(mmc->supply.vqmmc);
3359undma: 3578
3360 if (host->align_buffer) 3579 if (host->align_buffer)
3361 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3580 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3362 host->adma_table_sz, host->align_buffer, 3581 host->adma_table_sz, host->align_buffer,
@@ -3366,7 +3585,18 @@ undma:
3366 3585
3367 return ret; 3586 return ret;
3368} 3587}
3588EXPORT_SYMBOL_GPL(__sdhci_add_host);
3589
3590int sdhci_add_host(struct sdhci_host *host)
3591{
3592 int ret;
3369 3593
3594 ret = sdhci_setup_host(host);
3595 if (ret)
3596 return ret;
3597
3598 return __sdhci_add_host(host);
3599}
3370EXPORT_SYMBOL_GPL(sdhci_add_host); 3600EXPORT_SYMBOL_GPL(sdhci_add_host);
3371 3601
3372void sdhci_remove_host(struct sdhci_host *host, int dead) 3602void sdhci_remove_host(struct sdhci_host *host, int dead)
@@ -3379,12 +3609,10 @@ void sdhci_remove_host(struct sdhci_host *host, int dead)
3379 3609
3380 host->flags |= SDHCI_DEVICE_DEAD; 3610 host->flags |= SDHCI_DEVICE_DEAD;
3381 3611
3382 if (host->mrq) { 3612 if (sdhci_has_requests(host)) {
3383 pr_err("%s: Controller removed during " 3613 pr_err("%s: Controller removed during "
3384 " transfer!\n", mmc_hostname(mmc)); 3614 " transfer!\n", mmc_hostname(mmc));
3385 3615 sdhci_error_out_mrqs(host, -ENOMEDIUM);
3386 host->mrq->cmd->error = -ENOMEDIUM;
3387 tasklet_schedule(&host->finish_tasklet);
3388 } 3616 }
3389 3617
3390 spin_unlock_irqrestore(&host->lock, flags); 3618 spin_unlock_irqrestore(&host->lock, flags);
@@ -3404,6 +3632,7 @@ void sdhci_remove_host(struct sdhci_host *host, int dead)
3404 free_irq(host->irq, host); 3632 free_irq(host->irq, host);
3405 3633
3406 del_timer_sync(&host->timer); 3634 del_timer_sync(&host->timer);
3635 del_timer_sync(&host->data_timer);
3407 3636
3408 tasklet_kill(&host->finish_tasklet); 3637 tasklet_kill(&host->finish_tasklet);
3409 3638
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 609f87ca536b..0411c9f36461 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -128,6 +128,7 @@
128#define SDHCI_INT_CARD_INSERT 0x00000040 128#define SDHCI_INT_CARD_INSERT 0x00000040
129#define SDHCI_INT_CARD_REMOVE 0x00000080 129#define SDHCI_INT_CARD_REMOVE 0x00000080
130#define SDHCI_INT_CARD_INT 0x00000100 130#define SDHCI_INT_CARD_INT 0x00000100
131#define SDHCI_INT_RETUNE 0x00001000
131#define SDHCI_INT_ERROR 0x00008000 132#define SDHCI_INT_ERROR 0x00008000
132#define SDHCI_INT_TIMEOUT 0x00010000 133#define SDHCI_INT_TIMEOUT 0x00010000
133#define SDHCI_INT_CRC 0x00020000 134#define SDHCI_INT_CRC 0x00020000
@@ -186,6 +187,7 @@
186#define SDHCI_CAN_DO_ADMA1 0x00100000 187#define SDHCI_CAN_DO_ADMA1 0x00100000
187#define SDHCI_CAN_DO_HISPD 0x00200000 188#define SDHCI_CAN_DO_HISPD 0x00200000
188#define SDHCI_CAN_DO_SDMA 0x00400000 189#define SDHCI_CAN_DO_SDMA 0x00400000
190#define SDHCI_CAN_DO_SUSPEND 0x00800000
189#define SDHCI_CAN_VDD_330 0x01000000 191#define SDHCI_CAN_VDD_330 0x01000000
190#define SDHCI_CAN_VDD_300 0x02000000 192#define SDHCI_CAN_VDD_300 0x02000000
191#define SDHCI_CAN_VDD_180 0x04000000 193#define SDHCI_CAN_VDD_180 0x04000000
@@ -314,6 +316,9 @@ struct sdhci_adma2_64_desc {
314 */ 316 */
315#define SDHCI_MAX_SEGS 128 317#define SDHCI_MAX_SEGS 128
316 318
319/* Allow for a a command request and a data request at the same time */
320#define SDHCI_MAX_MRQS 2
321
317enum sdhci_cookie { 322enum sdhci_cookie {
318 COOKIE_UNMAPPED, 323 COOKIE_UNMAPPED,
319 COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ 324 COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */
@@ -447,6 +452,9 @@ struct sdhci_host {
447#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ 452#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
448#define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 453#define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
449#define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 454#define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */
455#define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */
456#define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */
457#define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */
450 458
451 unsigned int version; /* SDHCI spec. version */ 459 unsigned int version; /* SDHCI spec. version */
452 460
@@ -460,12 +468,13 @@ struct sdhci_host {
460 bool runtime_suspended; /* Host is runtime suspended */ 468 bool runtime_suspended; /* Host is runtime suspended */
461 bool bus_on; /* Bus power prevents runtime suspend */ 469 bool bus_on; /* Bus power prevents runtime suspend */
462 bool preset_enabled; /* Preset is enabled */ 470 bool preset_enabled; /* Preset is enabled */
471 bool pending_reset; /* Cmd/data reset is pending */
463 472
464 struct mmc_request *mrq; /* Current request */ 473 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */
465 struct mmc_command *cmd; /* Current command */ 474 struct mmc_command *cmd; /* Current command */
475 struct mmc_command *data_cmd; /* Current data command */
466 struct mmc_data *data; /* Current data request */ 476 struct mmc_data *data; /* Current data request */
467 unsigned int data_early:1; /* Data finished before cmd */ 477 unsigned int data_early:1; /* Data finished before cmd */
468 unsigned int busy_handle:1; /* Handling the order of Busy-end */
469 478
470 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 479 struct sg_mapping_iter sg_miter; /* SG state for PIO */
471 unsigned int blocks; /* remaining PIO blocks */ 480 unsigned int blocks; /* remaining PIO blocks */
@@ -486,9 +495,11 @@ struct sdhci_host {
486 struct tasklet_struct finish_tasklet; /* Tasklet structures */ 495 struct tasklet_struct finish_tasklet; /* Tasklet structures */
487 496
488 struct timer_list timer; /* Timer for timeouts */ 497 struct timer_list timer; /* Timer for timeouts */
498 struct timer_list data_timer; /* Timer for data timeouts */
489 499
490 u32 caps; /* Alternative CAPABILITY_0 */ 500 u32 caps; /* CAPABILITY_0 */
491 u32 caps1; /* Alternative CAPABILITY_1 */ 501 u32 caps1; /* CAPABILITY_1 */
502 bool read_caps; /* Capability flags have been read */
492 503
493 unsigned int ocr_avail_sdio; /* OCR bit masks */ 504 unsigned int ocr_avail_sdio; /* OCR bit masks */
494 unsigned int ocr_avail_sd; 505 unsigned int ocr_avail_sd;
@@ -508,6 +519,8 @@ struct sdhci_host {
508 unsigned int tuning_count; /* Timer count for re-tuning */ 519 unsigned int tuning_count; /* Timer count for re-tuning */
509 unsigned int tuning_mode; /* Re-tuning mode supported by host */ 520 unsigned int tuning_mode; /* Re-tuning mode supported by host */
510#define SDHCI_TUNING_MODE_1 0 521#define SDHCI_TUNING_MODE_1 0
522#define SDHCI_TUNING_MODE_2 1
523#define SDHCI_TUNING_MODE_3 2
511 524
512 unsigned long private[0] ____cacheline_aligned; 525 unsigned long private[0] ____cacheline_aligned;
513}; 526};
@@ -645,11 +658,20 @@ static inline void *sdhci_priv(struct sdhci_host *host)
645} 658}
646 659
647extern void sdhci_card_detect(struct sdhci_host *host); 660extern void sdhci_card_detect(struct sdhci_host *host);
661extern void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps,
662 u32 *caps1);
663extern int sdhci_setup_host(struct sdhci_host *host);
664extern int __sdhci_add_host(struct sdhci_host *host);
648extern int sdhci_add_host(struct sdhci_host *host); 665extern int sdhci_add_host(struct sdhci_host *host);
649extern void sdhci_remove_host(struct sdhci_host *host, int dead); 666extern void sdhci_remove_host(struct sdhci_host *host, int dead);
650extern void sdhci_send_command(struct sdhci_host *host, 667extern void sdhci_send_command(struct sdhci_host *host,
651 struct mmc_command *cmd); 668 struct mmc_command *cmd);
652 669
670static inline void sdhci_read_caps(struct sdhci_host *host)
671{
672 __sdhci_read_caps(host, NULL, NULL, NULL);
673}
674
653static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) 675static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host)
654{ 676{
655 return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); 677 return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED);
diff --git a/drivers/mmc/host/sdhci_f_sdh30.c b/drivers/mmc/host/sdhci_f_sdh30.c
index 983b8b32ef96..111b66f5439b 100644
--- a/drivers/mmc/host/sdhci_f_sdh30.c
+++ b/drivers/mmc/host/sdhci_f_sdh30.c
@@ -222,7 +222,7 @@ static struct platform_driver sdhci_f_sdh30_driver = {
222 .driver = { 222 .driver = {
223 .name = "f_sdh30", 223 .name = "f_sdh30",
224 .of_match_table = f_sdh30_dt_ids, 224 .of_match_table = f_sdh30_dt_ids,
225 .pm = SDHCI_PLTFM_PMOPS, 225 .pm = &sdhci_pltfm_pmops,
226 }, 226 },
227 .probe = sdhci_f_sdh30_probe, 227 .probe = sdhci_f_sdh30_probe,
228 .remove = sdhci_f_sdh30_remove, 228 .remove = sdhci_f_sdh30_remove,
diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c
index dd64b8663984..900778421be6 100644
--- a/drivers/mmc/host/sh_mmcif.c
+++ b/drivers/mmc/host/sh_mmcif.c
@@ -574,7 +574,7 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
574 if (state1 & STS1_CMDSEQ) { 574 if (state1 & STS1_CMDSEQ) {
575 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 575 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
576 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 576 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
577 for (timeout = 10000000; timeout; timeout--) { 577 for (timeout = 10000; timeout; timeout--) {
578 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 578 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
579 & STS1_CMDSEQ)) 579 & STS1_CMDSEQ))
580 break; 580 break;
@@ -819,10 +819,12 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
819 tmp |= CMD_SET_RTYP_NO; 819 tmp |= CMD_SET_RTYP_NO;
820 break; 820 break;
821 case MMC_RSP_R1: 821 case MMC_RSP_R1:
822 case MMC_RSP_R1B:
823 case MMC_RSP_R3: 822 case MMC_RSP_R3:
824 tmp |= CMD_SET_RTYP_6B; 823 tmp |= CMD_SET_RTYP_6B;
825 break; 824 break;
825 case MMC_RSP_R1B:
826 tmp |= CMD_SET_RBSY | CMD_SET_RTYP_6B;
827 break;
826 case MMC_RSP_R2: 828 case MMC_RSP_R2:
827 tmp |= CMD_SET_RTYP_17B; 829 tmp |= CMD_SET_RTYP_17B;
828 break; 830 break;
@@ -830,17 +832,7 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
830 dev_err(dev, "Unsupported response type.\n"); 832 dev_err(dev, "Unsupported response type.\n");
831 break; 833 break;
832 } 834 }
833 switch (opc) { 835
834 /* RBSY */
835 case MMC_SLEEP_AWAKE:
836 case MMC_SWITCH:
837 case MMC_STOP_TRANSMISSION:
838 case MMC_SET_WRITE_PROT:
839 case MMC_CLR_WRITE_PROT:
840 case MMC_ERASE:
841 tmp |= CMD_SET_RBSY;
842 break;
843 }
844 /* WDAT / DATW */ 836 /* WDAT / DATW */
845 if (data) { 837 if (data) {
846 tmp |= CMD_SET_WDAT; 838 tmp |= CMD_SET_WDAT;
@@ -925,23 +917,13 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
925{ 917{
926 struct mmc_command *cmd = mrq->cmd; 918 struct mmc_command *cmd = mrq->cmd;
927 u32 opc = cmd->opcode; 919 u32 opc = cmd->opcode;
928 u32 mask; 920 u32 mask = 0;
929 unsigned long flags; 921 unsigned long flags;
930 922
931 switch (opc) { 923 if (cmd->flags & MMC_RSP_BUSY)
932 /* response busy check */
933 case MMC_SLEEP_AWAKE:
934 case MMC_SWITCH:
935 case MMC_STOP_TRANSMISSION:
936 case MMC_SET_WRITE_PROT:
937 case MMC_CLR_WRITE_PROT:
938 case MMC_ERASE:
939 mask = MASK_START_CMD | MASK_MRBSYE; 924 mask = MASK_START_CMD | MASK_MRBSYE;
940 break; 925 else
941 default:
942 mask = MASK_START_CMD | MASK_MCRSPE; 926 mask = MASK_START_CMD | MASK_MCRSPE;
943 break;
944 }
945 927
946 if (host->ccs_enable) 928 if (host->ccs_enable)
947 mask |= MASK_MCCSTO; 929 mask |= MASK_MCCSTO;
@@ -1009,22 +991,6 @@ static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
1009 host->state = STATE_REQUEST; 991 host->state = STATE_REQUEST;
1010 spin_unlock_irqrestore(&host->lock, flags); 992 spin_unlock_irqrestore(&host->lock, flags);
1011 993
1012 switch (mrq->cmd->opcode) {
1013 /* MMCIF does not support SD/SDIO command */
1014 case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */
1015 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
1016 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)
1017 break;
1018 case MMC_APP_CMD:
1019 case SD_IO_RW_DIRECT:
1020 host->state = STATE_IDLE;
1021 mrq->cmd->error = -ETIMEDOUT;
1022 mmc_request_done(mmc, mrq);
1023 return;
1024 default:
1025 break;
1026 }
1027
1028 host->mrq = mrq; 994 host->mrq = mrq;
1029 995
1030 sh_mmcif_start_cmd(host, mrq); 996 sh_mmcif_start_cmd(host, mrq);
@@ -1488,6 +1454,9 @@ static int sh_mmcif_probe(struct platform_device *pdev)
1488 sh_mmcif_init_ocr(host); 1454 sh_mmcif_init_ocr(host);
1489 1455
1490 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; 1456 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY;
1457 mmc->caps2 |= MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
1458 mmc->max_busy_timeout = 10000;
1459
1491 if (pd && pd->caps) 1460 if (pd && pd->caps)
1492 mmc->caps |= pd->caps; 1461 mmc->caps |= pd->caps;
1493 mmc->max_segs = 32; 1462 mmc->max_segs = 32;
diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c
index f750f9494410..c3b651bf89cb 100644
--- a/drivers/mmc/host/sh_mobile_sdhi.c
+++ b/drivers/mmc/host/sh_mobile_sdhi.c
@@ -39,6 +39,12 @@
39 39
40#define EXT_ACC 0xe4 40#define EXT_ACC 0xe4
41 41
42#define SDHI_VER_GEN2_SDR50 0x490c
43/* very old datasheets said 0x490c for SDR104, too. They are wrong! */
44#define SDHI_VER_GEN2_SDR104 0xcb0d
45#define SDHI_VER_GEN3_SD 0xcc10
46#define SDHI_VER_GEN3_SDMMC 0xcd10
47
42#define host_to_priv(host) container_of((host)->pdata, struct sh_mobile_sdhi, mmc_data) 48#define host_to_priv(host) container_of((host)->pdata, struct sh_mobile_sdhi, mmc_data)
43 49
44struct sh_mobile_sdhi_of_data { 50struct sh_mobile_sdhi_of_data {
@@ -109,14 +115,14 @@ static void sh_mobile_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
109 * sh_mobile_sdhi_of_data :: dma_buswidth 115 * sh_mobile_sdhi_of_data :: dma_buswidth
110 */ 116 */
111 switch (sd_ctrl_read16(host, CTL_VERSION)) { 117 switch (sd_ctrl_read16(host, CTL_VERSION)) {
112 case 0x490C: 118 case SDHI_VER_GEN2_SDR50:
113 val = (width == 32) ? 0x0001 : 0x0000; 119 val = (width == 32) ? 0x0001 : 0x0000;
114 break; 120 break;
115 case 0xCB0D: 121 case SDHI_VER_GEN2_SDR104:
116 val = (width == 32) ? 0x0000 : 0x0001; 122 val = (width == 32) ? 0x0000 : 0x0001;
117 break; 123 break;
118 case 0xCC10: /* Gen3, SD only */ 124 case SDHI_VER_GEN3_SD:
119 case 0xCD10: /* Gen3, SD + MMC */ 125 case SDHI_VER_GEN3_SDMMC:
120 if (width == 64) 126 if (width == 64)
121 val = 0x0000; 127 val = 0x0000;
122 else if (width == 32) 128 else if (width == 32)
diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
index 1aac2ad8edf2..7f63ec05bdf4 100644
--- a/drivers/mmc/host/tmio_mmc.h
+++ b/drivers/mmc/host/tmio_mmc.h
@@ -259,7 +259,7 @@ static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
259 259
260static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host, int addr, u32 val) 260static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host, int addr, u32 val)
261{ 261{
262 writew(val, host->ctl + (addr << host->bus_shift)); 262 writew(val & 0xffff, host->ctl + (addr << host->bus_shift));
263 writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift)); 263 writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
264} 264}
265 265
diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c
index f44e2ab7aea2..92467efc4e2c 100644
--- a/drivers/mmc/host/tmio_mmc_pio.c
+++ b/drivers/mmc/host/tmio_mmc_pio.c
@@ -1086,7 +1086,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
1086 1086
1087 _host->native_hotplug = !(pdata->flags & TMIO_MMC_USE_GPIO_CD || 1087 _host->native_hotplug = !(pdata->flags & TMIO_MMC_USE_GPIO_CD ||
1088 mmc->caps & MMC_CAP_NEEDS_POLL || 1088 mmc->caps & MMC_CAP_NEEDS_POLL ||
1089 mmc->caps & MMC_CAP_NONREMOVABLE || 1089 !mmc_card_is_removable(mmc) ||
1090 mmc->slot.cd_irq >= 0); 1090 mmc->slot.cd_irq >= 0);
1091 1091
1092 if (tmio_mmc_clk_enable(_host) < 0) { 1092 if (tmio_mmc_clk_enable(_host) < 0) {
diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c
index 6ebcf3e41c46..fd57345ffed2 100644
--- a/drivers/phy/phy-rockchip-emmc.c
+++ b/drivers/phy/phy-rockchip-emmc.c
@@ -14,6 +14,7 @@
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 */ 15 */
16 16
17#include <linux/clk.h>
17#include <linux/delay.h> 18#include <linux/delay.h>
18#include <linux/mfd/syscon.h> 19#include <linux/mfd/syscon.h>
19#include <linux/module.h> 20#include <linux/module.h>
@@ -31,42 +32,64 @@
31 ((val) << (shift) | (mask) << ((shift) + 16)) 32 ((val) << (shift) | (mask) << ((shift) + 16))
32 33
33/* Register definition */ 34/* Register definition */
34#define GRF_EMMCPHY_CON0 0x0 35#define GRF_EMMCPHY_CON0 0x0
35#define GRF_EMMCPHY_CON1 0x4 36#define GRF_EMMCPHY_CON1 0x4
36#define GRF_EMMCPHY_CON2 0x8 37#define GRF_EMMCPHY_CON2 0x8
37#define GRF_EMMCPHY_CON3 0xc 38#define GRF_EMMCPHY_CON3 0xc
38#define GRF_EMMCPHY_CON4 0x10 39#define GRF_EMMCPHY_CON4 0x10
39#define GRF_EMMCPHY_CON5 0x14 40#define GRF_EMMCPHY_CON5 0x14
40#define GRF_EMMCPHY_CON6 0x18 41#define GRF_EMMCPHY_CON6 0x18
41#define GRF_EMMCPHY_STATUS 0x20 42#define GRF_EMMCPHY_STATUS 0x20
42 43
43#define PHYCTRL_PDB_MASK 0x1 44#define PHYCTRL_PDB_MASK 0x1
44#define PHYCTRL_PDB_SHIFT 0x0 45#define PHYCTRL_PDB_SHIFT 0x0
45#define PHYCTRL_PDB_PWR_ON 0x1 46#define PHYCTRL_PDB_PWR_ON 0x1
46#define PHYCTRL_PDB_PWR_OFF 0x0 47#define PHYCTRL_PDB_PWR_OFF 0x0
47#define PHYCTRL_ENDLL_MASK 0x1 48#define PHYCTRL_ENDLL_MASK 0x1
48#define PHYCTRL_ENDLL_SHIFT 0x1 49#define PHYCTRL_ENDLL_SHIFT 0x1
49#define PHYCTRL_ENDLL_ENABLE 0x1 50#define PHYCTRL_ENDLL_ENABLE 0x1
50#define PHYCTRL_ENDLL_DISABLE 0x0 51#define PHYCTRL_ENDLL_DISABLE 0x0
51#define PHYCTRL_CALDONE_MASK 0x1 52#define PHYCTRL_CALDONE_MASK 0x1
52#define PHYCTRL_CALDONE_SHIFT 0x6 53#define PHYCTRL_CALDONE_SHIFT 0x6
53#define PHYCTRL_CALDONE_DONE 0x1 54#define PHYCTRL_CALDONE_DONE 0x1
54#define PHYCTRL_CALDONE_GOING 0x0 55#define PHYCTRL_CALDONE_GOING 0x0
55#define PHYCTRL_DLLRDY_MASK 0x1 56#define PHYCTRL_DLLRDY_MASK 0x1
56#define PHYCTRL_DLLRDY_SHIFT 0x5 57#define PHYCTRL_DLLRDY_SHIFT 0x5
57#define PHYCTRL_DLLRDY_DONE 0x1 58#define PHYCTRL_DLLRDY_DONE 0x1
58#define PHYCTRL_DLLRDY_GOING 0x0 59#define PHYCTRL_DLLRDY_GOING 0x0
60#define PHYCTRL_FREQSEL_200M 0x0
61#define PHYCTRL_FREQSEL_50M 0x1
62#define PHYCTRL_FREQSEL_100M 0x2
63#define PHYCTRL_FREQSEL_150M 0x3
64#define PHYCTRL_FREQSEL_MASK 0x3
65#define PHYCTRL_FREQSEL_SHIFT 0xc
66#define PHYCTRL_DR_MASK 0x7
67#define PHYCTRL_DR_SHIFT 0x4
68#define PHYCTRL_DR_50OHM 0x0
69#define PHYCTRL_DR_33OHM 0x1
70#define PHYCTRL_DR_66OHM 0x2
71#define PHYCTRL_DR_100OHM 0x3
72#define PHYCTRL_DR_40OHM 0x4
73#define PHYCTRL_OTAPDLYENA 0x1
74#define PHYCTRL_OTAPDLYENA_MASK 0x1
75#define PHYCTRL_OTAPDLYENA_SHIFT 0xb
76#define PHYCTRL_OTAPDLYSEL_MASK 0xf
77#define PHYCTRL_OTAPDLYSEL_SHIFT 0x7
59 78
60struct rockchip_emmc_phy { 79struct rockchip_emmc_phy {
61 unsigned int reg_offset; 80 unsigned int reg_offset;
62 struct regmap *reg_base; 81 struct regmap *reg_base;
82 struct clk *emmcclk;
63}; 83};
64 84
65static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy, 85static int rockchip_emmc_phy_power(struct phy *phy, bool on_off)
66 bool on_off)
67{ 86{
87 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
68 unsigned int caldone; 88 unsigned int caldone;
69 unsigned int dllrdy; 89 unsigned int dllrdy;
90 unsigned int freqsel = PHYCTRL_FREQSEL_200M;
91 unsigned long rate;
92 unsigned long timeout;
70 93
71 /* 94 /*
72 * Keep phyctrl_pdb and phyctrl_endll low to allow 95 * Keep phyctrl_pdb and phyctrl_endll low to allow
@@ -87,6 +110,43 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
87 if (on_off == PHYCTRL_PDB_PWR_OFF) 110 if (on_off == PHYCTRL_PDB_PWR_OFF)
88 return 0; 111 return 0;
89 112
113 rate = clk_get_rate(rk_phy->emmcclk);
114
115 if (rate != 0) {
116 unsigned long ideal_rate;
117 unsigned long diff;
118
119 switch (rate) {
120 case 1 ... 74999999:
121 ideal_rate = 50000000;
122 freqsel = PHYCTRL_FREQSEL_50M;
123 break;
124 case 75000000 ... 124999999:
125 ideal_rate = 100000000;
126 freqsel = PHYCTRL_FREQSEL_100M;
127 break;
128 case 125000000 ... 174999999:
129 ideal_rate = 150000000;
130 freqsel = PHYCTRL_FREQSEL_150M;
131 break;
132 default:
133 ideal_rate = 200000000;
134 break;
135 };
136
137 diff = (rate > ideal_rate) ?
138 rate - ideal_rate : ideal_rate - rate;
139
140 /*
141 * In order for tuning delays to be accurate we need to be
142 * pretty spot on for the DLL range, so warn if we're too
143 * far off. Also warn if we're above the 200 MHz max. Don't
144 * warn for really slow rates since we won't be tuning then.
145 */
146 if ((rate > 50000000 && diff > 15000000) || (rate > 200000000))
147 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
148 }
149
90 /* 150 /*
91 * According to the user manual, calpad calibration 151 * According to the user manual, calpad calibration
92 * cycle takes more than 2us without the minimal recommended 152 * cycle takes more than 2us without the minimal recommended
@@ -113,20 +173,62 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
113 return -ETIMEDOUT; 173 return -ETIMEDOUT;
114 } 174 }
115 175
176 /* Set the frequency of the DLL operation */
177 regmap_write(rk_phy->reg_base,
178 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
179 HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK,
180 PHYCTRL_FREQSEL_SHIFT));
181
182 /* Turn on the DLL */
116 regmap_write(rk_phy->reg_base, 183 regmap_write(rk_phy->reg_base,
117 rk_phy->reg_offset + GRF_EMMCPHY_CON6, 184 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
118 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE, 185 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
119 PHYCTRL_ENDLL_MASK, 186 PHYCTRL_ENDLL_MASK,
120 PHYCTRL_ENDLL_SHIFT)); 187 PHYCTRL_ENDLL_SHIFT));
188
121 /* 189 /*
122 * After enable analog DLL circuits, we need extra 10.2us 190 * We turned on the DLL even though the rate was 0 because we the
123 * for dll to be ready for work. 191 * clock might be turned on later. ...but we can't wait for the DLL
192 * to lock when the rate is 0 because it will never lock with no
193 * input clock.
194 *
195 * Technically we should be checking the lock later when the clock
196 * is turned on, but for now we won't.
124 */ 197 */
125 udelay(11); 198 if (rate == 0)
126 regmap_read(rk_phy->reg_base, 199 return 0;
127 rk_phy->reg_offset + GRF_EMMCPHY_STATUS, 200
128 &dllrdy); 201 /*
129 dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK; 202 * After enabling analog DLL circuits docs say that we need 10.2 us if
203 * our source clock is at 50 MHz and that lock time scales linearly
204 * with clock speed. If we are powering on the PHY and the card clock
205 * is super slow (like 100 kHZ) this could take as long as 5.1 ms as
206 * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
207 * Hopefully we won't be running at 100 kHz, but we should still make
208 * sure we wait long enough.
209 *
210 * NOTE: There appear to be corner cases where the DLL seems to take
211 * extra long to lock for reasons that aren't understood. In some
212 * extreme cases we've seen it take up to over 10ms (!). We'll be
213 * generous and give it 50ms. We still busy wait here because:
214 * - In most cases it should be super fast.
215 * - This is not called lots during normal operation so it shouldn't
216 * be a power or performance problem to busy wait. We expect it
217 * only at boot / resume. In both cases, eMMC is probably on the
218 * critical path so busy waiting a little extra time should be OK.
219 */
220 timeout = jiffies + msecs_to_jiffies(50);
221 do {
222 udelay(1);
223
224 regmap_read(rk_phy->reg_base,
225 rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
226 &dllrdy);
227 dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
228 if (dllrdy == PHYCTRL_DLLRDY_DONE)
229 break;
230 } while (!time_after(jiffies, timeout));
231
130 if (dllrdy != PHYCTRL_DLLRDY_DONE) { 232 if (dllrdy != PHYCTRL_DLLRDY_DONE) {
131 pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n"); 233 pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
132 return -ETIMEDOUT; 234 return -ETIMEDOUT;
@@ -135,33 +237,82 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
135 return 0; 237 return 0;
136} 238}
137 239
138static int rockchip_emmc_phy_power_off(struct phy *phy) 240static int rockchip_emmc_phy_init(struct phy *phy)
139{ 241{
140 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); 242 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
141 int ret = 0; 243 int ret = 0;
142 244
143 /* Power down emmc phy analog blocks */ 245 /*
144 ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_OFF); 246 * We purposely get the clock here and not in probe to avoid the
145 if (ret) 247 * circular dependency problem. We expect:
146 return ret; 248 * - PHY driver to probe
249 * - SDHCI driver to start probe
250 * - SDHCI driver to register it's clock
251 * - SDHCI driver to get the PHY
252 * - SDHCI driver to init the PHY
253 *
254 * The clock is optional, so upon any error we just set to NULL.
255 *
256 * NOTE: we don't do anything special for EPROBE_DEFER here. Given the
257 * above expected use case, EPROBE_DEFER isn't sensible to expect, so
258 * it's just like any other error.
259 */
260 rk_phy->emmcclk = clk_get(&phy->dev, "emmcclk");
261 if (IS_ERR(rk_phy->emmcclk)) {
262 dev_dbg(&phy->dev, "Error getting emmcclk: %d\n", ret);
263 rk_phy->emmcclk = NULL;
264 }
265
266 return ret;
267}
268
269static int rockchip_emmc_phy_exit(struct phy *phy)
270{
271 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
272
273 clk_put(rk_phy->emmcclk);
147 274
148 return 0; 275 return 0;
149} 276}
150 277
278static int rockchip_emmc_phy_power_off(struct phy *phy)
279{
280 /* Power down emmc phy analog blocks */
281 return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_OFF);
282}
283
151static int rockchip_emmc_phy_power_on(struct phy *phy) 284static int rockchip_emmc_phy_power_on(struct phy *phy)
152{ 285{
153 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); 286 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
154 int ret = 0;
155 287
156 /* Power up emmc phy analog blocks */ 288 /* Drive impedance: 50 Ohm */
157 ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_ON); 289 regmap_write(rk_phy->reg_base,
158 if (ret) 290 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
159 return ret; 291 HIWORD_UPDATE(PHYCTRL_DR_50OHM,
292 PHYCTRL_DR_MASK,
293 PHYCTRL_DR_SHIFT));
160 294
161 return 0; 295 /* Output tap delay: enable */
296 regmap_write(rk_phy->reg_base,
297 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
298 HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
299 PHYCTRL_OTAPDLYENA_MASK,
300 PHYCTRL_OTAPDLYENA_SHIFT));
301
302 /* Output tap delay */
303 regmap_write(rk_phy->reg_base,
304 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
305 HIWORD_UPDATE(4,
306 PHYCTRL_OTAPDLYSEL_MASK,
307 PHYCTRL_OTAPDLYSEL_SHIFT));
308
309 /* Power up emmc phy analog blocks */
310 return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_ON);
162} 311}
163 312
164static const struct phy_ops ops = { 313static const struct phy_ops ops = {
314 .init = rockchip_emmc_phy_init,
315 .exit = rockchip_emmc_phy_exit,
165 .power_on = rockchip_emmc_phy_power_on, 316 .power_on = rockchip_emmc_phy_power_on,
166 .power_off = rockchip_emmc_phy_power_off, 317 .power_off = rockchip_emmc_phy_power_off,
167 .owner = THIS_MODULE, 318 .owner = THIS_MODULE,
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
index eb0151bac50c..d8673ca968ba 100644
--- a/include/linux/mmc/card.h
+++ b/include/linux/mmc/card.h
@@ -95,6 +95,7 @@ struct mmc_ext_csd {
95 u8 raw_partition_support; /* 160 */ 95 u8 raw_partition_support; /* 160 */
96 u8 raw_rpmb_size_mult; /* 168 */ 96 u8 raw_rpmb_size_mult; /* 168 */
97 u8 raw_erased_mem_count; /* 181 */ 97 u8 raw_erased_mem_count; /* 181 */
98 u8 strobe_support; /* 184 */
98 u8 raw_ext_csd_structure; /* 194 */ 99 u8 raw_ext_csd_structure; /* 194 */
99 u8 raw_card_type; /* 196 */ 100 u8 raw_card_type; /* 196 */
100 u8 raw_driver_strength; /* 197 */ 101 u8 raw_driver_strength; /* 197 */
@@ -279,6 +280,7 @@ struct mmc_card {
279#define MMC_QUIRK_SEC_ERASE_TRIM_BROKEN (1<<10) /* Skip secure for erase/trim */ 280#define MMC_QUIRK_SEC_ERASE_TRIM_BROKEN (1<<10) /* Skip secure for erase/trim */
280#define MMC_QUIRK_BROKEN_IRQ_POLLING (1<<11) /* Polling SDIO_CCCR_INTx could create a fake interrupt */ 281#define MMC_QUIRK_BROKEN_IRQ_POLLING (1<<11) /* Polling SDIO_CCCR_INTx could create a fake interrupt */
281#define MMC_QUIRK_TRIM_BROKEN (1<<12) /* Skip trim */ 282#define MMC_QUIRK_TRIM_BROKEN (1<<12) /* Skip trim */
283#define MMC_QUIRK_BROKEN_HPI (1<<13) /* Disable broken HPI support */
282 284
283 285
284 unsigned int erase_size; /* erase size in sectors */ 286 unsigned int erase_size; /* erase size in sectors */
@@ -353,6 +355,9 @@ struct mmc_fixup {
353 /* SDIO-specfic fields. You can use SDIO_ANY_ID here of course */ 355 /* SDIO-specfic fields. You can use SDIO_ANY_ID here of course */
354 u16 cis_vendor, cis_device; 356 u16 cis_vendor, cis_device;
355 357
358 /* for MMC cards */
359 unsigned int ext_csd_rev;
360
356 void (*vendor_fixup)(struct mmc_card *card, int data); 361 void (*vendor_fixup)(struct mmc_card *card, int data);
357 int data; 362 int data;
358}; 363};
@@ -361,11 +366,20 @@ struct mmc_fixup {
361#define CID_OEMID_ANY ((unsigned short) -1) 366#define CID_OEMID_ANY ((unsigned short) -1)
362#define CID_NAME_ANY (NULL) 367#define CID_NAME_ANY (NULL)
363 368
369#define EXT_CSD_REV_ANY (-1u)
370
371#define CID_MANFID_SANDISK 0x2
372#define CID_MANFID_TOSHIBA 0x11
373#define CID_MANFID_MICRON 0x13
374#define CID_MANFID_SAMSUNG 0x15
375#define CID_MANFID_KINGSTON 0x70
376#define CID_MANFID_HYNIX 0x90
377
364#define END_FIXUP { NULL } 378#define END_FIXUP { NULL }
365 379
366#define _FIXUP_EXT(_name, _manfid, _oemid, _rev_start, _rev_end, \ 380#define _FIXUP_EXT(_name, _manfid, _oemid, _rev_start, _rev_end, \
367 _cis_vendor, _cis_device, \ 381 _cis_vendor, _cis_device, \
368 _fixup, _data) \ 382 _fixup, _data, _ext_csd_rev) \
369 { \ 383 { \
370 .name = (_name), \ 384 .name = (_name), \
371 .manfid = (_manfid), \ 385 .manfid = (_manfid), \
@@ -376,23 +390,30 @@ struct mmc_fixup {
376 .cis_device = (_cis_device), \ 390 .cis_device = (_cis_device), \
377 .vendor_fixup = (_fixup), \ 391 .vendor_fixup = (_fixup), \
378 .data = (_data), \ 392 .data = (_data), \
393 .ext_csd_rev = (_ext_csd_rev), \
379 } 394 }
380 395
381#define MMC_FIXUP_REV(_name, _manfid, _oemid, _rev_start, _rev_end, \ 396#define MMC_FIXUP_REV(_name, _manfid, _oemid, _rev_start, _rev_end, \
382 _fixup, _data) \ 397 _fixup, _data, _ext_csd_rev) \
383 _FIXUP_EXT(_name, _manfid, \ 398 _FIXUP_EXT(_name, _manfid, \
384 _oemid, _rev_start, _rev_end, \ 399 _oemid, _rev_start, _rev_end, \
385 SDIO_ANY_ID, SDIO_ANY_ID, \ 400 SDIO_ANY_ID, SDIO_ANY_ID, \
386 _fixup, _data) \ 401 _fixup, _data, _ext_csd_rev) \
387 402
388#define MMC_FIXUP(_name, _manfid, _oemid, _fixup, _data) \ 403#define MMC_FIXUP(_name, _manfid, _oemid, _fixup, _data) \
389 MMC_FIXUP_REV(_name, _manfid, _oemid, 0, -1ull, _fixup, _data) 404 MMC_FIXUP_REV(_name, _manfid, _oemid, 0, -1ull, _fixup, _data, \
405 EXT_CSD_REV_ANY)
406
407#define MMC_FIXUP_EXT_CSD_REV(_name, _manfid, _oemid, _fixup, _data, \
408 _ext_csd_rev) \
409 MMC_FIXUP_REV(_name, _manfid, _oemid, 0, -1ull, _fixup, _data, \
410 _ext_csd_rev)
390 411
391#define SDIO_FIXUP(_vendor, _device, _fixup, _data) \ 412#define SDIO_FIXUP(_vendor, _device, _fixup, _data) \
392 _FIXUP_EXT(CID_NAME_ANY, CID_MANFID_ANY, \ 413 _FIXUP_EXT(CID_NAME_ANY, CID_MANFID_ANY, \
393 CID_OEMID_ANY, 0, -1ull, \ 414 CID_OEMID_ANY, 0, -1ull, \
394 _vendor, _device, \ 415 _vendor, _device, \
395 _fixup, _data) \ 416 _fixup, _data, EXT_CSD_REV_ANY) \
396 417
397#define cid_rev(hwrev, fwrev, year, month) \ 418#define cid_rev(hwrev, fwrev, year, month) \
398 (((u64) hwrev) << 40 | \ 419 (((u64) hwrev) << 40 | \
@@ -511,6 +532,11 @@ static inline int mmc_card_broken_irq_polling(const struct mmc_card *c)
511 return c->quirks & MMC_QUIRK_BROKEN_IRQ_POLLING; 532 return c->quirks & MMC_QUIRK_BROKEN_IRQ_POLLING;
512} 533}
513 534
535static inline int mmc_card_broken_hpi(const struct mmc_card *c)
536{
537 return c->quirks & MMC_QUIRK_BROKEN_HPI;
538}
539
514#define mmc_card_name(c) ((c)->cid.prod_name) 540#define mmc_card_name(c) ((c)->cid.prod_name)
515#define mmc_card_id(c) (dev_name(&(c)->dev)) 541#define mmc_card_id(c) (dev_name(&(c)->dev))
516 542
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index f7ed271a1d54..83b0edfce471 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -112,7 +112,6 @@ struct dw_mci_dma_slave {
112 * @part_buf: Simple buffer for partial fifo reads/writes. 112 * @part_buf: Simple buffer for partial fifo reads/writes.
113 * @push_data: Pointer to FIFO push function. 113 * @push_data: Pointer to FIFO push function.
114 * @pull_data: Pointer to FIFO pull function. 114 * @pull_data: Pointer to FIFO pull function.
115 * @quirks: Set of quirks that apply to specific versions of the IP.
116 * @vqmmc_enabled: Status of vqmmc, should be true or false. 115 * @vqmmc_enabled: Status of vqmmc, should be true or false.
117 * @irq_flags: The flags to be passed to request_irq. 116 * @irq_flags: The flags to be passed to request_irq.
118 * @irq: The irq value to be passed to request_irq. 117 * @irq: The irq value to be passed to request_irq.
@@ -218,9 +217,6 @@ struct dw_mci {
218 void (*push_data)(struct dw_mci *host, void *buf, int cnt); 217 void (*push_data)(struct dw_mci *host, void *buf, int cnt);
219 void (*pull_data)(struct dw_mci *host, void *buf, int cnt); 218 void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
220 219
221 /* Workaround flags */
222 u32 quirks;
223
224 bool vqmmc_enabled; 220 bool vqmmc_enabled;
225 unsigned long irq_flags; /* IRQ flags */ 221 unsigned long irq_flags; /* IRQ flags */
226 int irq; 222 int irq;
@@ -242,17 +238,12 @@ struct dw_mci_dma_ops {
242 void (*exit)(struct dw_mci *host); 238 void (*exit)(struct dw_mci *host);
243}; 239};
244 240
245/* IP Quirks/flags. */
246/* Timer for broken data transfer over scheme */
247#define DW_MCI_QUIRK_BROKEN_DTO BIT(0)
248
249struct dma_pdata; 241struct dma_pdata;
250 242
251/* Board platform data */ 243/* Board platform data */
252struct dw_mci_board { 244struct dw_mci_board {
253 u32 num_slots; 245 u32 num_slots;
254 246
255 u32 quirks; /* Workaround / Quirk flags */
256 unsigned int bus_hz; /* Clock speed at the cclk_in pad */ 247 unsigned int bus_hz; /* Clock speed at the cclk_in pad */
257 248
258 u32 caps; /* Capabilities */ 249 u32 caps; /* Capabilities */
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 45cde8cd39f2..aa4bfbf129e4 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -19,6 +19,7 @@
19 19
20#include <linux/mmc/core.h> 20#include <linux/mmc/core.h>
21#include <linux/mmc/card.h> 21#include <linux/mmc/card.h>
22#include <linux/mmc/mmc.h>
22#include <linux/mmc/pm.h> 23#include <linux/mmc/pm.h>
23 24
24struct mmc_ios { 25struct mmc_ios {
@@ -77,6 +78,8 @@ struct mmc_ios {
77#define MMC_SET_DRIVER_TYPE_A 1 78#define MMC_SET_DRIVER_TYPE_A 1
78#define MMC_SET_DRIVER_TYPE_C 2 79#define MMC_SET_DRIVER_TYPE_C 2
79#define MMC_SET_DRIVER_TYPE_D 3 80#define MMC_SET_DRIVER_TYPE_D 3
81
82 bool enhanced_strobe; /* hs400es selection */
80}; 83};
81 84
82struct mmc_host_ops { 85struct mmc_host_ops {
@@ -143,6 +146,9 @@ struct mmc_host_ops {
143 146
144 /* Prepare HS400 target operating frequency depending host driver */ 147 /* Prepare HS400 target operating frequency depending host driver */
145 int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios); 148 int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios);
149 /* Prepare enhanced strobe depending host driver */
150 void (*hs400_enhanced_strobe)(struct mmc_host *host,
151 struct mmc_ios *ios);
146 int (*select_drive_strength)(struct mmc_card *card, 152 int (*select_drive_strength)(struct mmc_card *card,
147 unsigned int max_dtr, int host_drv, 153 unsigned int max_dtr, int host_drv,
148 int card_drv, int *drv_type); 154 int card_drv, int *drv_type);
@@ -302,6 +308,9 @@ struct mmc_host {
302#define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17) 308#define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
303#define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */ 309#define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */
304#define MMC_CAP2_NO_SDIO (1 << 19) /* Do not send SDIO commands during initialization */ 310#define MMC_CAP2_NO_SDIO (1 << 19) /* Do not send SDIO commands during initialization */
311#define MMC_CAP2_HS400_ES (1 << 20) /* Host supports enhanced strobe */
312#define MMC_CAP2_NO_SD (1 << 21) /* Do not send SD commands during initialization */
313#define MMC_CAP2_NO_MMC (1 << 22) /* Do not send (e)MMC commands during initialization */
305 314
306 mmc_pm_flag_t pm_caps; /* supported pm features */ 315 mmc_pm_flag_t pm_caps; /* supported pm features */
307 316
@@ -513,6 +522,11 @@ static inline bool mmc_card_hs400(struct mmc_card *card)
513 return card->host->ios.timing == MMC_TIMING_MMC_HS400; 522 return card->host->ios.timing == MMC_TIMING_MMC_HS400;
514} 523}
515 524
525static inline bool mmc_card_hs400es(struct mmc_card *card)
526{
527 return card->host->ios.enhanced_strobe;
528}
529
516void mmc_retune_timer_stop(struct mmc_host *host); 530void mmc_retune_timer_stop(struct mmc_host *host);
517 531
518static inline void mmc_retune_needed(struct mmc_host *host) 532static inline void mmc_retune_needed(struct mmc_host *host)
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index 15f2c4a0a62c..c376209c70ef 100644
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -297,6 +297,7 @@ struct _mmc_csd {
297#define EXT_CSD_PART_CONFIG 179 /* R/W */ 297#define EXT_CSD_PART_CONFIG 179 /* R/W */
298#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */ 298#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
299#define EXT_CSD_BUS_WIDTH 183 /* R/W */ 299#define EXT_CSD_BUS_WIDTH 183 /* R/W */
300#define EXT_CSD_STROBE_SUPPORT 184 /* RO */
300#define EXT_CSD_HS_TIMING 185 /* R/W */ 301#define EXT_CSD_HS_TIMING 185 /* R/W */
301#define EXT_CSD_POWER_CLASS 187 /* R/W */ 302#define EXT_CSD_POWER_CLASS 187 /* R/W */
302#define EXT_CSD_REV 192 /* RO */ 303#define EXT_CSD_REV 192 /* RO */
@@ -380,12 +381,14 @@ struct _mmc_csd {
380#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */ 381#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */
381#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ 382#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
382 EXT_CSD_CARD_TYPE_HS400_1_2V) 383 EXT_CSD_CARD_TYPE_HS400_1_2V)
384#define EXT_CSD_CARD_TYPE_HS400ES (1<<8) /* Card can run at HS400ES */
383 385
384#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 386#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
385#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 387#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
386#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 388#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
387#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ 389#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
388#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ 390#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
391#define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
389 392
390#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */ 393#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
391#define EXT_CSD_TIMING_HS 1 /* High speed */ 394#define EXT_CSD_TIMING_HS 1 /* High speed */
diff --git a/include/linux/platform_data/mmc-esdhc-imx.h b/include/linux/platform_data/mmc-esdhc-imx.h
index 95ccab3f454a..7daa78a2f342 100644
--- a/include/linux/platform_data/mmc-esdhc-imx.h
+++ b/include/linux/platform_data/mmc-esdhc-imx.h
@@ -46,5 +46,6 @@ struct esdhc_platform_data {
46 bool support_vsel; 46 bool support_vsel;
47 unsigned int delay_line; 47 unsigned int delay_line;
48 unsigned int tuning_step; /* The delay cell steps in tuning procedure */ 48 unsigned int tuning_step; /* The delay cell steps in tuning procedure */
49 unsigned int tuning_start_tap; /* The start delay cell point in tuning procedure */
49}; 50};
50#endif /* __ASM_ARCH_IMX_ESDHC_H */ 51#endif /* __ASM_ARCH_IMX_ESDHC_H */