Merge branch 'irqchip/stacked-omap' into irqchip/core

30 files changed, 376 insertions, 278 deletions

diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index c97484b73e72..1e0d21201d3a 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -56,11 +56,6 @@ Optional
   regions, used when the GIC doesn't have banked registers. The offset is
   cpu-offset * cpu-nr.
 
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
-                  connected from the peripherals, but are routed dynamically
-                  by a crossbar/multiplexer preceding the GIC. The GIC irq
-                  input line is assigned dynamically when the corresponding
-                  peripheral's crossbar line is mapped.
 Example:
 
         intc: interrupt-controller@fff11000 {
@@ -68,7 +63,6 @@ Example:
                 #interrupt-cells = <3>;
                 #address-cells = <1>;
                 interrupt-controller;
-                arm,routable-irqs = <160>;
                 reg = <0xfff11000 0x1000>,
                       <0xfff10100 0x100>;
         };
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 4139db353d0a..a9b28d74d902 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -9,7 +9,9 @@ inputs.
 Required properties:
 - compatible : Should be "ti,irq-crossbar"
 - reg: Base address and the size of the crossbar registers.
-- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- interrupt-controller: indicates that this block is an interrupt controller.
+- interrupt-parent: the interrupt controller this block is connected to.
+- ti,max-irqs: Total number of irqs available at the parent interrupt controller.
 - ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
 - ti,reg-size: Size of a individual register in bytes. Every individual
             register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties:
   when the interrupt controller irq is unused (when not provided, default is 0)
 
 Examples:
-                crossbar_mpu: @4a020000 {
+                crossbar_mpu: crossbar@4a002a48 {
                         compatible = "ti,irq-crossbar";
                         reg = <0x4a002a48 0x130>;
                         ti,max-irqs = <160>;
                         ti,max-crossbar-sources = <400>;
                         ti,reg-size = <2>;
-                        ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
+                        ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
                         ti,irqs-skip = <10 133 139 140>;
                 };
 
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further details.
 
 An interrupt consumer on an SoC using crossbar will use:
         interrupts = <GIC_SPI request_number interrupt_level>
-When the request number is between 0 to that described by
-"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the
-request_number is greater than "ti,max-crossbar-sources", then it is mapped as a
-quirky hardware mapping direct to GIC.
 
 Example:
         device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example:
                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
                 ...
         };
-
-        device_y@0x4a033000 {
-                /* Direct mapped GIC SPI 1 used */
-                interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;
-                ...
-        };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
new file mode 100644
index 000000000000..43effa0a4fe7
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
@@ -0,0 +1,33 @@
+TI OMAP4 Wake-up Generator
+
+All TI OMAP4/5 (and their derivatives) an interrupt controller that
+routes interrupts to the GIC, and also serves as a wakeup source. It
+is also referred to as "WUGEN-MPU", hence the name of the binding.
+
+Reguired properties:
+
+- compatible : should contain at least "ti,omap4-wugen-mpu" or
+  "ti,omap5-wugen-mpu"
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+  to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+  interrupt specifier must be that of the GIC.
+- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
+  are explicitly forbiden.
+
+Example:
+
+       wakeupgen: interrupt-controller@48281000 {
+               compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
+               interrupt-controller;
+               #interrupt-cells = <3>;
+               reg = <0x48281000 0x1000>;
+               interrupt-parent = <&gic>;
+       };
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 1943fc333e7c..8a099bc10c1e 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -15,7 +15,7 @@
 
 / {
         compatible = "ti,am4372", "ti,am43";
-        interrupt-parent = <&gic>;
+        interrupt-parent = <&wakeupgen>;
 
 
         aliases {
@@ -48,6 +48,15 @@
                 #interrupt-cells = <3>;
                 reg = <0x48241000 0x1000>,
                       <0x48240100 0x0100>;
+                interrupt-parent = <&gic>;
+        };
+
+        wakeupgen: interrupt-controller@48281000 {
+                compatible = "ti,omap4-wugen-mpu";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x48281000 0x1000>;
+                interrupt-parent = <&gic>;
         };
 
         l2-cache-controller@48242000 {
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index f84d9715a4a9..26956cb50835 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -352,7 +352,6 @@
                 reg = <0x24>;
                 compatible = "ti,tps65218";
                 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
-                interrupt-parent = <&gic>;
                 interrupt-controller;
                 #interrupt-cells = <2>;
 
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index 832d24318f62..8ae29c955c11 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -392,7 +392,6 @@
         tps@24 {
                 compatible = "ti,tps65218";
                 reg = <0x24>;
-                interrupt-parent = <&gic>;
                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
                 interrupt-controller;
                 #interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 257c099c347e..1d7109196872 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -369,7 +369,6 @@
                 reg = <0x24>;
                 compatible = "ti,tps65218";
                 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
-                interrupt-parent = <&gic>;
                 interrupt-controller;
                 #interrupt-cells = <2>;
 
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 03750af3b49a..170fbf953e5d 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -454,7 +454,6 @@
         mcp_rtc: rtc@6f {
                 compatible = "microchip,mcp7941x";
                 reg = <0x6f>;
-                interrupt-parent = <&gic>;
                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>;  /* IRQ_SYS_1N */
 
                 pinctrl-names = "default";
@@ -477,7 +476,7 @@
 
 &uart3 {
         status = "okay";
-        interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+        interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
                               <&dra7_pmx_core 0x248>;
 
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 746cddb1b8f5..789ee58ba47e 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -446,7 +446,7 @@
         status = "okay";
         pinctrl-names = "default";
         pinctrl-0 = <&uart1_pins>;
-        interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+        interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
                               <&dra7_pmx_core 0x3e0>;
 };
 
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5827fedafd43..c65eea095afa 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -13,14 +13,13 @@
 #include "skeleton.dtsi"
 
 #define MAX_SOURCES 400
-#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
 
 / {
         #address-cells = <1>;
         #size-cells = <1>;
 
         compatible = "ti,dra7xx";
-        interrupt-parent = <&gic>;
+        interrupt-parent = <&crossbar_mpu>;
 
         aliases {
                 i2c0 = &i2c1;
@@ -50,18 +49,27 @@
                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+                interrupt-parent = <&gic>;
         };
 
         gic: interrupt-controller@48211000 {
                 compatible = "arm,cortex-a15-gic";
                 interrupt-controller;
                 #interrupt-cells = <3>;
-                arm,routable-irqs = <192>;
                 reg = <0x48211000 0x1000>,
                       <0x48212000 0x1000>,
                       <0x48214000 0x2000>,
                       <0x48216000 0x2000>;
                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                interrupt-parent = <&gic>;
+        };
+
+        wakeupgen: interrupt-controller@48281000 {
+                compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x48281000 0x1000>;
+                interrupt-parent = <&gic>;
         };
 
         /*
@@ -91,8 +99,8 @@
                 ti,hwmods = "l3_main_1", "l3_main_2";
                 reg = <0x44000000 0x1000000>,
                       <0x45000000 0x1000>;
-                interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
+                interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+                                      <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
                 prm: prm@4ae06000 {
                         compatible = "ti,dra7-prm";
@@ -344,7 +352,7 @@
                 uart1: serial@4806a000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806a000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -355,7 +363,7 @@
                 uart2: serial@4806c000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806c000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -366,7 +374,7 @@
                 uart3: serial@48020000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48020000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -377,7 +385,7 @@
                 uart4: serial@4806e000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806e000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -388,7 +396,7 @@
                 uart5: serial@48066000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48066000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart5";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -399,7 +407,7 @@
                 uart6: serial@48068000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48068000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart6";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -410,7 +418,7 @@
                 uart7: serial@48420000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48420000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart7";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -419,7 +427,7 @@
                 uart8: serial@48422000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48422000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart8";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -428,7 +436,7 @@
                 uart9: serial@48424000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48424000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart9";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -437,7 +445,7 @@
                 uart10: serial@4ae2b000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4ae2b000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart10";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -1337,9 +1345,12 @@
                         status = "disabled";
                 };
 
-                crossbar_mpu: crossbar@4a020000 {
+                crossbar_mpu: crossbar@4a002a48 {
                         compatible = "ti,irq-crossbar";
                         reg = <0x4a002a48 0x130>;
+                        interrupt-controller;
+                        interrupt-parent = <&wakeupgen>;
+                        #interrupt-cells = <3>;
                         ti,max-irqs = <160>;
                         ti,max-crossbar-sources = <MAX_SOURCES>;
                         ti,reg-size = <2>;
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 4d8711713610..2373054f588d 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -160,7 +160,6 @@
                 pinctrl-0 = <&tps65917_pins_default>;
 
                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
-                interrupt-parent = <&gic>;
                 interrupt-controller;
                 #interrupt-cells = <2>;
 
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index e5a3d23a3df1..f7fb0d0ef25a 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -25,6 +25,7 @@
 
         pmu {
                 compatible = "arm,cortex-a15-pmu";
-                interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-parent = <&wakeupgen>;
+                interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
         };
 };
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 10173fab1a15..00eeed789b4b 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -41,8 +41,9 @@
 
         pmu {
                 compatible = "arm,cortex-a15-pmu";
-                interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-parent = <&wakeupgen>;
+                interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         ocp {
diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi
index e860ccd9d09c..f2a94fa62552 100644
--- a/arch/arm/boot/dts/omap4-duovero.dtsi
+++ b/arch/arm/boot/dts/omap4-duovero.dtsi
@@ -173,14 +173,12 @@
         twl: twl@48 {
                 reg = <0x48>;
                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;           /* IRQ_SYS_1N cascaded to gic */
-                interrupt-parent = <&gic>;
         };
 
         twl6040: twl@4b {
                 compatible = "ti,twl6040";
                 reg = <0x4b>;
                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;         /* IRQ_SYS_2N cascaded to gic */
-                interrupt-parent = <&gic>;
                 ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>;         /* gpio_160 */
 
                 vio-supply = <&v1v8>;
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 150513506c19..7c15fb2e2fe4 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -372,7 +372,6 @@
                 reg = <0x48>;
                 /* IRQ# = 7 */
                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
-                interrupt-parent = <&gic>;
         };
 
         twl6040: twl@4b {
@@ -384,7 +383,6 @@
 
                 /* IRQ# = 119 */
                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
-                interrupt-parent = <&gic>;
                 ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>;  /* gpio line 127 */
 
                 vio-supply = <&v1v8>;
@@ -479,17 +477,17 @@
 };
 
 &uart2 {
-        interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
+        interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
                                &omap4_pmx_core OMAP4_UART2_RX>;
 };
 
 &uart3 {
-        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+        interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
                                &omap4_pmx_core OMAP4_UART3_RX>;
 };
 
 &uart4 {
-        interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+        interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
                                &omap4_pmx_core OMAP4_UART4_RX>;
 };
 
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 3e1da43068f6..8aca8dae968a 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -363,7 +363,6 @@
                 reg = <0x48>;
                 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
-                interrupt-parent = <&gic>;
         };
 
         twl6040: twl@4b {
@@ -375,7 +374,6 @@
 
                 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
-                interrupt-parent = <&gic>;
                 ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
 
                 vio-supply = <&v1v8>;
@@ -570,21 +568,21 @@
 };
 
 &uart2 {
-        interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
+        interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
                                &omap4_pmx_core OMAP4_UART2_RX>;
         pinctrl-names = "default";
         pinctrl-0 = <&uart2_pins>;
 };
 
 &uart3 {
-        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+        interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
                                &omap4_pmx_core OMAP4_UART3_RX>;
         pinctrl-names = "default";
         pinctrl-0 = <&uart3_pins>;
 };
 
 &uart4 {
-        interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+        interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
                                &omap4_pmx_core OMAP4_UART4_RX>;
         pinctrl-names = "default";
         pinctrl-0 = <&uart4_pins>;
diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi
index 062701e1a898..a4f1ba2e1903 100644
--- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi
+++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi
@@ -185,7 +185,6 @@
                 reg = <0x48>;
                 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
-                interrupt-parent = <&gic>;
         };
 
         twl6040: twl@4b {
@@ -197,7 +196,6 @@
 
                 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
-                interrupt-parent = <&gic>;
                 ti,audpwron-gpio = <&gpio6 22 0>; /* gpio 182 */
 
                 vio-supply = <&v1v8>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 074147cebae4..7cb5236f751d 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -14,7 +14,7 @@
 
 / {
         compatible = "ti,omap4430", "ti,omap4";
-        interrupt-parent = <&gic>;
+        interrupt-parent = <&wakeupgen>;
 
         aliases {
                 i2c0 = &i2c1;
@@ -56,6 +56,7 @@
                 #interrupt-cells = <3>;
                 reg = <0x48241000 0x1000>,
                       <0x48240100 0x0100>;
+                interrupt-parent = <&gic>;
         };
 
         L2: l2-cache-controller@48242000 {
@@ -70,6 +71,15 @@
                 clocks = <&mpu_periphclk>;
                 reg = <0x48240600 0x20>;
                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
+                interrupt-parent = <&gic>;
+        };
+
+        wakeupgen: interrupt-controller@48281000 {
+                compatible = "ti,omap4-wugen-mpu";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x48281000 0x1000>;
+                interrupt-parent = <&gic>;
         };
 
         /*
@@ -319,7 +329,7 @@
                 uart2: serial@4806c000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806c000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                 };
@@ -327,7 +337,7 @@
                 uart3: serial@48020000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48020000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                 };
@@ -335,7 +345,7 @@
                 uart4: serial@4806e000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806e000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                 };
diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts
index b54b271e153b..61ad2ea34720 100644
--- a/arch/arm/boot/dts/omap5-cm-t54.dts
+++ b/arch/arm/boot/dts/omap5-cm-t54.dts
@@ -412,7 +412,6 @@
         palmas: palmas@48 {
                 compatible = "ti,palmas";
                 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
-                interrupt-parent = <&gic>;
                 reg = <0x48>;
                 interrupt-controller;
                 #interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 159720d6c956..74777a6e200a 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -311,7 +311,6 @@
         palmas: palmas@48 {
                 compatible = "ti,palmas";
                 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
-                interrupt-parent = <&gic>;
                 reg = <0x48>;
                 interrupt-controller;
                 #interrupt-cells = <2>;
@@ -521,7 +520,6 @@
                 pinctrl-0 = <&twl6040_pins>;
 
                 interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
-                interrupt-parent = <&gic>;
                 ti,audpwron-gpio = <&gpio5 13 0>;  /* gpio line 141 */
 
                 vio-supply = <&smps7_reg>;
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index b321fdf42c9f..b056156e2a7a 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -18,7 +18,7 @@
         #size-cells = <1>;
 
         compatible = "ti,omap5";
-        interrupt-parent = <&gic>;
+        interrupt-parent = <&wakeupgen>;
 
         aliases {
                 i2c0 = &i2c1;
@@ -79,6 +79,7 @@
                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
+                interrupt-parent = <&gic>;
         };
 
         pmu {
@@ -95,6 +96,15 @@
                       <0x48212000 0x1000>,
                       <0x48214000 0x2000>,
                       <0x48216000 0x2000>;
+                interrupt-parent = <&gic>;
+        };
+
+        wakeupgen: interrupt-controller@48281000 {
+                compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x48281000 0x1000>;
+                interrupt-parent = <&gic>;
         };
 
         /*
@@ -458,7 +468,7 @@
                 uart1: serial@4806a000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806a000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
                 };
@@ -466,7 +476,7 @@
                 uart2: serial@4806c000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806c000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                 };
@@ -474,7 +484,7 @@
                 uart3: serial@48020000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48020000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                 };
@@ -482,7 +492,7 @@
                 uart4: serial@4806e000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806e000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                 };
@@ -490,7 +500,7 @@
                 uart5: serial@48066000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48066000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart5";
                         clock-frequency = <48000000>;
                 };
@@ -498,7 +508,7 @@
                 uart6: serial@48068000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48068000 0x100>;
-                        interrupts-extended = <&gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart6";
                         clock-frequency = <48000000>;
                 };
@@ -883,14 +893,12 @@
                         usbhsohci: ohci@4a064800 {
                                 compatible = "ti,ohci-omap3";
                                 reg = <0x4a064800 0x400>;
-                                interrupt-parent = <&gic>;
                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
                         };
 
                         usbhsehci: ehci@4a064c00 {
                                 compatible = "ti,ehci-omap";
                                 reg = <0x4a064c00 0x400>;
-                                interrupt-parent = <&gic>;
                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
                         };
                 };
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index f961c46453b9..3b56722dfd8a 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -20,11 +20,12 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include <linux/cpu.h>
 #include <linux/notifier.h>
 #include <linux/cpu_pm.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include "omap-wakeupgen.h"
 #include "omap-secure.h"
@@ -78,29 +79,12 @@ static inline void sar_writel(u32 val, u32 offset, u8 idx)
 
 static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
 {
-        unsigned int spi_irq;
-
-        /*
-         * PPIs and SGIs are not supported.
-         */
-        if (irq < OMAP44XX_IRQ_GIC_START)
-                return -EINVAL;
-
-        /*
-         * Subtract the GIC offset.
-         */
-        spi_irq = irq - OMAP44XX_IRQ_GIC_START;
-        if (spi_irq > MAX_IRQS) {
-                pr_err("omap wakeupGen: Invalid IRQ%d\n", irq);
-                return -EINVAL;
-        }
-
         /*
          * Each WakeupGen register controls 32 interrupt.
          * i.e. 1 bit per SPI IRQ
          */
-        *reg_index = spi_irq >> 5;
-        *bit_posn = spi_irq %= 32;
+        *reg_index = irq >> 5;
+        *bit_posn = irq %= 32;
 
         return 0;
 }
@@ -141,6 +125,7 @@ static void wakeupgen_mask(struct irq_data *d)
         raw_spin_lock_irqsave(&wakeupgen_lock, flags);
         _wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
         raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
+        irq_chip_mask_parent(d);
 }
 
 /*
@@ -153,6 +138,7 @@ static void wakeupgen_unmask(struct irq_data *d)
         raw_spin_lock_irqsave(&wakeupgen_lock, flags);
         _wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
         raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
+        irq_chip_unmask_parent(d);
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
@@ -400,15 +386,91 @@ int omap_secure_apis_support(void)
         return omap_secure_apis;
 }
 
+static struct irq_chip wakeupgen_chip = {
+        .name                   = "WUGEN",
+        .irq_eoi                = irq_chip_eoi_parent,
+        .irq_mask               = wakeupgen_mask,
+        .irq_unmask             = wakeupgen_unmask,
+        .irq_retrigger          = irq_chip_retrigger_hierarchy,
+        .flags                  = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
+#ifdef CONFIG_SMP
+        .irq_set_affinity       = irq_chip_set_affinity_parent,
+#endif
+};
+
+static int wakeupgen_domain_xlate(struct irq_domain *domain,
+                                  struct device_node *controller,
+                                  const u32 *intspec,
+                                  unsigned int intsize,
+                                  unsigned long *out_hwirq,
+                                  unsigned int *out_type)
+{
+        if (domain->of_node != controller)
+                return -EINVAL; /* Shouldn't happen, really... */
+        if (intsize != 3)
+                return -EINVAL; /* Not GIC compliant */
+        if (intspec[0] != 0)
+                return -EINVAL; /* No PPI should point to this domain */
+
+        *out_hwirq = intspec[1];
+        *out_type = intspec[2];
+        return 0;
+}
+
+static int wakeupgen_domain_alloc(struct irq_domain *domain,
+                                  unsigned int virq,
+                                  unsigned int nr_irqs, void *data)
+{
+        struct of_phandle_args *args = data;
+        struct of_phandle_args parent_args;
+        irq_hw_number_t hwirq;
+        int i;
+
+        if (args->args_count != 3)
+                return -EINVAL; /* Not GIC compliant */
+        if (args->args[0] != 0)
+                return -EINVAL; /* No PPI should point to this domain */
+
+        hwirq = args->args[1];
+        if (hwirq >= MAX_IRQS)
+                return -EINVAL; /* Can't deal with this */
+
+        for (i = 0; i < nr_irqs; i++)
+                irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
+                                              &wakeupgen_chip, NULL);
+
+        parent_args = *args;
+        parent_args.np = domain->parent->of_node;
+        return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args);
+}
+
+static struct irq_domain_ops wakeupgen_domain_ops = {
+        .xlate  = wakeupgen_domain_xlate,
+        .alloc  = wakeupgen_domain_alloc,
+        .free   = irq_domain_free_irqs_common,
+};
+
 /*
  * Initialise the wakeupgen module.
  */
-int __init omap_wakeupgen_init(void)
+static int __init wakeupgen_init(struct device_node *node,
+                                 struct device_node *parent)
 {
+        struct irq_domain *parent_domain, *domain;
         int i;
         unsigned int boot_cpu = smp_processor_id();
         u32 val;
 
+        if (!parent) {
+                pr_err("%s: no parent, giving up\n", node->full_name);
+                return -ENODEV;
+        }
+
+        parent_domain = irq_find_host(parent);
+        if (!parent_domain) {
+                pr_err("%s: unable to obtain parent domain\n", node->full_name);
+                return -ENXIO;
+        }
         /* Not supported on OMAP4 ES1.0 silicon */
         if (omap_rev() == OMAP4430_REV_ES1_0) {
                 WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
@@ -416,7 +478,7 @@ int __init omap_wakeupgen_init(void)
         }
 
         /* Static mapping, never released */
-        wakeupgen_base = ioremap(OMAP_WKUPGEN_BASE, SZ_4K);
+        wakeupgen_base = of_iomap(node, 0);
         if (WARN_ON(!wakeupgen_base))
                 return -ENOMEM;
 
@@ -429,6 +491,14 @@ int __init omap_wakeupgen_init(void)
                 max_irqs = AM43XX_IRQS;
         }
 
+        domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs,
+                                          node, &wakeupgen_domain_ops,
+                                          NULL);
+        if (!domain) {
+                iounmap(wakeupgen_base);
+                return -ENOMEM;
+        }
+
         /* Clear all IRQ bitmasks at wakeupGen level */
         for (i = 0; i < irq_banks; i++) {
                 wakeupgen_writel(0, i, CPU0_ID);
@@ -437,14 +507,6 @@ int __init omap_wakeupgen_init(void)
         }
 
         /*
-         * Override GIC architecture specific functions to add
-         * OMAP WakeupGen interrupt controller along with GIC
-         */
-        gic_arch_extn.irq_mask = wakeupgen_mask;
-        gic_arch_extn.irq_unmask = wakeupgen_unmask;
-        gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
-
-        /*
          * FIXME: Add support to set_smp_affinity() once the core
          * GIC code has necessary hooks in place.
          */
@@ -474,3 +536,9 @@ int __init omap_wakeupgen_init(void)
 
         return 0;
 }
+
+/*
+ * We cannot use the IRQCHIP_DECLARE macro that lives in
+ * drivers/irqchip, so we're forced to roll our own. Not very nice.
+ */
+OF_DECLARE_2(irqchip, ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.h b/arch/arm/mach-omap2/omap-wakeupgen.h
index b3c8eccfae79..a3491ad12368 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.h
+++ b/arch/arm/mach-omap2/omap-wakeupgen.h
@@ -33,7 +33,6 @@
 #define OMAP_TIMESTAMPCYCLELO                   0xc08
 #define OMAP_TIMESTAMPCYCLEHI                   0xc0c
 
-extern int __init omap_wakeupgen_init(void);
 extern void __iomem *omap_get_wakeupgen_base(void);
 extern int omap_secure_apis_support(void);
 #endif
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index cee0fe1ee6ff..7bb116a6f86f 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -22,7 +22,6 @@
 #include <linux/of_platform.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-gic.h>
-#include <linux/irqchip/irq-crossbar.h>
 #include <linux/of_address.h>
 #include <linux/reboot.h>
 #include <linux/genalloc.h>
@@ -242,26 +241,26 @@ static int __init omap4_sar_ram_init(void)
 }
 omap_early_initcall(omap4_sar_ram_init);
 
-static const struct of_device_id gic_match[] = {
-        { .compatible = "arm,cortex-a9-gic", },
-        { .compatible = "arm,cortex-a15-gic", },
+static const struct of_device_id intc_match[] = {
+        { .compatible = "ti,omap4-wugen-mpu", },
+        { .compatible = "ti,omap5-wugen-mpu", },
         { },
 };
 
-static struct device_node *gic_node;
+static struct device_node *intc_node;
 
 unsigned int omap4_xlate_irq(unsigned int hwirq)
 {
         struct of_phandle_args irq_data;
         unsigned int irq;
 
-        if (!gic_node)
-                gic_node = of_find_matching_node(NULL, gic_match);
+        if (!intc_node)
+                intc_node = of_find_matching_node(NULL, intc_match);
 
-        if (WARN_ON(!gic_node))
+        if (WARN_ON(!intc_node))
                 return hwirq;
 
-        irq_data.np = gic_node;
+        irq_data.np = intc_node;
         irq_data.args_count = 3;
         irq_data.args[0] = 0;
         irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
@@ -278,6 +277,12 @@ void __init omap_gic_of_init(void)
 {
         struct device_node *np;
 
+        intc_node = of_find_matching_node(NULL, intc_match);
+        if (WARN_ON(!intc_node)) {
+                pr_err("No WUGEN found in DT, system will misbehave.\n");
+                pr_err("UPDATE YOUR DEVICE TREE!\n");
+        }
+
         /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
         if (!cpu_is_omap446x())
                 goto skip_errata_init;
@@ -291,9 +296,5 @@ void __init omap_gic_of_init(void)
         WARN_ON(!twd_base);
 
 skip_errata_init:
-        omap_wakeupgen_init();
-#ifdef CONFIG_IRQ_CROSSBAR
-        irqcrossbar_init();
-#endif
         irqchip_init();
 }
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index bbbaf5de65d2..692fe2bc8197 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -11,11 +11,12 @@
  */
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/irqdomain.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/slab.h>
-#include <linux/irqchip/arm-gic.h>
-#include <linux/irqchip/irq-crossbar.h>
+
+#include "irqchip.h"
 
 #define IRQ_FREE        -1
 #define IRQ_RESERVED    -2
@@ -24,6 +25,7 @@
 
 /**
  * struct crossbar_device - crossbar device description
+ * @lock: spinlock serializing access to @irq_map
  * @int_max: maximum number of supported interrupts
  * @safe_map: safe default value to initialize the crossbar
  * @max_crossbar_sources: Maximum number of crossbar sources
@@ -33,6 +35,7 @@
  * @write: register write function pointer
  */
 struct crossbar_device {
+        raw_spinlock_t lock;
         uint int_max;
         uint safe_map;
         uint max_crossbar_sources;
@@ -44,72 +47,101 @@ struct crossbar_device {
 
 static struct crossbar_device *cb;
 
-static inline void crossbar_writel(int irq_no, int cb_no)
+static void crossbar_writel(int irq_no, int cb_no)
 {
         writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
 }
 
-static inline void crossbar_writew(int irq_no, int cb_no)
+static void crossbar_writew(int irq_no, int cb_no)
 {
         writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
 }
 
-static inline void crossbar_writeb(int irq_no, int cb_no)
+static void crossbar_writeb(int irq_no, int cb_no)
 {
         writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
 }
 
-static inline int get_prev_map_irq(int cb_no)
-{
-        int i;
-
-        for (i = cb->int_max - 1; i >= 0; i--)
-                if (cb->irq_map[i] == cb_no)
-                        return i;
-
-        return -ENODEV;
-}
+static struct irq_chip crossbar_chip = {
+        .name                   = "CBAR",
+        .irq_eoi                = irq_chip_eoi_parent,
+        .irq_mask               = irq_chip_mask_parent,
+        .irq_unmask             = irq_chip_unmask_parent,
+        .irq_retrigger          = irq_chip_retrigger_hierarchy,
+        .irq_set_wake           = irq_chip_set_wake_parent,
+#ifdef CONFIG_SMP
+        .irq_set_affinity       = irq_chip_set_affinity_parent,
+#endif
+};
 
-static inline int allocate_free_irq(int cb_no)
+static int allocate_gic_irq(struct irq_domain *domain, unsigned virq,
+                            irq_hw_number_t hwirq)
 {
+        struct of_phandle_args args;
         int i;
+        int err;
 
+        raw_spin_lock(&cb->lock);
         for (i = cb->int_max - 1; i >= 0; i--) {
                 if (cb->irq_map[i] == IRQ_FREE) {
-                        cb->irq_map[i] = cb_no;
-                        return i;
+                        cb->irq_map[i] = hwirq;
+                        break;
                 }
         }
+        raw_spin_unlock(&cb->lock);
 
-        return -ENODEV;
-}
+        if (i < 0)
+                return -ENODEV;
 
-static inline bool needs_crossbar_write(irq_hw_number_t hw)
-{
-        int cb_no;
+        args.np = domain->parent->of_node;
+        args.args_count = 3;
+        args.args[0] = 0;       /* SPI */
+        args.args[1] = i;
+        args.args[2] = IRQ_TYPE_LEVEL_HIGH;
 
-        if (hw > GIC_IRQ_START) {
-                cb_no = cb->irq_map[hw - GIC_IRQ_START];
-                if (cb_no != IRQ_RESERVED && cb_no != IRQ_SKIP)
-                        return true;
-        }
+        err = irq_domain_alloc_irqs_parent(domain, virq, 1, &args);
+        if (err)
+                cb->irq_map[i] = IRQ_FREE;
+        else
+                cb->write(i, hwirq);
 
-        return false;
+        return err;
 }
 
-static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
-                               irq_hw_number_t hw)
+static int crossbar_domain_alloc(struct irq_domain *d, unsigned int virq,
+                                 unsigned int nr_irqs, void *data)
 {
-        if (needs_crossbar_write(hw))
-                cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
+        struct of_phandle_args *args = data;
+        irq_hw_number_t hwirq;
+        int i;
+
+        if (args->args_count != 3)
+                return -EINVAL; /* Not GIC compliant */
+        if (args->args[0] != 0)
+                return -EINVAL; /* No PPI should point to this domain */
+
+        hwirq = args->args[1];
+        if ((hwirq + nr_irqs) > cb->max_crossbar_sources)
+                return -EINVAL; /* Can't deal with this */
+
+        for (i = 0; i < nr_irqs; i++) {
+                int err = allocate_gic_irq(d, virq + i, hwirq + i);
+
+                if (err)
+                        return err;
+
+                irq_domain_set_hwirq_and_chip(d, virq + i, hwirq + i,
+                                              &crossbar_chip, NULL);
+        }
 
         return 0;
 }
 
 /**
- * crossbar_domain_unmap - unmap a crossbar<->irq connection
- * @d: domain of irq to unmap
- * @irq: virq number
+ * crossbar_domain_free - unmap/free a crossbar<->irq connection
+ * @domain: domain of irq to unmap
+ * @virq: virq number
+ * @nr_irqs: number of irqs to free
  *
  * We do not maintain a use count of total number of map/unmap
  * calls for a particular irq to find out if a irq can be really
@@ -117,14 +149,20 @@ static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
  * after which irq is anyways unusable. So an explicit map has to be called
  * after that.
  */
-static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
+static void crossbar_domain_free(struct irq_domain *domain, unsigned int virq,
+                                 unsigned int nr_irqs)
 {
-        irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
+        int i;
 
-        if (needs_crossbar_write(hw)) {
-                cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
-                cb->write(hw - GIC_IRQ_START, cb->safe_map);
+        raw_spin_lock(&cb->lock);
+        for (i = 0; i < nr_irqs; i++) {
+                struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
+
+                irq_domain_reset_irq_data(d);
+                cb->irq_map[d->hwirq] = IRQ_FREE;
+                cb->write(d->hwirq, cb->safe_map);
         }
+        raw_spin_unlock(&cb->lock);
 }
 
 static int crossbar_domain_xlate(struct irq_domain *d,
@@ -133,44 +171,22 @@ static int crossbar_domain_xlate(struct irq_domain *d,
                                  unsigned long *out_hwirq,
                                  unsigned int *out_type)
 {
-        int ret;
-        int req_num = intspec[1];
-        int direct_map_num;
-
-        if (req_num >= cb->max_crossbar_sources) {
-                direct_map_num = req_num - cb->max_crossbar_sources;
-                if (direct_map_num < cb->int_max) {
-                        ret = cb->irq_map[direct_map_num];
-                        if (ret == IRQ_RESERVED || ret == IRQ_SKIP) {
-                                /* We use the interrupt num as h/w irq num */
-                                ret = direct_map_num;
-                                goto found;
-                        }
-                }
-
-                pr_err("%s: requested crossbar number %d > max %d\n",
-                       __func__, req_num, cb->max_crossbar_sources);
-                return -EINVAL;
-        }
-
-        ret = get_prev_map_irq(req_num);
-        if (ret >= 0)
-                goto found;
-
-        ret = allocate_free_irq(req_num);
-
-        if (ret < 0)
-                return ret;
-
-found:
-        *out_hwirq = ret + GIC_IRQ_START;
+        if (d->of_node != controller)
+                return -EINVAL; /* Shouldn't happen, really... */
+        if (intsize != 3)
+                return -EINVAL; /* Not GIC compliant */
+        if (intspec[0] != 0)
+                return -EINVAL; /* No PPI should point to this domain */
+
+        *out_hwirq = intspec[1];
+        *out_type = intspec[2];
         return 0;
 }
 
-static const struct irq_domain_ops routable_irq_domain_ops = {
-        .map = crossbar_domain_map,
-        .unmap = crossbar_domain_unmap,
-        .xlate = crossbar_domain_xlate
+static const struct irq_domain_ops crossbar_domain_ops = {
+        .alloc  = crossbar_domain_alloc,
+        .free   = crossbar_domain_free,
+        .xlate  = crossbar_domain_xlate,
 };
 
 static int __init crossbar_of_init(struct device_node *node)
@@ -293,7 +309,8 @@ static int __init crossbar_of_init(struct device_node *node)
                 cb->write(i, cb->safe_map);
         }
 
-        register_routable_domain_ops(&routable_irq_domain_ops);
+        raw_spin_lock_init(&cb->lock);
+
         return 0;
 
 err_reg_offset:
@@ -309,18 +326,37 @@ err_cb:
         return ret;
 }
 
-static const struct of_device_id crossbar_match[] __initconst = {
-        { .compatible = "ti,irq-crossbar" },
-        {}
-};
-
-int __init irqcrossbar_init(void)
+static int __init irqcrossbar_init(struct device_node *node,
+                                   struct device_node *parent)
 {
-        struct device_node *np;
-        np = of_find_matching_node(NULL, crossbar_match);
-        if (!np)
+        struct irq_domain *parent_domain, *domain;
+        int err;
+
+        if (!parent) {
+                pr_err("%s: no parent, giving up\n", node->full_name);
                 return -ENODEV;
+        }
+
+        parent_domain = irq_find_host(parent);
+        if (!parent_domain) {
+                pr_err("%s: unable to obtain parent domain\n", node->full_name);
+                return -ENXIO;
+        }
+
+        err = crossbar_of_init(node);
+        if (err)
+                return err;
+
+        domain = irq_domain_add_hierarchy(parent_domain, 0,
+                                          cb->max_crossbar_sources,
+                                          node, &crossbar_domain_ops,
+                                          NULL);
+        if (!domain) {
+                pr_err("%s: failed to allocated domain\n", node->full_name);
+                return -ENOMEM;
+        }
 
-        crossbar_of_init(np);
         return 0;
 }
+
+IRQCHIP_DECLARE(ti_irqcrossbar, "ti,irq-crossbar", irqcrossbar_init);
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 50e70a8c7ec4..868983c6aa5e 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -798,15 +798,12 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
                 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
                                     handle_fasteoi_irq, NULL, NULL);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-
-                gic_routable_irq_domain_ops->map(d, irq, hw);
         }
         return 0;
 }
 
 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
 {
-        gic_routable_irq_domain_ops->unmap(d, irq);
 }
 
 static int gic_irq_domain_xlate(struct irq_domain *d,
@@ -825,16 +822,8 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
         *out_hwirq = intspec[1] + 16;
 
         /* For SPIs, we need to add 16 more to get the GIC irq ID number */
-        if (!intspec[0]) {
-                ret = gic_routable_irq_domain_ops->xlate(d, controller,
-                                                         intspec,
-                                                         intsize,
-                                                         out_hwirq,
-                                                         out_type);
-
-                if (IS_ERR_VALUE(ret))
-                        return ret;
-        }
+        if (!intspec[0])
+                *out_hwirq += 16;
 
         *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
 
@@ -891,37 +880,6 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
         .xlate = gic_irq_domain_xlate,
 };
 
-/* Default functions for routable irq domain */
-static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
-                              irq_hw_number_t hw)
-{
-        return 0;
-}
-
-static void gic_routable_irq_domain_unmap(struct irq_domain *d,
-                                          unsigned int irq)
-{
-}
-
-static int gic_routable_irq_domain_xlate(struct irq_domain *d,
-                                struct device_node *controller,
-                                const u32 *intspec, unsigned int intsize,
-                                unsigned long *out_hwirq,
-                                unsigned int *out_type)
-{
-        *out_hwirq += 16;
-        return 0;
-}
-
-static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
-        .map = gic_routable_irq_domain_map,
-        .unmap = gic_routable_irq_domain_unmap,
-        .xlate = gic_routable_irq_domain_xlate,
-};
-
-const struct irq_domain_ops *gic_routable_irq_domain_ops =
-                                        &gic_default_routable_irq_domain_ops;
-
 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
                            void __iomem *dist_base, void __iomem *cpu_base,
                            u32 percpu_offset, struct device_node *node)
@@ -929,7 +887,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
         irq_hw_number_t hwirq_base;
         struct gic_chip_data *gic;
         int gic_irqs, irq_base, i;
-        int nr_routable_irqs;
 
         BUG_ON(gic_nr >= MAX_GIC_NR);
 
@@ -985,15 +942,9 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
         gic->gic_irqs = gic_irqs;
 
         if (node) {             /* DT case */
-                const struct irq_domain_ops *ops = &gic_irq_domain_hierarchy_ops;
-
-                if (!of_property_read_u32(node, "arm,routable-irqs",
-                                          &nr_routable_irqs)) {
-                        ops = &gic_irq_domain_ops;
-                        gic_irqs = nr_routable_irqs;
-                }
-
-                gic->domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
+                gic->domain = irq_domain_add_linear(node, gic_irqs,
+                                                    &gic_irq_domain_hierarchy_ops,
+                                                    gic);
         } else {                /* Non-DT case */
                 /*
                  * For primary GICs, skip over SGIs.
diff --git a/include/linux/irq.h b/include/linux/irq.h
index d09ec7a1243e..3057c48e4933 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -460,6 +460,7 @@ extern void irq_chip_eoi_parent(struct irq_data *data);
 extern int irq_chip_set_affinity_parent(struct irq_data *data,
                                         const struct cpumask *dest,
                                         bool force);
+extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
 #endif
 
 /* Handling of unhandled and spurious interrupts: */
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 71d706d5f169..3978c5be4edc 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -115,11 +115,5 @@ int gic_get_cpu_id(unsigned int cpu);
 void gic_migrate_target(unsigned int new_cpu_id);
 unsigned long gic_get_sgir_physaddr(void);
 
-extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
-static inline void __init register_routable_domain_ops
-                                        (const struct irq_domain_ops *ops)
-{
-        gic_routable_irq_domain_ops = ops;
-}
 #endif /* __ASSEMBLY */
 #endif
diff --git a/include/linux/irqchip/irq-crossbar.h b/include/linux/irqchip/irq-crossbar.h
deleted file mode 100644
index e5537b81df8d..000000000000
--- a/include/linux/irqchip/irq-crossbar.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- *  drivers/irqchip/irq-crossbar.h
- *
- *  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-int irqcrossbar_init(void);
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index 6f1c7a566b95..eb9a4ea394ab 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -948,6 +948,22 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data)
 
         return -ENOSYS;
 }
+
+/**
+ * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
+ * @data:       Pointer to interrupt specific data
+ * @on:         Whether to set or reset the wake-up capability of this irq
+ *
+ * Conditional, as the underlying parent chip might not implement it.
+ */
+int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
+{
+        data = data->parent_data;
+        if (data->chip->irq_set_wake)
+                return data->chip->irq_set_wake(data, on);
+
+        return -ENOSYS;
+}
 #endif
 
 /**