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authorDinh Nguyen <dinguyen@kernel.org>2018-03-21 10:20:12 -0400
committerStephen Boyd <sboyd@kernel.org>2018-04-06 13:12:35 -0400
commit07afb8db7340f9b6051a26c5c28f2ce74148f6b5 (patch)
tree0832c3b259b1427d079c8c574a99f266dd63b8b0
parent89727949ea1e5f8ec481cba4d5c71c32d8bff3bc (diff)
clk: socfpga: stratix10: add clock driver for Stratix10 platform
Add a clock driver for the Stratix10 SoC. The driver is similar to the Cyclone5/Arria10 platforms, with the exception that this driver only uses one single clock binding. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/socfpga/Makefile9
-rw-r--r--drivers/clk/socfpga/clk-gate-s10.c125
-rw-r--r--drivers/clk/socfpga/clk-periph-s10.c149
-rw-r--r--drivers/clk/socfpga/clk-pll-s10.c146
-rw-r--r--drivers/clk/socfpga/clk-s10.c345
-rw-r--r--drivers/clk/socfpga/clk.h4
-rw-r--r--drivers/clk/socfpga/stratix10-clk.h80
8 files changed, 854 insertions, 5 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 71ec41e6364f..80ab422438ee 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -88,6 +88,7 @@ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
88obj-$(CONFIG_PLAT_SPEAR) += spear/ 88obj-$(CONFIG_PLAT_SPEAR) += spear/
89obj-$(CONFIG_ARCH_SPRD) += sprd/ 89obj-$(CONFIG_ARCH_SPRD) += sprd/
90obj-$(CONFIG_ARCH_STI) += st/ 90obj-$(CONFIG_ARCH_STI) += st/
91obj-$(CONFIG_ARCH_STRATIX10) += socfpga/
91obj-$(CONFIG_ARCH_SUNXI) += sunxi/ 92obj-$(CONFIG_ARCH_SUNXI) += sunxi/
92obj-$(CONFIG_ARCH_SUNXI) += sunxi-ng/ 93obj-$(CONFIG_ARCH_SUNXI) += sunxi-ng/
93obj-$(CONFIG_ARCH_TEGRA) += tegra/ 94obj-$(CONFIG_ARCH_TEGRA) += tegra/
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
index 9146c20fe21f..ce5aa7802eb8 100644
--- a/drivers/clk/socfpga/Makefile
+++ b/drivers/clk/socfpga/Makefile
@@ -1,6 +1,5 @@
1# SPDX-License-Identifier: GPL-2.0 1# SPDX-License-Identifier: GPL-2.0
2obj-y += clk.o 2obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o
3obj-y += clk-gate.o 3obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
4obj-y += clk-pll.o 4obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o
5obj-y += clk-periph.o 5obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
6obj-y += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c
new file mode 100644
index 000000000000..eee2d48ab656
--- /dev/null
+++ b/drivers/clk/socfpga/clk-gate-s10.c
@@ -0,0 +1,125 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017, Intel Corporation
4 */
5#include <linux/clk-provider.h>
6#include <linux/slab.h>
7#include "stratix10-clk.h"
8#include "clk.h"
9
10#define SOCFPGA_CS_PDBG_CLK "cs_pdbg_clk"
11#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
12
13static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
14 unsigned long parent_rate)
15{
16 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
17 u32 div = 1, val;
18
19 if (socfpgaclk->fixed_div) {
20 div = socfpgaclk->fixed_div;
21 } else if (socfpgaclk->div_reg) {
22 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
23 val &= GENMASK(socfpgaclk->width - 1, 0);
24 div = (1 << val);
25 }
26 return parent_rate / div;
27}
28
29static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk,
30 unsigned long parent_rate)
31{
32 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
33 u32 div = 1, val;
34
35 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
36 val &= GENMASK(socfpgaclk->width - 1, 0);
37 div = (1 << val);
38 div = div ? 4 : 1;
39
40 return parent_rate / div;
41}
42
43static u8 socfpga_gate_get_parent(struct clk_hw *hwclk)
44{
45 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
46 u32 mask;
47 u8 parent = 0;
48
49 if (socfpgaclk->bypass_reg) {
50 mask = (0x1 << socfpgaclk->bypass_shift);
51 parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
52 socfpgaclk->bypass_shift);
53 }
54 return parent;
55}
56
57static struct clk_ops gateclk_ops = {
58 .recalc_rate = socfpga_gate_clk_recalc_rate,
59 .get_parent = socfpga_gate_get_parent,
60};
61
62static const struct clk_ops dbgclk_ops = {
63 .recalc_rate = socfpga_dbg_clk_recalc_rate,
64 .get_parent = socfpga_gate_get_parent,
65};
66
67struct clk *s10_register_gate(const char *name, const char *parent_name,
68 const char * const *parent_names,
69 u8 num_parents, unsigned long flags,
70 void __iomem *regbase, unsigned long gate_reg,
71 unsigned long gate_idx, unsigned long div_reg,
72 unsigned long div_offset, u8 div_width,
73 unsigned long bypass_reg, u8 bypass_shift,
74 u8 fixed_div)
75{
76 struct clk *clk;
77 struct socfpga_gate_clk *socfpga_clk;
78 struct clk_init_data init;
79
80 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
81 if (!socfpga_clk)
82 return NULL;
83
84 socfpga_clk->hw.reg = regbase + gate_reg;
85 socfpga_clk->hw.bit_idx = gate_idx;
86
87 gateclk_ops.enable = clk_gate_ops.enable;
88 gateclk_ops.disable = clk_gate_ops.disable;
89
90 socfpga_clk->fixed_div = fixed_div;
91
92 if (div_reg)
93 socfpga_clk->div_reg = regbase + div_reg;
94 else
95 socfpga_clk->div_reg = NULL;
96
97 socfpga_clk->width = div_width;
98 socfpga_clk->shift = div_offset;
99
100 if (bypass_reg)
101 socfpga_clk->bypass_reg = regbase + bypass_reg;
102 else
103 socfpga_clk->bypass_reg = NULL;
104 socfpga_clk->bypass_shift = bypass_shift;
105
106 if (streq(name, "cs_pdbg_clk"))
107 init.ops = &dbgclk_ops;
108 else
109 init.ops = &gateclk_ops;
110
111 init.name = name;
112 init.flags = flags;
113
114 init.num_parents = num_parents;
115 init.parent_names = parent_names ? parent_names : &parent_name;
116 socfpga_clk->hw.hw.init = &init;
117
118 clk = clk_register(NULL, &socfpga_clk->hw.hw);
119 if (WARN_ON(IS_ERR(clk))) {
120 kfree(socfpga_clk);
121 return NULL;
122 }
123
124 return clk;
125}
diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c
new file mode 100644
index 000000000000..568f59b58ddf
--- /dev/null
+++ b/drivers/clk/socfpga/clk-periph-s10.c
@@ -0,0 +1,149 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017, Intel Corporation
4 */
5#include <linux/slab.h>
6#include <linux/clk-provider.h>
7
8#include "stratix10-clk.h"
9#include "clk.h"
10
11#define CLK_MGR_FREE_SHIFT 16
12#define CLK_MGR_FREE_MASK 0x7
13#define SWCTRLBTCLKSEN_SHIFT 8
14
15#define to_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
16
17static unsigned long clk_peri_c_clk_recalc_rate(struct clk_hw *hwclk,
18 unsigned long parent_rate)
19{
20 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
21 unsigned long div = 1;
22 u32 val;
23
24 val = readl(socfpgaclk->hw.reg);
25 val &= GENMASK(SWCTRLBTCLKSEN_SHIFT - 1, 0);
26 parent_rate /= val;
27
28 return parent_rate / div;
29}
30
31static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk,
32 unsigned long parent_rate)
33{
34 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
35 unsigned long div = 1;
36
37 if (socfpgaclk->fixed_div) {
38 div = socfpgaclk->fixed_div;
39 } else {
40 if (!socfpgaclk->bypass_reg)
41 div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
42 }
43
44 return parent_rate / div;
45}
46
47static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
48{
49 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
50 u32 clk_src, mask;
51 u8 parent;
52
53 if (socfpgaclk->bypass_reg) {
54 mask = (0x1 << socfpgaclk->bypass_shift);
55 parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
56 socfpgaclk->bypass_shift);
57 } else {
58 clk_src = readl(socfpgaclk->hw.reg);
59 parent = (clk_src >> CLK_MGR_FREE_SHIFT) &
60 CLK_MGR_FREE_MASK;
61 }
62 return parent;
63}
64
65static const struct clk_ops peri_c_clk_ops = {
66 .recalc_rate = clk_peri_c_clk_recalc_rate,
67 .get_parent = clk_periclk_get_parent,
68};
69
70static const struct clk_ops peri_cnt_clk_ops = {
71 .recalc_rate = clk_peri_cnt_clk_recalc_rate,
72 .get_parent = clk_periclk_get_parent,
73};
74
75struct clk *s10_register_periph(const char *name, const char *parent_name,
76 const char * const *parent_names,
77 u8 num_parents, unsigned long flags,
78 void __iomem *reg, unsigned long offset)
79{
80 struct clk *clk;
81 struct socfpga_periph_clk *periph_clk;
82 struct clk_init_data init;
83
84 periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
85 if (WARN_ON(!periph_clk))
86 return NULL;
87
88 periph_clk->hw.reg = reg + offset;
89
90 init.name = name;
91 init.ops = &peri_c_clk_ops;
92 init.flags = flags;
93
94 init.num_parents = num_parents;
95 init.parent_names = parent_names ? parent_names : &parent_name;
96
97 periph_clk->hw.hw.init = &init;
98
99 clk = clk_register(NULL, &periph_clk->hw.hw);
100 if (WARN_ON(IS_ERR(clk))) {
101 kfree(periph_clk);
102 return NULL;
103 }
104 return clk;
105}
106
107struct clk *s10_register_cnt_periph(const char *name, const char *parent_name,
108 const char * const *parent_names,
109 u8 num_parents, unsigned long flags,
110 void __iomem *regbase, unsigned long offset,
111 u8 fixed_divider, unsigned long bypass_reg,
112 unsigned long bypass_shift)
113{
114 struct clk *clk;
115 struct socfpga_periph_clk *periph_clk;
116 struct clk_init_data init;
117
118 periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
119 if (WARN_ON(!periph_clk))
120 return NULL;
121
122 if (offset)
123 periph_clk->hw.reg = regbase + offset;
124 else
125 periph_clk->hw.reg = NULL;
126
127 if (bypass_reg)
128 periph_clk->bypass_reg = regbase + bypass_reg;
129 else
130 periph_clk->bypass_reg = NULL;
131 periph_clk->bypass_shift = bypass_shift;
132 periph_clk->fixed_div = fixed_divider;
133
134 init.name = name;
135 init.ops = &peri_cnt_clk_ops;
136 init.flags = flags;
137
138 init.num_parents = num_parents;
139 init.parent_names = parent_names ? parent_names : &parent_name;
140
141 periph_clk->hw.hw.init = &init;
142
143 clk = clk_register(NULL, &periph_clk->hw.hw);
144 if (WARN_ON(IS_ERR(clk))) {
145 kfree(periph_clk);
146 return NULL;
147 }
148 return clk;
149}
diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
new file mode 100644
index 000000000000..2d5d8b43727e
--- /dev/null
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -0,0 +1,146 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017, Intel Corporation
4 */
5#include <linux/slab.h>
6#include <linux/clk-provider.h>
7
8#include "stratix10-clk.h"
9#include "clk.h"
10
11/* Clock Manager offsets */
12#define CLK_MGR_PLL_CLK_SRC_SHIFT 16
13#define CLK_MGR_PLL_CLK_SRC_MASK 0x3
14
15/* PLL Clock enable bits */
16#define SOCFPGA_PLL_POWER 0
17#define SOCFPGA_PLL_RESET_MASK 0x2
18#define SOCFPGA_PLL_REFDIV_MASK 0x00003F00
19#define SOCFPGA_PLL_REFDIV_SHIFT 8
20#define SOCFPGA_PLL_MDIV_MASK 0xFF000000
21#define SOCFPGA_PLL_MDIV_SHIFT 24
22#define SWCTRLBTCLKSEL_MASK 0x200
23#define SWCTRLBTCLKSEL_SHIFT 9
24
25#define SOCFPGA_BOOT_CLK "boot_clk"
26
27#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
28
29static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
30 unsigned long parent_rate)
31{
32 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
33 unsigned long mdiv;
34 unsigned long refdiv;
35 unsigned long reg;
36 unsigned long long vco_freq;
37
38 /* read VCO1 reg for numerator and denominator */
39 reg = readl(socfpgaclk->hw.reg);
40 refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
41 vco_freq = (unsigned long long)parent_rate / refdiv;
42
43 /* Read mdiv and fdiv from the fdbck register */
44 reg = readl(socfpgaclk->hw.reg + 0x4);
45 mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
46 vco_freq = (unsigned long long)parent_rate * (mdiv + 6);
47
48 return (unsigned long)vco_freq;
49}
50
51static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk,
52 unsigned long parent_rate)
53{
54 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
55 u32 div = 1;
56
57 div = ((readl(socfpgaclk->hw.reg) &
58 SWCTRLBTCLKSEL_MASK) >>
59 SWCTRLBTCLKSEL_SHIFT);
60 div += 1;
61 return parent_rate /= div;
62}
63
64
65static u8 clk_pll_get_parent(struct clk_hw *hwclk)
66{
67 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
68 u32 pll_src;
69
70 pll_src = readl(socfpgaclk->hw.reg);
71 return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
72 CLK_MGR_PLL_CLK_SRC_MASK;
73}
74
75static u8 clk_boot_get_parent(struct clk_hw *hwclk)
76{
77 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
78 u32 pll_src;
79
80 pll_src = readl(socfpgaclk->hw.reg);
81 return (pll_src >> SWCTRLBTCLKSEL_SHIFT) &
82 SWCTRLBTCLKSEL_MASK;
83}
84
85static int clk_pll_prepare(struct clk_hw *hwclk)
86{
87 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
88 u32 reg;
89
90 /* Bring PLL out of reset */
91 reg = readl(socfpgaclk->hw.reg);
92 reg |= SOCFPGA_PLL_RESET_MASK;
93 writel(reg, socfpgaclk->hw.reg);
94
95 return 0;
96}
97
98static struct clk_ops clk_pll_ops = {
99 .recalc_rate = clk_pll_recalc_rate,
100 .get_parent = clk_pll_get_parent,
101 .prepare = clk_pll_prepare,
102};
103
104static struct clk_ops clk_boot_ops = {
105 .recalc_rate = clk_boot_clk_recalc_rate,
106 .get_parent = clk_boot_get_parent,
107 .prepare = clk_pll_prepare,
108};
109
110struct clk *s10_register_pll(const char *name, const char * const *parent_names,
111 u8 num_parents, unsigned long flags,
112 void __iomem *reg, unsigned long offset)
113{
114 struct clk *clk;
115 struct socfpga_pll *pll_clk;
116 struct clk_init_data init;
117
118 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
119 if (WARN_ON(!pll_clk))
120 return NULL;
121
122 pll_clk->hw.reg = reg + offset;
123
124 if (streq(name, SOCFPGA_BOOT_CLK))
125 init.ops = &clk_boot_ops;
126 else
127 init.ops = &clk_pll_ops;
128
129 init.name = name;
130 init.flags = flags;
131
132 init.num_parents = num_parents;
133 init.parent_names = parent_names;
134 pll_clk->hw.hw.init = &init;
135
136 pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
137 clk_pll_ops.enable = clk_gate_ops.enable;
138 clk_pll_ops.disable = clk_gate_ops.disable;
139
140 clk = clk_register(NULL, &pll_clk->hw.hw);
141 if (WARN_ON(IS_ERR(clk))) {
142 kfree(pll_clk);
143 return NULL;
144 }
145 return clk;
146}
diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
new file mode 100644
index 000000000000..3a11c382a663
--- /dev/null
+++ b/drivers/clk/socfpga/clk-s10.c
@@ -0,0 +1,345 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017, Intel Corporation
4 */
5#include <linux/slab.h>
6#include <linux/clk-provider.h>
7#include <linux/of_device.h>
8#include <linux/of_address.h>
9#include <linux/platform_device.h>
10
11#include <dt-bindings/clock/stratix10-clock.h>
12
13#include "stratix10-clk.h"
14
15static const char * const pll_mux[] = { "osc1", "cb_intosc_hs_div2_clk",
16 "f2s_free_clk",};
17static const char * const cntr_mux[] = { "main_pll", "periph_pll",
18 "osc1", "cb_intosc_hs_div2_clk",
19 "f2s_free_clk"};
20static const char * const boot_mux[] = { "osc1", "cb_intosc_hs_div2_clk",};
21
22static const char * const noc_free_mux[] = {"main_noc_base_clk",
23 "peri_noc_base_clk",
24 "osc1", "cb_intosc_hs_div2_clk",
25 "f2s_free_clk"};
26
27static const char * const emaca_free_mux[] = {"peri_emaca_clk", "boot_clk"};
28static const char * const emacb_free_mux[] = {"peri_emacb_clk", "boot_clk"};
29static const char * const emac_ptp_free_mux[] = {"peri_emac_ptp_clk", "boot_clk"};
30static const char * const gpio_db_free_mux[] = {"peri_gpio_db_clk", "boot_clk"};
31static const char * const sdmmc_free_mux[] = {"peri_sdmmc_clk", "boot_clk"};
32static const char * const s2f_usr1_free_mux[] = {"peri_s2f_usr1_clk", "boot_clk"};
33static const char * const psi_ref_free_mux[] = {"peri_psi_ref_clk", "boot_clk"};
34static const char * const mpu_mux[] = { "mpu_free_clk", "boot_clk",};
35
36static const char * const s2f_usr0_mux[] = {"f2s_free_clk", "boot_clk"};
37static const char * const emac_mux[] = {"emaca_free_clk", "emacb_free_clk"};
38static const char * const noc_mux[] = {"noc_free_clk", "boot_clk"};
39
40/* clocks in AO (always on) controller */
41static const struct stratix10_pll_clock s10_pll_clks[] = {
42 { STRATIX10_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
43 0x0},
44 { STRATIX10_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
45 0, 0x74},
46 { STRATIX10_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
47 0, 0xe4},
48};
49
50static const struct stratix10_perip_c_clock s10_main_perip_c_clks[] = {
51 { STRATIX10_MAIN_MPU_BASE_CLK, "main_mpu_base_clk", "main_pll", NULL, 1, 0, 0x84},
52 { STRATIX10_MAIN_NOC_BASE_CLK, "main_noc_base_clk", "main_pll", NULL, 1, 0, 0x88},
53 { STRATIX10_PERI_MPU_BASE_CLK, "peri_mpu_base_clk", "periph_pll", NULL, 1, 0,
54 0xF4},
55 { STRATIX10_PERI_NOC_BASE_CLK, "peri_noc_base_clk", "periph_pll", NULL, 1, 0,
56 0xF8},
57};
58
59static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = {
60 { STRATIX10_MPU_FREE_CLK, "mpu_free_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
61 0, 0x48, 0, 0, 0},
62 { STRATIX10_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
63 0, 0x4C, 0, 0, 0},
64 { STRATIX10_MAIN_EMACA_CLK, "main_emaca_clk", "main_noc_base_clk", NULL, 1, 0,
65 0x50, 0, 0, 0},
66 { STRATIX10_MAIN_EMACB_CLK, "main_emacb_clk", "main_noc_base_clk", NULL, 1, 0,
67 0x54, 0, 0, 0},
68 { STRATIX10_MAIN_EMAC_PTP_CLK, "main_emac_ptp_clk", "main_noc_base_clk", NULL, 1, 0,
69 0x58, 0, 0, 0},
70 { STRATIX10_MAIN_GPIO_DB_CLK, "main_gpio_db_clk", "main_noc_base_clk", NULL, 1, 0,
71 0x5C, 0, 0, 0},
72 { STRATIX10_MAIN_SDMMC_CLK, "main_sdmmc_clk", "main_noc_base_clk", NULL, 1, 0,
73 0x60, 0, 0, 0},
74 { STRATIX10_MAIN_S2F_USR0_CLK, "main_s2f_usr0_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
75 0, 0x64, 0, 0, 0},
76 { STRATIX10_MAIN_S2F_USR1_CLK, "main_s2f_usr1_clk", "main_noc_base_clk", NULL, 1, 0,
77 0x68, 0, 0, 0},
78 { STRATIX10_MAIN_PSI_REF_CLK, "main_psi_ref_clk", "main_noc_base_clk", NULL, 1, 0,
79 0x6C, 0, 0, 0},
80 { STRATIX10_PERI_EMACA_CLK, "peri_emaca_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
81 0, 0xBC, 0, 0, 0},
82 { STRATIX10_PERI_EMACB_CLK, "peri_emacb_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
83 0, 0xC0, 0, 0, 0},
84 { STRATIX10_PERI_EMAC_PTP_CLK, "peri_emac_ptp_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
85 0, 0xC4, 0, 0, 0},
86 { STRATIX10_PERI_GPIO_DB_CLK, "peri_gpio_db_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
87 0, 0xC8, 0, 0, 0},
88 { STRATIX10_PERI_SDMMC_CLK, "peri_sdmmc_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
89 0, 0xCC, 0, 0, 0},
90 { STRATIX10_PERI_S2F_USR0_CLK, "peri_s2f_usr0_clk", "peri_noc_base_clk", NULL, 1, 0,
91 0xD0, 0, 0, 0},
92 { STRATIX10_PERI_S2F_USR1_CLK, "peri_s2f_usr1_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
93 0, 0xD4, 0, 0, 0},
94 { STRATIX10_PERI_PSI_REF_CLK, "peri_psi_ref_clk", "peri_noc_base_clk", NULL, 1, 0,
95 0xD8, 0, 0, 0},
96 { STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0,
97 0, 4, 0, 0},
98 { STRATIX10_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
99 0, 0, 0, 0x3C, 1},
100 { STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
101 0, 0, 4, 0xB0, 0},
102 { STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
103 0, 0, 4, 0xB0, 1},
104 { STRATIX10_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
105 ARRAY_SIZE(emac_ptp_free_mux), 0, 0, 4, 0xB0, 2},
106 { STRATIX10_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
107 ARRAY_SIZE(gpio_db_free_mux), 0, 0, 0, 0xB0, 3},
108 { STRATIX10_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
109 ARRAY_SIZE(sdmmc_free_mux), 0, 0, 0, 0xB0, 4},
110 { STRATIX10_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
111 ARRAY_SIZE(s2f_usr1_free_mux), 0, 0, 0, 0xB0, 5},
112 { STRATIX10_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
113 ARRAY_SIZE(psi_ref_free_mux), 0, 0, 0, 0xB0, 6},
114};
115
116static const struct stratix10_gate_clock s10_gate_clks[] = {
117 { STRATIX10_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x30,
118 0, 0, 0, 0, 0x3C, 0, 0},
119 { STRATIX10_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x30,
120 0, 0, 0, 0, 0, 0, 4},
121 { STRATIX10_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x30,
122 0, 0, 0, 0, 0, 0, 2},
123 { STRATIX10_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x30,
124 1, 0x70, 0, 2, 0, 0, 0},
125 { STRATIX10_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x30,
126 2, 0x70, 8, 2, 0, 0, 0},
127 { STRATIX10_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x30,
128 3, 0x70, 16, 2, 0, 0, 0},
129 { STRATIX10_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x30,
130 4, 0x70, 24, 2, 0, 0, 0},
131 { STRATIX10_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x30,
132 4, 0x70, 26, 2, 0, 0, 0},
133 { STRATIX10_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x30,
134 4, 0x70, 28, 1, 0, 0, 0},
135 { STRATIX10_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x30,
136 5, 0, 0, 0, 0, 0, 0},
137 { STRATIX10_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x30,
138 6, 0, 0, 0, 0, 0, 0},
139 { STRATIX10_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
140 0, 0, 0, 0, 0xDC, 26, 0},
141 { STRATIX10_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
142 1, 0, 0, 0, 0xDC, 27, 0},
143 { STRATIX10_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
144 2, 0, 0, 0, 0xDC, 28, 0},
145 { STRATIX10_EMAC_PTP_CLK, "emac_ptp_clk", "emac_ptp_free_clk", NULL, 1, 0, 0xA4,
146 3, 0, 0, 0, 0, 0, 0},
147 { STRATIX10_GPIO_DB_CLK, "gpio_db_clk", "gpio_db_free_clk", NULL, 1, 0, 0xA4,
148 4, 0xE0, 0, 16, 0, 0, 0},
149 { STRATIX10_SDMMC_CLK, "sdmmc_clk", "sdmmc_free_clk", NULL, 1, 0, 0xA4,
150 5, 0, 0, 0, 0, 0, 4},
151 { STRATIX10_S2F_USER1_CLK, "s2f_user1_clk", "s2f_user1_free_clk", NULL, 1, 0, 0xA4,
152 6, 0, 0, 0, 0, 0, 0},
153 { STRATIX10_PSI_REF_CLK, "psi_ref_clk", "psi_ref_free_clk", NULL, 1, 0, 0xA4,
154 7, 0, 0, 0, 0, 0, 0},
155 { STRATIX10_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
156 8, 0, 0, 0, 0, 0, 0},
157 { STRATIX10_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
158 9, 0, 0, 0, 0, 0, 0},
159 { STRATIX10_NAND_CLK, "nand_clk", "l4_main_clk", NULL, 1, 0, 0xA4,
160 10, 0, 0, 0, 0, 0, 0},
161};
162
163static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
164 int nums, struct stratix10_clock_data *data)
165{
166 struct clk *clk;
167 void __iomem *base = data->base;
168 int i;
169
170 for (i = 0; i < nums; i++) {
171 clk = s10_register_periph(clks[i].name, clks[i].parent_name,
172 clks[i].parent_names, clks[i].num_parents,
173 clks[i].flags, base, clks[i].offset);
174 if (IS_ERR(clk)) {
175 pr_err("%s: failed to register clock %s\n",
176 __func__, clks[i].name);
177 continue;
178 }
179 data->clk_data.clks[clks[i].id] = clk;
180 }
181 return 0;
182}
183
184static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
185 int nums, struct stratix10_clock_data *data)
186{
187 struct clk *clk;
188 void __iomem *base = data->base;
189 int i;
190
191 for (i = 0; i < nums; i++) {
192 clk = s10_register_cnt_periph(clks[i].name, clks[i].parent_name,
193 clks[i].parent_names,
194 clks[i].num_parents,
195 clks[i].flags, base,
196 clks[i].offset,
197 clks[i].fixed_divider,
198 clks[i].bypass_reg,
199 clks[i].bypass_shift);
200 if (IS_ERR(clk)) {
201 pr_err("%s: failed to register clock %s\n",
202 __func__, clks[i].name);
203 continue;
204 }
205 data->clk_data.clks[clks[i].id] = clk;
206 }
207
208 return 0;
209}
210
211static int s10_clk_register_gate(const struct stratix10_gate_clock *clks,
212 int nums, struct stratix10_clock_data *data)
213{
214 struct clk *clk;
215 void __iomem *base = data->base;
216 int i;
217
218 for (i = 0; i < nums; i++) {
219 clk = s10_register_gate(clks[i].name, clks[i].parent_name,
220 clks[i].parent_names,
221 clks[i].num_parents,
222 clks[i].flags, base,
223 clks[i].gate_reg,
224 clks[i].gate_idx, clks[i].div_reg,
225 clks[i].div_offset, clks[i].div_width,
226 clks[i].bypass_reg,
227 clks[i].bypass_shift,
228 clks[i].fixed_div);
229 if (IS_ERR(clk)) {
230 pr_err("%s: failed to register clock %s\n",
231 __func__, clks[i].name);
232 continue;
233 }
234 data->clk_data.clks[clks[i].id] = clk;
235 }
236
237 return 0;
238}
239
240static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
241 int nums, struct stratix10_clock_data *data)
242{
243 struct clk *clk;
244 void __iomem *base = data->base;
245 int i;
246
247 for (i = 0; i < nums; i++) {
248 clk = s10_register_pll(clks[i].name, clks[i].parent_names,
249 clks[i].num_parents,
250 clks[i].flags, base,
251 clks[i].offset);
252 if (IS_ERR(clk)) {
253 pr_err("%s: failed to register clock %s\n",
254 __func__, clks[i].name);
255 continue;
256 }
257 data->clk_data.clks[clks[i].id] = clk;
258 }
259
260 return 0;
261}
262
263static struct stratix10_clock_data *__socfpga_s10_clk_init(struct device_node *np,
264 int nr_clks)
265{
266 struct stratix10_clock_data *clk_data;
267 struct clk **clk_table;
268 void __iomem *base;
269
270 base = of_iomap(np, 0);
271 if (!base) {
272 pr_err("%s: failed to map clock registers\n", __func__);
273 goto err;
274 }
275
276 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
277 if (!clk_data)
278 goto err;
279
280 clk_data->base = base;
281 clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL);
282 if (!clk_table)
283 goto err_data;
284
285 clk_data->clk_data.clks = clk_table;
286 clk_data->clk_data.clk_num = nr_clks;
287 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
288 return clk_data;
289
290err_data:
291 kfree(clk_data);
292err:
293 return NULL;
294}
295
296static int s10_clkmgr_init(struct device_node *np)
297{
298 struct stratix10_clock_data *clk_data;
299
300 clk_data = __socfpga_s10_clk_init(np, STRATIX10_NUM_CLKS);
301 if (!clk_data)
302 return -ENOMEM;
303
304 s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
305
306 s10_clk_register_c_perip(s10_main_perip_c_clks,
307 ARRAY_SIZE(s10_main_perip_c_clks), clk_data);
308
309 s10_clk_register_cnt_perip(s10_main_perip_cnt_clks,
310 ARRAY_SIZE(s10_main_perip_cnt_clks),
311 clk_data);
312
313 s10_clk_register_gate(s10_gate_clks, ARRAY_SIZE(s10_gate_clks),
314 clk_data);
315 return 0;
316}
317
318static int s10_clkmgr_probe(struct platform_device *pdev)
319{
320 struct device_node *np = pdev->dev.of_node;
321
322 s10_clkmgr_init(np);
323
324 return 0;
325}
326
327static const struct of_device_id stratix10_clkmgr_match_table[] = {
328 { .compatible = "intel,stratix10-clkmgr",
329 .data = s10_clkmgr_init },
330 { }
331};
332
333static struct platform_driver stratix10_clkmgr_driver = {
334 .probe = s10_clkmgr_probe,
335 .driver = {
336 .name = "stratix10-clkmgr",
337 .of_match_table = stratix10_clkmgr_match_table,
338 },
339};
340
341static int __init s10_clk_init(void)
342{
343 return platform_driver_register(&stratix10_clkmgr_driver);
344}
345core_initcall(s10_clk_init);
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index 9cf1230115b1..26c3a265cf78 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -54,9 +54,11 @@ struct socfpga_gate_clk {
54 char *parent_name; 54 char *parent_name;
55 u32 fixed_div; 55 u32 fixed_div;
56 void __iomem *div_reg; 56 void __iomem *div_reg;
57 void __iomem *bypass_reg;
57 struct regmap *sys_mgr_base_addr; 58 struct regmap *sys_mgr_base_addr;
58 u32 width; /* only valid if div_reg != 0 */ 59 u32 width; /* only valid if div_reg != 0 */
59 u32 shift; /* only valid if div_reg != 0 */ 60 u32 shift; /* only valid if div_reg != 0 */
61 u32 bypass_shift; /* only valid if bypass_reg != 0 */
60 u32 clk_phase[2]; 62 u32 clk_phase[2];
61}; 63};
62 64
@@ -65,8 +67,10 @@ struct socfpga_periph_clk {
65 char *parent_name; 67 char *parent_name;
66 u32 fixed_div; 68 u32 fixed_div;
67 void __iomem *div_reg; 69 void __iomem *div_reg;
70 void __iomem *bypass_reg;
68 u32 width; /* only valid if div_reg != 0 */ 71 u32 width; /* only valid if div_reg != 0 */
69 u32 shift; /* only valid if div_reg != 0 */ 72 u32 shift; /* only valid if div_reg != 0 */
73 u32 bypass_shift; /* only valid if bypass_reg != 0 */
70}; 74};
71 75
72#endif /* SOCFPGA_CLK_H */ 76#endif /* SOCFPGA_CLK_H */
diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h
new file mode 100644
index 000000000000..e8e121907952
--- /dev/null
+++ b/drivers/clk/socfpga/stratix10-clk.h
@@ -0,0 +1,80 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2017, Intel Corporation
4 */
5
6#ifndef __STRATIX10_CLK_H
7#define __STRATIX10_CLK_H
8
9struct stratix10_clock_data {
10 struct clk_onecell_data clk_data;
11 void __iomem *base;
12};
13
14struct stratix10_pll_clock {
15 unsigned int id;
16 const char *name;
17 const char *const *parent_names;
18 u8 num_parents;
19 unsigned long flags;
20 unsigned long offset;
21};
22
23struct stratix10_perip_c_clock {
24 unsigned int id;
25 const char *name;
26 const char *parent_name;
27 const char *const *parent_names;
28 u8 num_parents;
29 unsigned long flags;
30 unsigned long offset;
31};
32
33struct stratix10_perip_cnt_clock {
34 unsigned int id;
35 const char *name;
36 const char *parent_name;
37 const char *const *parent_names;
38 u8 num_parents;
39 unsigned long flags;
40 unsigned long offset;
41 u8 fixed_divider;
42 unsigned long bypass_reg;
43 unsigned long bypass_shift;
44};
45
46struct stratix10_gate_clock {
47 unsigned int id;
48 const char *name;
49 const char *parent_name;
50 const char *const *parent_names;
51 u8 num_parents;
52 unsigned long flags;
53 unsigned long gate_reg;
54 u8 gate_idx;
55 unsigned long div_reg;
56 u8 div_offset;
57 u8 div_width;
58 unsigned long bypass_reg;
59 u8 bypass_shift;
60 u8 fixed_div;
61};
62
63struct clk *s10_register_pll(const char *, const char *const *, u8,
64 unsigned long, void __iomem *, unsigned long);
65
66struct clk *s10_register_periph(const char *, const char *,
67 const char * const *, u8, unsigned long,
68 void __iomem *, unsigned long);
69struct clk *s10_register_cnt_periph(const char *, const char *,
70 const char * const *, u8,
71 unsigned long, void __iomem *,
72 unsigned long, u8, unsigned long,
73 unsigned long);
74struct clk *s10_register_gate(const char *, const char *,
75 const char * const *, u8,
76 unsigned long, void __iomem *,
77 unsigned long, unsigned long,
78 unsigned long, unsigned long, u8,
79 unsigned long, u8, u8);
80#endif /* __STRATIX10_CLK_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-31 05:14:05 -0500