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authorAndreas Färber <afaerber@suse.de>2017-02-14 16:24:21 -0500
committerAndreas Färber <afaerber@suse.de>2017-06-18 18:33:22 -0400
commit06edb80f8c79f457983c9af93c1364fc1077c190 (patch)
tree3d9258b8976ea3bd17e29a6697376ea6e143202c
parent1c750fc116e1fcb01a57a8dbabef4ab35ac71e05 (diff)
arm64: dts: Add Actions Semi S900 and Bubblegum-96
Add Device Trees for Actions Semiconductor S900 SoC and uCRobotics Bubblegum-96 board. UART0/1/4/6 interrupts are guesses. Cc: 96boards@ucrobotics.com Signed-off-by: Andreas Färber <afaerber@suse.de>
-rw-r--r--arch/arm64/boot/dts/Makefile1
-rw-r--r--arch/arm64/boot/dts/actions/Makefile5
-rw-r--r--arch/arm64/boot/dts/actions/s900-bubblegum-96.dts35
-rw-r--r--arch/arm64/boot/dts/actions/s900.dtsi164
4 files changed, 205 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 080232b0270e..d1a6b0af12cf 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
1dts-dirs += actions
1dts-dirs += al 2dts-dirs += al
2dts-dirs += allwinner 3dts-dirs += allwinner
3dts-dirs += altera 4dts-dirs += altera
diff --git a/arch/arm64/boot/dts/actions/Makefile b/arch/arm64/boot/dts/actions/Makefile
new file mode 100644
index 000000000000..62922d688ce3
--- /dev/null
+++ b/arch/arm64/boot/dts/actions/Makefile
@@ -0,0 +1,5 @@
1dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb
2
3always := $(dtb-y)
4subdir-y := $(dts-dirs)
5clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
new file mode 100644
index 000000000000..a0c3484dbd12
--- /dev/null
+++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
@@ -0,0 +1,35 @@
1/*
2 * Copyright (c) 2017 Andreas Färber
3 *
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 */
6
7/dts-v1/;
8
9#include "s900.dtsi"
10
11/ {
12 compatible = "ucrobotics,bubblegum-96", "actions,s900";
13 model = "Bubblegum-96";
14
15 aliases {
16 serial5 = &uart5;
17 };
18
19 chosen {
20 stdout-path = "serial5:115200n8";
21 };
22
23 memory@0 {
24 device_type = "memory";
25 reg = <0x0 0x0 0x0 0x80000000>;
26 };
27};
28
29&timer {
30 clocks = <&hosc>;
31};
32
33&uart5 {
34 status = "okay";
35};
diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi
new file mode 100644
index 000000000000..11406f6d3a6d
--- /dev/null
+++ b/arch/arm64/boot/dts/actions/s900.dtsi
@@ -0,0 +1,164 @@
1/*
2 * Copyright (c) 2017 Andreas Färber
3 *
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/ {
10 compatible = "actions,s900";
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 cpus {
16 #address-cells = <2>;
17 #size-cells = <0>;
18
19 cpu0: cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a53", "arm,armv8";
22 reg = <0x0 0x0>;
23 enable-method = "psci";
24 };
25
26 cpu1: cpu@1 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a53", "arm,armv8";
29 reg = <0x0 0x1>;
30 enable-method = "psci";
31 };
32
33 cpu2: cpu@2 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a53", "arm,armv8";
36 reg = <0x0 0x2>;
37 enable-method = "psci";
38 };
39
40 cpu3: cpu@3 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a53", "arm,armv8";
43 reg = <0x0 0x3>;
44 enable-method = "psci";
45 };
46 };
47
48 reserved-memory {
49 #address-cells = <2>;
50 #size-cells = <2>;
51 ranges;
52
53 secmon@1f000000 {
54 reg = <0x0 0x1f000000 0x0 0x1000000>;
55 no-map;
56 };
57 };
58
59 psci {
60 compatible = "arm,psci-0.2";
61 method = "smc";
62 };
63
64 arm-pmu {
65 compatible = "arm,cortex-a53-pmu";
66 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
70 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
71 };
72
73 timer {
74 compatible = "arm,armv8-timer";
75 interrupts = <GIC_PPI 13
76 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 14
78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 11
80 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 10
82 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
83 };
84
85 hosc: hosc {
86 compatible = "fixed-clock";
87 clock-frequency = <24000000>;
88 #clock-cells = <0>;
89 };
90
91 soc {
92 compatible = "simple-bus";
93 #address-cells = <2>;
94 #size-cells = <2>;
95 ranges;
96
97 gic: interrupt-controller@e00f1000 {
98 compatible = "arm,gic-400";
99 reg = <0x0 0xe00f1000 0x0 0x1000>,
100 <0x0 0xe00f2000 0x0 0x2000>,
101 <0x0 0xe00f4000 0x0 0x2000>,
102 <0x0 0xe00f6000 0x0 0x2000>;
103 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
104 interrupt-controller;
105 #interrupt-cells = <3>;
106 };
107
108 uart0: serial@e0120000 {
109 compatible = "actions,s900-uart", "actions,owl-uart";
110 reg = <0x0 0xe0120000 0x0 0x2000>;
111 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
112 status = "disabled";
113 };
114
115 uart1: serial@e0122000 {
116 compatible = "actions,s900-uart", "actions,owl-uart";
117 reg = <0x0 0xe0122000 0x0 0x2000>;
118 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
119 status = "disabled";
120 };
121
122 uart2: serial@e0124000 {
123 compatible = "actions,s900-uart", "actions,owl-uart";
124 reg = <0x0 0xe0124000 0x0 0x2000>;
125 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
126 status = "disabled";
127 };
128
129 uart3: serial@e0126000 {
130 compatible = "actions,s900-uart", "actions,owl-uart";
131 reg = <0x0 0xe0126000 0x0 0x2000>;
132 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
133 status = "disabled";
134 };
135
136 uart4: serial@e0128000 {
137 compatible = "actions,s900-uart", "actions,owl-uart";
138 reg = <0x0 0xe0128000 0x0 0x2000>;
139 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
140 status = "disabled";
141 };
142
143 uart5: serial@e012a000 {
144 compatible = "actions,s900-uart", "actions,owl-uart";
145 reg = <0x0 0xe012a000 0x0 0x2000>;
146 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
147 status = "disabled";
148 };
149
150 uart6: serial@e012c000 {
151 compatible = "actions,s900-uart", "actions,owl-uart";
152 reg = <0x0 0xe012c000 0x0 0x2000>;
153 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
154 status = "disabled";
155 };
156
157 timer: timer@e0228000 {
158 compatible = "actions,s900-timer";
159 reg = <0x0 0xe0228000 0x0 0x8000>;
160 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
161 interrupt-names = "timer1";
162 };
163 };
164};