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authorArnd Bergmann <arnd@arndb.de>2016-04-25 17:01:39 -0400
committerArnd Bergmann <arnd@arndb.de>2016-04-25 17:01:39 -0400
commit05ad9c3e77885e89accb104ab42c48ff9b31d133 (patch)
tree1c3d8c872e426d86f1f4f4427a960b071fe48436
parent9b61aefce7b41cf3ae1c3c2b205fdfca3a537adc (diff)
parent6f92cb2f454c26d9bdada902e22af4bc361a5202 (diff)
Merge tag 'renesas-dt-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Merge "Renesas ARM Based SoC DT Updates for v4.7" from Simon Horman: * Configure NMI key as wakeup source in DT of kzm9g board * Add SDHI support to DT of gose board * Add support of UHS-I SDR-50 for SDHI to DT of r8a7790 SoC * Correct interrupt type for ARM TWD in DT of r8a7779 and sh73a0 SoCs * Add IIC support to DT of r8a7794 SoC * Add CAN support to DT of r8a7793 and r8a7794 SoCs * Add SCIF2 support to r8a7790 device tree * Use CAN, JPU and USB3.0 fallback compatibility string in DT of r8a7791 and r8a7790 SoCs * tag 'renesas-dt-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (22 commits) ARM: dts: gose: Enable SDHI controllers ARM: dts: r8a7793: Add SDHI controllers ARM: dts: r8a7790: fix max-frequency for SDHI ARM: dts: kzm9g: Configure NMI key as wake-up source ARM: dts: r8a7790: lager: Enable UHS-I SDR-50 ARM: dts: r8a7790: Set maximum frequencies for SDHI clocks ARM: dts: r8a7791: Use USB3.0 fallback compatibility string ARM: dts: r8a7790: Use USB3.0 fallback compatibility string ARM: dts: r8a7779: Correct interrupt type for ARM TWD ARM: dts: sh73a0: Correct interrupt type for ARM TWD ARM: dts: r8a7794: Add IIC nodes ARM: dts: r8a7794: add IIC clocks ARM: dts: r8a7793: add CAN nodes to device tree ARM: dts: r8a7793: add CAN clocks to device tree ARM: dts: r8a7794: add CAN nodes to device tree ARM: dts: r8a7794: add CAN clocks to device tree ARM: dts: r8a7790: use fallback can compatibility string ARM: dts: r8a7791: use fallback can compatibility string ARM: dts: r8a7790: Add SCIF2 device node ARM: dts: r8a7790: Add SCIF2 clock ...
Diffstat
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi2
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts22
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi32
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi8
-rw-r--r--arch/arm/boot/dts/r8a7793-gose.dts119
-rw-r--r--arch/arm/boot/dts/r8a7793.dtsi82
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi92
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g.dts7
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi2
-rw-r--r--include/dt-bindings/clock/r8a7790-clock.h1
-rw-r--r--include/dt-bindings/clock/r8a7794-clock.h5
11 files changed, 343 insertions, 29 deletions
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 60bc1e66bba9..5c1d48d712a1 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -67,7 +67,7 @@
67 compatible = "arm,cortex-a9-twd-timer"; 67 compatible = "arm,cortex-a9-twd-timer";
68 reg = <0xf0000600 0x20>; 68 reg = <0xf0000600 0x20>;
69 interrupts = <GIC_PPI 13 69 interrupts = <GIC_PPI 13
70 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 70 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
71 clocks = <&cpg_clocks R8A7779_CLK_ZS>; 71 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
72 }; 72 };
73 73
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 823a119cb1b4..749ba02b6a53 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -345,11 +345,25 @@
345 sdhi0_pins: sd0 { 345 sdhi0_pins: sd0 {
346 groups = "sdhi0_data4", "sdhi0_ctrl"; 346 groups = "sdhi0_data4", "sdhi0_ctrl";
347 function = "sdhi0"; 347 function = "sdhi0";
348 power-source = <3300>;
349 };
350
351 sdhi0_pins_uhs: sd0_uhs {
352 groups = "sdhi0_data4", "sdhi0_ctrl";
353 function = "sdhi0";
354 power-source = <1800>;
348 }; 355 };
349 356
350 sdhi2_pins: sd2 { 357 sdhi2_pins: sd2 {
351 groups = "sdhi2_data4", "sdhi2_ctrl"; 358 groups = "sdhi2_data4", "sdhi2_ctrl";
352 function = "sdhi2"; 359 function = "sdhi2";
360 power-source = <3300>;
361 };
362
363 sdhi2_pins_uhs: sd2_uhs {
364 groups = "sdhi2_data4", "sdhi2_ctrl";
365 function = "sdhi2";
366 power-source = <1800>;
353 }; 367 };
354 368
355 mmc1_pins: mmc1 { 369 mmc1_pins: mmc1 {
@@ -538,21 +552,25 @@
538 552
539&sdhi0 { 553&sdhi0 {
540 pinctrl-0 = <&sdhi0_pins>; 554 pinctrl-0 = <&sdhi0_pins>;
541 pinctrl-names = "default"; 555 pinctrl-1 = <&sdhi0_pins_uhs>;
556 pinctrl-names = "default", "state_uhs";
542 557
543 vmmc-supply = <&vcc_sdhi0>; 558 vmmc-supply = <&vcc_sdhi0>;
544 vqmmc-supply = <&vccq_sdhi0>; 559 vqmmc-supply = <&vccq_sdhi0>;
545 cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; 560 cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
561 sd-uhs-sdr50;
546 status = "okay"; 562 status = "okay";
547}; 563};
548 564
549&sdhi2 { 565&sdhi2 {
550 pinctrl-0 = <&sdhi2_pins>; 566 pinctrl-0 = <&sdhi2_pins>;
551 pinctrl-names = "default"; 567 pinctrl-1 = <&sdhi2_pins_uhs>;
568 pinctrl-names = "default", "state_uhs";
552 569
553 vmmc-supply = <&vcc_sdhi2>; 570 vmmc-supply = <&vcc_sdhi2>;
554 vqmmc-supply = <&vccq_sdhi2>; 571 vqmmc-supply = <&vccq_sdhi2>;
555 cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; 572 cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
573 sd-uhs-sdr50;
556 status = "okay"; 574 status = "okay";
557}; 575};
558 576
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 283698fc0fea..776a2aed81d2 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -589,6 +589,7 @@
589 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; 589 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
590 dmas = <&dmac1 0xcd>, <&dmac1 0xce>; 590 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
591 dma-names = "tx", "rx"; 591 dma-names = "tx", "rx";
592 max-frequency = <195000000>;
592 power-domains = <&cpg_clocks>; 593 power-domains = <&cpg_clocks>;
593 status = "disabled"; 594 status = "disabled";
594 }; 595 };
@@ -600,6 +601,7 @@
600 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; 601 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
601 dmas = <&dmac1 0xc9>, <&dmac1 0xca>; 602 dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
602 dma-names = "tx", "rx"; 603 dma-names = "tx", "rx";
604 max-frequency = <195000000>;
603 power-domains = <&cpg_clocks>; 605 power-domains = <&cpg_clocks>;
604 status = "disabled"; 606 status = "disabled";
605 }; 607 };
@@ -611,6 +613,7 @@
611 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; 613 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
612 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; 614 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
613 dma-names = "tx", "rx"; 615 dma-names = "tx", "rx";
616 max-frequency = <97500000>;
614 power-domains = <&cpg_clocks>; 617 power-domains = <&cpg_clocks>;
615 status = "disabled"; 618 status = "disabled";
616 }; 619 };
@@ -622,6 +625,7 @@
622 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; 625 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
623 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; 626 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
624 dma-names = "tx", "rx"; 627 dma-names = "tx", "rx";
628 max-frequency = <97500000>;
625 power-domains = <&cpg_clocks>; 629 power-domains = <&cpg_clocks>;
626 status = "disabled"; 630 status = "disabled";
627 }; 631 };
@@ -732,6 +736,20 @@
732 status = "disabled"; 736 status = "disabled";
733 }; 737 };
734 738
739 scif2: serial@e6e56000 {
740 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
741 "renesas,scif";
742 reg = <0 0xe6e56000 0 64>;
743 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,
745 <&scif_clk>;
746 clock-names = "fck", "brg_int", "scif_clk";
747 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
748 dma-names = "tx", "rx";
749 power-domains = <&cpg_clocks>;
750 status = "disabled";
751 };
752
735 hscif0: serial@e62c0000 { 753 hscif0: serial@e62c0000 {
736 compatible = "renesas,hscif-r8a7790", 754 compatible = "renesas,hscif-r8a7790",
737 "renesas,rcar-gen2-hscif", "renesas,hscif"; 755 "renesas,rcar-gen2-hscif", "renesas,hscif";
@@ -968,7 +986,7 @@
968 }; 986 };
969 987
970 can0: can@e6e80000 { 988 can0: can@e6e80000 {
971 compatible = "renesas,can-r8a7790"; 989 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
972 reg = <0 0xe6e80000 0 0x1000>; 990 reg = <0 0xe6e80000 0 0x1000>;
973 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 991 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, 992 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
@@ -979,7 +997,7 @@
979 }; 997 };
980 998
981 can1: can@e6e88000 { 999 can1: can@e6e88000 {
982 compatible = "renesas,can-r8a7790"; 1000 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
983 reg = <0 0xe6e88000 0 0x1000>; 1001 reg = <0 0xe6e88000 0 0x1000>;
984 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1002 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
985 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, 1003 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
@@ -990,7 +1008,7 @@
990 }; 1008 };
991 1009
992 jpu: jpeg-codec@fe980000 { 1010 jpu: jpeg-codec@fe980000 {
993 compatible = "renesas,jpu-r8a7790"; 1011 compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
994 reg = <0 0xfe980000 0 0x10300>; 1012 reg = <0 0xfe980000 0 0x10300>;
995 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1013 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&mstp1_clks R8A7790_CLK_JPU>; 1014 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
@@ -1302,19 +1320,19 @@
1302 mstp3_clks: mstp3_clks@e615013c { 1320 mstp3_clks: mstp3_clks@e615013c {
1303 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1321 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1304 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 1322 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1305 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, 1323 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
1306 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, 1324 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1307 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, 1325 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1308 <&hp_clk>, <&hp_clk>; 1326 <&hp_clk>, <&hp_clk>;
1309 #clock-cells = <1>; 1327 #clock-cells = <1>;
1310 clock-indices = < 1328 clock-indices = <
1311 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 1329 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3
1312 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 1330 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1313 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 1331 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1314 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1 1332 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1315 >; 1333 >;
1316 clock-output-names = 1334 clock-output-names =
1317 "iic2", "tpu0", "mmcif1", "sdhi3", 1335 "iic2", "tpu0", "mmcif1", "scif2", "sdhi3",
1318 "sdhi2", "sdhi1", "sdhi0", "mmcif0", 1336 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1319 "iic0", "pciec", "iic1", "ssusb", "cmt1", 1337 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1320 "usbdmac0", "usbdmac1"; 1338 "usbdmac0", "usbdmac1";
@@ -1499,7 +1517,7 @@
1499 }; 1517 };
1500 1518
1501 xhci: usb@ee000000 { 1519 xhci: usb@ee000000 {
1502 compatible = "renesas,xhci-r8a7790"; 1520 compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
1503 reg = <0 0xee000000 0 0xc00>; 1521 reg = <0 0xee000000 0 0xc00>;
1504 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1522 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1505 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; 1523 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 8010d935300f..6d4a0b6e4df9 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1013,7 +1013,7 @@
1013 }; 1013 };
1014 1014
1015 can0: can@e6e80000 { 1015 can0: can@e6e80000 {
1016 compatible = "renesas,can-r8a7791"; 1016 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
1017 reg = <0 0xe6e80000 0 0x1000>; 1017 reg = <0 0xe6e80000 0 0x1000>;
1018 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1018 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, 1019 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
@@ -1024,7 +1024,7 @@
1024 }; 1024 };
1025 1025
1026 can1: can@e6e88000 { 1026 can1: can@e6e88000 {
1027 compatible = "renesas,can-r8a7791"; 1027 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
1028 reg = <0 0xe6e88000 0 0x1000>; 1028 reg = <0 0xe6e88000 0 0x1000>;
1029 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1029 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1030 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, 1030 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
@@ -1035,7 +1035,7 @@
1035 }; 1035 };
1036 1036
1037 jpu: jpeg-codec@fe980000 { 1037 jpu: jpeg-codec@fe980000 {
1038 compatible = "renesas,jpu-r8a7791"; 1038 compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";
1039 reg = <0 0xfe980000 0 0x10300>; 1039 reg = <0 0xfe980000 0 0x10300>;
1040 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1040 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1041 clocks = <&mstp1_clks R8A7791_CLK_JPU>; 1041 clocks = <&mstp1_clks R8A7791_CLK_JPU>;
@@ -1520,7 +1520,7 @@
1520 }; 1520 };
1521 1521
1522 xhci: usb@ee000000 { 1522 xhci: usb@ee000000 {
1523 compatible = "renesas,xhci-r8a7791"; 1523 compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";
1524 reg = <0 0xee000000 0 0xc00>; 1524 reg = <0 0xee000000 0 0xc00>;
1525 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1525 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1526 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; 1526 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 3cd1c804621f..0ebc3ee34923 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -158,6 +158,78 @@
158 }; 158 };
159 }; 159 };
160 160
161 vcc_sdhi0: regulator@0 {
162 compatible = "regulator-fixed";
163
164 regulator-name = "SDHI0 Vcc";
165 regulator-min-microvolt = <3300000>;
166 regulator-max-microvolt = <3300000>;
167
168 gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
169 enable-active-high;
170 };
171
172 vccq_sdhi0: regulator@1 {
173 compatible = "regulator-gpio";
174
175 regulator-name = "SDHI0 VccQ";
176 regulator-min-microvolt = <1800000>;
177 regulator-max-microvolt = <3300000>;
178
179 gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
180 gpios-states = <1>;
181 states = <3300000 1
182 1800000 0>;
183 };
184
185 vcc_sdhi1: regulator@2 {
186 compatible = "regulator-fixed";
187
188 regulator-name = "SDHI1 Vcc";
189 regulator-min-microvolt = <3300000>;
190 regulator-max-microvolt = <3300000>;
191
192 gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
193 enable-active-high;
194 };
195
196 vccq_sdhi1: regulator@3 {
197 compatible = "regulator-gpio";
198
199 regulator-name = "SDHI1 VccQ";
200 regulator-min-microvolt = <1800000>;
201 regulator-max-microvolt = <3300000>;
202
203 gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
204 gpios-states = <1>;
205 states = <3300000 1
206 1800000 0>;
207 };
208
209 vcc_sdhi2: regulator@4 {
210 compatible = "regulator-fixed";
211
212 regulator-name = "SDHI2 Vcc";
213 regulator-min-microvolt = <3300000>;
214 regulator-max-microvolt = <3300000>;
215
216 gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
217 enable-active-high;
218 };
219
220 vccq_sdhi2: regulator@5 {
221 compatible = "regulator-gpio";
222
223 regulator-name = "SDHI2 VccQ";
224 regulator-min-microvolt = <1800000>;
225 regulator-max-microvolt = <3300000>;
226
227 gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
228 gpios-states = <1>;
229 states = <3300000 1
230 1800000 0>;
231 };
232
161 audio_clock: audio_clock { 233 audio_clock: audio_clock {
162 compatible = "fixed-clock"; 234 compatible = "fixed-clock";
163 #clock-cells = <0>; 235 #clock-cells = <0>;
@@ -273,6 +345,21 @@
273 function = "intc"; 345 function = "intc";
274 }; 346 };
275 347
348 sdhi0_pins: sd0 {
349 renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
350 renesas,function = "sdhi0";
351 };
352
353 sdhi1_pins: sd1 {
354 renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
355 renesas,function = "sdhi1";
356 };
357
358 sdhi2_pins: sd2 {
359 renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
360 renesas,function = "sdhi2";
361 };
362
276 qspi_pins: spi0 { 363 qspi_pins: spi0 {
277 groups = "qspi_ctrl", "qspi_data4"; 364 groups = "qspi_ctrl", "qspi_data4";
278 function = "qspi"; 365 function = "qspi";
@@ -328,6 +415,38 @@
328 status = "okay"; 415 status = "okay";
329}; 416};
330 417
418&sdhi0 {
419 pinctrl-0 = <&sdhi0_pins>;
420 pinctrl-names = "default";
421
422 vmmc-supply = <&vcc_sdhi0>;
423 vqmmc-supply = <&vccq_sdhi0>;
424 cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
425 wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
426 status = "okay";
427};
428
429&sdhi1 {
430 pinctrl-0 = <&sdhi1_pins>;
431 pinctrl-names = "default";
432
433 vmmc-supply = <&vcc_sdhi1>;
434 vqmmc-supply = <&vccq_sdhi1>;
435 cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
436 wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
437 status = "okay";
438};
439
440&sdhi2 {
441 pinctrl-0 = <&sdhi2_pins>;
442 pinctrl-names = "default";
443
444 vmmc-supply = <&vcc_sdhi2>;
445 vqmmc-supply = <&vccq_sdhi2>;
446 cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
447 status = "okay";
448};
449
331&qspi { 450&qspi {
332 pinctrl-0 = <&qspi_pins>; 451 pinctrl-0 = <&qspi_pins>;
333 pinctrl-names = "default"; 452 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 95bbed95b0c1..6186179fd66d 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -507,6 +507,39 @@
507 reg = <0 0xe6060000 0 0x250>; 507 reg = <0 0xe6060000 0 0x250>;
508 }; 508 };
509 509
510 sdhi0: sd@ee100000 {
511 compatible = "renesas,sdhi-r8a7793";
512 reg = <0 0xee100000 0 0x328>;
513 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
515 dmas = <&dmac0 0xcd>, <&dmac0 0xce>;
516 dma-names = "tx", "rx";
517 power-domains = <&cpg_clocks>;
518 status = "disabled";
519 };
520
521 sdhi1: sd@ee140000 {
522 compatible = "renesas,sdhi-r8a7793";
523 reg = <0 0xee140000 0 0x100>;
524 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
526 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>;
527 dma-names = "tx", "rx";
528 power-domains = <&cpg_clocks>;
529 status = "disabled";
530 };
531
532 sdhi2: sd@ee160000 {
533 compatible = "renesas,sdhi-r8a7793";
534 reg = <0 0xee160000 0 0x100>;
535 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
537 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>;
538 dma-names = "tx", "rx";
539 power-domains = <&cpg_clocks>;
540 status = "disabled";
541 };
542
510 scifa0: serial@e6c40000 { 543 scifa0: serial@e6c40000 {
511 compatible = "renesas,scifa-r8a7793", 544 compatible = "renesas,scifa-r8a7793",
512 "renesas,rcar-gen2-scifa", "renesas,scifa"; 545 "renesas,rcar-gen2-scifa", "renesas,scifa";
@@ -806,6 +839,28 @@
806 }; 839 };
807 }; 840 };
808 841
842 can0: can@e6e80000 {
843 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
844 reg = <0 0xe6e80000 0 0x1000>;
845 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
847 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
848 clock-names = "clkp1", "clkp2", "can_clk";
849 power-domains = <&cpg_clocks>;
850 status = "disabled";
851 };
852
853 can1: can@e6e88000 {
854 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
855 reg = <0 0xe6e88000 0 0x1000>;
856 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
858 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
859 clock-names = "clkp1", "clkp2", "can_clk";
860 power-domains = <&cpg_clocks>;
861 status = "disabled";
862 };
863
809 clocks { 864 clocks {
810 #address-cells = <2>; 865 #address-cells = <2>;
811 #size-cells = <2>; 866 #size-cells = <2>;
@@ -839,6 +894,22 @@
839 clock-frequency = <0>; 894 clock-frequency = <0>;
840 }; 895 };
841 896
897 /* External USB clock - can be overridden by the board */
898 usb_extal_clk: usb_extal {
899 compatible = "fixed-clock";
900 #clock-cells = <0>;
901 clock-frequency = <48000000>;
902 };
903
904 /* External CAN clock */
905 can_clk: can {
906 compatible = "fixed-clock";
907 #clock-cells = <0>;
908 /* This value must be overridden by the board. */
909 clock-frequency = <0>;
910 status = "disabled";
911 };
912
842 /* External SCIF clock */ 913 /* External SCIF clock */
843 scif_clk: scif { 914 scif_clk: scif {
844 compatible = "fixed-clock"; 915 compatible = "fixed-clock";
@@ -853,7 +924,7 @@
853 compatible = "renesas,r8a7793-cpg-clocks", 924 compatible = "renesas,r8a7793-cpg-clocks",
854 "renesas,rcar-gen2-cpg-clocks"; 925 "renesas,rcar-gen2-cpg-clocks";
855 reg = <0 0xe6150000 0 0x1000>; 926 reg = <0 0xe6150000 0 0x1000>;
856 clocks = <&extal_clk>; 927 clocks = <&extal_clk &usb_extal_clk>;
857 #clock-cells = <1>; 928 #clock-cells = <1>;
858 clock-output-names = "main", "pll0", "pll1", "pll3", 929 clock-output-names = "main", "pll0", "pll1", "pll3",
859 "lb", "qspi", "sdh", "sd0", "z", 930 "lb", "qspi", "sdh", "sd0", "z",
@@ -1081,6 +1152,7 @@
1081 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; 1152 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1082 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, 1153 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1083 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, 1154 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1155 <&p_clk>, <&p_clk>,
1084 <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>, 1156 <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
1085 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, 1157 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1086 <&hp_clk>, <&hp_clk>; 1158 <&hp_clk>, <&hp_clk>;
@@ -1090,7 +1162,8 @@
1090 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4 1162 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
1091 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2 1163 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
1092 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0 1164 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
1093 R8A7793_CLK_QSPI_MOD R8A7793_CLK_I2C5 1165 R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1
1166 R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5
1094 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4 1167 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
1095 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2 1168 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
1096 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0 1169 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
@@ -1098,8 +1171,9 @@
1098 clock-output-names = 1171 clock-output-names =
1099 "gpio7", "gpio6", "gpio5", "gpio4", 1172 "gpio7", "gpio6", "gpio5", "gpio4",
1100 "gpio3", "gpio2", "gpio1", "gpio0", 1173 "gpio3", "gpio2", "gpio1", "gpio0",
1101 "qspi_mod", "i2c5", "i2c6", "i2c4", 1174 "rcan1", "rcan0", "qspi_mod", "i2c5",
1102 "i2c3", "i2c2", "i2c1", "i2c0"; 1175 "i2c6", "i2c4", "i2c3", "i2c2", "i2c1",
1176 "i2c0";
1103 }; 1177 };
1104 mstp10_clks: mstp10_clks@e6150998 { 1178 mstp10_clks: mstp10_clks@e6150998 {
1105 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; 1179 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 7d7d18766540..b0bce43779f1 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -26,6 +26,8 @@
26 i2c3 = &i2c3; 26 i2c3 = &i2c3;
27 i2c4 = &i2c4; 27 i2c4 = &i2c4;
28 i2c5 = &i2c5; 28 i2c5 = &i2c5;
29 i2c6 = &i2c6;
30 i2c7 = &i2c7;
29 spi0 = &qspi; 31 spi0 = &qspi;
30 vin0 = &vin0; 32 vin0 = &vin0;
31 vin1 = &vin1; 33 vin1 = &vin1;
@@ -629,6 +631,32 @@
629 status = "disabled"; 631 status = "disabled";
630 }; 632 };
631 633
634 i2c6: i2c@e6500000 {
635 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
636 reg = <0 0xe6500000 0 0x425>;
637 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
639 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
640 dma-names = "tx", "rx";
641 power-domains = <&cpg_clocks>;
642 #address-cells = <1>;
643 #size-cells = <0>;
644 status = "disabled";
645 };
646
647 i2c7: i2c@e6510000 {
648 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
649 reg = <0 0xe6510000 0 0x425>;
650 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
652 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
653 dma-names = "tx", "rx";
654 power-domains = <&cpg_clocks>;
655 #address-cells = <1>;
656 #size-cells = <0>;
657 status = "disabled";
658 };
659
632 mmcif0: mmc@ee200000 { 660 mmcif0: mmc@ee200000 {
633 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; 661 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
634 reg = <0 0xee200000 0 0x80>; 662 reg = <0 0xee200000 0 0x80>;
@@ -830,6 +858,28 @@
830 }; 858 };
831 }; 859 };
832 860
861 can0: can@e6e80000 {
862 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
863 reg = <0 0xe6e80000 0 0x1000>;
864 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
866 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
867 clock-names = "clkp1", "clkp2", "can_clk";
868 power-domains = <&cpg_clocks>;
869 status = "disabled";
870 };
871
872 can1: can@e6e88000 {
873 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
874 reg = <0 0xe6e88000 0 0x1000>;
875 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
877 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
878 clock-names = "clkp1", "clkp2", "can_clk";
879 power-domains = <&cpg_clocks>;
880 status = "disabled";
881 };
882
833 clocks { 883 clocks {
834 #address-cells = <2>; 884 #address-cells = <2>;
835 #size-cells = <2>; 885 #size-cells = <2>;
@@ -843,6 +893,22 @@
843 clock-frequency = <0>; 893 clock-frequency = <0>;
844 }; 894 };
845 895
896 /* External USB clock - can be overridden by the board */
897 usb_extal_clk: usb_extal {
898 compatible = "fixed-clock";
899 #clock-cells = <0>;
900 clock-frequency = <48000000>;
901 };
902
903 /* External CAN clock */
904 can_clk: can {
905 compatible = "fixed-clock";
906 #clock-cells = <0>;
907 /* This value must be overridden by the board. */
908 clock-frequency = <0>;
909 status = "disabled";
910 };
911
846 /* External SCIF clock */ 912 /* External SCIF clock */
847 scif_clk: scif { 913 scif_clk: scif {
848 compatible = "fixed-clock"; 914 compatible = "fixed-clock";
@@ -857,10 +923,11 @@
857 compatible = "renesas,r8a7794-cpg-clocks", 923 compatible = "renesas,r8a7794-cpg-clocks",
858 "renesas,rcar-gen2-cpg-clocks"; 924 "renesas,rcar-gen2-cpg-clocks";
859 reg = <0 0xe6150000 0 0x1000>; 925 reg = <0 0xe6150000 0 0x1000>;
860 clocks = <&extal_clk>; 926 clocks = <&extal_clk &usb_extal_clk>;
861 #clock-cells = <1>; 927 #clock-cells = <1>;
862 clock-output-names = "main", "pll0", "pll1", "pll3", 928 clock-output-names = "main", "pll0", "pll1", "pll3",
863 "lb", "qspi", "sdh", "sd0", "z"; 929 "lb", "qspi", "sdh", "sd0", "z",
930 "rcan";
864 #power-domain-cells = <0>; 931 #power-domain-cells = <0>;
865 }; 932 };
866 /* Variable factor clocks */ 933 /* Variable factor clocks */
@@ -1060,16 +1127,19 @@
1060 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 1127 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1061 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 1128 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1062 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, 1129 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
1063 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; 1130 <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
1131 <&hp_clk>, <&hp_clk>;
1064 #clock-cells = <1>; 1132 #clock-cells = <1>;
1065 clock-indices = < 1133 clock-indices = <
1066 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 1134 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
1067 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1 1135 R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
1136 R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
1068 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 1137 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
1069 >; 1138 >;
1070 clock-output-names = 1139 clock-output-names =
1071 "sdhi2", "sdhi1", "sdhi0", 1140 "sdhi2", "sdhi1", "sdhi0",
1072 "mmcif0", "cmt1", "usbdmac0", "usbdmac1"; 1141 "mmcif0", "i2c6", "i2c7",
1142 "cmt1", "usbdmac0", "usbdmac1";
1073 }; 1143 };
1074 mstp4_clks: mstp4_clks@e6150140 { 1144 mstp4_clks: mstp4_clks@e6150140 {
1075 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 1145 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1115,20 +1185,22 @@
1115 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 1185 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1116 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; 1186 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1117 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, 1187 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1118 <&cp_clk>, <&cp_clk>, <&cp_clk>, 1188 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
1119 <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>, 1189 <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
1120 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; 1190 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1191 <&hp_clk>, <&hp_clk>;
1121 #clock-cells = <1>; 1192 #clock-cells = <1>;
1122 clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5 1193 clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1123 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3 1194 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1124 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1 1195 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1125 R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD 1196 R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
1197 R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
1126 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4 1198 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1127 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 1199 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1128 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>; 1200 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
1129 clock-output-names = 1201 clock-output-names =
1130 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", 1202 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1131 "gpio1", "gpio0", "qspi_mod", 1203 "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
1132 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; 1204 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
1133 }; 1205 };
1134 mstp11_clks: mstp11_clks@e615099c { 1206 mstp11_clks: mstp11_clks@e615099c {
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
index e40a2f23b6cd..c2d8a080e392 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -149,6 +149,13 @@
149 label = "SW1"; 149 label = "SW1";
150 wakeup-source; 150 wakeup-source;
151 }; 151 };
152
153 wakeup-key {
154 gpios = <&pfc 159 GPIO_ACTIVE_LOW>;
155 linux,code = <KEY_WAKEUP>;
156 label = "NMI";
157 wakeup-source;
158 };
152 }; 159 };
153 160
154 sound { 161 sound {
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 639ea2d76970..c4f434cdec60 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -43,7 +43,7 @@
43 timer@f0000600 { 43 timer@f0000600 {
44 compatible = "arm,cortex-a9-twd-timer"; 44 compatible = "arm,cortex-a9-twd-timer";
45 reg = <0xf0000600 0x20>; 45 reg = <0xf0000600 0x20>;
46 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 46 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
47 clocks = <&twd_clk>; 47 clocks = <&twd_clk>;
48 }; 48 };
49 49
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 7b1ad8922eec..fa5e8da809f2 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -66,6 +66,7 @@
66#define R8A7790_CLK_IIC2 0 66#define R8A7790_CLK_IIC2 0
67#define R8A7790_CLK_TPU0 4 67#define R8A7790_CLK_TPU0 4
68#define R8A7790_CLK_MMCIF1 5 68#define R8A7790_CLK_MMCIF1 5
69#define R8A7790_CLK_SCIF2 10
69#define R8A7790_CLK_SDHI3 11 70#define R8A7790_CLK_SDHI3 11
70#define R8A7790_CLK_SDHI2 12 71#define R8A7790_CLK_SDHI2 12
71#define R8A7790_CLK_SDHI1 13 72#define R8A7790_CLK_SDHI1 13
diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
index f843de6bf377..4d3ecd626c1f 100644
--- a/include/dt-bindings/clock/r8a7794-clock.h
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -21,6 +21,7 @@
21#define R8A7794_CLK_SDH 6 21#define R8A7794_CLK_SDH 6
22#define R8A7794_CLK_SD0 7 22#define R8A7794_CLK_SD0 7
23#define R8A7794_CLK_Z 8 23#define R8A7794_CLK_Z 8
24#define R8A7794_CLK_RCAN 9
24 25
25/* MSTP0 */ 26/* MSTP0 */
26#define R8A7794_CLK_MSIOF0 0 27#define R8A7794_CLK_MSIOF0 0
@@ -56,6 +57,8 @@
56#define R8A7794_CLK_SDHI1 12 57#define R8A7794_CLK_SDHI1 12
57#define R8A7794_CLK_SDHI0 14 58#define R8A7794_CLK_SDHI0 14
58#define R8A7794_CLK_MMCIF0 15 59#define R8A7794_CLK_MMCIF0 15
60#define R8A7794_CLK_IIC0 18
61#define R8A7794_CLK_IIC1 23
59#define R8A7794_CLK_CMT1 29 62#define R8A7794_CLK_CMT1 29
60#define R8A7794_CLK_USBDMAC0 30 63#define R8A7794_CLK_USBDMAC0 30
61#define R8A7794_CLK_USBDMAC1 31 64#define R8A7794_CLK_USBDMAC1 31
@@ -95,6 +98,8 @@
95#define R8A7794_CLK_GPIO2 10 98#define R8A7794_CLK_GPIO2 10
96#define R8A7794_CLK_GPIO1 11 99#define R8A7794_CLK_GPIO1 11
97#define R8A7794_CLK_GPIO0 12 100#define R8A7794_CLK_GPIO0 12
101#define R8A7794_CLK_RCAN1 15
102#define R8A7794_CLK_RCAN0 16
98#define R8A7794_CLK_QSPI_MOD 17 103#define R8A7794_CLK_QSPI_MOD 17
99#define R8A7794_CLK_I2C5 25 104#define R8A7794_CLK_I2C5 25
100#define R8A7794_CLK_I2C4 27 105#define R8A7794_CLK_I2C4 27
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 05:01:59 -0400