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author | Linus Torvalds <torvalds@linux-foundation.org> | 2015-08-12 14:13:54 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2015-08-12 14:13:54 -0400 |
commit | 04da002d98852b38083beb9725967609945a8747 (patch) | |
tree | d5a755b46ecf39c7efe2a00d075ab27c5e030a70 | |
parent | cec45d901ef4a8529b319436fdaf391955a39c7a (diff) | |
parent | e037239e5e7b61007763984aa35a8329596d8c88 (diff) |
Merge branch 'drm-fixes-4.2' of git://people.freedesktop.org/~agd5f/linux
Pull amd drm fixes from Alex Deucher:
"Dave is on vacation at the moment, so please pull these radeon and
amdgpu fixes directly.
Just a few minor things for 4.2:
- add a new radeon pci id
- fix a power management regression in amdgpu
- fix HEVC command buffer validation in amdgpu"
* 'drm-fixes-4.2' of git://people.freedesktop.org/~agd5f/linux:
drm/radeon: add new OLAND pci id
Revert "drm/amdgpu: Configure doorbell to maximum slots"
drm/amdgpu: add context buffer size check for HEVC
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 17 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 | ||||
-rw-r--r-- | include/drm/drm_pciids.h | 1 |
3 files changed, 16 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 2f7a5efa21c2..f5c22556ec2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | |||
@@ -374,7 +374,7 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) | |||
374 | unsigned height_in_mb = ALIGN(height / 16, 2); | 374 | unsigned height_in_mb = ALIGN(height / 16, 2); |
375 | unsigned fs_in_mb = width_in_mb * height_in_mb; | 375 | unsigned fs_in_mb = width_in_mb * height_in_mb; |
376 | 376 | ||
377 | unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; | 377 | unsigned image_size, tmp, min_dpb_size, num_dpb_buffer, min_ctx_size; |
378 | 378 | ||
379 | image_size = width * height; | 379 | image_size = width * height; |
380 | image_size += image_size / 2; | 380 | image_size += image_size / 2; |
@@ -466,6 +466,8 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) | |||
466 | 466 | ||
467 | num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; | 467 | num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; |
468 | min_dpb_size = image_size * num_dpb_buffer; | 468 | min_dpb_size = image_size * num_dpb_buffer; |
469 | min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) | ||
470 | * 16 * num_dpb_buffer + 52 * 1024; | ||
469 | break; | 471 | break; |
470 | 472 | ||
471 | default: | 473 | default: |
@@ -486,6 +488,7 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) | |||
486 | 488 | ||
487 | buf_sizes[0x1] = dpb_size; | 489 | buf_sizes[0x1] = dpb_size; |
488 | buf_sizes[0x2] = image_size; | 490 | buf_sizes[0x2] = image_size; |
491 | buf_sizes[0x4] = min_ctx_size; | ||
489 | return 0; | 492 | return 0; |
490 | } | 493 | } |
491 | 494 | ||
@@ -628,6 +631,13 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) | |||
628 | return -EINVAL; | 631 | return -EINVAL; |
629 | } | 632 | } |
630 | 633 | ||
634 | } else if (cmd == 0x206) { | ||
635 | if ((end - start) < ctx->buf_sizes[4]) { | ||
636 | DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, | ||
637 | (unsigned)(end - start), | ||
638 | ctx->buf_sizes[4]); | ||
639 | return -EINVAL; | ||
640 | } | ||
631 | } else if ((cmd != 0x100) && (cmd != 0x204)) { | 641 | } else if ((cmd != 0x100) && (cmd != 0x204)) { |
632 | DRM_ERROR("invalid UVD command %X!\n", cmd); | 642 | DRM_ERROR("invalid UVD command %X!\n", cmd); |
633 | return -EINVAL; | 643 | return -EINVAL; |
@@ -755,9 +765,10 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) | |||
755 | struct amdgpu_uvd_cs_ctx ctx = {}; | 765 | struct amdgpu_uvd_cs_ctx ctx = {}; |
756 | unsigned buf_sizes[] = { | 766 | unsigned buf_sizes[] = { |
757 | [0x00000000] = 2048, | 767 | [0x00000000] = 2048, |
758 | [0x00000001] = 32 * 1024 * 1024, | 768 | [0x00000001] = 0xFFFFFFFF, |
759 | [0x00000002] = 2048 * 1152 * 3, | 769 | [0x00000002] = 0xFFFFFFFF, |
760 | [0x00000003] = 2048, | 770 | [0x00000003] = 2048, |
771 | [0x00000004] = 0xFFFFFFFF, | ||
761 | }; | 772 | }; |
762 | struct amdgpu_ib *ib = &parser->ibs[ib_idx]; | 773 | struct amdgpu_ib *ib = &parser->ibs[ib_idx]; |
763 | int r; | 774 | int r; |
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index f5a42ab1f65c..20e2cfd521d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | |||
@@ -3135,7 +3135,7 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) | |||
3135 | WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, | 3135 | WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, |
3136 | AMDGPU_DOORBELL_KIQ << 2); | 3136 | AMDGPU_DOORBELL_KIQ << 2); |
3137 | WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, | 3137 | WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, |
3138 | 0x7FFFF << 2); | 3138 | AMDGPU_DOORBELL_MEC_RING7 << 2); |
3139 | } | 3139 | } |
3140 | tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); | 3140 | tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); |
3141 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, | 3141 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, |
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h index 45c39a37f924..8bc073d297db 100644 --- a/include/drm/drm_pciids.h +++ b/include/drm/drm_pciids.h | |||
@@ -172,6 +172,7 @@ | |||
172 | {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ | 172 | {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ |
173 | {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ | 173 | {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ |
174 | {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ | 174 | {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ |
175 | {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
175 | {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 176 | {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
176 | {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 177 | {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
177 | {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 178 | {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |