drm/amdgpu/uvd: reduce IB parsing overhead on UVD5+ (v2)

UVD 5 and newer do not have the same placement limitations
as older chips, so skip the first pass since it's just
overhead on chips where we don't have to force placement.

v2: fix inverted logic

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 10 insertions, 5 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 330c4749b32c..a81dfaeeb8c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -712,8 +712,10 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
         int r;
 
         mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
-        if (mapping == NULL)
+        if (mapping == NULL) {
+                DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
                 return -EINVAL;
+        }
 
         start = amdgpu_bo_gpu_offset(bo);
 
@@ -897,10 +899,13 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
         ctx.buf_sizes = buf_sizes;
         ctx.ib_idx = ib_idx;
 
-        /* first round, make sure the buffers are actually in the UVD segment */
-        r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
-        if (r)
-                return r;
+        /* first round only required on chips without UVD 64 bit address support */
+        if (!parser->adev->uvd.address_64_bit) {
+                /* first round, make sure the buffers are actually in the UVD segment */
+                r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
+                if (r)
+                        return r;
+        }
 
         /* second round, patch buffer addresses into the command stream */
         r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);