Merge tag 'v4.16-next-soc' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/drivers

Pull "ARM: mediatek: updates for soc drivers for v4.16-next" from Matthias Brugger:

scpsy:
- mt2712: update power domains to reflect design changes in the SoC
- fix initialisation of power subdomains
- add support for mt7623a SoC
- use defines for mt2701 bus protection mask

* tag 'v4.16-next-soc' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  soc: mediatek: update power domain data of MT2712
  dt-bindings: soc: update MT2712 power dt-bindings
  soc: mediatek: fix the mistaken pointer accessed when subdomains are added
  soc: mediatek: add SCPSYS power domain driver for MediaTek MT7623A SoC
  soc: mediatek: avoid hardcoded value with bus_prot_mask
  dt-bindings: soc: add header files required for MT7623A SCPSYS dt-binding
  dt-bindings: soc: add SCPSYS binding for MT7623 and MT7623A SoC

5 files changed, 120 insertions, 6 deletions

diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index 76bf45b893fa..d6fe16f094af 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -21,6 +21,8 @@ Required properties:
         - "mediatek,mt2712-scpsys"
         - "mediatek,mt6797-scpsys"
         - "mediatek,mt7622-scpsys"
+        - "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC
+        - "mediatek,mt7623a-scpsys": For MT7623A SoC
         - "mediatek,mt8173-scpsys"
 - #power-domain-cells: Must be 1
 - reg: Address range of the SCPSYS unit
@@ -28,10 +30,11 @@ Required properties:
 - clock, clock-names: clocks according to the common clock binding.
                       These are clocks which hardware needs to be
                       enabled before enabling certain power domains.
-        Required clocks for MT2701: "mm", "mfg", "ethif"
+        Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
         Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
         Required clocks for MT6797: "mm", "mfg", "vdec"
         Required clocks for MT7622: "hif_sel"
+        Required clocks for MT7622A: "ethif"
         Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
 
 Optional properties:
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 435ce5ec648a..d762a46d434f 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -24,6 +24,7 @@
 #include <dt-bindings/power/mt2712-power.h>
 #include <dt-bindings/power/mt6797-power.h>
 #include <dt-bindings/power/mt7622-power.h>
+#include <dt-bindings/power/mt7623a-power.h>
 #include <dt-bindings/power/mt8173-power.h>
 
 #define SPM_VDE_PWR_CON                 0x0210
@@ -518,7 +519,8 @@ static const struct scp_domain_data scp_domain_data_mt2701[] = {
                 .name = "conn",
                 .sta_mask = PWR_STATUS_CONN,
                 .ctl_offs = SPM_CONN_PWR_CON,
-                .bus_prot_mask = 0x0104,
+                .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
+                                 MT2701_TOP_AXI_PROT_EN_CONN_S,
                 .clk_id = {CLK_NONE},
                 .active_wakeup = true,
         },
@@ -528,7 +530,7 @@ static const struct scp_domain_data scp_domain_data_mt2701[] = {
                 .ctl_offs = SPM_DIS_PWR_CON,
                 .sram_pdn_bits = GENMASK(11, 8),
                 .clk_id = {CLK_MM},
-                .bus_prot_mask = 0x0002,
+                .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
                 .active_wakeup = true,
         },
         [MT2701_POWER_DOMAIN_MFG] = {
@@ -664,12 +666,48 @@ static const struct scp_domain_data scp_domain_data_mt2712[] = {
                 .name = "mfg",
                 .sta_mask = PWR_STATUS_MFG,
                 .ctl_offs = SPM_MFG_PWR_CON,
-                .sram_pdn_bits = GENMASK(11, 8),
-                .sram_pdn_ack_bits = GENMASK(19, 16),
+                .sram_pdn_bits = GENMASK(8, 8),
+                .sram_pdn_ack_bits = GENMASK(16, 16),
                 .clk_id = {CLK_MFG},
                 .bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
                 .active_wakeup = true,
         },
+        [MT2712_POWER_DOMAIN_MFG_SC1] = {
+                .name = "mfg_sc1",
+                .sta_mask = BIT(22),
+                .ctl_offs = 0x02c0,
+                .sram_pdn_bits = GENMASK(8, 8),
+                .sram_pdn_ack_bits = GENMASK(16, 16),
+                .clk_id = {CLK_NONE},
+                .active_wakeup = true,
+        },
+        [MT2712_POWER_DOMAIN_MFG_SC2] = {
+                .name = "mfg_sc2",
+                .sta_mask = BIT(23),
+                .ctl_offs = 0x02c4,
+                .sram_pdn_bits = GENMASK(8, 8),
+                .sram_pdn_ack_bits = GENMASK(16, 16),
+                .clk_id = {CLK_NONE},
+                .active_wakeup = true,
+        },
+        [MT2712_POWER_DOMAIN_MFG_SC3] = {
+                .name = "mfg_sc3",
+                .sta_mask = BIT(30),
+                .ctl_offs = 0x01f8,
+                .sram_pdn_bits = GENMASK(8, 8),
+                .sram_pdn_ack_bits = GENMASK(16, 16),
+                .clk_id = {CLK_NONE},
+                .active_wakeup = true,
+        },
+};
+
+static const struct scp_subdomain scp_subdomain_mt2712[] = {
+        {MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_VDEC},
+        {MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_VENC},
+        {MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_ISP},
+        {MT2712_POWER_DOMAIN_MFG, MT2712_POWER_DOMAIN_MFG_SC1},
+        {MT2712_POWER_DOMAIN_MFG_SC1, MT2712_POWER_DOMAIN_MFG_SC2},
+        {MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3},
 };
 
 /*
@@ -794,6 +832,47 @@ static const struct scp_domain_data scp_domain_data_mt7622[] = {
 };
 
 /*
+ * MT7623A power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt7623a[] = {
+        [MT7623A_POWER_DOMAIN_CONN] = {
+                .name = "conn",
+                .sta_mask = PWR_STATUS_CONN,
+                .ctl_offs = SPM_CONN_PWR_CON,
+                .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
+                                 MT2701_TOP_AXI_PROT_EN_CONN_S,
+                .clk_id = {CLK_NONE},
+                .active_wakeup = true,
+        },
+        [MT7623A_POWER_DOMAIN_ETH] = {
+                .name = "eth",
+                .sta_mask = PWR_STATUS_ETH,
+                .ctl_offs = SPM_ETH_PWR_CON,
+                .sram_pdn_bits = GENMASK(11, 8),
+                .sram_pdn_ack_bits = GENMASK(15, 12),
+                .clk_id = {CLK_ETHIF},
+                .active_wakeup = true,
+        },
+        [MT7623A_POWER_DOMAIN_HIF] = {
+                .name = "hif",
+                .sta_mask = PWR_STATUS_HIF,
+                .ctl_offs = SPM_HIF_PWR_CON,
+                .sram_pdn_bits = GENMASK(11, 8),
+                .sram_pdn_ack_bits = GENMASK(15, 12),
+                .clk_id = {CLK_ETHIF},
+                .active_wakeup = true,
+        },
+        [MT7623A_POWER_DOMAIN_IFR_MSC] = {
+                .name = "ifr_msc",
+                .sta_mask = PWR_STATUS_IFR_MSC,
+                .ctl_offs = SPM_IFR_MSC_PWR_CON,
+                .clk_id = {CLK_NONE},
+                .active_wakeup = true,
+        },
+};
+
+/*
  * MT8173 power domain support
  */
 
@@ -905,6 +984,8 @@ static const struct scp_soc_data mt2701_data = {
 static const struct scp_soc_data mt2712_data = {
         .domains = scp_domain_data_mt2712,
         .num_domains = ARRAY_SIZE(scp_domain_data_mt2712),
+        .subdomains = scp_subdomain_mt2712,
+        .num_subdomains = ARRAY_SIZE(scp_subdomain_mt2712),
         .regs = {
                 .pwr_sta_offs = SPM_PWR_STATUS,
                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
@@ -934,6 +1015,16 @@ static const struct scp_soc_data mt7622_data = {
         .bus_prot_reg_update = true,
 };
 
+static const struct scp_soc_data mt7623a_data = {
+        .domains = scp_domain_data_mt7623a,
+        .num_domains = ARRAY_SIZE(scp_domain_data_mt7623a),
+        .regs = {
+                .pwr_sta_offs = SPM_PWR_STATUS,
+                .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+        },
+        .bus_prot_reg_update = true,
+};
+
 static const struct scp_soc_data mt8173_data = {
         .domains = scp_domain_data_mt8173,
         .num_domains = ARRAY_SIZE(scp_domain_data_mt8173),
@@ -964,6 +1055,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = {
                 .compatible = "mediatek,mt7622-scpsys",
                 .data = &mt7622_data,
         }, {
+                .compatible = "mediatek,mt7623a-scpsys",
+                .data = &mt7623a_data,
+        }, {
                 .compatible = "mediatek,mt8173-scpsys",
                 .data = &mt8173_data,
         }, {
@@ -992,7 +1086,7 @@ static int scpsys_probe(struct platform_device *pdev)
 
         pd_data = &scp->pd_data;
 
-        for (i = 0, sd = soc->subdomains ; i < soc->num_subdomains ; i++) {
+        for (i = 0, sd = soc->subdomains; i < soc->num_subdomains; i++, sd++) {
                 ret = pm_genpd_add_subdomain(pd_data->domains[sd->origin],
                                              pd_data->domains[sd->subdomain]);
                 if (ret && IS_ENABLED(CONFIG_PM))
diff --git a/include/dt-bindings/power/mt2712-power.h b/include/dt-bindings/power/mt2712-power.h
index 92b46d772fae..2c147817efc2 100644
--- a/include/dt-bindings/power/mt2712-power.h
+++ b/include/dt-bindings/power/mt2712-power.h
@@ -22,5 +22,8 @@
 #define MT2712_POWER_DOMAIN_USB         5
 #define MT2712_POWER_DOMAIN_USB2        6
 #define MT2712_POWER_DOMAIN_MFG         7
+#define MT2712_POWER_DOMAIN_MFG_SC1     8
+#define MT2712_POWER_DOMAIN_MFG_SC2     9
+#define MT2712_POWER_DOMAIN_MFG_SC3     10
 
 #endif /* _DT_BINDINGS_POWER_MT2712_POWER_H */
diff --git a/include/dt-bindings/power/mt7623a-power.h b/include/dt-bindings/power/mt7623a-power.h
new file mode 100644
index 000000000000..2544822aa76b
--- /dev/null
+++ b/include/dt-bindings/power/mt7623a-power.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _DT_BINDINGS_POWER_MT7623A_POWER_H
+#define _DT_BINDINGS_POWER_MT7623A_POWER_H
+
+#define MT7623A_POWER_DOMAIN_CONN       0
+#define MT7623A_POWER_DOMAIN_ETH        1
+#define MT7623A_POWER_DOMAIN_HIF        2
+#define MT7623A_POWER_DOMAIN_IFR_MSC    3
+
+#endif /* _DT_BINDINGS_POWER_MT7623A_POWER_H */
diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
index b0a507d356ef..fd25f0148566 100644
--- a/include/linux/soc/mediatek/infracfg.h
+++ b/include/linux/soc/mediatek/infracfg.h
@@ -21,6 +21,10 @@
 #define MT8173_TOP_AXI_PROT_EN_MFG_M1           BIT(22)
 #define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT    BIT(23)
 
+#define MT2701_TOP_AXI_PROT_EN_MM_M0            BIT(1)
+#define MT2701_TOP_AXI_PROT_EN_CONN_M           BIT(2)
+#define MT2701_TOP_AXI_PROT_EN_CONN_S           BIT(8)
+
 #define MT7622_TOP_AXI_PROT_EN_ETHSYS           (BIT(3) | BIT(17))
 #define MT7622_TOP_AXI_PROT_EN_HIF0             (BIT(24) | BIT(25))
 #define MT7622_TOP_AXI_PROT_EN_HIF1             (BIT(26) | BIT(27) | \