diff options
| author | Rob Clark <robdclark@gmail.com> | 2015-01-27 09:05:59 -0500 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2015-04-01 19:29:33 -0400 |
| commit | 034c5150ae8777265f5beae257f8e7f2721ebccc (patch) | |
| tree | 9905aa2a6c72e5777f4eb39b4b78b1d20412a96d | |
| parent | 072f1f9168ed67d6ddc94bb76b1dfc04795062b4 (diff) | |
drm/msm/hdmi: add 74.176MHz and 154.0MHz pix clks
Signed-off-by: Rob Clark <robdclark@gmail.com>
| -rw-r--r-- | drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c index eeed006eed13..6997ec636c6d 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | |||
| @@ -53,6 +53,23 @@ struct pll_rate { | |||
| 53 | 53 | ||
| 54 | /* NOTE: keep sorted highest freq to lowest: */ | 54 | /* NOTE: keep sorted highest freq to lowest: */ |
| 55 | static const struct pll_rate freqtbl[] = { | 55 | static const struct pll_rate freqtbl[] = { |
| 56 | { 154000000, { | ||
| 57 | { 0x08, REG_HDMI_8960_PHY_PLL_REFCLK_CFG }, | ||
| 58 | { 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 }, | ||
| 59 | { 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 }, | ||
| 60 | { 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 }, | ||
| 61 | { 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 }, | ||
| 62 | { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 }, | ||
| 63 | { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 }, | ||
| 64 | { 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 }, | ||
| 65 | { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 }, | ||
| 66 | { 0x0d, REG_HDMI_8960_PHY_PLL_SDM_CFG0 }, | ||
| 67 | { 0x4d, REG_HDMI_8960_PHY_PLL_SDM_CFG1 }, | ||
| 68 | { 0x5e, REG_HDMI_8960_PHY_PLL_SDM_CFG2 }, | ||
| 69 | { 0x42, REG_HDMI_8960_PHY_PLL_SDM_CFG3 }, | ||
| 70 | { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 }, | ||
| 71 | { 0, 0 } } | ||
| 72 | }, | ||
| 56 | /* 1080p60/1080p50 case */ | 73 | /* 1080p60/1080p50 case */ |
| 57 | { 148500000, { | 74 | { 148500000, { |
| 58 | { 0x02, REG_HDMI_8960_PHY_PLL_REFCLK_CFG }, | 75 | { 0x02, REG_HDMI_8960_PHY_PLL_REFCLK_CFG }, |
| @@ -112,6 +129,23 @@ static const struct pll_rate freqtbl[] = { | |||
| 112 | { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 }, | 129 | { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 }, |
| 113 | { 0, 0 } } | 130 | { 0, 0 } } |
| 114 | }, | 131 | }, |
| 132 | { 74176000, { | ||
| 133 | { 0x18, REG_HDMI_8960_PHY_PLL_REFCLK_CFG }, | ||
| 134 | { 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 }, | ||
| 135 | { 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 }, | ||
| 136 | { 0xe5, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 }, | ||
| 137 | { 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 }, | ||
| 138 | { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 }, | ||
| 139 | { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 }, | ||
| 140 | { 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 }, | ||
| 141 | { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 }, | ||
| 142 | { 0x0c, REG_HDMI_8960_PHY_PLL_SDM_CFG0 }, | ||
| 143 | { 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG1 }, | ||
| 144 | { 0x7d, REG_HDMI_8960_PHY_PLL_SDM_CFG2 }, | ||
| 145 | { 0xbc, REG_HDMI_8960_PHY_PLL_SDM_CFG3 }, | ||
| 146 | { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 }, | ||
| 147 | { 0, 0 } } | ||
| 148 | }, | ||
| 115 | { 65000000, { | 149 | { 65000000, { |
| 116 | { 0x18, REG_HDMI_8960_PHY_PLL_REFCLK_CFG }, | 150 | { 0x18, REG_HDMI_8960_PHY_PLL_REFCLK_CFG }, |
| 117 | { 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 }, | 151 | { 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 }, |