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authorGajanan Bhat <gajanan.bhat@intel.com>2014-08-07 07:33:30 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-08-08 11:44:00 -0400
commit01e184cc85d4516cab0ecea7c2c43a2dd3ad432b (patch)
tree6ab7b96daf14df5c93fb7452b9a22b1ab1a9d536
parenta398e9c79eea74ba2f3f24ac08902661682f008c (diff)
drm/i915: Add sprite watermark programming for VLV and CHV
Program DDL register as part of sprite watermark programming for CHV and VLV. v2: Rename DRAIN_LATENCY_MAX by DRAIN_LATENCY_MASK v3: Addressed review comments by Ville - Changed Sprite DDL definitions to more generic to avoid multiple if-else - Changed bit masking to customary form - Changed to bitwise shorthand operator for sprite_dl assignment Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h9
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c33
2 files changed, 36 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d0cff5630569..7a6cc69cdc2b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4000,12 +4000,9 @@ enum punit_power_well {
4000#define DDL_CURSOR_PRECISION_64 (1<<31) 4000#define DDL_CURSOR_PRECISION_64 (1<<31)
4001#define DDL_CURSOR_PRECISION_32 (0<<31) 4001#define DDL_CURSOR_PRECISION_32 (0<<31)
4002#define DDL_CURSOR_SHIFT 24 4002#define DDL_CURSOR_SHIFT 24
4003#define DDL_SPRITE1_PRECISION_64 (1<<23) 4003#define DDL_SPRITE_PRECISION_64(sprite) (1<<(15+8*(sprite)))
4004#define DDL_SPRITE1_PRECISION_32 (0<<23) 4004#define DDL_SPRITE_PRECISION_32(sprite) (0<<(15+8*(sprite)))
4005#define DDL_SPRITE1_SHIFT 16 4005#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
4006#define DDL_SPRITE0_PRECISION_64 (1<<15)
4007#define DDL_SPRITE0_PRECISION_32 (0<<15)
4008#define DDL_SPRITE0_SHIFT 8
4009#define DDL_PLANE_PRECISION_64 (1<<7) 4006#define DDL_PLANE_PRECISION_64 (1<<7)
4010#define DDL_PLANE_PRECISION_32 (0<<7) 4007#define DDL_PLANE_PRECISION_32 (0<<7)
4011#define DDL_PLANE_SHIFT 0 4008#define DDL_PLANE_SHIFT 0
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 19bd7212f4a2..41de760bf1d4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1494,6 +1494,37 @@ static void cherryview_update_wm(struct drm_crtc *crtc)
1494 intel_set_memory_cxsr(dev_priv, true); 1494 intel_set_memory_cxsr(dev_priv, true);
1495} 1495}
1496 1496
1497static void valleyview_update_sprite_wm(struct drm_plane *plane,
1498 struct drm_crtc *crtc,
1499 uint32_t sprite_width,
1500 uint32_t sprite_height,
1501 int pixel_size,
1502 bool enabled, bool scaled)
1503{
1504 struct drm_device *dev = crtc->dev;
1505 struct drm_i915_private *dev_priv = dev->dev_private;
1506 int pipe = to_intel_plane(plane)->pipe;
1507 int sprite = to_intel_plane(plane)->plane;
1508 int drain_latency;
1509 int plane_prec;
1510 int sprite_dl;
1511 int prec_mult;
1512
1513 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
1514 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1515
1516 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1517 &drain_latency)) {
1518 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1519 DDL_SPRITE_PRECISION_64(sprite) :
1520 DDL_SPRITE_PRECISION_32(sprite);
1521 sprite_dl |= plane_prec |
1522 (drain_latency << DDL_SPRITE_SHIFT(sprite));
1523 }
1524
1525 I915_WRITE(VLV_DDL(pipe), sprite_dl);
1526}
1527
1497static void g4x_update_wm(struct drm_crtc *crtc) 1528static void g4x_update_wm(struct drm_crtc *crtc)
1498{ 1529{
1499 struct drm_device *dev = crtc->dev; 1530 struct drm_device *dev = crtc->dev;
@@ -7225,10 +7256,12 @@ void intel_init_pm(struct drm_device *dev)
7225 dev_priv->display.init_clock_gating = gen8_init_clock_gating; 7256 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
7226 } else if (IS_CHERRYVIEW(dev)) { 7257 } else if (IS_CHERRYVIEW(dev)) {
7227 dev_priv->display.update_wm = cherryview_update_wm; 7258 dev_priv->display.update_wm = cherryview_update_wm;
7259 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7228 dev_priv->display.init_clock_gating = 7260 dev_priv->display.init_clock_gating =
7229 cherryview_init_clock_gating; 7261 cherryview_init_clock_gating;
7230 } else if (IS_VALLEYVIEW(dev)) { 7262 } else if (IS_VALLEYVIEW(dev)) {
7231 dev_priv->display.update_wm = valleyview_update_wm; 7263 dev_priv->display.update_wm = valleyview_update_wm;
7264 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
7232 dev_priv->display.init_clock_gating = 7265 dev_priv->display.init_clock_gating =
7233 valleyview_init_clock_gating; 7266 valleyview_init_clock_gating;
7234 } else if (IS_PINEVIEW(dev)) { 7267 } else if (IS_PINEVIEW(dev)) {