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authorAlex Deucher <alexander.deucher@amd.com>2017-03-23 02:06:04 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-03-29 23:54:12 -0400
commit015c23600a4dc9844c4a6195a343604bcc88ba01 (patch)
tree9d9c4df0ad45ff3a9149cfc6a90129536dc95b84
parentf2effd49e7093978aebf1f79cb586cfd19aa7fb0 (diff)
drm/amdgpu/gfx8: reduce the functon params for mpq setup
Everything we need is in the ring structure. No need to pass all the bits explicitly. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c32
1 files changed, 14 insertions, 18 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 0fc29959f412..d66a061bfbe7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4691,12 +4691,11 @@ static void gfx_v8_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
4691 udelay(50); 4691 udelay(50);
4692} 4692}
4693 4693
4694static int gfx_v8_0_mqd_init(struct amdgpu_device *adev, 4694static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring,
4695 struct vi_mqd *mqd, 4695 struct vi_mqd *mqd,
4696 uint64_t mqd_gpu_addr, 4696 uint64_t eop_gpu_addr)
4697 uint64_t eop_gpu_addr,
4698 struct amdgpu_ring *ring)
4699{ 4697{
4698 struct amdgpu_device *adev = ring->adev;
4700 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 4699 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
4701 uint32_t tmp; 4700 uint32_t tmp;
4702 4701
@@ -4737,8 +4736,8 @@ static int gfx_v8_0_mqd_init(struct amdgpu_device *adev,
4737 mqd->cp_hqd_pq_wptr = 0; 4736 mqd->cp_hqd_pq_wptr = 0;
4738 4737
4739 /* set the pointer to the MQD */ 4738 /* set the pointer to the MQD */
4740 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; 4739 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
4741 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 4740 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
4742 4741
4743 /* set MQD vmid to 0 */ 4742 /* set MQD vmid to 0 */
4744 tmp = RREG32(mmCP_MQD_CONTROL); 4743 tmp = RREG32(mmCP_MQD_CONTROL);
@@ -4811,10 +4810,10 @@ static int gfx_v8_0_mqd_init(struct amdgpu_device *adev,
4811 return 0; 4810 return 0;
4812} 4811}
4813 4812
4814static int gfx_v8_0_kiq_init_register(struct amdgpu_device *adev, 4813static int gfx_v8_0_kiq_init_register(struct amdgpu_ring *ring,
4815 struct vi_mqd *mqd, 4814 struct vi_mqd *mqd)
4816 struct amdgpu_ring *ring)
4817{ 4815{
4816 struct amdgpu_device *adev = ring->adev;
4818 uint32_t tmp; 4817 uint32_t tmp;
4819 int j; 4818 int j;
4820 4819
@@ -4903,8 +4902,7 @@ static int gfx_v8_0_kiq_init_register(struct amdgpu_device *adev,
4903} 4902}
4904 4903
4905static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring, 4904static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring,
4906 struct vi_mqd *mqd, 4905 struct vi_mqd *mqd)
4907 u64 mqd_gpu_addr)
4908{ 4906{
4909 struct amdgpu_device *adev = ring->adev; 4907 struct amdgpu_device *adev = ring->adev;
4910 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4908 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
@@ -4925,9 +4923,9 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring,
4925 memset((void *)mqd, 0, sizeof(*mqd)); 4923 memset((void *)mqd, 0, sizeof(*mqd));
4926 mutex_lock(&adev->srbm_mutex); 4924 mutex_lock(&adev->srbm_mutex);
4927 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4925 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4928 gfx_v8_0_mqd_init(adev, mqd, mqd_gpu_addr, eop_gpu_addr, ring); 4926 gfx_v8_0_mqd_init(ring, mqd, eop_gpu_addr);
4929 if (is_kiq) 4927 if (is_kiq)
4930 gfx_v8_0_kiq_init_register(adev, mqd, ring); 4928 gfx_v8_0_kiq_init_register(ring, mqd);
4931 vi_srbm_select(adev, 0, 0, 0, 0); 4929 vi_srbm_select(adev, 0, 0, 0, 0);
4932 mutex_unlock(&adev->srbm_mutex); 4930 mutex_unlock(&adev->srbm_mutex);
4933 4931
@@ -4945,7 +4943,7 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring,
4945 if (is_kiq) { 4943 if (is_kiq) {
4946 mutex_lock(&adev->srbm_mutex); 4944 mutex_lock(&adev->srbm_mutex);
4947 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4945 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4948 gfx_v8_0_kiq_init_register(adev, mqd, ring); 4946 gfx_v8_0_kiq_init_register(ring, mqd);
4949 vi_srbm_select(adev, 0, 0, 0, 0); 4947 vi_srbm_select(adev, 0, 0, 0, 0);
4950 mutex_unlock(&adev->srbm_mutex); 4948 mutex_unlock(&adev->srbm_mutex);
4951 } 4949 }
@@ -4975,8 +4973,7 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
4975 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr); 4973 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4976 if (!r) { 4974 if (!r) {
4977 r = gfx_v8_0_kiq_init_queue(ring, 4975 r = gfx_v8_0_kiq_init_queue(ring,
4978 (struct vi_mqd *)ring->mqd_ptr, 4976 (struct vi_mqd *)ring->mqd_ptr);
4979 ring->mqd_gpu_addr);
4980 amdgpu_bo_kunmap(ring->mqd_obj); 4977 amdgpu_bo_kunmap(ring->mqd_obj);
4981 ring->mqd_ptr = NULL; 4978 ring->mqd_ptr = NULL;
4982 } 4979 }
@@ -5000,8 +4997,7 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
5000 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr); 4997 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
5001 if (!r) { 4998 if (!r) {
5002 r = gfx_v8_0_kiq_init_queue(ring, 4999 r = gfx_v8_0_kiq_init_queue(ring,
5003 (struct vi_mqd *)ring->mqd_ptr, 5000 (struct vi_mqd *)ring->mqd_ptr);
5004 ring->mqd_gpu_addr);
5005 amdgpu_bo_kunmap(ring->mqd_obj); 5001 amdgpu_bo_kunmap(ring->mqd_obj);
5006 ring->mqd_ptr = NULL; 5002 ring->mqd_ptr = NULL;
5007 } 5003 }