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authorLinus Torvalds <torvalds@linux-foundation.org>2016-12-23 13:41:53 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2016-12-23 13:41:53 -0500
commit01302aac12c782bf7cadfd9d902cd382359dca93 (patch)
treee7c4a93f3d74a40cfcbf75412be33542ca4e2c73
parent296915912d89d1ed2f47472b67fc594b15383d71 (diff)
parent4a401ceeef7bf3bc55f5e913cbf19d6038cf83c6 (diff)
Merge tag 'drm-fixes-for-4.10-rc1' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "Some fixes came in while I was out, mostly intel and amdgpu ones, with one ast fix" Daniel Vetter says: "This should also shut up the WARN_ON(!intel_dp->lane_count) noise" * tag 'drm-fixes-for-4.10-rc1' of git://people.freedesktop.org/~airlied/linux: (35 commits) drm/amdgpu: update tile table for oland/hainan drm/amdgpu: update tile table for verde drm/amdgpu: update rev id for verde drm/amdgpu: update golden setting for verde drm/amdgpu: update rev id for oland drm/amdgpu: update golden setting for oland drm/amdgpu: update rev id for hainan drm/amdgpu: update golden setting for hainan drm/amdgpu: update rev id for pitcairn drm/amdgpu: update golden setting for pitcairn drm/amdgpu: update golden setting/tiling table of tahiti drm/i915: skip the first 4k of stolen memory on everything >= gen8 drm/i915: Fallback to single PAGE_SIZE segments for DMA remapping drm/i915: Fix use after free in logical_render_ring_init drm/i915: disable PSR by default on HSW/BDW drm/i915: Fix setting of boost freq tunable drm/i915: tune down the fast link training vs boot fail drm/i915: Reorder phys backing storage release drm/i915/gen9: Fix PCODE polling during SAGV disabling drm/i915/gen9: Fix PCODE polling during CDCLK change notification ...
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v6_0.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c935
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c249
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si.c442
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c211
-rw-r--r--drivers/gpu/drm/amd/include/amd_shared.h4
-rw-r--r--drivers/gpu/drm/ast/ast_main.c7
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c79
-rw-r--r--drivers/gpu/drm/i915/i915_gem_stolen.c5
-rw-r--r--drivers/gpu/drm/i915/i915_sysfs.c2
-rw-r--r--drivers/gpu/drm/i915/intel_bios.h12
-rw-r--r--drivers/gpu/drm/i915/intel_display.c31
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c4
-rw-r--r--drivers/gpu/drm/i915/intel_dsi_panel_vbt.c7
-rw-r--r--drivers/gpu/drm/i915/intel_lrc.c7
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c109
-rw-r--r--drivers/gpu/drm/i915/intel_psr.c10
-rw-r--r--drivers/gpu/drm/i915/intel_runtime_pm.c13
20 files changed, 1409 insertions, 728 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index e564442b6393..b4e4ec630e8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -1944,9 +1944,7 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
1944 1944
1945 dce_v6_0_lock_cursor(crtc, true); 1945 dce_v6_0_lock_cursor(crtc, true);
1946 1946
1947 if (width != amdgpu_crtc->cursor_width || 1947 if (hot_x != amdgpu_crtc->cursor_hot_x ||
1948 height != amdgpu_crtc->cursor_height ||
1949 hot_x != amdgpu_crtc->cursor_hot_x ||
1950 hot_y != amdgpu_crtc->cursor_hot_y) { 1948 hot_y != amdgpu_crtc->cursor_hot_y) {
1951 int x, y; 1949 int x, y;
1952 1950
@@ -1955,8 +1953,6 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
1955 1953
1956 dce_v6_0_cursor_move_locked(crtc, x, y); 1954 dce_v6_0_cursor_move_locked(crtc, x, y);
1957 1955
1958 amdgpu_crtc->cursor_width = width;
1959 amdgpu_crtc->cursor_height = height;
1960 amdgpu_crtc->cursor_hot_x = hot_x; 1956 amdgpu_crtc->cursor_hot_x = hot_x;
1961 amdgpu_crtc->cursor_hot_y = hot_y; 1957 amdgpu_crtc->cursor_hot_y = hot_y;
1962 } 1958 }
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 6ce7fb42dbef..584abe834a3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2438,8 +2438,6 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2438 2438
2439 dce_v8_0_cursor_move_locked(crtc, x, y); 2439 dce_v8_0_cursor_move_locked(crtc, x, y);
2440 2440
2441 amdgpu_crtc->cursor_width = width;
2442 amdgpu_crtc->cursor_height = height;
2443 amdgpu_crtc->cursor_hot_x = hot_x; 2441 amdgpu_crtc->cursor_hot_x = hot_x;
2444 amdgpu_crtc->cursor_hot_y = hot_y; 2442 amdgpu_crtc->cursor_hot_y = hot_y;
2445 } 2443 }
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 558640aee15a..b323f5ef64d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -411,244 +411,587 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
411 break; 411 break;
412 } 412 }
413 413
414 if (adev->asic_type == CHIP_VERDE || 414 if (adev->asic_type == CHIP_VERDE) {
415 adev->asic_type == CHIP_OLAND ||
416 adev->asic_type == CHIP_HAINAN) {
417 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 415 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
418 switch (reg_offset) { 416 switch (reg_offset) {
419 case 0: 417 case 0:
420 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 418 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
421 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 419 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
422 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 420 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
423 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 421 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
424 NUM_BANKS(ADDR_SURF_16_BANK) |
425 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 422 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
426 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 423 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
427 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 424 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
425 NUM_BANKS(ADDR_SURF_16_BANK));
428 break; 426 break;
429 case 1: 427 case 1:
430 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 428 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
431 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 429 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
432 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 430 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
433 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 431 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
434 NUM_BANKS(ADDR_SURF_16_BANK) |
435 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 432 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
436 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 433 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
437 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 434 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
435 NUM_BANKS(ADDR_SURF_16_BANK));
438 break; 436 break;
439 case 2: 437 case 2:
440 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 438 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
441 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 439 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
442 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 440 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
443 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 441 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
444 NUM_BANKS(ADDR_SURF_16_BANK) |
445 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 442 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
446 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 443 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
447 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 444 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
445 NUM_BANKS(ADDR_SURF_16_BANK));
448 break; 446 break;
449 case 3: 447 case 3:
450 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 448 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
451 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 449 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
452 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 450 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
453 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
454 NUM_BANKS(ADDR_SURF_16_BANK) |
455 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 451 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
456 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 452 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
457 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 453 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
454 NUM_BANKS(ADDR_SURF_8_BANK) |
455 TILE_SPLIT(split_equal_to_row_size));
458 break; 456 break;
459 case 4: 457 case 4:
460 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 458 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
461 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 459 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
462 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 460 PIPE_CONFIG(ADDR_SURF_P4_8x16));
463 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
464 NUM_BANKS(ADDR_SURF_16_BANK) |
465 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
466 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
467 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
468 break; 461 break;
469 case 5: 462 case 5:
470 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 463 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
471 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 464 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
472 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 465 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
473 TILE_SPLIT(split_equal_to_row_size) | 466 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
474 NUM_BANKS(ADDR_SURF_16_BANK) |
475 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 467 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
476 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 468 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
477 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 469 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
470 NUM_BANKS(ADDR_SURF_4_BANK));
478 break; 471 break;
479 case 6: 472 case 6:
480 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 473 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
481 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 474 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
482 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 475 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
483 TILE_SPLIT(split_equal_to_row_size) | 476 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
484 NUM_BANKS(ADDR_SURF_16_BANK) |
485 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 477 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
486 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 478 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
487 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 479 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
480 NUM_BANKS(ADDR_SURF_4_BANK));
488 break; 481 break;
489 case 7: 482 case 7:
490 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 483 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
491 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 484 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
492 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 485 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
493 TILE_SPLIT(split_equal_to_row_size) | 486 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
494 NUM_BANKS(ADDR_SURF_16_BANK) |
495 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 487 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
496 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 488 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
497 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 489 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
490 NUM_BANKS(ADDR_SURF_2_BANK));
498 break; 491 break;
499 case 8: 492 case 8:
500 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 493 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
501 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
502 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
503 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
504 NUM_BANKS(ADDR_SURF_16_BANK) |
505 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
508 break; 494 break;
509 case 9: 495 case 9:
510 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 496 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
511 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 497 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
512 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 498 PIPE_CONFIG(ADDR_SURF_P4_8x16));
513 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
514 NUM_BANKS(ADDR_SURF_16_BANK) |
515 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
516 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
517 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
518 break; 499 break;
519 case 10: 500 case 10:
520 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 501 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
521 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 502 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
522 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 503 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
523 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 504 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
524 NUM_BANKS(ADDR_SURF_16_BANK) |
525 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 505 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
508 NUM_BANKS(ADDR_SURF_16_BANK));
528 break; 509 break;
529 case 11: 510 case 11:
530 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 511 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
531 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 512 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
532 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 513 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
533 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 514 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
534 NUM_BANKS(ADDR_SURF_16_BANK) |
535 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 515 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
536 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 516 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
537 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 517 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
518 NUM_BANKS(ADDR_SURF_16_BANK));
538 break; 519 break;
539 case 12: 520 case 12:
540 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 521 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
541 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 522 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
542 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 523 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
543 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 524 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
544 NUM_BANKS(ADDR_SURF_16_BANK) |
545 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 525 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
528 NUM_BANKS(ADDR_SURF_16_BANK));
548 break; 529 break;
549 case 13: 530 case 13:
550 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 531 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
551 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 532 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
552 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 533 PIPE_CONFIG(ADDR_SURF_P4_8x16));
553 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
554 NUM_BANKS(ADDR_SURF_16_BANK) |
555 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
556 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
557 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
558 break; 534 break;
559 case 14: 535 case 14:
560 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 536 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
561 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 537 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
562 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 538 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
563 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 539 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
564 NUM_BANKS(ADDR_SURF_16_BANK) |
565 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 540 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
566 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 541 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
567 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 542 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
543 NUM_BANKS(ADDR_SURF_16_BANK));
568 break; 544 break;
569 case 15: 545 case 15:
570 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 546 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
571 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 547 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
572 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 548 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
573 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 549 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
574 NUM_BANKS(ADDR_SURF_16_BANK) |
575 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 550 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
576 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 551 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
577 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 552 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
553 NUM_BANKS(ADDR_SURF_16_BANK));
578 break; 554 break;
579 case 16: 555 case 16:
580 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 556 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
581 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 557 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
582 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 558 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
583 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 559 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
584 NUM_BANKS(ADDR_SURF_16_BANK) |
585 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 560 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
586 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 561 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
587 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 562 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
563 NUM_BANKS(ADDR_SURF_16_BANK));
588 break; 564 break;
589 case 17: 565 case 17:
590 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 566 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
591 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 567 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
568 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
569 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
570 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
571 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
572 NUM_BANKS(ADDR_SURF_16_BANK) |
573 TILE_SPLIT(split_equal_to_row_size));
574 break;
575 case 18:
576 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
577 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
578 PIPE_CONFIG(ADDR_SURF_P4_8x16));
579 break;
580 case 19:
581 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
582 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
592 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 583 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
593 TILE_SPLIT(split_equal_to_row_size) | 584 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
585 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
586 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
594 NUM_BANKS(ADDR_SURF_16_BANK) | 587 NUM_BANKS(ADDR_SURF_16_BANK) |
588 TILE_SPLIT(split_equal_to_row_size));
589 break;
590 case 20:
591 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
592 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
593 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
595 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 594 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
596 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 595 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
597 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 596 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
597 NUM_BANKS(ADDR_SURF_16_BANK) |
598 TILE_SPLIT(split_equal_to_row_size));
598 break; 599 break;
599 case 21: 600 case 21:
600 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 601 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
601 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 602 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
602 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 603 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
603 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 604 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
604 NUM_BANKS(ADDR_SURF_16_BANK) | 605 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
605 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
606 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 606 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
607 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 607 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
608 NUM_BANKS(ADDR_SURF_8_BANK));
608 break; 609 break;
609 case 22: 610 case 22:
610 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 611 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
611 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 612 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
612 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 613 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
614 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
615 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
616 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
617 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
618 NUM_BANKS(ADDR_SURF_8_BANK));
619 break;
620 case 23:
621 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
622 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
623 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
613 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 624 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
625 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
626 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
628 NUM_BANKS(ADDR_SURF_4_BANK));
629 break;
630 case 24:
631 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
632 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
633 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
634 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
635 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
636 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
637 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
638 NUM_BANKS(ADDR_SURF_4_BANK));
639 break;
640 case 25:
641 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
642 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
643 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
644 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
645 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
646 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
647 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
648 NUM_BANKS(ADDR_SURF_2_BANK));
649 break;
650 case 26:
651 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
652 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
653 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
654 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
655 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
656 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
657 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
658 NUM_BANKS(ADDR_SURF_2_BANK));
659 break;
660 case 27:
661 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
662 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
663 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
664 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
665 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
666 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
667 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
668 NUM_BANKS(ADDR_SURF_2_BANK));
669 break;
670 case 28:
671 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
672 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
673 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
674 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
675 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
676 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
677 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
678 NUM_BANKS(ADDR_SURF_2_BANK));
679 break;
680 case 29:
681 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
682 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
683 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
684 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
685 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
686 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
687 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
688 NUM_BANKS(ADDR_SURF_2_BANK));
689 break;
690 case 30:
691 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
692 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
693 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
694 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
695 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
696 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
697 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
698 NUM_BANKS(ADDR_SURF_2_BANK));
699 break;
700 default:
701 continue;
702 }
703 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
704 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
705 }
706 } else if (adev->asic_type == CHIP_OLAND ||
707 adev->asic_type == CHIP_HAINAN) {
708 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
709 switch (reg_offset) {
710 case 0:
711 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
712 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
713 PIPE_CONFIG(ADDR_SURF_P2) |
714 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
715 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
716 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
717 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
718 NUM_BANKS(ADDR_SURF_16_BANK));
719 break;
720 case 1:
721 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
722 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
723 PIPE_CONFIG(ADDR_SURF_P2) |
724 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
725 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
726 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
727 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
728 NUM_BANKS(ADDR_SURF_16_BANK));
729 break;
730 case 2:
731 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
732 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
733 PIPE_CONFIG(ADDR_SURF_P2) |
734 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
735 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
736 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
737 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
738 NUM_BANKS(ADDR_SURF_16_BANK));
739 break;
740 case 3:
741 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
742 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
743 PIPE_CONFIG(ADDR_SURF_P2) |
744 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
745 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
746 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
747 NUM_BANKS(ADDR_SURF_8_BANK) |
748 TILE_SPLIT(split_equal_to_row_size));
749 break;
750 case 4:
751 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
752 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
753 PIPE_CONFIG(ADDR_SURF_P2));
754 break;
755 case 5:
756 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
757 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
758 PIPE_CONFIG(ADDR_SURF_P2) |
759 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
760 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
761 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
762 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
763 NUM_BANKS(ADDR_SURF_8_BANK));
764 break;
765 case 6:
766 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
767 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
768 PIPE_CONFIG(ADDR_SURF_P2) |
769 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
770 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
771 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
772 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
773 NUM_BANKS(ADDR_SURF_8_BANK));
774 break;
775 case 7:
776 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
777 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
778 PIPE_CONFIG(ADDR_SURF_P2) |
779 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
780 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
781 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
782 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
783 NUM_BANKS(ADDR_SURF_4_BANK));
784 break;
785 case 8:
786 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
787 break;
788 case 9:
789 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
790 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
791 PIPE_CONFIG(ADDR_SURF_P2));
792 break;
793 case 10:
794 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
795 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
796 PIPE_CONFIG(ADDR_SURF_P2) |
797 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
798 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
799 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
800 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
801 NUM_BANKS(ADDR_SURF_16_BANK));
802 break;
803 case 11:
804 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
805 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
806 PIPE_CONFIG(ADDR_SURF_P2) |
807 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
808 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
809 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
810 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
811 NUM_BANKS(ADDR_SURF_16_BANK));
812 break;
813 case 12:
814 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
815 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
816 PIPE_CONFIG(ADDR_SURF_P2) |
817 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
818 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
819 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
820 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
821 NUM_BANKS(ADDR_SURF_16_BANK));
822 break;
823 case 13:
824 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
825 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
826 PIPE_CONFIG(ADDR_SURF_P2));
827 break;
828 case 14:
829 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
830 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
831 PIPE_CONFIG(ADDR_SURF_P2) |
832 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
833 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
835 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
836 NUM_BANKS(ADDR_SURF_16_BANK));
837 break;
838 case 15:
839 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
840 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
841 PIPE_CONFIG(ADDR_SURF_P2) |
842 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
843 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
844 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
845 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
846 NUM_BANKS(ADDR_SURF_16_BANK));
847 break;
848 case 16:
849 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
850 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
851 PIPE_CONFIG(ADDR_SURF_P2) |
852 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
853 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
854 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
855 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
856 NUM_BANKS(ADDR_SURF_16_BANK));
857 break;
858 case 17:
859 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
860 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
861 PIPE_CONFIG(ADDR_SURF_P2) |
862 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
863 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
864 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
614 NUM_BANKS(ADDR_SURF_16_BANK) | 865 NUM_BANKS(ADDR_SURF_16_BANK) |
866 TILE_SPLIT(split_equal_to_row_size));
867 break;
868 case 18:
869 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
870 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
871 PIPE_CONFIG(ADDR_SURF_P2));
872 break;
873 case 19:
874 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
875 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
876 PIPE_CONFIG(ADDR_SURF_P2) |
615 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 877 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
878 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
879 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
880 NUM_BANKS(ADDR_SURF_16_BANK) |
881 TILE_SPLIT(split_equal_to_row_size));
882 break;
883 case 20:
884 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
885 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
886 PIPE_CONFIG(ADDR_SURF_P2) |
887 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
888 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
889 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
890 NUM_BANKS(ADDR_SURF_16_BANK) |
891 TILE_SPLIT(split_equal_to_row_size));
892 break;
893 case 21:
894 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
895 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
896 PIPE_CONFIG(ADDR_SURF_P2) |
897 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
898 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
616 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 899 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
617 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 900 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
901 NUM_BANKS(ADDR_SURF_8_BANK));
902 break;
903 case 22:
904 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
905 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
906 PIPE_CONFIG(ADDR_SURF_P2) |
907 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
908 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
909 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
910 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
911 NUM_BANKS(ADDR_SURF_8_BANK));
618 break; 912 break;
619 case 23: 913 case 23:
620 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 914 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
621 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 915 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
622 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 916 PIPE_CONFIG(ADDR_SURF_P2) |
623 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 917 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
624 NUM_BANKS(ADDR_SURF_16_BANK) |
625 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 918 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
626 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 919 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 920 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
921 NUM_BANKS(ADDR_SURF_8_BANK));
628 break; 922 break;
629 case 24: 923 case 24:
630 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 924 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
631 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 925 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
632 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 926 PIPE_CONFIG(ADDR_SURF_P2) |
633 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 927 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
634 NUM_BANKS(ADDR_SURF_16_BANK) |
635 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 928 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
636 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 929 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
637 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 930 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
931 NUM_BANKS(ADDR_SURF_8_BANK));
638 break; 932 break;
639 case 25: 933 case 25:
640 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 934 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
641 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 935 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
642 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 936 PIPE_CONFIG(ADDR_SURF_P2) |
643 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 937 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
644 NUM_BANKS(ADDR_SURF_8_BANK) | 938 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
939 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
940 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
941 NUM_BANKS(ADDR_SURF_4_BANK));
942 break;
943 case 26:
944 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
945 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
946 PIPE_CONFIG(ADDR_SURF_P2) |
947 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
948 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
949 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
950 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
951 NUM_BANKS(ADDR_SURF_4_BANK));
952 break;
953 case 27:
954 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
955 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
956 PIPE_CONFIG(ADDR_SURF_P2) |
957 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
958 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
959 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
960 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
961 NUM_BANKS(ADDR_SURF_4_BANK));
962 break;
963 case 28:
964 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
965 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
966 PIPE_CONFIG(ADDR_SURF_P2) |
967 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
968 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
969 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
970 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
971 NUM_BANKS(ADDR_SURF_4_BANK));
972 break;
973 case 29:
974 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
975 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
976 PIPE_CONFIG(ADDR_SURF_P2) |
977 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
978 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
979 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
980 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
981 NUM_BANKS(ADDR_SURF_4_BANK));
982 break;
983 case 30:
984 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
985 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
986 PIPE_CONFIG(ADDR_SURF_P2) |
987 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
645 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 988 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
646 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 989 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
647 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 990 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
991 NUM_BANKS(ADDR_SURF_4_BANK));
648 break; 992 break;
649 default: 993 default:
650 gb_tile_moden = 0; 994 continue;
651 break;
652 } 995 }
653 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 996 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
654 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 997 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
@@ -656,239 +999,291 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
656 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 999 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
657 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1000 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
658 switch (reg_offset) { 1001 switch (reg_offset) {
659 case 0: /* non-AA compressed depth or any compressed stencil */ 1002 case 0:
660 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1003 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
661 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1004 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
662 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1005 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
663 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1006 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
664 NUM_BANKS(ADDR_SURF_16_BANK) |
665 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1007 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
666 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1008 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
667 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1009 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1010 NUM_BANKS(ADDR_SURF_16_BANK));
668 break; 1011 break;
669 case 1: /* 2xAA/4xAA compressed depth only */ 1012 case 1:
670 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1013 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
671 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1014 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
672 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1015 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
673 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1016 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
674 NUM_BANKS(ADDR_SURF_16_BANK) |
675 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1017 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
676 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1018 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
677 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1019 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1020 NUM_BANKS(ADDR_SURF_16_BANK));
678 break; 1021 break;
679 case 2: /* 8xAA compressed depth only */ 1022 case 2:
680 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1023 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
681 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1024 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
682 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1025 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
683 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1026 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
684 NUM_BANKS(ADDR_SURF_16_BANK) |
685 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1027 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
686 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1028 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
687 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1029 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1030 NUM_BANKS(ADDR_SURF_16_BANK));
688 break; 1031 break;
689 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ 1032 case 3:
690 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1033 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
691 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1034 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
692 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1035 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
693 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
694 NUM_BANKS(ADDR_SURF_16_BANK) |
695 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1036 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
696 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1037 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
697 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1038 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1039 NUM_BANKS(ADDR_SURF_4_BANK) |
1040 TILE_SPLIT(split_equal_to_row_size));
698 break; 1041 break;
699 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ 1042 case 4:
700 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1043 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
701 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1044 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
702 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1045 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
703 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
704 NUM_BANKS(ADDR_SURF_16_BANK) |
705 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
706 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
707 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
708 break; 1046 break;
709 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ 1047 case 5:
710 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1048 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
711 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1049 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
712 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1050 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
713 TILE_SPLIT(split_equal_to_row_size) | 1051 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
714 NUM_BANKS(ADDR_SURF_16_BANK) |
715 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1052 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
716 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1053 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
717 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1054 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1055 NUM_BANKS(ADDR_SURF_2_BANK));
718 break; 1056 break;
719 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ 1057 case 6:
720 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1058 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
721 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1059 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
722 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1060 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
723 TILE_SPLIT(split_equal_to_row_size) | 1061 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
724 NUM_BANKS(ADDR_SURF_16_BANK) |
725 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1062 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
726 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1063 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
727 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1064 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1065 NUM_BANKS(ADDR_SURF_2_BANK));
728 break; 1066 break;
729 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ 1067 case 7:
730 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1068 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
731 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1069 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
732 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1070 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
733 TILE_SPLIT(split_equal_to_row_size) | 1071 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
734 NUM_BANKS(ADDR_SURF_16_BANK) |
735 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1072 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
736 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1073 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
737 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1074 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1075 NUM_BANKS(ADDR_SURF_2_BANK));
738 break; 1076 break;
739 case 8: /* 1D and 1D Array Surfaces */ 1077 case 8:
740 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1078 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
741 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
742 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
743 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
744 NUM_BANKS(ADDR_SURF_16_BANK) |
745 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
746 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
747 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
748 break; 1079 break;
749 case 9: /* Displayable maps. */ 1080 case 9:
750 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1081 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
751 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1082 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
752 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1083 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
753 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
754 NUM_BANKS(ADDR_SURF_16_BANK) |
755 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
756 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
757 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
758 break; 1084 break;
759 case 10: /* Display 8bpp. */ 1085 case 10:
760 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1086 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
761 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1087 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
762 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1088 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
763 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1089 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
764 NUM_BANKS(ADDR_SURF_16_BANK) |
765 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1090 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
766 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1091 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
767 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1092 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1093 NUM_BANKS(ADDR_SURF_16_BANK));
768 break; 1094 break;
769 case 11: /* Display 16bpp. */ 1095 case 11:
770 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1096 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
771 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1097 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
772 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1098 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
773 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1099 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
774 NUM_BANKS(ADDR_SURF_16_BANK) |
775 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1100 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
776 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1101 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
777 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1102 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1103 NUM_BANKS(ADDR_SURF_16_BANK));
778 break; 1104 break;
779 case 12: /* Display 32bpp. */ 1105 case 12:
780 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1106 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
781 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1107 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
782 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1108 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
783 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1109 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
784 NUM_BANKS(ADDR_SURF_16_BANK) |
785 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1110 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
786 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1111 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
787 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1112 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1113 NUM_BANKS(ADDR_SURF_16_BANK));
788 break; 1114 break;
789 case 13: /* Thin. */ 1115 case 13:
790 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1116 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
791 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1117 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
792 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1118 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
793 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
794 NUM_BANKS(ADDR_SURF_16_BANK) |
795 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
796 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
797 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
798 break; 1119 break;
799 case 14: /* Thin 8 bpp. */ 1120 case 14:
800 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1121 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
801 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1122 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
802 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1123 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
803 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1124 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
804 NUM_BANKS(ADDR_SURF_16_BANK) |
805 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1125 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
806 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1126 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
807 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1127 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1128 NUM_BANKS(ADDR_SURF_16_BANK));
808 break; 1129 break;
809 case 15: /* Thin 16 bpp. */ 1130 case 15:
810 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1131 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
811 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1132 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
812 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1133 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
813 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1134 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
814 NUM_BANKS(ADDR_SURF_16_BANK) |
815 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1135 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
816 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1136 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
817 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1137 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1138 NUM_BANKS(ADDR_SURF_16_BANK));
818 break; 1139 break;
819 case 16: /* Thin 32 bpp. */ 1140 case 16:
820 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1141 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
821 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1142 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
822 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1143 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
823 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1144 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
824 NUM_BANKS(ADDR_SURF_16_BANK) |
825 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1145 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
826 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1146 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
827 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1147 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1148 NUM_BANKS(ADDR_SURF_16_BANK));
828 break; 1149 break;
829 case 17: /* Thin 64 bpp. */ 1150 case 17:
830 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1151 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
831 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1152 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
832 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1153 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
833 TILE_SPLIT(split_equal_to_row_size) | 1154 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
834 NUM_BANKS(ADDR_SURF_16_BANK) | 1157 NUM_BANKS(ADDR_SURF_16_BANK) |
1158 TILE_SPLIT(split_equal_to_row_size));
1159 break;
1160 case 18:
1161 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1162 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1163 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
1164 break;
1165 case 19:
1166 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1167 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1168 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
835 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1169 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
836 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
837 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1172 NUM_BANKS(ADDR_SURF_16_BANK) |
1173 TILE_SPLIT(split_equal_to_row_size));
838 break; 1174 break;
839 case 21: /* 8 bpp PRT. */ 1175 case 20:
840 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1176 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
841 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1177 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
842 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1178 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
843 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1179 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
844 NUM_BANKS(ADDR_SURF_16_BANK) | 1182 NUM_BANKS(ADDR_SURF_16_BANK) |
845 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1183 TILE_SPLIT(split_equal_to_row_size));
846 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
847 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
848 break; 1184 break;
849 case 22: /* 16 bpp PRT */ 1185 case 21:
850 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1186 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
851 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1187 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1188 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1189 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1190 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1191 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1193 NUM_BANKS(ADDR_SURF_4_BANK));
1194 break;
1195 case 22:
1196 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1197 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
852 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1198 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
853 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1199 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
854 NUM_BANKS(ADDR_SURF_16_BANK) |
855 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1200 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
856 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
857 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1203 NUM_BANKS(ADDR_SURF_4_BANK));
858 break; 1204 break;
859 case 23: /* 32 bpp PRT */ 1205 case 23:
860 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1206 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
861 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1207 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
862 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1208 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
863 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1209 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
864 NUM_BANKS(ADDR_SURF_16_BANK) |
865 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1210 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
866 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1211 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
867 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1212 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1213 NUM_BANKS(ADDR_SURF_2_BANK));
868 break; 1214 break;
869 case 24: /* 64 bpp PRT */ 1215 case 24:
870 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1216 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
871 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1217 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
872 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1218 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
873 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1219 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
874 NUM_BANKS(ADDR_SURF_16_BANK) |
875 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1220 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
876 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1221 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
877 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1222 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1223 NUM_BANKS(ADDR_SURF_2_BANK));
878 break; 1224 break;
879 case 25: /* 128 bpp PRT */ 1225 case 25:
880 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1226 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
881 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1227 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
882 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1228 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
883 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
884 NUM_BANKS(ADDR_SURF_8_BANK) |
885 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1230 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
886 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1231 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
887 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1232 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1233 NUM_BANKS(ADDR_SURF_2_BANK));
888 break; 1234 break;
889 default: 1235 case 26:
890 gb_tile_moden = 0; 1236 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1237 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1238 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1239 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1240 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1241 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1242 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1243 NUM_BANKS(ADDR_SURF_2_BANK));
1244 break;
1245 case 27:
1246 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1247 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1248 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1249 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1250 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1251 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1252 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1253 NUM_BANKS(ADDR_SURF_2_BANK));
1254 break;
1255 case 28:
1256 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1257 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1258 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1259 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1260 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1261 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1262 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1263 NUM_BANKS(ADDR_SURF_2_BANK));
891 break; 1264 break;
1265 case 29:
1266 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1267 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1268 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1269 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1270 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1271 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1272 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1273 NUM_BANKS(ADDR_SURF_2_BANK));
1274 break;
1275 case 30:
1276 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1277 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1278 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1279 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1280 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1281 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1282 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1283 NUM_BANKS(ADDR_SURF_2_BANK));
1284 break;
1285 default:
1286 continue;
892 } 1287 }
893 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 1288 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
894 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 1289 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 6324f67bdb1f..d0ec00986f38 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3949,8 +3949,12 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3949 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0; 3949 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
3950 data = mmRLC_SRM_INDEX_CNTL_DATA_0; 3950 data = mmRLC_SRM_INDEX_CNTL_DATA_0;
3951 for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) { 3951 for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
3952 amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false); 3952 if (unique_indices[i] != 0) {
3953 amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false); 3953 amdgpu_mm_wreg(adev, temp + i,
3954 unique_indices[i] & 0x3FFFF, false);
3955 amdgpu_mm_wreg(adev, data + i,
3956 unique_indices[i] >> 20, false);
3957 }
3954 } 3958 }
3955 kfree(register_list_format); 3959 kfree(register_list_format);
3956 3960
@@ -3966,20 +3970,17 @@ static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
3966{ 3970{
3967 uint32_t data; 3971 uint32_t data;
3968 3972
3969 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3973 WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
3970 AMD_PG_SUPPORT_GFX_SMG |
3971 AMD_PG_SUPPORT_GFX_DMG)) {
3972 WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
3973 3974
3974 data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10); 3975 data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
3975 data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10); 3976 data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
3976 data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10); 3977 data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
3977 data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10); 3978 data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
3978 WREG32(mmRLC_PG_DELAY, data); 3979 WREG32(mmRLC_PG_DELAY, data);
3980
3981 WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
3982 WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
3979 3983
3980 WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
3981 WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
3982 }
3983} 3984}
3984 3985
3985static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 3986static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
@@ -3996,41 +3997,37 @@ static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
3996 3997
3997static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable) 3998static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
3998{ 3999{
3999 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 1 : 0); 4000 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
4000} 4001}
4001 4002
4002static void gfx_v8_0_init_pg(struct amdgpu_device *adev) 4003static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
4003{ 4004{
4004 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4005 if ((adev->asic_type == CHIP_CARRIZO) ||
4005 AMD_PG_SUPPORT_GFX_SMG | 4006 (adev->asic_type == CHIP_STONEY)) {
4006 AMD_PG_SUPPORT_GFX_DMG |
4007 AMD_PG_SUPPORT_CP |
4008 AMD_PG_SUPPORT_GDS |
4009 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4010 gfx_v8_0_init_csb(adev); 4007 gfx_v8_0_init_csb(adev);
4011 gfx_v8_0_init_save_restore_list(adev); 4008 gfx_v8_0_init_save_restore_list(adev);
4012 gfx_v8_0_enable_save_restore_machine(adev); 4009 gfx_v8_0_enable_save_restore_machine(adev);
4013 4010 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4014 if ((adev->asic_type == CHIP_CARRIZO) || 4011 gfx_v8_0_init_power_gating(adev);
4015 (adev->asic_type == CHIP_STONEY)) { 4012 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
4016 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); 4013 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
4017 gfx_v8_0_init_power_gating(adev); 4014 cz_enable_sck_slow_down_on_power_up(adev, true);
4018 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 4015 cz_enable_sck_slow_down_on_power_down(adev, true);
4019 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 4016 } else {
4020 cz_enable_sck_slow_down_on_power_up(adev, true); 4017 cz_enable_sck_slow_down_on_power_up(adev, false);
4021 cz_enable_sck_slow_down_on_power_down(adev, true); 4018 cz_enable_sck_slow_down_on_power_down(adev, false);
4022 } else {
4023 cz_enable_sck_slow_down_on_power_up(adev, false);
4024 cz_enable_sck_slow_down_on_power_down(adev, false);
4025 }
4026 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
4027 cz_enable_cp_power_gating(adev, true);
4028 else
4029 cz_enable_cp_power_gating(adev, false);
4030 } else if (adev->asic_type == CHIP_POLARIS11) {
4031 gfx_v8_0_init_power_gating(adev);
4032 } 4019 }
4020 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
4021 cz_enable_cp_power_gating(adev, true);
4022 else
4023 cz_enable_cp_power_gating(adev, false);
4024 } else if (adev->asic_type == CHIP_POLARIS11) {
4025 gfx_v8_0_init_csb(adev);
4026 gfx_v8_0_init_save_restore_list(adev);
4027 gfx_v8_0_enable_save_restore_machine(adev);
4028 gfx_v8_0_init_power_gating(adev);
4033 } 4029 }
4030
4034} 4031}
4035 4032
4036static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev) 4033static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
@@ -5339,14 +5336,11 @@ static int gfx_v8_0_set_powergating_state(void *handle,
5339 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5336 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5340 bool enable = (state == AMD_PG_STATE_GATE) ? true : false; 5337 bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
5341 5338
5342 if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
5343 return 0;
5344
5345 switch (adev->asic_type) { 5339 switch (adev->asic_type) {
5346 case CHIP_CARRIZO: 5340 case CHIP_CARRIZO:
5347 case CHIP_STONEY: 5341 case CHIP_STONEY:
5348 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) 5342
5349 cz_update_gfx_cg_power_gating(adev, enable); 5343 cz_update_gfx_cg_power_gating(adev, enable);
5350 5344
5351 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 5345 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5352 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true); 5346 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
@@ -5791,25 +5785,49 @@ static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5791static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev, 5785static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
5792 enum amd_clockgating_state state) 5786 enum amd_clockgating_state state)
5793{ 5787{
5794 uint32_t msg_id, pp_state; 5788 uint32_t msg_id, pp_state = 0;
5789 uint32_t pp_support_state = 0;
5795 void *pp_handle = adev->powerplay.pp_handle; 5790 void *pp_handle = adev->powerplay.pp_handle;
5796 5791
5797 if (state == AMD_CG_STATE_UNGATE) 5792 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5798 pp_state = 0; 5793 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5799 else 5794 pp_support_state = PP_STATE_SUPPORT_LS;
5800 pp_state = PP_STATE_CG | PP_STATE_LS; 5795 pp_state = PP_STATE_LS;
5796 }
5797 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5798 pp_support_state |= PP_STATE_SUPPORT_CG;
5799 pp_state |= PP_STATE_CG;
5800 }
5801 if (state == AMD_CG_STATE_UNGATE)
5802 pp_state = 0;
5803
5804 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5805 PP_BLOCK_GFX_CG,
5806 pp_support_state,
5807 pp_state);
5808 amd_set_clockgating_by_smu(pp_handle, msg_id);
5809 }
5801 5810
5802 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5811 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5803 PP_BLOCK_GFX_CG, 5812 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5804 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 5813 pp_support_state = PP_STATE_SUPPORT_LS;
5805 pp_state); 5814 pp_state = PP_STATE_LS;
5806 amd_set_clockgating_by_smu(pp_handle, msg_id); 5815 }
5807 5816
5808 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5817 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5809 PP_BLOCK_GFX_MG, 5818 pp_support_state |= PP_STATE_SUPPORT_CG;
5810 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 5819 pp_state |= PP_STATE_CG;
5811 pp_state); 5820 }
5812 amd_set_clockgating_by_smu(pp_handle, msg_id); 5821
5822 if (state == AMD_CG_STATE_UNGATE)
5823 pp_state = 0;
5824
5825 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5826 PP_BLOCK_GFX_MG,
5827 pp_support_state,
5828 pp_state);
5829 amd_set_clockgating_by_smu(pp_handle, msg_id);
5830 }
5813 5831
5814 return 0; 5832 return 0;
5815} 5833}
@@ -5817,43 +5835,98 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
5817static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, 5835static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
5818 enum amd_clockgating_state state) 5836 enum amd_clockgating_state state)
5819{ 5837{
5820 uint32_t msg_id, pp_state; 5838
5839 uint32_t msg_id, pp_state = 0;
5840 uint32_t pp_support_state = 0;
5821 void *pp_handle = adev->powerplay.pp_handle; 5841 void *pp_handle = adev->powerplay.pp_handle;
5822 5842
5823 if (state == AMD_CG_STATE_UNGATE) 5843 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5824 pp_state = 0; 5844 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5825 else 5845 pp_support_state = PP_STATE_SUPPORT_LS;
5826 pp_state = PP_STATE_CG | PP_STATE_LS; 5846 pp_state = PP_STATE_LS;
5847 }
5848 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5849 pp_support_state |= PP_STATE_SUPPORT_CG;
5850 pp_state |= PP_STATE_CG;
5851 }
5852 if (state == AMD_CG_STATE_UNGATE)
5853 pp_state = 0;
5854
5855 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5856 PP_BLOCK_GFX_CG,
5857 pp_support_state,
5858 pp_state);
5859 amd_set_clockgating_by_smu(pp_handle, msg_id);
5860 }
5827 5861
5828 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5862 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
5829 PP_BLOCK_GFX_CG, 5863 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
5830 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 5864 pp_support_state = PP_STATE_SUPPORT_LS;
5831 pp_state); 5865 pp_state = PP_STATE_LS;
5832 amd_set_clockgating_by_smu(pp_handle, msg_id); 5866 }
5867 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
5868 pp_support_state |= PP_STATE_SUPPORT_CG;
5869 pp_state |= PP_STATE_CG;
5870 }
5871 if (state == AMD_CG_STATE_UNGATE)
5872 pp_state = 0;
5873
5874 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5875 PP_BLOCK_GFX_3D,
5876 pp_support_state,
5877 pp_state);
5878 amd_set_clockgating_by_smu(pp_handle, msg_id);
5879 }
5833 5880
5834 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5881 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5835 PP_BLOCK_GFX_3D, 5882 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5836 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 5883 pp_support_state = PP_STATE_SUPPORT_LS;
5837 pp_state); 5884 pp_state = PP_STATE_LS;
5838 amd_set_clockgating_by_smu(pp_handle, msg_id); 5885 }
5839 5886
5840 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5887 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5841 PP_BLOCK_GFX_MG, 5888 pp_support_state |= PP_STATE_SUPPORT_CG;
5842 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 5889 pp_state |= PP_STATE_CG;
5843 pp_state); 5890 }
5844 amd_set_clockgating_by_smu(pp_handle, msg_id);
5845 5891
5846 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5892 if (state == AMD_CG_STATE_UNGATE)
5847 PP_BLOCK_GFX_RLC, 5893 pp_state = 0;
5848 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 5894
5849 pp_state); 5895 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5850 amd_set_clockgating_by_smu(pp_handle, msg_id); 5896 PP_BLOCK_GFX_MG,
5897 pp_support_state,
5898 pp_state);
5899 amd_set_clockgating_by_smu(pp_handle, msg_id);
5900 }
5901
5902 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5903 pp_support_state = PP_STATE_SUPPORT_LS;
5851 5904
5852 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5905 if (state == AMD_CG_STATE_UNGATE)
5906 pp_state = 0;
5907 else
5908 pp_state = PP_STATE_LS;
5909
5910 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5911 PP_BLOCK_GFX_RLC,
5912 pp_support_state,
5913 pp_state);
5914 amd_set_clockgating_by_smu(pp_handle, msg_id);
5915 }
5916
5917 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5918 pp_support_state = PP_STATE_SUPPORT_LS;
5919
5920 if (state == AMD_CG_STATE_UNGATE)
5921 pp_state = 0;
5922 else
5923 pp_state = PP_STATE_LS;
5924 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5853 PP_BLOCK_GFX_CP, 5925 PP_BLOCK_GFX_CP,
5854 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 5926 pp_support_state,
5855 pp_state); 5927 pp_state);
5856 amd_set_clockgating_by_smu(pp_handle, msg_id); 5928 amd_set_clockgating_by_smu(pp_handle, msg_id);
5929 }
5857 5930
5858 return 0; 5931 return 0;
5859} 5932}
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 3ed8ad8725b9..c46b0159007d 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -43,13 +43,14 @@
43 43
44static const u32 tahiti_golden_registers[] = 44static const u32 tahiti_golden_registers[] =
45{ 45{
46 0x17bc, 0x00000030, 0x00000011,
46 0x2684, 0x00010000, 0x00018208, 47 0x2684, 0x00010000, 0x00018208,
47 0x260c, 0xffffffff, 0x00000000, 48 0x260c, 0xffffffff, 0x00000000,
48 0x260d, 0xf00fffff, 0x00000400, 49 0x260d, 0xf00fffff, 0x00000400,
49 0x260e, 0x0002021c, 0x00020200, 50 0x260e, 0x0002021c, 0x00020200,
50 0x031e, 0x00000080, 0x00000000, 51 0x031e, 0x00000080, 0x00000000,
51 0x340c, 0x000300c0, 0x00800040, 52 0x340c, 0x000000c0, 0x00800040,
52 0x360c, 0x000300c0, 0x00800040, 53 0x360c, 0x000000c0, 0x00800040,
53 0x16ec, 0x000000f0, 0x00000070, 54 0x16ec, 0x000000f0, 0x00000070,
54 0x16f0, 0x00200000, 0x50100000, 55 0x16f0, 0x00200000, 0x50100000,
55 0x1c0c, 0x31000311, 0x00000011, 56 0x1c0c, 0x31000311, 0x00000011,
@@ -60,7 +61,7 @@ static const u32 tahiti_golden_registers[] =
60 0x22c4, 0x0000ff0f, 0x00000000, 61 0x22c4, 0x0000ff0f, 0x00000000,
61 0xa293, 0x07ffffff, 0x4e000000, 62 0xa293, 0x07ffffff, 0x4e000000,
62 0xa0d4, 0x3f3f3fff, 0x2a00126a, 63 0xa0d4, 0x3f3f3fff, 0x2a00126a,
63 0x000c, 0x000000ff, 0x0040, 64 0x000c, 0xffffffff, 0x0040,
64 0x000d, 0x00000040, 0x00004040, 65 0x000d, 0x00000040, 0x00004040,
65 0x2440, 0x07ffffff, 0x03000000, 66 0x2440, 0x07ffffff, 0x03000000,
66 0x23a2, 0x01ff1f3f, 0x00000000, 67 0x23a2, 0x01ff1f3f, 0x00000000,
@@ -73,7 +74,11 @@ static const u32 tahiti_golden_registers[] =
73 0x2234, 0xffffffff, 0x000fff40, 74 0x2234, 0xffffffff, 0x000fff40,
74 0x2235, 0x0000001f, 0x00000010, 75 0x2235, 0x0000001f, 0x00000010,
75 0x0504, 0x20000000, 0x20fffed8, 76 0x0504, 0x20000000, 0x20fffed8,
76 0x0570, 0x000c0fc0, 0x000c0400 77 0x0570, 0x000c0fc0, 0x000c0400,
78 0x052c, 0x0fffffff, 0xffffffff,
79 0x052d, 0x0fffffff, 0x0fffffff,
80 0x052e, 0x0fffffff, 0x0fffffff,
81 0x052f, 0x0fffffff, 0x0fffffff
77}; 82};
78 83
79static const u32 tahiti_golden_registers2[] = 84static const u32 tahiti_golden_registers2[] =
@@ -83,16 +88,18 @@ static const u32 tahiti_golden_registers2[] =
83 88
84static const u32 tahiti_golden_rlc_registers[] = 89static const u32 tahiti_golden_rlc_registers[] =
85{ 90{
91 0x263e, 0xffffffff, 0x12011003,
86 0x3109, 0xffffffff, 0x00601005, 92 0x3109, 0xffffffff, 0x00601005,
87 0x311f, 0xffffffff, 0x10104040, 93 0x311f, 0xffffffff, 0x10104040,
88 0x3122, 0xffffffff, 0x0100000a, 94 0x3122, 0xffffffff, 0x0100000a,
89 0x30c5, 0xffffffff, 0x00000800, 95 0x30c5, 0xffffffff, 0x00000800,
90 0x30c3, 0xffffffff, 0x800000f4, 96 0x30c3, 0xffffffff, 0x800000f4,
91 0x3d2a, 0xffffffff, 0x00000000 97 0x3d2a, 0x00000008, 0x00000000
92}; 98};
93 99
94static const u32 pitcairn_golden_registers[] = 100static const u32 pitcairn_golden_registers[] =
95{ 101{
102 0x17bc, 0x00000030, 0x00000011,
96 0x2684, 0x00010000, 0x00018208, 103 0x2684, 0x00010000, 0x00018208,
97 0x260c, 0xffffffff, 0x00000000, 104 0x260c, 0xffffffff, 0x00000000,
98 0x260d, 0xf00fffff, 0x00000400, 105 0x260d, 0xf00fffff, 0x00000400,
@@ -110,7 +117,7 @@ static const u32 pitcairn_golden_registers[] =
110 0x22c4, 0x0000ff0f, 0x00000000, 117 0x22c4, 0x0000ff0f, 0x00000000,
111 0xa293, 0x07ffffff, 0x4e000000, 118 0xa293, 0x07ffffff, 0x4e000000,
112 0xa0d4, 0x3f3f3fff, 0x2a00126a, 119 0xa0d4, 0x3f3f3fff, 0x2a00126a,
113 0x000c, 0x000000ff, 0x0040, 120 0x000c, 0xffffffff, 0x0040,
114 0x000d, 0x00000040, 0x00004040, 121 0x000d, 0x00000040, 0x00004040,
115 0x2440, 0x07ffffff, 0x03000000, 122 0x2440, 0x07ffffff, 0x03000000,
116 0x2418, 0x0000007f, 0x00000020, 123 0x2418, 0x0000007f, 0x00000020,
@@ -119,11 +126,16 @@ static const u32 pitcairn_golden_registers[] =
119 0x2b04, 0xffffffff, 0x00000000, 126 0x2b04, 0xffffffff, 0x00000000,
120 0x2b03, 0xffffffff, 0x32761054, 127 0x2b03, 0xffffffff, 0x32761054,
121 0x2235, 0x0000001f, 0x00000010, 128 0x2235, 0x0000001f, 0x00000010,
122 0x0570, 0x000c0fc0, 0x000c0400 129 0x0570, 0x000c0fc0, 0x000c0400,
130 0x052c, 0x0fffffff, 0xffffffff,
131 0x052d, 0x0fffffff, 0x0fffffff,
132 0x052e, 0x0fffffff, 0x0fffffff,
133 0x052f, 0x0fffffff, 0x0fffffff
123}; 134};
124 135
125static const u32 pitcairn_golden_rlc_registers[] = 136static const u32 pitcairn_golden_rlc_registers[] =
126{ 137{
138 0x263e, 0xffffffff, 0x12011003,
127 0x3109, 0xffffffff, 0x00601004, 139 0x3109, 0xffffffff, 0x00601004,
128 0x311f, 0xffffffff, 0x10102020, 140 0x311f, 0xffffffff, 0x10102020,
129 0x3122, 0xffffffff, 0x01000020, 141 0x3122, 0xffffffff, 0x01000020,
@@ -133,133 +145,134 @@ static const u32 pitcairn_golden_rlc_registers[] =
133 145
134static const u32 verde_pg_init[] = 146static const u32 verde_pg_init[] =
135{ 147{
136 0xd4f, 0xffffffff, 0x40000, 148 0x0d4f, 0xffffffff, 0x40000,
137 0xd4e, 0xffffffff, 0x200010ff, 149 0x0d4e, 0xffffffff, 0x200010ff,
138 0xd4f, 0xffffffff, 0x0, 150 0x0d4f, 0xffffffff, 0x0,
139 0xd4f, 0xffffffff, 0x0, 151 0x0d4f, 0xffffffff, 0x0,
140 0xd4f, 0xffffffff, 0x0, 152 0x0d4f, 0xffffffff, 0x0,
141 0xd4f, 0xffffffff, 0x0, 153 0x0d4f, 0xffffffff, 0x0,
142 0xd4f, 0xffffffff, 0x0, 154 0x0d4f, 0xffffffff, 0x0,
143 0xd4f, 0xffffffff, 0x7007, 155 0x0d4f, 0xffffffff, 0x7007,
144 0xd4e, 0xffffffff, 0x300010ff, 156 0x0d4e, 0xffffffff, 0x300010ff,
145 0xd4f, 0xffffffff, 0x0, 157 0x0d4f, 0xffffffff, 0x0,
146 0xd4f, 0xffffffff, 0x0, 158 0x0d4f, 0xffffffff, 0x0,
147 0xd4f, 0xffffffff, 0x0, 159 0x0d4f, 0xffffffff, 0x0,
148 0xd4f, 0xffffffff, 0x0, 160 0x0d4f, 0xffffffff, 0x0,
149 0xd4f, 0xffffffff, 0x0, 161 0x0d4f, 0xffffffff, 0x0,
150 0xd4f, 0xffffffff, 0x400000, 162 0x0d4f, 0xffffffff, 0x400000,
151 0xd4e, 0xffffffff, 0x100010ff, 163 0x0d4e, 0xffffffff, 0x100010ff,
152 0xd4f, 0xffffffff, 0x0, 164 0x0d4f, 0xffffffff, 0x0,
153 0xd4f, 0xffffffff, 0x0, 165 0x0d4f, 0xffffffff, 0x0,
154 0xd4f, 0xffffffff, 0x0, 166 0x0d4f, 0xffffffff, 0x0,
155 0xd4f, 0xffffffff, 0x0, 167 0x0d4f, 0xffffffff, 0x0,
156 0xd4f, 0xffffffff, 0x0, 168 0x0d4f, 0xffffffff, 0x0,
157 0xd4f, 0xffffffff, 0x120200, 169 0x0d4f, 0xffffffff, 0x120200,
158 0xd4e, 0xffffffff, 0x500010ff, 170 0x0d4e, 0xffffffff, 0x500010ff,
159 0xd4f, 0xffffffff, 0x0, 171 0x0d4f, 0xffffffff, 0x0,
160 0xd4f, 0xffffffff, 0x0, 172 0x0d4f, 0xffffffff, 0x0,
161 0xd4f, 0xffffffff, 0x0, 173 0x0d4f, 0xffffffff, 0x0,
162 0xd4f, 0xffffffff, 0x0, 174 0x0d4f, 0xffffffff, 0x0,
163 0xd4f, 0xffffffff, 0x0, 175 0x0d4f, 0xffffffff, 0x0,
164 0xd4f, 0xffffffff, 0x1e1e16, 176 0x0d4f, 0xffffffff, 0x1e1e16,
165 0xd4e, 0xffffffff, 0x600010ff, 177 0x0d4e, 0xffffffff, 0x600010ff,
166 0xd4f, 0xffffffff, 0x0, 178 0x0d4f, 0xffffffff, 0x0,
167 0xd4f, 0xffffffff, 0x0, 179 0x0d4f, 0xffffffff, 0x0,
168 0xd4f, 0xffffffff, 0x0, 180 0x0d4f, 0xffffffff, 0x0,
169 0xd4f, 0xffffffff, 0x0, 181 0x0d4f, 0xffffffff, 0x0,
170 0xd4f, 0xffffffff, 0x0, 182 0x0d4f, 0xffffffff, 0x0,
171 0xd4f, 0xffffffff, 0x171f1e, 183 0x0d4f, 0xffffffff, 0x171f1e,
172 0xd4e, 0xffffffff, 0x700010ff, 184 0x0d4e, 0xffffffff, 0x700010ff,
173 0xd4f, 0xffffffff, 0x0, 185 0x0d4f, 0xffffffff, 0x0,
174 0xd4f, 0xffffffff, 0x0, 186 0x0d4f, 0xffffffff, 0x0,
175 0xd4f, 0xffffffff, 0x0, 187 0x0d4f, 0xffffffff, 0x0,
176 0xd4f, 0xffffffff, 0x0, 188 0x0d4f, 0xffffffff, 0x0,
177 0xd4f, 0xffffffff, 0x0, 189 0x0d4f, 0xffffffff, 0x0,
178 0xd4f, 0xffffffff, 0x0, 190 0x0d4f, 0xffffffff, 0x0,
179 0xd4e, 0xffffffff, 0x9ff, 191 0x0d4e, 0xffffffff, 0x9ff,
180 0xd40, 0xffffffff, 0x0, 192 0x0d40, 0xffffffff, 0x0,
181 0xd41, 0xffffffff, 0x10000800, 193 0x0d41, 0xffffffff, 0x10000800,
182 0xd41, 0xffffffff, 0xf, 194 0x0d41, 0xffffffff, 0xf,
183 0xd41, 0xffffffff, 0xf, 195 0x0d41, 0xffffffff, 0xf,
184 0xd40, 0xffffffff, 0x4, 196 0x0d40, 0xffffffff, 0x4,
185 0xd41, 0xffffffff, 0x1000051e, 197 0x0d41, 0xffffffff, 0x1000051e,
186 0xd41, 0xffffffff, 0xffff, 198 0x0d41, 0xffffffff, 0xffff,
187 0xd41, 0xffffffff, 0xffff, 199 0x0d41, 0xffffffff, 0xffff,
188 0xd40, 0xffffffff, 0x8, 200 0x0d40, 0xffffffff, 0x8,
189 0xd41, 0xffffffff, 0x80500, 201 0x0d41, 0xffffffff, 0x80500,
190 0xd40, 0xffffffff, 0x12, 202 0x0d40, 0xffffffff, 0x12,
191 0xd41, 0xffffffff, 0x9050c, 203 0x0d41, 0xffffffff, 0x9050c,
192 0xd40, 0xffffffff, 0x1d, 204 0x0d40, 0xffffffff, 0x1d,
193 0xd41, 0xffffffff, 0xb052c, 205 0x0d41, 0xffffffff, 0xb052c,
194 0xd40, 0xffffffff, 0x2a, 206 0x0d40, 0xffffffff, 0x2a,
195 0xd41, 0xffffffff, 0x1053e, 207 0x0d41, 0xffffffff, 0x1053e,
196 0xd40, 0xffffffff, 0x2d, 208 0x0d40, 0xffffffff, 0x2d,
197 0xd41, 0xffffffff, 0x10546, 209 0x0d41, 0xffffffff, 0x10546,
198 0xd40, 0xffffffff, 0x30, 210 0x0d40, 0xffffffff, 0x30,
199 0xd41, 0xffffffff, 0xa054e, 211 0x0d41, 0xffffffff, 0xa054e,
200 0xd40, 0xffffffff, 0x3c, 212 0x0d40, 0xffffffff, 0x3c,
201 0xd41, 0xffffffff, 0x1055f, 213 0x0d41, 0xffffffff, 0x1055f,
202 0xd40, 0xffffffff, 0x3f, 214 0x0d40, 0xffffffff, 0x3f,
203 0xd41, 0xffffffff, 0x10567, 215 0x0d41, 0xffffffff, 0x10567,
204 0xd40, 0xffffffff, 0x42, 216 0x0d40, 0xffffffff, 0x42,
205 0xd41, 0xffffffff, 0x1056f, 217 0x0d41, 0xffffffff, 0x1056f,
206 0xd40, 0xffffffff, 0x45, 218 0x0d40, 0xffffffff, 0x45,
207 0xd41, 0xffffffff, 0x10572, 219 0x0d41, 0xffffffff, 0x10572,
208 0xd40, 0xffffffff, 0x48, 220 0x0d40, 0xffffffff, 0x48,
209 0xd41, 0xffffffff, 0x20575, 221 0x0d41, 0xffffffff, 0x20575,
210 0xd40, 0xffffffff, 0x4c, 222 0x0d40, 0xffffffff, 0x4c,
211 0xd41, 0xffffffff, 0x190801, 223 0x0d41, 0xffffffff, 0x190801,
212 0xd40, 0xffffffff, 0x67, 224 0x0d40, 0xffffffff, 0x67,
213 0xd41, 0xffffffff, 0x1082a, 225 0x0d41, 0xffffffff, 0x1082a,
214 0xd40, 0xffffffff, 0x6a, 226 0x0d40, 0xffffffff, 0x6a,
215 0xd41, 0xffffffff, 0x1b082d, 227 0x0d41, 0xffffffff, 0x1b082d,
216 0xd40, 0xffffffff, 0x87, 228 0x0d40, 0xffffffff, 0x87,
217 0xd41, 0xffffffff, 0x310851, 229 0x0d41, 0xffffffff, 0x310851,
218 0xd40, 0xffffffff, 0xba, 230 0x0d40, 0xffffffff, 0xba,
219 0xd41, 0xffffffff, 0x891, 231 0x0d41, 0xffffffff, 0x891,
220 0xd40, 0xffffffff, 0xbc, 232 0x0d40, 0xffffffff, 0xbc,
221 0xd41, 0xffffffff, 0x893, 233 0x0d41, 0xffffffff, 0x893,
222 0xd40, 0xffffffff, 0xbe, 234 0x0d40, 0xffffffff, 0xbe,
223 0xd41, 0xffffffff, 0x20895, 235 0x0d41, 0xffffffff, 0x20895,
224 0xd40, 0xffffffff, 0xc2, 236 0x0d40, 0xffffffff, 0xc2,
225 0xd41, 0xffffffff, 0x20899, 237 0x0d41, 0xffffffff, 0x20899,
226 0xd40, 0xffffffff, 0xc6, 238 0x0d40, 0xffffffff, 0xc6,
227 0xd41, 0xffffffff, 0x2089d, 239 0x0d41, 0xffffffff, 0x2089d,
228 0xd40, 0xffffffff, 0xca, 240 0x0d40, 0xffffffff, 0xca,
229 0xd41, 0xffffffff, 0x8a1, 241 0x0d41, 0xffffffff, 0x8a1,
230 0xd40, 0xffffffff, 0xcc, 242 0x0d40, 0xffffffff, 0xcc,
231 0xd41, 0xffffffff, 0x8a3, 243 0x0d41, 0xffffffff, 0x8a3,
232 0xd40, 0xffffffff, 0xce, 244 0x0d40, 0xffffffff, 0xce,
233 0xd41, 0xffffffff, 0x308a5, 245 0x0d41, 0xffffffff, 0x308a5,
234 0xd40, 0xffffffff, 0xd3, 246 0x0d40, 0xffffffff, 0xd3,
235 0xd41, 0xffffffff, 0x6d08cd, 247 0x0d41, 0xffffffff, 0x6d08cd,
236 0xd40, 0xffffffff, 0x142, 248 0x0d40, 0xffffffff, 0x142,
237 0xd41, 0xffffffff, 0x2000095a, 249 0x0d41, 0xffffffff, 0x2000095a,
238 0xd41, 0xffffffff, 0x1, 250 0x0d41, 0xffffffff, 0x1,
239 0xd40, 0xffffffff, 0x144, 251 0x0d40, 0xffffffff, 0x144,
240 0xd41, 0xffffffff, 0x301f095b, 252 0x0d41, 0xffffffff, 0x301f095b,
241 0xd40, 0xffffffff, 0x165, 253 0x0d40, 0xffffffff, 0x165,
242 0xd41, 0xffffffff, 0xc094d, 254 0x0d41, 0xffffffff, 0xc094d,
243 0xd40, 0xffffffff, 0x173, 255 0x0d40, 0xffffffff, 0x173,
244 0xd41, 0xffffffff, 0xf096d, 256 0x0d41, 0xffffffff, 0xf096d,
245 0xd40, 0xffffffff, 0x184, 257 0x0d40, 0xffffffff, 0x184,
246 0xd41, 0xffffffff, 0x15097f, 258 0x0d41, 0xffffffff, 0x15097f,
247 0xd40, 0xffffffff, 0x19b, 259 0x0d40, 0xffffffff, 0x19b,
248 0xd41, 0xffffffff, 0xc0998, 260 0x0d41, 0xffffffff, 0xc0998,
249 0xd40, 0xffffffff, 0x1a9, 261 0x0d40, 0xffffffff, 0x1a9,
250 0xd41, 0xffffffff, 0x409a7, 262 0x0d41, 0xffffffff, 0x409a7,
251 0xd40, 0xffffffff, 0x1af, 263 0x0d40, 0xffffffff, 0x1af,
252 0xd41, 0xffffffff, 0xcdc, 264 0x0d41, 0xffffffff, 0xcdc,
253 0xd40, 0xffffffff, 0x1b1, 265 0x0d40, 0xffffffff, 0x1b1,
254 0xd41, 0xffffffff, 0x800, 266 0x0d41, 0xffffffff, 0x800,
255 0xd42, 0xffffffff, 0x6c9b2000, 267 0x0d42, 0xffffffff, 0x6c9b2000,
256 0xd44, 0xfc00, 0x2000, 268 0x0d44, 0xfc00, 0x2000,
257 0xd51, 0xffffffff, 0xfc0, 269 0x0d51, 0xffffffff, 0xfc0,
258 0xa35, 0x00000100, 0x100 270 0x0a35, 0x00000100, 0x100
259}; 271};
260 272
261static const u32 verde_golden_rlc_registers[] = 273static const u32 verde_golden_rlc_registers[] =
262{ 274{
275 0x263e, 0xffffffff, 0x02010002,
263 0x3109, 0xffffffff, 0x033f1005, 276 0x3109, 0xffffffff, 0x033f1005,
264 0x311f, 0xffffffff, 0x10808020, 277 0x311f, 0xffffffff, 0x10808020,
265 0x3122, 0xffffffff, 0x00800008, 278 0x3122, 0xffffffff, 0x00800008,
@@ -269,65 +282,45 @@ static const u32 verde_golden_rlc_registers[] =
269 282
270static const u32 verde_golden_registers[] = 283static const u32 verde_golden_registers[] =
271{ 284{
285 0x17bc, 0x00000030, 0x00000011,
272 0x2684, 0x00010000, 0x00018208, 286 0x2684, 0x00010000, 0x00018208,
273 0x260c, 0xffffffff, 0x00000000, 287 0x260c, 0xffffffff, 0x00000000,
274 0x260d, 0xf00fffff, 0x00000400, 288 0x260d, 0xf00fffff, 0x00000400,
275 0x260e, 0x0002021c, 0x00020200, 289 0x260e, 0x0002021c, 0x00020200,
276 0x031e, 0x00000080, 0x00000000, 290 0x031e, 0x00000080, 0x00000000,
277 0x340c, 0x000300c0, 0x00800040, 291 0x340c, 0x000300c0, 0x00800040,
278 0x340c, 0x000300c0, 0x00800040,
279 0x360c, 0x000300c0, 0x00800040,
280 0x360c, 0x000300c0, 0x00800040, 292 0x360c, 0x000300c0, 0x00800040,
281 0x16ec, 0x000000f0, 0x00000070, 293 0x16ec, 0x000000f0, 0x00000070,
282 0x16f0, 0x00200000, 0x50100000, 294 0x16f0, 0x00200000, 0x50100000,
283
284 0x1c0c, 0x31000311, 0x00000011, 295 0x1c0c, 0x31000311, 0x00000011,
285 0x0ab9, 0x00073ffe, 0x000022a2, 296 0x0ab9, 0x00073ffe, 0x000022a2,
286 0x0ab9, 0x00073ffe, 0x000022a2,
287 0x0ab9, 0x00073ffe, 0x000022a2,
288 0x0903, 0x000007ff, 0x00000000,
289 0x0903, 0x000007ff, 0x00000000,
290 0x0903, 0x000007ff, 0x00000000, 297 0x0903, 0x000007ff, 0x00000000,
291 0x2285, 0xf000001f, 0x00000007, 298 0x2285, 0xf000001f, 0x00000007,
292 0x2285, 0xf000001f, 0x00000007, 299 0x22c9, 0xffffffff, 0x00ffffff,
293 0x2285, 0xf000001f, 0x00000007,
294 0x2285, 0xffffffff, 0x00ffffff,
295 0x22c4, 0x0000ff0f, 0x00000000, 300 0x22c4, 0x0000ff0f, 0x00000000,
296
297 0xa293, 0x07ffffff, 0x4e000000, 301 0xa293, 0x07ffffff, 0x4e000000,
298 0xa0d4, 0x3f3f3fff, 0x0000124a, 302 0xa0d4, 0x3f3f3fff, 0x0000124a,
299 0xa0d4, 0x3f3f3fff, 0x0000124a, 303 0x000c, 0xffffffff, 0x0040,
300 0xa0d4, 0x3f3f3fff, 0x0000124a,
301 0x000c, 0x000000ff, 0x0040,
302 0x000d, 0x00000040, 0x00004040, 304 0x000d, 0x00000040, 0x00004040,
303 0x2440, 0x07ffffff, 0x03000000, 305 0x2440, 0x07ffffff, 0x03000000,
304 0x2440, 0x07ffffff, 0x03000000,
305 0x23a2, 0x01ff1f3f, 0x00000000,
306 0x23a3, 0x01ff1f3f, 0x00000000,
307 0x23a2, 0x01ff1f3f, 0x00000000, 306 0x23a2, 0x01ff1f3f, 0x00000000,
308 0x23a1, 0x01ff1f3f, 0x00000000, 307 0x23a1, 0x01ff1f3f, 0x00000000,
309 0x23a1, 0x01ff1f3f, 0x00000000,
310
311 0x23a1, 0x01ff1f3f, 0x00000000,
312 0x2418, 0x0000007f, 0x00000020, 308 0x2418, 0x0000007f, 0x00000020,
313 0x2542, 0x00010000, 0x00010000, 309 0x2542, 0x00010000, 0x00010000,
314 0x2b01, 0x000003ff, 0x00000003,
315 0x2b05, 0x000003ff, 0x00000003,
316 0x2b05, 0x000003ff, 0x00000003, 310 0x2b05, 0x000003ff, 0x00000003,
317 0x2b04, 0xffffffff, 0x00000000, 311 0x2b04, 0xffffffff, 0x00000000,
318 0x2b04, 0xffffffff, 0x00000000,
319 0x2b04, 0xffffffff, 0x00000000,
320 0x2b03, 0xffffffff, 0x00001032,
321 0x2b03, 0xffffffff, 0x00001032,
322 0x2b03, 0xffffffff, 0x00001032, 312 0x2b03, 0xffffffff, 0x00001032,
323 0x2235, 0x0000001f, 0x00000010, 313 0x2235, 0x0000001f, 0x00000010,
324 0x2235, 0x0000001f, 0x00000010, 314 0x0570, 0x000c0fc0, 0x000c0400,
325 0x2235, 0x0000001f, 0x00000010, 315 0x052c, 0x0fffffff, 0xffffffff,
326 0x0570, 0x000c0fc0, 0x000c0400 316 0x052d, 0x0fffffff, 0x0fffffff,
317 0x052e, 0x0fffffff, 0x0fffffff,
318 0x052f, 0x0fffffff, 0x0fffffff
327}; 319};
328 320
329static const u32 oland_golden_registers[] = 321static const u32 oland_golden_registers[] =
330{ 322{
323 0x17bc, 0x00000030, 0x00000011,
331 0x2684, 0x00010000, 0x00018208, 324 0x2684, 0x00010000, 0x00018208,
332 0x260c, 0xffffffff, 0x00000000, 325 0x260c, 0xffffffff, 0x00000000,
333 0x260d, 0xf00fffff, 0x00000400, 326 0x260d, 0xf00fffff, 0x00000400,
@@ -336,7 +329,7 @@ static const u32 oland_golden_registers[] =
336 0x340c, 0x000300c0, 0x00800040, 329 0x340c, 0x000300c0, 0x00800040,
337 0x360c, 0x000300c0, 0x00800040, 330 0x360c, 0x000300c0, 0x00800040,
338 0x16ec, 0x000000f0, 0x00000070, 331 0x16ec, 0x000000f0, 0x00000070,
339 0x16f9, 0x00200000, 0x50100000, 332 0x16f0, 0x00200000, 0x50100000,
340 0x1c0c, 0x31000311, 0x00000011, 333 0x1c0c, 0x31000311, 0x00000011,
341 0x0ab9, 0x00073ffe, 0x000022a2, 334 0x0ab9, 0x00073ffe, 0x000022a2,
342 0x0903, 0x000007ff, 0x00000000, 335 0x0903, 0x000007ff, 0x00000000,
@@ -345,7 +338,7 @@ static const u32 oland_golden_registers[] =
345 0x22c4, 0x0000ff0f, 0x00000000, 338 0x22c4, 0x0000ff0f, 0x00000000,
346 0xa293, 0x07ffffff, 0x4e000000, 339 0xa293, 0x07ffffff, 0x4e000000,
347 0xa0d4, 0x3f3f3fff, 0x00000082, 340 0xa0d4, 0x3f3f3fff, 0x00000082,
348 0x000c, 0x000000ff, 0x0040, 341 0x000c, 0xffffffff, 0x0040,
349 0x000d, 0x00000040, 0x00004040, 342 0x000d, 0x00000040, 0x00004040,
350 0x2440, 0x07ffffff, 0x03000000, 343 0x2440, 0x07ffffff, 0x03000000,
351 0x2418, 0x0000007f, 0x00000020, 344 0x2418, 0x0000007f, 0x00000020,
@@ -354,11 +347,16 @@ static const u32 oland_golden_registers[] =
354 0x2b04, 0xffffffff, 0x00000000, 347 0x2b04, 0xffffffff, 0x00000000,
355 0x2b03, 0xffffffff, 0x00003210, 348 0x2b03, 0xffffffff, 0x00003210,
356 0x2235, 0x0000001f, 0x00000010, 349 0x2235, 0x0000001f, 0x00000010,
357 0x0570, 0x000c0fc0, 0x000c0400 350 0x0570, 0x000c0fc0, 0x000c0400,
351 0x052c, 0x0fffffff, 0xffffffff,
352 0x052d, 0x0fffffff, 0x0fffffff,
353 0x052e, 0x0fffffff, 0x0fffffff,
354 0x052f, 0x0fffffff, 0x0fffffff
358}; 355};
359 356
360static const u32 oland_golden_rlc_registers[] = 357static const u32 oland_golden_rlc_registers[] =
361{ 358{
359 0x263e, 0xffffffff, 0x02010002,
362 0x3109, 0xffffffff, 0x00601005, 360 0x3109, 0xffffffff, 0x00601005,
363 0x311f, 0xffffffff, 0x10104040, 361 0x311f, 0xffffffff, 0x10104040,
364 0x3122, 0xffffffff, 0x0100000a, 362 0x3122, 0xffffffff, 0x0100000a,
@@ -368,22 +366,27 @@ static const u32 oland_golden_rlc_registers[] =
368 366
369static const u32 hainan_golden_registers[] = 367static const u32 hainan_golden_registers[] =
370{ 368{
369 0x17bc, 0x00000030, 0x00000011,
371 0x2684, 0x00010000, 0x00018208, 370 0x2684, 0x00010000, 0x00018208,
372 0x260c, 0xffffffff, 0x00000000, 371 0x260c, 0xffffffff, 0x00000000,
373 0x260d, 0xf00fffff, 0x00000400, 372 0x260d, 0xf00fffff, 0x00000400,
374 0x260e, 0x0002021c, 0x00020200, 373 0x260e, 0x0002021c, 0x00020200,
375 0x4595, 0xff000fff, 0x00000100, 374 0x031e, 0x00000080, 0x00000000,
375 0x3430, 0xff000fff, 0x00000100,
376 0x340c, 0x000300c0, 0x00800040, 376 0x340c, 0x000300c0, 0x00800040,
377 0x3630, 0xff000fff, 0x00000100, 377 0x3630, 0xff000fff, 0x00000100,
378 0x360c, 0x000300c0, 0x00800040, 378 0x360c, 0x000300c0, 0x00800040,
379 0x16ec, 0x000000f0, 0x00000070,
380 0x16f0, 0x00200000, 0x50100000,
381 0x1c0c, 0x31000311, 0x00000011,
379 0x0ab9, 0x00073ffe, 0x000022a2, 382 0x0ab9, 0x00073ffe, 0x000022a2,
380 0x0903, 0x000007ff, 0x00000000, 383 0x0903, 0x000007ff, 0x00000000,
381 0x2285, 0xf000001f, 0x00000007, 384 0x2285, 0xf000001f, 0x00000007,
382 0x22c9, 0xffffffff, 0x00ffffff, 385 0x22c9, 0xffffffff, 0x00ffffff,
383 0x22c4, 0x0000ff0f, 0x00000000, 386 0x22c4, 0x0000ff0f, 0x00000000,
384 0xa393, 0x07ffffff, 0x4e000000, 387 0xa293, 0x07ffffff, 0x4e000000,
385 0xa0d4, 0x3f3f3fff, 0x00000000, 388 0xa0d4, 0x3f3f3fff, 0x00000000,
386 0x000c, 0x000000ff, 0x0040, 389 0x000c, 0xffffffff, 0x0040,
387 0x000d, 0x00000040, 0x00004040, 390 0x000d, 0x00000040, 0x00004040,
388 0x2440, 0x03e00000, 0x03600000, 391 0x2440, 0x03e00000, 0x03600000,
389 0x2418, 0x0000007f, 0x00000020, 392 0x2418, 0x0000007f, 0x00000020,
@@ -392,12 +395,16 @@ static const u32 hainan_golden_registers[] =
392 0x2b04, 0xffffffff, 0x00000000, 395 0x2b04, 0xffffffff, 0x00000000,
393 0x2b03, 0xffffffff, 0x00003210, 396 0x2b03, 0xffffffff, 0x00003210,
394 0x2235, 0x0000001f, 0x00000010, 397 0x2235, 0x0000001f, 0x00000010,
395 0x0570, 0x000c0fc0, 0x000c0400 398 0x0570, 0x000c0fc0, 0x000c0400,
399 0x052c, 0x0fffffff, 0xffffffff,
400 0x052d, 0x0fffffff, 0x0fffffff,
401 0x052e, 0x0fffffff, 0x0fffffff,
402 0x052f, 0x0fffffff, 0x0fffffff
396}; 403};
397 404
398static const u32 hainan_golden_registers2[] = 405static const u32 hainan_golden_registers2[] =
399{ 406{
400 0x263e, 0xffffffff, 0x02010001 407 0x263e, 0xffffffff, 0x2011003
401}; 408};
402 409
403static const u32 tahiti_mgcg_cgcg_init[] = 410static const u32 tahiti_mgcg_cgcg_init[] =
@@ -513,18 +520,18 @@ static const u32 tahiti_mgcg_cgcg_init[] =
513 0x21c2, 0xffffffff, 0x00900100, 520 0x21c2, 0xffffffff, 0x00900100,
514 0x311e, 0xffffffff, 0x00000080, 521 0x311e, 0xffffffff, 0x00000080,
515 0x3101, 0xffffffff, 0x0020003f, 522 0x3101, 0xffffffff, 0x0020003f,
516 0xc, 0xffffffff, 0x0000001c, 523 0x000c, 0xffffffff, 0x0000001c,
517 0xd, 0x000f0000, 0x000f0000, 524 0x000d, 0x000f0000, 0x000f0000,
518 0x583, 0xffffffff, 0x00000100, 525 0x0583, 0xffffffff, 0x00000100,
519 0x409, 0xffffffff, 0x00000100, 526 0x0409, 0xffffffff, 0x00000100,
520 0x40b, 0x00000101, 0x00000000, 527 0x040b, 0x00000101, 0x00000000,
521 0x82a, 0xffffffff, 0x00000104, 528 0x082a, 0xffffffff, 0x00000104,
522 0x993, 0x000c0000, 0x000c0000, 529 0x0993, 0x000c0000, 0x000c0000,
523 0x992, 0x000c0000, 0x000c0000, 530 0x0992, 0x000c0000, 0x000c0000,
524 0x1579, 0xff000fff, 0x00000100, 531 0x1579, 0xff000fff, 0x00000100,
525 0x157a, 0x00000001, 0x00000001, 532 0x157a, 0x00000001, 0x00000001,
526 0xbd4, 0x00000001, 0x00000001, 533 0x0bd4, 0x00000001, 0x00000001,
527 0xc33, 0xc0000fff, 0x00000104, 534 0x0c33, 0xc0000fff, 0x00000104,
528 0x3079, 0x00000001, 0x00000001, 535 0x3079, 0x00000001, 0x00000001,
529 0x3430, 0xfffffff0, 0x00000100, 536 0x3430, 0xfffffff0, 0x00000100,
530 0x3630, 0xfffffff0, 0x00000100 537 0x3630, 0xfffffff0, 0x00000100
@@ -612,16 +619,16 @@ static const u32 pitcairn_mgcg_cgcg_init[] =
612 0x21c2, 0xffffffff, 0x00900100, 619 0x21c2, 0xffffffff, 0x00900100,
613 0x311e, 0xffffffff, 0x00000080, 620 0x311e, 0xffffffff, 0x00000080,
614 0x3101, 0xffffffff, 0x0020003f, 621 0x3101, 0xffffffff, 0x0020003f,
615 0xc, 0xffffffff, 0x0000001c, 622 0x000c, 0xffffffff, 0x0000001c,
616 0xd, 0x000f0000, 0x000f0000, 623 0x000d, 0x000f0000, 0x000f0000,
617 0x583, 0xffffffff, 0x00000100, 624 0x0583, 0xffffffff, 0x00000100,
618 0x409, 0xffffffff, 0x00000100, 625 0x0409, 0xffffffff, 0x00000100,
619 0x40b, 0x00000101, 0x00000000, 626 0x040b, 0x00000101, 0x00000000,
620 0x82a, 0xffffffff, 0x00000104, 627 0x082a, 0xffffffff, 0x00000104,
621 0x1579, 0xff000fff, 0x00000100, 628 0x1579, 0xff000fff, 0x00000100,
622 0x157a, 0x00000001, 0x00000001, 629 0x157a, 0x00000001, 0x00000001,
623 0xbd4, 0x00000001, 0x00000001, 630 0x0bd4, 0x00000001, 0x00000001,
624 0xc33, 0xc0000fff, 0x00000104, 631 0x0c33, 0xc0000fff, 0x00000104,
625 0x3079, 0x00000001, 0x00000001, 632 0x3079, 0x00000001, 0x00000001,
626 0x3430, 0xfffffff0, 0x00000100, 633 0x3430, 0xfffffff0, 0x00000100,
627 0x3630, 0xfffffff0, 0x00000100 634 0x3630, 0xfffffff0, 0x00000100
@@ -709,18 +716,18 @@ static const u32 verde_mgcg_cgcg_init[] =
709 0x21c2, 0xffffffff, 0x00900100, 716 0x21c2, 0xffffffff, 0x00900100,
710 0x311e, 0xffffffff, 0x00000080, 717 0x311e, 0xffffffff, 0x00000080,
711 0x3101, 0xffffffff, 0x0020003f, 718 0x3101, 0xffffffff, 0x0020003f,
712 0xc, 0xffffffff, 0x0000001c, 719 0x000c, 0xffffffff, 0x0000001c,
713 0xd, 0x000f0000, 0x000f0000, 720 0x000d, 0x000f0000, 0x000f0000,
714 0x583, 0xffffffff, 0x00000100, 721 0x0583, 0xffffffff, 0x00000100,
715 0x409, 0xffffffff, 0x00000100, 722 0x0409, 0xffffffff, 0x00000100,
716 0x40b, 0x00000101, 0x00000000, 723 0x040b, 0x00000101, 0x00000000,
717 0x82a, 0xffffffff, 0x00000104, 724 0x082a, 0xffffffff, 0x00000104,
718 0x993, 0x000c0000, 0x000c0000, 725 0x0993, 0x000c0000, 0x000c0000,
719 0x992, 0x000c0000, 0x000c0000, 726 0x0992, 0x000c0000, 0x000c0000,
720 0x1579, 0xff000fff, 0x00000100, 727 0x1579, 0xff000fff, 0x00000100,
721 0x157a, 0x00000001, 0x00000001, 728 0x157a, 0x00000001, 0x00000001,
722 0xbd4, 0x00000001, 0x00000001, 729 0x0bd4, 0x00000001, 0x00000001,
723 0xc33, 0xc0000fff, 0x00000104, 730 0x0c33, 0xc0000fff, 0x00000104,
724 0x3079, 0x00000001, 0x00000001, 731 0x3079, 0x00000001, 0x00000001,
725 0x3430, 0xfffffff0, 0x00000100, 732 0x3430, 0xfffffff0, 0x00000100,
726 0x3630, 0xfffffff0, 0x00000100 733 0x3630, 0xfffffff0, 0x00000100
@@ -788,18 +795,18 @@ static const u32 oland_mgcg_cgcg_init[] =
788 0x21c2, 0xffffffff, 0x00900100, 795 0x21c2, 0xffffffff, 0x00900100,
789 0x311e, 0xffffffff, 0x00000080, 796 0x311e, 0xffffffff, 0x00000080,
790 0x3101, 0xffffffff, 0x0020003f, 797 0x3101, 0xffffffff, 0x0020003f,
791 0xc, 0xffffffff, 0x0000001c, 798 0x000c, 0xffffffff, 0x0000001c,
792 0xd, 0x000f0000, 0x000f0000, 799 0x000d, 0x000f0000, 0x000f0000,
793 0x583, 0xffffffff, 0x00000100, 800 0x0583, 0xffffffff, 0x00000100,
794 0x409, 0xffffffff, 0x00000100, 801 0x0409, 0xffffffff, 0x00000100,
795 0x40b, 0x00000101, 0x00000000, 802 0x040b, 0x00000101, 0x00000000,
796 0x82a, 0xffffffff, 0x00000104, 803 0x082a, 0xffffffff, 0x00000104,
797 0x993, 0x000c0000, 0x000c0000, 804 0x0993, 0x000c0000, 0x000c0000,
798 0x992, 0x000c0000, 0x000c0000, 805 0x0992, 0x000c0000, 0x000c0000,
799 0x1579, 0xff000fff, 0x00000100, 806 0x1579, 0xff000fff, 0x00000100,
800 0x157a, 0x00000001, 0x00000001, 807 0x157a, 0x00000001, 0x00000001,
801 0xbd4, 0x00000001, 0x00000001, 808 0x0bd4, 0x00000001, 0x00000001,
802 0xc33, 0xc0000fff, 0x00000104, 809 0x0c33, 0xc0000fff, 0x00000104,
803 0x3079, 0x00000001, 0x00000001, 810 0x3079, 0x00000001, 0x00000001,
804 0x3430, 0xfffffff0, 0x00000100, 811 0x3430, 0xfffffff0, 0x00000100,
805 0x3630, 0xfffffff0, 0x00000100 812 0x3630, 0xfffffff0, 0x00000100
@@ -867,15 +874,15 @@ static const u32 hainan_mgcg_cgcg_init[] =
867 0x21c2, 0xffffffff, 0x00900100, 874 0x21c2, 0xffffffff, 0x00900100,
868 0x311e, 0xffffffff, 0x00000080, 875 0x311e, 0xffffffff, 0x00000080,
869 0x3101, 0xffffffff, 0x0020003f, 876 0x3101, 0xffffffff, 0x0020003f,
870 0xc, 0xffffffff, 0x0000001c, 877 0x000c, 0xffffffff, 0x0000001c,
871 0xd, 0x000f0000, 0x000f0000, 878 0x000d, 0x000f0000, 0x000f0000,
872 0x583, 0xffffffff, 0x00000100, 879 0x0583, 0xffffffff, 0x00000100,
873 0x409, 0xffffffff, 0x00000100, 880 0x0409, 0xffffffff, 0x00000100,
874 0x82a, 0xffffffff, 0x00000104, 881 0x082a, 0xffffffff, 0x00000104,
875 0x993, 0x000c0000, 0x000c0000, 882 0x0993, 0x000c0000, 0x000c0000,
876 0x992, 0x000c0000, 0x000c0000, 883 0x0992, 0x000c0000, 0x000c0000,
877 0xbd4, 0x00000001, 0x00000001, 884 0x0bd4, 0x00000001, 0x00000001,
878 0xc33, 0xc0000fff, 0x00000104, 885 0x0c33, 0xc0000fff, 0x00000104,
879 0x3079, 0x00000001, 0x00000001, 886 0x3079, 0x00000001, 0x00000001,
880 0x3430, 0xfffffff0, 0x00000100, 887 0x3430, 0xfffffff0, 0x00000100,
881 0x3630, 0xfffffff0, 0x00000100 888 0x3630, 0xfffffff0, 0x00000100
@@ -1179,6 +1186,8 @@ static int si_common_early_init(void *handle)
1179 AMD_CG_SUPPORT_HDP_LS | 1186 AMD_CG_SUPPORT_HDP_LS |
1180 AMD_CG_SUPPORT_HDP_MGCG; 1187 AMD_CG_SUPPORT_HDP_MGCG;
1181 adev->pg_flags = 0; 1188 adev->pg_flags = 0;
1189 adev->external_rev_id = (adev->rev_id == 0) ? 1 :
1190 (adev->rev_id == 1) ? 5 : 6;
1182 break; 1191 break;
1183 case CHIP_PITCAIRN: 1192 case CHIP_PITCAIRN:
1184 adev->cg_flags = 1193 adev->cg_flags =
@@ -1198,6 +1207,7 @@ static int si_common_early_init(void *handle)
1198 AMD_CG_SUPPORT_HDP_LS | 1207 AMD_CG_SUPPORT_HDP_LS |
1199 AMD_CG_SUPPORT_HDP_MGCG; 1208 AMD_CG_SUPPORT_HDP_MGCG;
1200 adev->pg_flags = 0; 1209 adev->pg_flags = 0;
1210 adev->external_rev_id = adev->rev_id + 20;
1201 break; 1211 break;
1202 1212
1203 case CHIP_VERDE: 1213 case CHIP_VERDE:
@@ -1219,7 +1229,7 @@ static int si_common_early_init(void *handle)
1219 AMD_CG_SUPPORT_HDP_MGCG; 1229 AMD_CG_SUPPORT_HDP_MGCG;
1220 adev->pg_flags = 0; 1230 adev->pg_flags = 0;
1221 //??? 1231 //???
1222 adev->external_rev_id = adev->rev_id + 0x14; 1232 adev->external_rev_id = adev->rev_id + 40;
1223 break; 1233 break;
1224 case CHIP_OLAND: 1234 case CHIP_OLAND:
1225 adev->cg_flags = 1235 adev->cg_flags =
@@ -1238,6 +1248,7 @@ static int si_common_early_init(void *handle)
1238 AMD_CG_SUPPORT_HDP_LS | 1248 AMD_CG_SUPPORT_HDP_LS |
1239 AMD_CG_SUPPORT_HDP_MGCG; 1249 AMD_CG_SUPPORT_HDP_MGCG;
1240 adev->pg_flags = 0; 1250 adev->pg_flags = 0;
1251 adev->external_rev_id = 60;
1241 break; 1252 break;
1242 case CHIP_HAINAN: 1253 case CHIP_HAINAN:
1243 adev->cg_flags = 1254 adev->cg_flags =
@@ -1255,6 +1266,7 @@ static int si_common_early_init(void *handle)
1255 AMD_CG_SUPPORT_HDP_LS | 1266 AMD_CG_SUPPORT_HDP_LS |
1256 AMD_CG_SUPPORT_HDP_MGCG; 1267 AMD_CG_SUPPORT_HDP_MGCG;
1257 adev->pg_flags = 0; 1268 adev->pg_flags = 0;
1269 adev->external_rev_id = 70;
1258 break; 1270 break;
1259 1271
1260 default: 1272 default:
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 9f771f4ffcb7..bf088d6d9bf1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -932,18 +932,64 @@ static int vi_common_early_init(void *handle)
932 adev->external_rev_id = adev->rev_id + 0x3c; 932 adev->external_rev_id = adev->rev_id + 0x3c;
933 break; 933 break;
934 case CHIP_TONGA: 934 case CHIP_TONGA:
935 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; 935 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
936 adev->pg_flags = AMD_PG_SUPPORT_UVD; 936 AMD_CG_SUPPORT_GFX_CGCG |
937 AMD_CG_SUPPORT_GFX_CGLS |
938 AMD_CG_SUPPORT_SDMA_MGCG |
939 AMD_CG_SUPPORT_SDMA_LS |
940 AMD_CG_SUPPORT_BIF_LS |
941 AMD_CG_SUPPORT_HDP_MGCG |
942 AMD_CG_SUPPORT_HDP_LS |
943 AMD_CG_SUPPORT_ROM_MGCG |
944 AMD_CG_SUPPORT_MC_MGCG |
945 AMD_CG_SUPPORT_MC_LS |
946 AMD_CG_SUPPORT_DRM_LS |
947 AMD_CG_SUPPORT_UVD_MGCG;
948 adev->pg_flags = 0;
937 adev->external_rev_id = adev->rev_id + 0x14; 949 adev->external_rev_id = adev->rev_id + 0x14;
938 break; 950 break;
939 case CHIP_POLARIS11: 951 case CHIP_POLARIS11:
940 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | 952 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
953 AMD_CG_SUPPORT_GFX_RLC_LS |
954 AMD_CG_SUPPORT_GFX_CP_LS |
955 AMD_CG_SUPPORT_GFX_CGCG |
956 AMD_CG_SUPPORT_GFX_CGLS |
957 AMD_CG_SUPPORT_GFX_3D_CGCG |
958 AMD_CG_SUPPORT_GFX_3D_CGLS |
959 AMD_CG_SUPPORT_SDMA_MGCG |
960 AMD_CG_SUPPORT_SDMA_LS |
961 AMD_CG_SUPPORT_BIF_MGCG |
962 AMD_CG_SUPPORT_BIF_LS |
963 AMD_CG_SUPPORT_HDP_MGCG |
964 AMD_CG_SUPPORT_HDP_LS |
965 AMD_CG_SUPPORT_ROM_MGCG |
966 AMD_CG_SUPPORT_MC_MGCG |
967 AMD_CG_SUPPORT_MC_LS |
968 AMD_CG_SUPPORT_DRM_LS |
969 AMD_CG_SUPPORT_UVD_MGCG |
941 AMD_CG_SUPPORT_VCE_MGCG; 970 AMD_CG_SUPPORT_VCE_MGCG;
942 adev->pg_flags = 0; 971 adev->pg_flags = 0;
943 adev->external_rev_id = adev->rev_id + 0x5A; 972 adev->external_rev_id = adev->rev_id + 0x5A;
944 break; 973 break;
945 case CHIP_POLARIS10: 974 case CHIP_POLARIS10:
946 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | 975 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
976 AMD_CG_SUPPORT_GFX_RLC_LS |
977 AMD_CG_SUPPORT_GFX_CP_LS |
978 AMD_CG_SUPPORT_GFX_CGCG |
979 AMD_CG_SUPPORT_GFX_CGLS |
980 AMD_CG_SUPPORT_GFX_3D_CGCG |
981 AMD_CG_SUPPORT_GFX_3D_CGLS |
982 AMD_CG_SUPPORT_SDMA_MGCG |
983 AMD_CG_SUPPORT_SDMA_LS |
984 AMD_CG_SUPPORT_BIF_MGCG |
985 AMD_CG_SUPPORT_BIF_LS |
986 AMD_CG_SUPPORT_HDP_MGCG |
987 AMD_CG_SUPPORT_HDP_LS |
988 AMD_CG_SUPPORT_ROM_MGCG |
989 AMD_CG_SUPPORT_MC_MGCG |
990 AMD_CG_SUPPORT_MC_LS |
991 AMD_CG_SUPPORT_DRM_LS |
992 AMD_CG_SUPPORT_UVD_MGCG |
947 AMD_CG_SUPPORT_VCE_MGCG; 993 AMD_CG_SUPPORT_VCE_MGCG;
948 adev->pg_flags = 0; 994 adev->pg_flags = 0;
949 adev->external_rev_id = adev->rev_id + 0x50; 995 adev->external_rev_id = adev->rev_id + 0x50;
@@ -971,6 +1017,7 @@ static int vi_common_early_init(void *handle)
971 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1017 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
972 AMD_PG_SUPPORT_GFX_SMG | 1018 AMD_PG_SUPPORT_GFX_SMG |
973 AMD_PG_SUPPORT_GFX_PIPELINE | 1019 AMD_PG_SUPPORT_GFX_PIPELINE |
1020 AMD_PG_SUPPORT_CP |
974 AMD_PG_SUPPORT_UVD | 1021 AMD_PG_SUPPORT_UVD |
975 AMD_PG_SUPPORT_VCE; 1022 AMD_PG_SUPPORT_VCE;
976 } 1023 }
@@ -996,6 +1043,7 @@ static int vi_common_early_init(void *handle)
996 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 1043 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
997 AMD_PG_SUPPORT_GFX_SMG | 1044 AMD_PG_SUPPORT_GFX_SMG |
998 AMD_PG_SUPPORT_GFX_PIPELINE | 1045 AMD_PG_SUPPORT_GFX_PIPELINE |
1046 AMD_PG_SUPPORT_CP |
999 AMD_PG_SUPPORT_UVD | 1047 AMD_PG_SUPPORT_UVD |
1000 AMD_PG_SUPPORT_VCE; 1048 AMD_PG_SUPPORT_VCE;
1001 adev->external_rev_id = adev->rev_id + 0x61; 1049 adev->external_rev_id = adev->rev_id + 0x61;
@@ -1155,57 +1203,118 @@ static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1155static int vi_common_set_clockgating_state_by_smu(void *handle, 1203static int vi_common_set_clockgating_state_by_smu(void *handle,
1156 enum amd_clockgating_state state) 1204 enum amd_clockgating_state state)
1157{ 1205{
1158 uint32_t msg_id, pp_state; 1206 uint32_t msg_id, pp_state = 0;
1207 uint32_t pp_support_state = 0;
1159 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1208 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1160 void *pp_handle = adev->powerplay.pp_handle; 1209 void *pp_handle = adev->powerplay.pp_handle;
1161 1210
1162 if (state == AMD_CG_STATE_UNGATE) 1211 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1163 pp_state = 0; 1212 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
1164 else 1213 pp_support_state = AMD_CG_SUPPORT_MC_LS;
1165 pp_state = PP_STATE_CG | PP_STATE_LS; 1214 pp_state = PP_STATE_LS;
1166 1215 }
1167 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1216 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
1168 PP_BLOCK_SYS_MC, 1217 pp_support_state |= AMD_CG_SUPPORT_MC_MGCG;
1169 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 1218 pp_state |= PP_STATE_CG;
1170 pp_state); 1219 }
1171 amd_set_clockgating_by_smu(pp_handle, msg_id); 1220 if (state == AMD_CG_STATE_UNGATE)
1172 1221 pp_state = 0;
1173 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1222 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1174 PP_BLOCK_SYS_SDMA, 1223 PP_BLOCK_SYS_MC,
1175 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 1224 pp_support_state,
1176 pp_state); 1225 pp_state);
1177 amd_set_clockgating_by_smu(pp_handle, msg_id); 1226 amd_set_clockgating_by_smu(pp_handle, msg_id);
1178 1227 }
1179 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1228
1180 PP_BLOCK_SYS_HDP, 1229 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1181 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 1230 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
1182 pp_state); 1231 pp_support_state = AMD_CG_SUPPORT_SDMA_LS;
1183 amd_set_clockgating_by_smu(pp_handle, msg_id); 1232 pp_state = PP_STATE_LS;
1184 1233 }
1185 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1234 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
1186 PP_BLOCK_SYS_BIF, 1235 pp_support_state |= AMD_CG_SUPPORT_SDMA_MGCG;
1187 PP_STATE_SUPPORT_LS, 1236 pp_state |= PP_STATE_CG;
1188 pp_state); 1237 }
1189 amd_set_clockgating_by_smu(pp_handle, msg_id); 1238 if (state == AMD_CG_STATE_UNGATE)
1190 1239 pp_state = 0;
1191 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1240 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1192 PP_BLOCK_SYS_BIF, 1241 PP_BLOCK_SYS_SDMA,
1193 PP_STATE_SUPPORT_CG, 1242 pp_support_state,
1194 pp_state); 1243 pp_state);
1195 amd_set_clockgating_by_smu(pp_handle, msg_id); 1244 amd_set_clockgating_by_smu(pp_handle, msg_id);
1196 1245 }
1197 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1246
1198 PP_BLOCK_SYS_DRM, 1247 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1199 PP_STATE_SUPPORT_LS, 1248 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
1200 pp_state); 1249 pp_support_state = AMD_CG_SUPPORT_HDP_LS;
1201 amd_set_clockgating_by_smu(pp_handle, msg_id); 1250 pp_state = PP_STATE_LS;
1202 1251 }
1203 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1252 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
1204 PP_BLOCK_SYS_ROM, 1253 pp_support_state |= AMD_CG_SUPPORT_HDP_MGCG;
1205 PP_STATE_SUPPORT_CG, 1254 pp_state |= PP_STATE_CG;
1206 pp_state); 1255 }
1207 amd_set_clockgating_by_smu(pp_handle, msg_id); 1256 if (state == AMD_CG_STATE_UNGATE)
1257 pp_state = 0;
1258 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1259 PP_BLOCK_SYS_HDP,
1260 pp_support_state,
1261 pp_state);
1262 amd_set_clockgating_by_smu(pp_handle, msg_id);
1263 }
1208 1264
1265
1266 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
1267 if (state == AMD_CG_STATE_UNGATE)
1268 pp_state = 0;
1269 else
1270 pp_state = PP_STATE_LS;
1271
1272 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1273 PP_BLOCK_SYS_BIF,
1274 PP_STATE_SUPPORT_LS,
1275 pp_state);
1276 amd_set_clockgating_by_smu(pp_handle, msg_id);
1277 }
1278 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
1279 if (state == AMD_CG_STATE_UNGATE)
1280 pp_state = 0;
1281 else
1282 pp_state = PP_STATE_CG;
1283
1284 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1285 PP_BLOCK_SYS_BIF,
1286 PP_STATE_SUPPORT_CG,
1287 pp_state);
1288 amd_set_clockgating_by_smu(pp_handle, msg_id);
1289 }
1290
1291 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
1292
1293 if (state == AMD_CG_STATE_UNGATE)
1294 pp_state = 0;
1295 else
1296 pp_state = PP_STATE_LS;
1297
1298 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1299 PP_BLOCK_SYS_DRM,
1300 PP_STATE_SUPPORT_LS,
1301 pp_state);
1302 amd_set_clockgating_by_smu(pp_handle, msg_id);
1303 }
1304
1305 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
1306
1307 if (state == AMD_CG_STATE_UNGATE)
1308 pp_state = 0;
1309 else
1310 pp_state = PP_STATE_CG;
1311
1312 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1313 PP_BLOCK_SYS_ROM,
1314 PP_STATE_SUPPORT_CG,
1315 pp_state);
1316 amd_set_clockgating_by_smu(pp_handle, msg_id);
1317 }
1209 return 0; 1318 return 0;
1210} 1319}
1211 1320
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index d1986276dbbd..c02469ada9f1 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -126,6 +126,10 @@ enum amd_vce_level {
126#define AMD_CG_SUPPORT_HDP_LS (1 << 15) 126#define AMD_CG_SUPPORT_HDP_LS (1 << 15)
127#define AMD_CG_SUPPORT_HDP_MGCG (1 << 16) 127#define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
128#define AMD_CG_SUPPORT_ROM_MGCG (1 << 17) 128#define AMD_CG_SUPPORT_ROM_MGCG (1 << 17)
129#define AMD_CG_SUPPORT_DRM_LS (1 << 18)
130#define AMD_CG_SUPPORT_BIF_MGCG (1 << 19)
131#define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20)
132#define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21)
129 133
130/* PG flags */ 134/* PG flags */
131#define AMD_PG_SUPPORT_GFX_PG (1 << 0) 135#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index 904beaa932d0..f75c6421db62 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -223,7 +223,8 @@ static int ast_get_dram_info(struct drm_device *dev)
223 ast_write32(ast, 0x10000, 0xfc600309); 223 ast_write32(ast, 0x10000, 0xfc600309);
224 224
225 do { 225 do {
226 ; 226 if (pci_channel_offline(dev->pdev))
227 return -EIO;
227 } while (ast_read32(ast, 0x10000) != 0x01); 228 } while (ast_read32(ast, 0x10000) != 0x01);
228 data = ast_read32(ast, 0x10004); 229 data = ast_read32(ast, 0x10004);
229 230
@@ -428,7 +429,9 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
428 ast_detect_chip(dev, &need_post); 429 ast_detect_chip(dev, &need_post);
429 430
430 if (ast->chip != AST1180) { 431 if (ast->chip != AST1180) {
431 ast_get_dram_info(dev); 432 ret = ast_get_dram_info(dev);
433 if (ret)
434 goto out_free;
432 ast->vram_size = ast_get_vram_info(dev); 435 ast->vram_size = ast_get_vram_info(dev);
433 DRM_INFO("dram %d %d %d %08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size); 436 DRM_INFO("dram %d %d %d %08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size);
434 } 437 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 56002a52936d..243224aeabf8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3509,6 +3509,8 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3509 3509
3510int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); 3510int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3511int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); 3511int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3512int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3513 u32 reply_mask, u32 reply, int timeout_base_ms);
3512 3514
3513/* intel_sideband.c */ 3515/* intel_sideband.c */
3514u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); 3516u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 412f3513f269..4a31b7a891ec 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -174,21 +174,35 @@ static struct sg_table *
174i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) 174i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
175{ 175{
176 struct address_space *mapping = obj->base.filp->f_mapping; 176 struct address_space *mapping = obj->base.filp->f_mapping;
177 char *vaddr = obj->phys_handle->vaddr; 177 drm_dma_handle_t *phys;
178 struct sg_table *st; 178 struct sg_table *st;
179 struct scatterlist *sg; 179 struct scatterlist *sg;
180 char *vaddr;
180 int i; 181 int i;
181 182
182 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) 183 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
183 return ERR_PTR(-EINVAL); 184 return ERR_PTR(-EINVAL);
184 185
186 /* Always aligning to the object size, allows a single allocation
187 * to handle all possible callers, and given typical object sizes,
188 * the alignment of the buddy allocation will naturally match.
189 */
190 phys = drm_pci_alloc(obj->base.dev,
191 obj->base.size,
192 roundup_pow_of_two(obj->base.size));
193 if (!phys)
194 return ERR_PTR(-ENOMEM);
195
196 vaddr = phys->vaddr;
185 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { 197 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
186 struct page *page; 198 struct page *page;
187 char *src; 199 char *src;
188 200
189 page = shmem_read_mapping_page(mapping, i); 201 page = shmem_read_mapping_page(mapping, i);
190 if (IS_ERR(page)) 202 if (IS_ERR(page)) {
191 return ERR_CAST(page); 203 st = ERR_CAST(page);
204 goto err_phys;
205 }
192 206
193 src = kmap_atomic(page); 207 src = kmap_atomic(page);
194 memcpy(vaddr, src, PAGE_SIZE); 208 memcpy(vaddr, src, PAGE_SIZE);
@@ -202,21 +216,29 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
202 i915_gem_chipset_flush(to_i915(obj->base.dev)); 216 i915_gem_chipset_flush(to_i915(obj->base.dev));
203 217
204 st = kmalloc(sizeof(*st), GFP_KERNEL); 218 st = kmalloc(sizeof(*st), GFP_KERNEL);
205 if (st == NULL) 219 if (!st) {
206 return ERR_PTR(-ENOMEM); 220 st = ERR_PTR(-ENOMEM);
221 goto err_phys;
222 }
207 223
208 if (sg_alloc_table(st, 1, GFP_KERNEL)) { 224 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
209 kfree(st); 225 kfree(st);
210 return ERR_PTR(-ENOMEM); 226 st = ERR_PTR(-ENOMEM);
227 goto err_phys;
211 } 228 }
212 229
213 sg = st->sgl; 230 sg = st->sgl;
214 sg->offset = 0; 231 sg->offset = 0;
215 sg->length = obj->base.size; 232 sg->length = obj->base.size;
216 233
217 sg_dma_address(sg) = obj->phys_handle->busaddr; 234 sg_dma_address(sg) = phys->busaddr;
218 sg_dma_len(sg) = obj->base.size; 235 sg_dma_len(sg) = obj->base.size;
219 236
237 obj->phys_handle = phys;
238 return st;
239
240err_phys:
241 drm_pci_free(obj->base.dev, phys);
220 return st; 242 return st;
221} 243}
222 244
@@ -272,12 +294,13 @@ i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
272 294
273 sg_free_table(pages); 295 sg_free_table(pages);
274 kfree(pages); 296 kfree(pages);
297
298 drm_pci_free(obj->base.dev, obj->phys_handle);
275} 299}
276 300
277static void 301static void
278i915_gem_object_release_phys(struct drm_i915_gem_object *obj) 302i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
279{ 303{
280 drm_pci_free(obj->base.dev, obj->phys_handle);
281 i915_gem_object_unpin_pages(obj); 304 i915_gem_object_unpin_pages(obj);
282} 305}
283 306
@@ -538,15 +561,13 @@ int
538i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, 561i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
539 int align) 562 int align)
540{ 563{
541 drm_dma_handle_t *phys;
542 int ret; 564 int ret;
543 565
544 if (obj->phys_handle) { 566 if (align > obj->base.size)
545 if ((unsigned long)obj->phys_handle->vaddr & (align -1)) 567 return -EINVAL;
546 return -EBUSY;
547 568
569 if (obj->ops == &i915_gem_phys_ops)
548 return 0; 570 return 0;
549 }
550 571
551 if (obj->mm.madv != I915_MADV_WILLNEED) 572 if (obj->mm.madv != I915_MADV_WILLNEED)
552 return -EFAULT; 573 return -EFAULT;
@@ -562,12 +583,6 @@ i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
562 if (obj->mm.pages) 583 if (obj->mm.pages)
563 return -EBUSY; 584 return -EBUSY;
564 585
565 /* create a new object */
566 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
567 if (!phys)
568 return -ENOMEM;
569
570 obj->phys_handle = phys;
571 obj->ops = &i915_gem_phys_ops; 586 obj->ops = &i915_gem_phys_ops;
572 587
573 return i915_gem_object_pin_pages(obj); 588 return i915_gem_object_pin_pages(obj);
@@ -2326,7 +2341,8 @@ static struct sg_table *
2326i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) 2341i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2327{ 2342{
2328 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 2343 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2329 int page_count, i; 2344 const unsigned long page_count = obj->base.size / PAGE_SIZE;
2345 unsigned long i;
2330 struct address_space *mapping; 2346 struct address_space *mapping;
2331 struct sg_table *st; 2347 struct sg_table *st;
2332 struct scatterlist *sg; 2348 struct scatterlist *sg;
@@ -2352,7 +2368,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2352 if (st == NULL) 2368 if (st == NULL)
2353 return ERR_PTR(-ENOMEM); 2369 return ERR_PTR(-ENOMEM);
2354 2370
2355 page_count = obj->base.size / PAGE_SIZE; 2371rebuild_st:
2356 if (sg_alloc_table(st, page_count, GFP_KERNEL)) { 2372 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2357 kfree(st); 2373 kfree(st);
2358 return ERR_PTR(-ENOMEM); 2374 return ERR_PTR(-ENOMEM);
@@ -2411,8 +2427,25 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2411 i915_sg_trim(st); 2427 i915_sg_trim(st);
2412 2428
2413 ret = i915_gem_gtt_prepare_pages(obj, st); 2429 ret = i915_gem_gtt_prepare_pages(obj, st);
2414 if (ret) 2430 if (ret) {
2415 goto err_pages; 2431 /* DMA remapping failed? One possible cause is that
2432 * it could not reserve enough large entries, asking
2433 * for PAGE_SIZE chunks instead may be helpful.
2434 */
2435 if (max_segment > PAGE_SIZE) {
2436 for_each_sgt_page(page, sgt_iter, st)
2437 put_page(page);
2438 sg_free_table(st);
2439
2440 max_segment = PAGE_SIZE;
2441 goto rebuild_st;
2442 } else {
2443 dev_warn(&dev_priv->drm.pdev->dev,
2444 "Failed to DMA remap %lu pages\n",
2445 page_count);
2446 goto err_pages;
2447 }
2448 }
2416 2449
2417 if (i915_gem_object_needs_bit17_swizzle(obj)) 2450 if (i915_gem_object_needs_bit17_swizzle(obj))
2418 i915_gem_object_do_bit_17_swizzle(obj, st); 2451 i915_gem_object_do_bit_17_swizzle(obj, st);
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index ebaa941c83af..abc78bbfc1dc 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -55,10 +55,9 @@ int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
55 return -ENODEV; 55 return -ENODEV;
56 56
57 /* See the comment at the drm_mm_init() call for more about this check. 57 /* See the comment at the drm_mm_init() call for more about this check.
58 * WaSkipStolenMemoryFirstPage:bdw,chv,kbl (incomplete) 58 * WaSkipStolenMemoryFirstPage:bdw+ (incomplete)
59 */ 59 */
60 if (start < 4096 && (IS_GEN8(dev_priv) || 60 if (start < 4096 && INTEL_GEN(dev_priv) >= 8)
61 IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)))
62 start = 4096; 61 start = 4096;
63 62
64 mutex_lock(&dev_priv->mm.stolen_lock); 63 mutex_lock(&dev_priv->mm.stolen_lock);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 47590ab08d7e..3df8d3dd31cd 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -460,7 +460,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
460 460
461static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL); 461static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL);
462static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL); 462static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
463static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO, gt_boost_freq_mhz_show, gt_boost_freq_mhz_store); 463static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO | S_IWUSR, gt_boost_freq_mhz_show, gt_boost_freq_mhz_store);
464static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store); 464static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
465static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store); 465static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
466 466
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 8405b5a367d7..7e3545f65257 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -46,14 +46,20 @@ struct edp_power_seq {
46 u16 t11_t12; 46 u16 t11_t12;
47} __packed; 47} __packed;
48 48
49/* MIPI Sequence Block definitions */ 49/*
50 * MIPI Sequence Block definitions
51 *
52 * Note the VBT spec has AssertReset / DeassertReset swapped from their
53 * usual naming, we use the proper names here to avoid confusion when
54 * reading the code.
55 */
50enum mipi_seq { 56enum mipi_seq {
51 MIPI_SEQ_END = 0, 57 MIPI_SEQ_END = 0,
52 MIPI_SEQ_ASSERT_RESET, 58 MIPI_SEQ_DEASSERT_RESET, /* Spec says MipiAssertResetPin */
53 MIPI_SEQ_INIT_OTP, 59 MIPI_SEQ_INIT_OTP,
54 MIPI_SEQ_DISPLAY_ON, 60 MIPI_SEQ_DISPLAY_ON,
55 MIPI_SEQ_DISPLAY_OFF, 61 MIPI_SEQ_DISPLAY_OFF,
56 MIPI_SEQ_DEASSERT_RESET, 62 MIPI_SEQ_ASSERT_RESET, /* Spec says MipiDeassertResetPin */
57 MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */ 63 MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */
58 MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */ 64 MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */
59 MIPI_SEQ_TEAR_ON, /* sequence block v2+ */ 65 MIPI_SEQ_TEAR_ON, /* sequence block v2+ */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cf5cff7b03b8..6daad8613760 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6244,35 +6244,24 @@ skl_dpll0_disable(struct drm_i915_private *dev_priv)
6244 dev_priv->cdclk_pll.vco = 0; 6244 dev_priv->cdclk_pll.vco = 0;
6245} 6245}
6246 6246
6247static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6248{
6249 int ret;
6250 u32 val;
6251
6252 /* inform PCU we want to change CDCLK */
6253 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6254 mutex_lock(&dev_priv->rps.hw_lock);
6255 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6256 mutex_unlock(&dev_priv->rps.hw_lock);
6257
6258 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6259}
6260
6261static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6262{
6263 return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6264}
6265
6266static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) 6247static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6267{ 6248{
6268 u32 freq_select, pcu_ack; 6249 u32 freq_select, pcu_ack;
6250 int ret;
6269 6251
6270 WARN_ON((cdclk == 24000) != (vco == 0)); 6252 WARN_ON((cdclk == 24000) != (vco == 0));
6271 6253
6272 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); 6254 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6273 6255
6274 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { 6256 mutex_lock(&dev_priv->rps.hw_lock);
6275 DRM_ERROR("failed to inform PCU about cdclk change\n"); 6257 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
6258 SKL_CDCLK_PREPARE_FOR_CHANGE,
6259 SKL_CDCLK_READY_FOR_CHANGE,
6260 SKL_CDCLK_READY_FOR_CHANGE, 3);
6261 mutex_unlock(&dev_priv->rps.hw_lock);
6262 if (ret) {
6263 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
6264 ret);
6276 return; 6265 return;
6277 } 6266 }
6278 6267
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 90283edcafba..d9bc19be855e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4014,8 +4014,8 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
4014 return; 4014 return;
4015 4015
4016 /* FIXME: we need to synchronize this sort of stuff with hardware 4016 /* FIXME: we need to synchronize this sort of stuff with hardware
4017 * readout */ 4017 * readout. Currently fast link training doesn't work on boot-up. */
4018 if (WARN_ON_ONCE(!intel_dp->lane_count)) 4018 if (!intel_dp->lane_count)
4019 return; 4019 return;
4020 4020
4021 /* if link training is requested we should perform it always */ 4021 /* if link training is requested we should perform it always */
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 0d8ff0034b88..47cd1b20fb3e 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -300,7 +300,8 @@ static void chv_exec_gpio(struct drm_i915_private *dev_priv,
300 mutex_lock(&dev_priv->sb_lock); 300 mutex_lock(&dev_priv->sb_lock);
301 vlv_iosf_sb_write(dev_priv, port, cfg1, 0); 301 vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
302 vlv_iosf_sb_write(dev_priv, port, cfg0, 302 vlv_iosf_sb_write(dev_priv, port, cfg0,
303 CHV_GPIO_GPIOCFG_GPO | CHV_GPIO_GPIOTXSTATE(value)); 303 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
304 CHV_GPIO_GPIOTXSTATE(value));
304 mutex_unlock(&dev_priv->sb_lock); 305 mutex_unlock(&dev_priv->sb_lock);
305} 306}
306 307
@@ -376,11 +377,11 @@ static const fn_mipi_elem_exec exec_elem[] = {
376 */ 377 */
377 378
378static const char * const seq_name[] = { 379static const char * const seq_name[] = {
379 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", 380 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
380 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", 381 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
381 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", 382 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
382 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", 383 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF",
383 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", 384 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
384 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", 385 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
385 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", 386 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
386 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", 387 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0a09024d6ca3..d4961fa20c73 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1968,12 +1968,7 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
1968 ret); 1968 ret);
1969 } 1969 }
1970 1970
1971 ret = logical_ring_init(engine); 1971 return logical_ring_init(engine);
1972 if (ret) {
1973 lrc_destroy_wa_ctx_obj(engine);
1974 }
1975
1976 return ret;
1977} 1972}
1978 1973
1979int logical_xcs_ring_init(struct intel_engine_cs *engine) 1974int logical_xcs_ring_init(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d67974eb127a..ae2c0bb4b2e8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2964,24 +2964,10 @@ intel_enable_sagv(struct drm_i915_private *dev_priv)
2964 return 0; 2964 return 0;
2965} 2965}
2966 2966
2967static int
2968intel_do_sagv_disable(struct drm_i915_private *dev_priv)
2969{
2970 int ret;
2971 uint32_t temp = GEN9_SAGV_DISABLE;
2972
2973 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2974 &temp);
2975 if (ret)
2976 return ret;
2977 else
2978 return temp & GEN9_SAGV_IS_DISABLED;
2979}
2980
2981int 2967int
2982intel_disable_sagv(struct drm_i915_private *dev_priv) 2968intel_disable_sagv(struct drm_i915_private *dev_priv)
2983{ 2969{
2984 int ret, result; 2970 int ret;
2985 2971
2986 if (!intel_has_sagv(dev_priv)) 2972 if (!intel_has_sagv(dev_priv))
2987 return 0; 2973 return 0;
@@ -2993,25 +2979,23 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
2993 mutex_lock(&dev_priv->rps.hw_lock); 2979 mutex_lock(&dev_priv->rps.hw_lock);
2994 2980
2995 /* bspec says to keep retrying for at least 1 ms */ 2981 /* bspec says to keep retrying for at least 1 ms */
2996 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1); 2982 ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2983 GEN9_SAGV_DISABLE,
2984 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
2985 1);
2997 mutex_unlock(&dev_priv->rps.hw_lock); 2986 mutex_unlock(&dev_priv->rps.hw_lock);
2998 2987
2999 if (ret == -ETIMEDOUT) {
3000 DRM_ERROR("Request to disable SAGV timed out\n");
3001 return -ETIMEDOUT;
3002 }
3003
3004 /* 2988 /*
3005 * Some skl systems, pre-release machines in particular, 2989 * Some skl systems, pre-release machines in particular,
3006 * don't actually have an SAGV. 2990 * don't actually have an SAGV.
3007 */ 2991 */
3008 if (IS_SKYLAKE(dev_priv) && result == -ENXIO) { 2992 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3009 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n"); 2993 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3010 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; 2994 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3011 return 0; 2995 return 0;
3012 } else if (result < 0) { 2996 } else if (ret < 0) {
3013 DRM_ERROR("Failed to disable the SAGV\n"); 2997 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
3014 return result; 2998 return ret;
3015 } 2999 }
3016 3000
3017 dev_priv->sagv_status = I915_SAGV_DISABLED; 3001 dev_priv->sagv_status = I915_SAGV_DISABLED;
@@ -7890,6 +7874,81 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7890 return 0; 7874 return 0;
7891} 7875}
7892 7876
7877static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
7878 u32 request, u32 reply_mask, u32 reply,
7879 u32 *status)
7880{
7881 u32 val = request;
7882
7883 *status = sandybridge_pcode_read(dev_priv, mbox, &val);
7884
7885 return *status || ((val & reply_mask) == reply);
7886}
7887
7888/**
7889 * skl_pcode_request - send PCODE request until acknowledgment
7890 * @dev_priv: device private
7891 * @mbox: PCODE mailbox ID the request is targeted for
7892 * @request: request ID
7893 * @reply_mask: mask used to check for request acknowledgment
7894 * @reply: value used to check for request acknowledgment
7895 * @timeout_base_ms: timeout for polling with preemption enabled
7896 *
7897 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
7898 * reports an error or an overall timeout of @timeout_base_ms+10 ms expires.
7899 * The request is acknowledged once the PCODE reply dword equals @reply after
7900 * applying @reply_mask. Polling is first attempted with preemption enabled
7901 * for @timeout_base_ms and if this times out for another 10 ms with
7902 * preemption disabled.
7903 *
7904 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
7905 * other error as reported by PCODE.
7906 */
7907int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
7908 u32 reply_mask, u32 reply, int timeout_base_ms)
7909{
7910 u32 status;
7911 int ret;
7912
7913 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7914
7915#define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
7916 &status)
7917
7918 /*
7919 * Prime the PCODE by doing a request first. Normally it guarantees
7920 * that a subsequent request, at most @timeout_base_ms later, succeeds.
7921 * _wait_for() doesn't guarantee when its passed condition is evaluated
7922 * first, so send the first request explicitly.
7923 */
7924 if (COND) {
7925 ret = 0;
7926 goto out;
7927 }
7928 ret = _wait_for(COND, timeout_base_ms * 1000, 10);
7929 if (!ret)
7930 goto out;
7931
7932 /*
7933 * The above can time out if the number of requests was low (2 in the
7934 * worst case) _and_ PCODE was busy for some reason even after a
7935 * (queued) request and @timeout_base_ms delay. As a workaround retry
7936 * the poll with preemption disabled to maximize the number of
7937 * requests. Increase the timeout from @timeout_base_ms to 10ms to
7938 * account for interrupts that could reduce the number of these
7939 * requests.
7940 */
7941 DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
7942 WARN_ON_ONCE(timeout_base_ms > 3);
7943 preempt_disable();
7944 ret = wait_for_atomic(COND, 10);
7945 preempt_enable();
7946
7947out:
7948 return ret ? ret : status;
7949#undef COND
7950}
7951
7893static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) 7952static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7894{ 7953{
7895 /* 7954 /*
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 7b488e2793d9..c6be70686b4a 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -825,13 +825,9 @@ void intel_psr_init(struct drm_device *dev)
825 dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ? 825 dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
826 HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE; 826 HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
827 827
828 /* Per platform default */ 828 /* Per platform default: all disabled. */
829 if (i915.enable_psr == -1) { 829 if (i915.enable_psr == -1)
830 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 830 i915.enable_psr = 0;
831 i915.enable_psr = 1;
832 else
833 i915.enable_psr = 0;
834 }
835 831
836 /* Set link_standby x link_off defaults */ 832 /* Set link_standby x link_off defaults */
837 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 833 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 356c662ad453..87b4af092d54 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1039,7 +1039,18 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
1039 1039
1040static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 1040static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
1041{ 1041{
1042 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); 1042 u32 val;
1043
1044 /*
1045 * On driver load, a pipe may be active and driving a DSI display.
1046 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
1047 * (and never recovering) in this case. intel_dsi_post_disable() will
1048 * clear it when we turn off the display.
1049 */
1050 val = I915_READ(DSPCLK_GATE_D);
1051 val &= DPOUNIT_CLOCK_GATE_DISABLE;
1052 val |= VRHUNIT_CLOCK_GATE_DISABLE;
1053 I915_WRITE(DSPCLK_GATE_D, val);
1043 1054
1044 /* 1055 /*
1045 * Disable trickle feed and enable pnd deadline calculation 1056 * Disable trickle feed and enable pnd deadline calculation
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-27 14:57:07 -0400