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authorAndre Przywara <andre.przywara@arm.com>2017-03-06 12:17:48 -0500
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-03-27 07:40:53 -0400
commit0127216f2217e63fcf976343d1504d2ba1d83a45 (patch)
tree0985fb82b64e5aad379e8558b05d68f539176e37
parenta0f4e1836b3d83cf8270533870a96e87674655f2 (diff)
arm: sun8i: h3: split Allwinner H3 .dtsi
The new Allwinner H5 SoC is pin-compatible to the H3 SoC, but with the Cortex-A7 cores replaced by Cortex-A53 cores and the MMC controller updated. So we should really share almost the whole .dtsi. In preparation for that move the peripheral parts of the existing sun8i-h3.dtsi into a new sunxi-h3-h5.dtsi. The actual sun8i-h3.dtsi then includes that and defines the H3 specific parts on top of it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [Icenowy: also split out mmc and gic, as well as pio and ccu's compatible, and make drop of skeleton into a seperated patch] Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/sun8i-h3.dtsi599
-rw-r--r--arch/arm/boot/dts/sunxi-h3-h5.dtsi586
2 files changed, 626 insertions, 559 deletions
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index c13fbfb92592..b36f9f423c39 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -40,13 +40,9 @@
40 * OTHER DEALINGS IN THE SOFTWARE. 40 * OTHER DEALINGS IN THE SOFTWARE.
41 */ 41 */
42 42
43#include <dt-bindings/clock/sun8i-h3-ccu.h> 43#include "sunxi-h3-h5.dtsi"
44#include <dt-bindings/interrupt-controller/arm-gic.h>
45#include <dt-bindings/reset/sun8i-h3-ccu.h>
46 44
47/ { 45/ {
48 interrupt-parent = <&gic>;
49
50 cpus { 46 cpus {
51 #address-cells = <1>; 47 #address-cells = <1>;
52 #size-cells = <0>; 48 #size-cells = <0>;
@@ -83,563 +79,48 @@
83 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 79 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
84 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 80 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
85 }; 81 };
82};
86 83
87 clocks { 84&ccu {
88 #address-cells = <1>; 85 compatible = "allwinner,sun8i-h3-ccu";
89 #size-cells = <1>; 86};
90 ranges;
91
92 osc24M: osc24M_clk {
93 #clock-cells = <0>;
94 compatible = "fixed-clock";
95 clock-frequency = <24000000>;
96 clock-output-names = "osc24M";
97 };
98
99 osc32k: osc32k_clk {
100 #clock-cells = <0>;
101 compatible = "fixed-clock";
102 clock-frequency = <32768>;
103 clock-output-names = "osc32k";
104 };
105
106 apb0: apb0_clk {
107 compatible = "fixed-factor-clock";
108 #clock-cells = <0>;
109 clock-div = <1>;
110 clock-mult = <1>;
111 clocks = <&osc24M>;
112 clock-output-names = "apb0";
113 };
114
115 apb0_gates: clk@01f01428 {
116 compatible = "allwinner,sun8i-h3-apb0-gates-clk",
117 "allwinner,sun4i-a10-gates-clk";
118 reg = <0x01f01428 0x4>;
119 #clock-cells = <1>;
120 clocks = <&apb0>;
121 clock-indices = <0>, <1>;
122 clock-output-names = "apb0_pio", "apb0_ir";
123 };
124
125 ir_clk: ir_clk@01f01454 {
126 compatible = "allwinner,sun4i-a10-mod0-clk";
127 reg = <0x01f01454 0x4>;
128 #clock-cells = <0>;
129 clocks = <&osc32k>, <&osc24M>;
130 clock-output-names = "ir";
131 };
132 };
133
134 soc {
135 compatible = "simple-bus";
136 #address-cells = <1>;
137 #size-cells = <1>;
138 ranges;
139
140 dma: dma-controller@01c02000 {
141 compatible = "allwinner,sun8i-h3-dma";
142 reg = <0x01c02000 0x1000>;
143 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&ccu CLK_BUS_DMA>;
145 resets = <&ccu RST_BUS_DMA>;
146 #dma-cells = <1>;
147 };
148
149 mmc0: mmc@01c0f000 {
150 compatible = "allwinner,sun7i-a20-mmc";
151 reg = <0x01c0f000 0x1000>;
152 clocks = <&ccu CLK_BUS_MMC0>,
153 <&ccu CLK_MMC0>,
154 <&ccu CLK_MMC0_OUTPUT>,
155 <&ccu CLK_MMC0_SAMPLE>;
156 clock-names = "ahb",
157 "mmc",
158 "output",
159 "sample";
160 resets = <&ccu RST_BUS_MMC0>;
161 reset-names = "ahb";
162 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
163 status = "disabled";
164 #address-cells = <1>;
165 #size-cells = <0>;
166 };
167
168 mmc1: mmc@01c10000 {
169 compatible = "allwinner,sun7i-a20-mmc";
170 reg = <0x01c10000 0x1000>;
171 clocks = <&ccu CLK_BUS_MMC1>,
172 <&ccu CLK_MMC1>,
173 <&ccu CLK_MMC1_OUTPUT>,
174 <&ccu CLK_MMC1_SAMPLE>;
175 clock-names = "ahb",
176 "mmc",
177 "output",
178 "sample";
179 resets = <&ccu RST_BUS_MMC1>;
180 reset-names = "ahb";
181 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
182 status = "disabled";
183 #address-cells = <1>;
184 #size-cells = <0>;
185 };
186
187 mmc2: mmc@01c11000 {
188 compatible = "allwinner,sun7i-a20-mmc";
189 reg = <0x01c11000 0x1000>;
190 clocks = <&ccu CLK_BUS_MMC2>,
191 <&ccu CLK_MMC2>,
192 <&ccu CLK_MMC2_OUTPUT>,
193 <&ccu CLK_MMC2_SAMPLE>;
194 clock-names = "ahb",
195 "mmc",
196 "output",
197 "sample";
198 resets = <&ccu RST_BUS_MMC2>;
199 reset-names = "ahb";
200 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
201 status = "disabled";
202 #address-cells = <1>;
203 #size-cells = <0>;
204 };
205
206 usbphy: phy@01c19400 {
207 compatible = "allwinner,sun8i-h3-usb-phy";
208 reg = <0x01c19400 0x2c>,
209 <0x01c1a800 0x4>,
210 <0x01c1b800 0x4>,
211 <0x01c1c800 0x4>,
212 <0x01c1d800 0x4>;
213 reg-names = "phy_ctrl",
214 "pmu0",
215 "pmu1",
216 "pmu2",
217 "pmu3";
218 clocks = <&ccu CLK_USB_PHY0>,
219 <&ccu CLK_USB_PHY1>,
220 <&ccu CLK_USB_PHY2>,
221 <&ccu CLK_USB_PHY3>;
222 clock-names = "usb0_phy",
223 "usb1_phy",
224 "usb2_phy",
225 "usb3_phy";
226 resets = <&ccu RST_USB_PHY0>,
227 <&ccu RST_USB_PHY1>,
228 <&ccu RST_USB_PHY2>,
229 <&ccu RST_USB_PHY3>;
230 reset-names = "usb0_reset",
231 "usb1_reset",
232 "usb2_reset",
233 "usb3_reset";
234 status = "disabled";
235 #phy-cells = <1>;
236 };
237
238 ehci1: usb@01c1b000 {
239 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
240 reg = <0x01c1b000 0x100>;
241 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
243 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
244 phys = <&usbphy 1>;
245 phy-names = "usb";
246 status = "disabled";
247 };
248
249 ohci1: usb@01c1b400 {
250 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
251 reg = <0x01c1b400 0x100>;
252 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
254 <&ccu CLK_USB_OHCI1>;
255 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
256 phys = <&usbphy 1>;
257 phy-names = "usb";
258 status = "disabled";
259 };
260
261 ehci2: usb@01c1c000 {
262 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
263 reg = <0x01c1c000 0x100>;
264 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
266 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
267 phys = <&usbphy 2>;
268 phy-names = "usb";
269 status = "disabled";
270 };
271
272 ohci2: usb@01c1c400 {
273 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
274 reg = <0x01c1c400 0x100>;
275 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
277 <&ccu CLK_USB_OHCI2>;
278 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
279 phys = <&usbphy 2>;
280 phy-names = "usb";
281 status = "disabled";
282 };
283
284 ehci3: usb@01c1d000 {
285 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
286 reg = <0x01c1d000 0x100>;
287 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
289 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
290 phys = <&usbphy 3>;
291 phy-names = "usb";
292 status = "disabled";
293 };
294
295 ohci3: usb@01c1d400 {
296 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
297 reg = <0x01c1d400 0x100>;
298 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
300 <&ccu CLK_USB_OHCI3>;
301 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
302 phys = <&usbphy 3>;
303 phy-names = "usb";
304 status = "disabled";
305 };
306
307 ccu: clock@01c20000 {
308 compatible = "allwinner,sun8i-h3-ccu";
309 reg = <0x01c20000 0x400>;
310 clocks = <&osc24M>, <&osc32k>;
311 clock-names = "hosc", "losc";
312 #clock-cells = <1>;
313 #reset-cells = <1>;
314 };
315
316 pio: pinctrl@01c20800 {
317 compatible = "allwinner,sun8i-h3-pinctrl";
318 reg = <0x01c20800 0x400>;
319 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
322 clock-names = "apb", "hosc", "losc";
323 gpio-controller;
324 #gpio-cells = <3>;
325 interrupt-controller;
326 #interrupt-cells = <3>;
327
328 i2c0_pins: i2c0 {
329 pins = "PA11", "PA12";
330 function = "i2c0";
331 };
332
333 i2c1_pins: i2c1 {
334 pins = "PA18", "PA19";
335 function = "i2c1";
336 };
337
338 i2c2_pins: i2c2 {
339 pins = "PE12", "PE13";
340 function = "i2c2";
341 };
342
343 mmc0_pins_a: mmc0@0 {
344 pins = "PF0", "PF1", "PF2", "PF3",
345 "PF4", "PF5";
346 function = "mmc0";
347 drive-strength = <30>;
348 bias-pull-up;
349 };
350
351 mmc0_cd_pin: mmc0_cd_pin@0 {
352 pins = "PF6";
353 function = "gpio_in";
354 bias-pull-up;
355 };
356
357 mmc1_pins_a: mmc1@0 {
358 pins = "PG0", "PG1", "PG2", "PG3",
359 "PG4", "PG5";
360 function = "mmc1";
361 drive-strength = <30>;
362 bias-pull-up;
363 };
364
365 mmc2_8bit_pins: mmc2_8bit {
366 pins = "PC5", "PC6", "PC8",
367 "PC9", "PC10", "PC11",
368 "PC12", "PC13", "PC14",
369 "PC15", "PC16";
370 function = "mmc2";
371 drive-strength = <30>;
372 bias-pull-up;
373 };
374
375 spdif_tx_pins_a: spdif@0 {
376 pins = "PA17";
377 function = "spdif";
378 };
379
380 spi0_pins: spi0 {
381 pins = "PC0", "PC1", "PC2", "PC3";
382 function = "spi0";
383 };
384
385 spi1_pins: spi1 {
386 pins = "PA15", "PA16", "PA14", "PA13";
387 function = "spi1";
388 };
389
390 uart0_pins_a: uart0@0 {
391 pins = "PA4", "PA5";
392 function = "uart0";
393 };
394
395 uart1_pins: uart1 {
396 pins = "PG6", "PG7";
397 function = "uart1";
398 };
399
400 uart1_rts_cts_pins: uart1_rts_cts {
401 pins = "PG8", "PG9";
402 function = "uart1";
403 };
404
405 uart2_pins: uart2 {
406 pins = "PA0", "PA1";
407 function = "uart2";
408 };
409
410 uart3_pins: uart3 {
411 pins = "PA13", "PA14";
412 function = "uart3";
413 };
414 };
415
416 timer@01c20c00 {
417 compatible = "allwinner,sun4i-a10-timer";
418 reg = <0x01c20c00 0xa0>;
419 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&osc24M>;
422 };
423
424 spi0: spi@01c68000 {
425 compatible = "allwinner,sun8i-h3-spi";
426 reg = <0x01c68000 0x1000>;
427 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
429 clock-names = "ahb", "mod";
430 dmas = <&dma 23>, <&dma 23>;
431 dma-names = "rx", "tx";
432 pinctrl-names = "default";
433 pinctrl-0 = <&spi0_pins>;
434 resets = <&ccu RST_BUS_SPI0>;
435 status = "disabled";
436 #address-cells = <1>;
437 #size-cells = <0>;
438 };
439
440 spi1: spi@01c69000 {
441 compatible = "allwinner,sun8i-h3-spi";
442 reg = <0x01c69000 0x1000>;
443 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
445 clock-names = "ahb", "mod";
446 dmas = <&dma 24>, <&dma 24>;
447 dma-names = "rx", "tx";
448 pinctrl-names = "default";
449 pinctrl-0 = <&spi1_pins>;
450 resets = <&ccu RST_BUS_SPI1>;
451 status = "disabled";
452 #address-cells = <1>;
453 #size-cells = <0>;
454 };
455
456 wdt0: watchdog@01c20ca0 {
457 compatible = "allwinner,sun6i-a31-wdt";
458 reg = <0x01c20ca0 0x20>;
459 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
460 };
461
462 spdif: spdif@01c21000 {
463 #sound-dai-cells = <0>;
464 compatible = "allwinner,sun8i-h3-spdif";
465 reg = <0x01c21000 0x400>;
466 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
468 resets = <&ccu RST_BUS_SPDIF>;
469 clock-names = "apb", "spdif";
470 dmas = <&dma 2>;
471 dma-names = "tx";
472 status = "disabled";
473 };
474
475 pwm: pwm@01c21400 {
476 compatible = "allwinner,sun8i-h3-pwm";
477 reg = <0x01c21400 0x8>;
478 clocks = <&osc24M>;
479 #pwm-cells = <3>;
480 status = "disabled";
481 };
482
483 codec: codec@01c22c00 {
484 #sound-dai-cells = <0>;
485 compatible = "allwinner,sun8i-h3-codec";
486 reg = <0x01c22c00 0x400>;
487 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
489 clock-names = "apb", "codec";
490 resets = <&ccu RST_BUS_CODEC>;
491 dmas = <&dma 15>, <&dma 15>;
492 dma-names = "rx", "tx";
493 allwinner,codec-analog-controls = <&codec_analog>;
494 status = "disabled";
495 };
496
497 uart0: serial@01c28000 {
498 compatible = "snps,dw-apb-uart";
499 reg = <0x01c28000 0x400>;
500 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
501 reg-shift = <2>;
502 reg-io-width = <4>;
503 clocks = <&ccu CLK_BUS_UART0>;
504 resets = <&ccu RST_BUS_UART0>;
505 dmas = <&dma 6>, <&dma 6>;
506 dma-names = "rx", "tx";
507 status = "disabled";
508 };
509
510 uart1: serial@01c28400 {
511 compatible = "snps,dw-apb-uart";
512 reg = <0x01c28400 0x400>;
513 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
514 reg-shift = <2>;
515 reg-io-width = <4>;
516 clocks = <&ccu CLK_BUS_UART1>;
517 resets = <&ccu RST_BUS_UART1>;
518 dmas = <&dma 7>, <&dma 7>;
519 dma-names = "rx", "tx";
520 status = "disabled";
521 };
522
523 uart2: serial@01c28800 {
524 compatible = "snps,dw-apb-uart";
525 reg = <0x01c28800 0x400>;
526 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
527 reg-shift = <2>;
528 reg-io-width = <4>;
529 clocks = <&ccu CLK_BUS_UART2>;
530 resets = <&ccu RST_BUS_UART2>;
531 dmas = <&dma 8>, <&dma 8>;
532 dma-names = "rx", "tx";
533 status = "disabled";
534 };
535
536 uart3: serial@01c28c00 {
537 compatible = "snps,dw-apb-uart";
538 reg = <0x01c28c00 0x400>;
539 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
540 reg-shift = <2>;
541 reg-io-width = <4>;
542 clocks = <&ccu CLK_BUS_UART3>;
543 resets = <&ccu RST_BUS_UART3>;
544 dmas = <&dma 9>, <&dma 9>;
545 dma-names = "rx", "tx";
546 status = "disabled";
547 };
548
549 i2c0: i2c@01c2ac00 {
550 compatible = "allwinner,sun6i-a31-i2c";
551 reg = <0x01c2ac00 0x400>;
552 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&ccu CLK_BUS_I2C0>;
554 resets = <&ccu RST_BUS_I2C0>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&i2c0_pins>;
557 status = "disabled";
558 #address-cells = <1>;
559 #size-cells = <0>;
560 };
561
562 i2c1: i2c@01c2b000 {
563 compatible = "allwinner,sun6i-a31-i2c";
564 reg = <0x01c2b000 0x400>;
565 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&ccu CLK_BUS_I2C1>;
567 resets = <&ccu RST_BUS_I2C1>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&i2c1_pins>;
570 status = "disabled";
571 #address-cells = <1>;
572 #size-cells = <0>;
573 };
574
575 i2c2: i2c@01c2b400 {
576 compatible = "allwinner,sun6i-a31-i2c";
577 reg = <0x01c2b000 0x400>;
578 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&ccu CLK_BUS_I2C2>;
580 resets = <&ccu RST_BUS_I2C2>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&i2c2_pins>;
583 status = "disabled";
584 #address-cells = <1>;
585 #size-cells = <0>;
586 };
587
588 gic: interrupt-controller@01c81000 {
589 compatible = "arm,gic-400";
590 reg = <0x01c81000 0x1000>,
591 <0x01c82000 0x2000>,
592 <0x01c84000 0x2000>,
593 <0x01c86000 0x2000>;
594 interrupt-controller;
595 #interrupt-cells = <3>;
596 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
597 };
598
599 rtc: rtc@01f00000 {
600 compatible = "allwinner,sun6i-a31-rtc";
601 reg = <0x01f00000 0x54>;
602 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
604 };
605
606 apb0_reset: reset@01f014b0 {
607 reg = <0x01f014b0 0x4>;
608 compatible = "allwinner,sun6i-a31-clock-reset";
609 #reset-cells = <1>;
610 };
611 87
612 codec_analog: codec-analog@01f015c0 { 88&mmc0 {
613 compatible = "allwinner,sun8i-h3-codec-analog"; 89 compatible = "allwinner,sun7i-a20-mmc";
614 reg = <0x01f015c0 0x4>; 90 clocks = <&ccu CLK_BUS_MMC0>,
615 }; 91 <&ccu CLK_MMC0>,
92 <&ccu CLK_MMC0_OUTPUT>,
93 <&ccu CLK_MMC0_SAMPLE>;
94 clock-names = "ahb",
95 "mmc",
96 "output",
97 "sample";
98};
616 99
617 ir: ir@01f02000 { 100&mmc1 {
618 compatible = "allwinner,sun5i-a13-ir"; 101 compatible = "allwinner,sun7i-a20-mmc";
619 clocks = <&apb0_gates 1>, <&ir_clk>; 102 clocks = <&ccu CLK_BUS_MMC1>,
620 clock-names = "apb", "ir"; 103 <&ccu CLK_MMC1>,
621 resets = <&apb0_reset 1>; 104 <&ccu CLK_MMC1_OUTPUT>,
622 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 105 <&ccu CLK_MMC1_SAMPLE>;
623 reg = <0x01f02000 0x40>; 106 clock-names = "ahb",
624 status = "disabled"; 107 "mmc",
625 }; 108 "output",
109 "sample";
110};
626 111
627 r_pio: pinctrl@01f02c00 { 112&mmc2 {
628 compatible = "allwinner,sun8i-h3-r-pinctrl"; 113 compatible = "allwinner,sun7i-a20-mmc";
629 reg = <0x01f02c00 0x400>; 114 clocks = <&ccu CLK_BUS_MMC2>,
630 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 115 <&ccu CLK_MMC2>,
631 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; 116 <&ccu CLK_MMC2_OUTPUT>,
632 clock-names = "apb", "hosc", "losc"; 117 <&ccu CLK_MMC2_SAMPLE>;
633 resets = <&apb0_reset 0>; 118 clock-names = "ahb",
634 gpio-controller; 119 "mmc",
635 #gpio-cells = <3>; 120 "output",
636 interrupt-controller; 121 "sample";
637 #interrupt-cells = <3>; 122};
638 123
639 ir_pins_a: ir@0 { 124&pio {
640 pins = "PL11"; 125 compatible = "allwinner,sun8i-h3-pinctrl";
641 function = "s_cir_rx";
642 };
643 };
644 };
645}; 126};
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
new file mode 100644
index 000000000000..2494ea063cd4
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -0,0 +1,586 @@
1/*
2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/clock/sun8i-h3-ccu.h>
44#include <dt-bindings/interrupt-controller/arm-gic.h>
45#include <dt-bindings/reset/sun8i-h3-ccu.h>
46
47/ {
48 interrupt-parent = <&gic>;
49 #address-cells = <1>;
50 #size-cells = <1>;
51
52 clocks {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 osc24M: osc24M_clk {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <24000000>;
61 clock-output-names = "osc24M";
62 };
63
64 osc32k: osc32k_clk {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-frequency = <32768>;
68 clock-output-names = "osc32k";
69 };
70
71 apb0: apb0_clk {
72 compatible = "fixed-factor-clock";
73 #clock-cells = <0>;
74 clock-div = <1>;
75 clock-mult = <1>;
76 clocks = <&osc24M>;
77 clock-output-names = "apb0";
78 };
79
80 apb0_gates: clk@01f01428 {
81 compatible = "allwinner,sun8i-h3-apb0-gates-clk",
82 "allwinner,sun4i-a10-gates-clk";
83 reg = <0x01f01428 0x4>;
84 #clock-cells = <1>;
85 clocks = <&apb0>;
86 clock-indices = <0>, <1>;
87 clock-output-names = "apb0_pio", "apb0_ir";
88 };
89
90 ir_clk: ir_clk@01f01454 {
91 compatible = "allwinner,sun4i-a10-mod0-clk";
92 reg = <0x01f01454 0x4>;
93 #clock-cells = <0>;
94 clocks = <&osc32k>, <&osc24M>;
95 clock-output-names = "ir";
96 };
97 };
98
99 soc {
100 compatible = "simple-bus";
101 #address-cells = <1>;
102 #size-cells = <1>;
103 ranges;
104
105 dma: dma-controller@01c02000 {
106 compatible = "allwinner,sun8i-h3-dma";
107 reg = <0x01c02000 0x1000>;
108 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
109 clocks = <&ccu CLK_BUS_DMA>;
110 resets = <&ccu RST_BUS_DMA>;
111 #dma-cells = <1>;
112 };
113
114 mmc0: mmc@01c0f000 {
115 /* compatible and clocks are in per SoC .dtsi file */
116 reg = <0x01c0f000 0x1000>;
117 resets = <&ccu RST_BUS_MMC0>;
118 reset-names = "ahb";
119 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
120 status = "disabled";
121 #address-cells = <1>;
122 #size-cells = <0>;
123 };
124
125 mmc1: mmc@01c10000 {
126 /* compatible and clocks are in per SoC .dtsi file */
127 reg = <0x01c10000 0x1000>;
128 resets = <&ccu RST_BUS_MMC1>;
129 reset-names = "ahb";
130 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
131 status = "disabled";
132 #address-cells = <1>;
133 #size-cells = <0>;
134 };
135
136 mmc2: mmc@01c11000 {
137 /* compatible and clocks are in per SoC .dtsi file */
138 reg = <0x01c11000 0x1000>;
139 resets = <&ccu RST_BUS_MMC2>;
140 reset-names = "ahb";
141 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
142 status = "disabled";
143 #address-cells = <1>;
144 #size-cells = <0>;
145 };
146
147 usbphy: phy@01c19400 {
148 compatible = "allwinner,sun8i-h3-usb-phy";
149 reg = <0x01c19400 0x2c>,
150 <0x01c1a800 0x4>,
151 <0x01c1b800 0x4>,
152 <0x01c1c800 0x4>,
153 <0x01c1d800 0x4>;
154 reg-names = "phy_ctrl",
155 "pmu0",
156 "pmu1",
157 "pmu2",
158 "pmu3";
159 clocks = <&ccu CLK_USB_PHY0>,
160 <&ccu CLK_USB_PHY1>,
161 <&ccu CLK_USB_PHY2>,
162 <&ccu CLK_USB_PHY3>;
163 clock-names = "usb0_phy",
164 "usb1_phy",
165 "usb2_phy",
166 "usb3_phy";
167 resets = <&ccu RST_USB_PHY0>,
168 <&ccu RST_USB_PHY1>,
169 <&ccu RST_USB_PHY2>,
170 <&ccu RST_USB_PHY3>;
171 reset-names = "usb0_reset",
172 "usb1_reset",
173 "usb2_reset",
174 "usb3_reset";
175 status = "disabled";
176 #phy-cells = <1>;
177 };
178
179 ehci1: usb@01c1b000 {
180 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
181 reg = <0x01c1b000 0x100>;
182 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
184 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
185 phys = <&usbphy 1>;
186 phy-names = "usb";
187 status = "disabled";
188 };
189
190 ohci1: usb@01c1b400 {
191 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
192 reg = <0x01c1b400 0x100>;
193 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
195 <&ccu CLK_USB_OHCI1>;
196 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
197 phys = <&usbphy 1>;
198 phy-names = "usb";
199 status = "disabled";
200 };
201
202 ehci2: usb@01c1c000 {
203 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
204 reg = <0x01c1c000 0x100>;
205 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
207 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
208 phys = <&usbphy 2>;
209 phy-names = "usb";
210 status = "disabled";
211 };
212
213 ohci2: usb@01c1c400 {
214 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
215 reg = <0x01c1c400 0x100>;
216 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
218 <&ccu CLK_USB_OHCI2>;
219 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
220 phys = <&usbphy 2>;
221 phy-names = "usb";
222 status = "disabled";
223 };
224
225 ehci3: usb@01c1d000 {
226 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
227 reg = <0x01c1d000 0x100>;
228 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
230 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
231 phys = <&usbphy 3>;
232 phy-names = "usb";
233 status = "disabled";
234 };
235
236 ohci3: usb@01c1d400 {
237 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
238 reg = <0x01c1d400 0x100>;
239 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
241 <&ccu CLK_USB_OHCI3>;
242 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
243 phys = <&usbphy 3>;
244 phy-names = "usb";
245 status = "disabled";
246 };
247
248 ccu: clock@01c20000 {
249 /* compatible is in per SoC .dtsi file */
250 reg = <0x01c20000 0x400>;
251 clocks = <&osc24M>, <&osc32k>;
252 clock-names = "hosc", "losc";
253 #clock-cells = <1>;
254 #reset-cells = <1>;
255 };
256
257 pio: pinctrl@01c20800 {
258 /* compatible is in per SoC .dtsi file */
259 reg = <0x01c20800 0x400>;
260 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
263 clock-names = "apb", "hosc", "losc";
264 gpio-controller;
265 #gpio-cells = <3>;
266 interrupt-controller;
267 #interrupt-cells = <3>;
268
269 i2c0_pins: i2c0 {
270 pins = "PA11", "PA12";
271 function = "i2c0";
272 };
273
274 i2c1_pins: i2c1 {
275 pins = "PA18", "PA19";
276 function = "i2c1";
277 };
278
279 i2c2_pins: i2c2 {
280 pins = "PE12", "PE13";
281 function = "i2c2";
282 };
283
284 mmc0_pins_a: mmc0@0 {
285 pins = "PF0", "PF1", "PF2", "PF3",
286 "PF4", "PF5";
287 function = "mmc0";
288 drive-strength = <30>;
289 bias-pull-up;
290 };
291
292 mmc0_cd_pin: mmc0_cd_pin@0 {
293 pins = "PF6";
294 function = "gpio_in";
295 bias-pull-up;
296 };
297
298 mmc1_pins_a: mmc1@0 {
299 pins = "PG0", "PG1", "PG2", "PG3",
300 "PG4", "PG5";
301 function = "mmc1";
302 drive-strength = <30>;
303 bias-pull-up;
304 };
305
306 mmc2_8bit_pins: mmc2_8bit {
307 pins = "PC5", "PC6", "PC8",
308 "PC9", "PC10", "PC11",
309 "PC12", "PC13", "PC14",
310 "PC15", "PC16";
311 function = "mmc2";
312 drive-strength = <30>;
313 bias-pull-up;
314 };
315
316 spdif_tx_pins_a: spdif@0 {
317 pins = "PA17";
318 function = "spdif";
319 };
320
321 spi0_pins: spi0 {
322 pins = "PC0", "PC1", "PC2", "PC3";
323 function = "spi0";
324 };
325
326 spi1_pins: spi1 {
327 pins = "PA15", "PA16", "PA14", "PA13";
328 function = "spi1";
329 };
330
331 uart0_pins_a: uart0@0 {
332 pins = "PA4", "PA5";
333 function = "uart0";
334 };
335
336 uart1_pins: uart1 {
337 pins = "PG6", "PG7";
338 function = "uart1";
339 };
340
341 uart1_rts_cts_pins: uart1_rts_cts {
342 pins = "PG8", "PG9";
343 function = "uart1";
344 };
345
346 uart2_pins: uart2 {
347 pins = "PA0", "PA1";
348 function = "uart2";
349 };
350
351 uart3_pins: uart3 {
352 pins = "PA13", "PA14";
353 function = "uart3";
354 };
355 };
356
357 timer@01c20c00 {
358 compatible = "allwinner,sun4i-a10-timer";
359 reg = <0x01c20c00 0xa0>;
360 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&osc24M>;
363 };
364
365 spi0: spi@01c68000 {
366 compatible = "allwinner,sun8i-h3-spi";
367 reg = <0x01c68000 0x1000>;
368 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
370 clock-names = "ahb", "mod";
371 dmas = <&dma 23>, <&dma 23>;
372 dma-names = "rx", "tx";
373 pinctrl-names = "default";
374 pinctrl-0 = <&spi0_pins>;
375 resets = <&ccu RST_BUS_SPI0>;
376 status = "disabled";
377 #address-cells = <1>;
378 #size-cells = <0>;
379 };
380
381 spi1: spi@01c69000 {
382 compatible = "allwinner,sun8i-h3-spi";
383 reg = <0x01c69000 0x1000>;
384 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
386 clock-names = "ahb", "mod";
387 dmas = <&dma 24>, <&dma 24>;
388 dma-names = "rx", "tx";
389 pinctrl-names = "default";
390 pinctrl-0 = <&spi1_pins>;
391 resets = <&ccu RST_BUS_SPI1>;
392 status = "disabled";
393 #address-cells = <1>;
394 #size-cells = <0>;
395 };
396
397 wdt0: watchdog@01c20ca0 {
398 compatible = "allwinner,sun6i-a31-wdt";
399 reg = <0x01c20ca0 0x20>;
400 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
401 };
402
403 spdif: spdif@01c21000 {
404 #sound-dai-cells = <0>;
405 compatible = "allwinner,sun8i-h3-spdif";
406 reg = <0x01c21000 0x400>;
407 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
409 resets = <&ccu RST_BUS_SPDIF>;
410 clock-names = "apb", "spdif";
411 dmas = <&dma 2>;
412 dma-names = "tx";
413 status = "disabled";
414 };
415
416 pwm: pwm@01c21400 {
417 compatible = "allwinner,sun8i-h3-pwm";
418 reg = <0x01c21400 0x8>;
419 clocks = <&osc24M>;
420 #pwm-cells = <3>;
421 status = "disabled";
422 };
423
424 codec: codec@01c22c00 {
425 #sound-dai-cells = <0>;
426 compatible = "allwinner,sun8i-h3-codec";
427 reg = <0x01c22c00 0x400>;
428 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
430 clock-names = "apb", "codec";
431 resets = <&ccu RST_BUS_CODEC>;
432 dmas = <&dma 15>, <&dma 15>;
433 dma-names = "rx", "tx";
434 allwinner,codec-analog-controls = <&codec_analog>;
435 status = "disabled";
436 };
437
438 uart0: serial@01c28000 {
439 compatible = "snps,dw-apb-uart";
440 reg = <0x01c28000 0x400>;
441 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
442 reg-shift = <2>;
443 reg-io-width = <4>;
444 clocks = <&ccu CLK_BUS_UART0>;
445 resets = <&ccu RST_BUS_UART0>;
446 dmas = <&dma 6>, <&dma 6>;
447 dma-names = "rx", "tx";
448 status = "disabled";
449 };
450
451 uart1: serial@01c28400 {
452 compatible = "snps,dw-apb-uart";
453 reg = <0x01c28400 0x400>;
454 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
455 reg-shift = <2>;
456 reg-io-width = <4>;
457 clocks = <&ccu CLK_BUS_UART1>;
458 resets = <&ccu RST_BUS_UART1>;
459 dmas = <&dma 7>, <&dma 7>;
460 dma-names = "rx", "tx";
461 status = "disabled";
462 };
463
464 uart2: serial@01c28800 {
465 compatible = "snps,dw-apb-uart";
466 reg = <0x01c28800 0x400>;
467 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
468 reg-shift = <2>;
469 reg-io-width = <4>;
470 clocks = <&ccu CLK_BUS_UART2>;
471 resets = <&ccu RST_BUS_UART2>;
472 dmas = <&dma 8>, <&dma 8>;
473 dma-names = "rx", "tx";
474 status = "disabled";
475 };
476
477 uart3: serial@01c28c00 {
478 compatible = "snps,dw-apb-uart";
479 reg = <0x01c28c00 0x400>;
480 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
481 reg-shift = <2>;
482 reg-io-width = <4>;
483 clocks = <&ccu CLK_BUS_UART3>;
484 resets = <&ccu RST_BUS_UART3>;
485 dmas = <&dma 9>, <&dma 9>;
486 dma-names = "rx", "tx";
487 status = "disabled";
488 };
489
490 i2c0: i2c@01c2ac00 {
491 compatible = "allwinner,sun6i-a31-i2c";
492 reg = <0x01c2ac00 0x400>;
493 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&ccu CLK_BUS_I2C0>;
495 resets = <&ccu RST_BUS_I2C0>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&i2c0_pins>;
498 status = "disabled";
499 #address-cells = <1>;
500 #size-cells = <0>;
501 };
502
503 i2c1: i2c@01c2b000 {
504 compatible = "allwinner,sun6i-a31-i2c";
505 reg = <0x01c2b000 0x400>;
506 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&ccu CLK_BUS_I2C1>;
508 resets = <&ccu RST_BUS_I2C1>;
509 pinctrl-names = "default";
510 pinctrl-0 = <&i2c1_pins>;
511 status = "disabled";
512 #address-cells = <1>;
513 #size-cells = <0>;
514 };
515
516 i2c2: i2c@01c2b400 {
517 compatible = "allwinner,sun6i-a31-i2c";
518 reg = <0x01c2b000 0x400>;
519 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&ccu CLK_BUS_I2C2>;
521 resets = <&ccu RST_BUS_I2C2>;
522 pinctrl-names = "default";
523 pinctrl-0 = <&i2c2_pins>;
524 status = "disabled";
525 #address-cells = <1>;
526 #size-cells = <0>;
527 };
528
529 gic: interrupt-controller@01c81000 {
530 compatible = "arm,gic-400";
531 reg = <0x01c81000 0x1000>,
532 <0x01c82000 0x2000>,
533 <0x01c84000 0x2000>,
534 <0x01c86000 0x2000>;
535 interrupt-controller;
536 #interrupt-cells = <3>;
537 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
538 };
539
540 rtc: rtc@01f00000 {
541 compatible = "allwinner,sun6i-a31-rtc";
542 reg = <0x01f00000 0x54>;
543 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
545 };
546
547 apb0_reset: reset@01f014b0 {
548 reg = <0x01f014b0 0x4>;
549 compatible = "allwinner,sun6i-a31-clock-reset";
550 #reset-cells = <1>;
551 };
552
553 codec_analog: codec-analog@01f015c0 {
554 compatible = "allwinner,sun8i-h3-codec-analog";
555 reg = <0x01f015c0 0x4>;
556 };
557
558 ir: ir@01f02000 {
559 compatible = "allwinner,sun5i-a13-ir";
560 clocks = <&apb0_gates 1>, <&ir_clk>;
561 clock-names = "apb", "ir";
562 resets = <&apb0_reset 1>;
563 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
564 reg = <0x01f02000 0x40>;
565 status = "disabled";
566 };
567
568 r_pio: pinctrl@01f02c00 {
569 compatible = "allwinner,sun8i-h3-r-pinctrl";
570 reg = <0x01f02c00 0x400>;
571 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
573 clock-names = "apb", "hosc", "losc";
574 resets = <&apb0_reset 0>;
575 gpio-controller;
576 #gpio-cells = <3>;
577 interrupt-controller;
578 #interrupt-cells = <3>;
579
580 ir_pins_a: ir@0 {
581 pins = "PL11";
582 function = "s_cir_rx";
583 };
584 };
585 };
586};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 15:46:22 -0400