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authorJerome Brunet <jbrunet@baylibre.com>2017-12-18 04:44:41 -0500
committerDavid S. Miller <davem@davemloft.net>2017-12-18 13:24:55 -0500
commit00fd73eb29205c1c94805fe5e39a09135d870e96 (patch)
treec7729c24af7aed29b50cec6527498d06d175dfc1
parent9042b46eda33ef5db3cdfc9e12b3c8cabb196141 (diff)
net: phy: meson-gxl: define control registers
Define registers and bits in meson-gxl PHY driver to make a bit more human friendly. No functional change. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/phy/meson-gxl.c86
1 files changed, 66 insertions, 20 deletions
diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
index 900606204c0a..61bcc17098d7 100644
--- a/drivers/net/phy/meson-gxl.c
+++ b/drivers/net/phy/meson-gxl.c
@@ -24,53 +24,95 @@
24#include <linux/netdevice.h> 24#include <linux/netdevice.h>
25#include <linux/bitfield.h> 25#include <linux/bitfield.h>
26 26
27#define TSTCNTL 20
28#define TSTCNTL_READ BIT(15)
29#define TSTCNTL_WRITE BIT(14)
30#define TSTCNTL_REG_BANK_SEL GENMASK(12, 11)
31#define TSTCNTL_TEST_MODE BIT(10)
32#define TSTCNTL_READ_ADDRESS GENMASK(9, 5)
33#define TSTCNTL_WRITE_ADDRESS GENMASK(4, 0)
34#define TSTREAD1 21
35#define TSTWRITE 23
36
37#define BANK_ANALOG_DSP 0
38#define BANK_WOL 1
39#define BANK_BIST 3
40
41/* Analog/DSP Registers */
42#define A6_CONFIG_REG 0x17
43
44/* WOL Registers */
45#define LPI_STATUS 0xc
46#define LPI_STATUS_RSV12 BIT(12)
47
48/* BIST Registers */
49#define FR_PLL_CONTROL 0x1b
50#define FR_PLL_DIV0 0x1c
51#define FR_PLL_DIV1 0x1d
52
27static int meson_gxl_config_init(struct phy_device *phydev) 53static int meson_gxl_config_init(struct phy_device *phydev)
28{ 54{
29 int ret; 55 int ret;
30 56
31 /* Enable Analog and DSP register Bank access by */ 57 /* Enable Analog and DSP register Bank access by */
32 ret = phy_write(phydev, 0x14, 0x0000); 58 ret = phy_write(phydev, TSTCNTL, 0);
33 if (ret) 59 if (ret)
34 return ret; 60 return ret;
35 ret = phy_write(phydev, 0x14, 0x0400); 61 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
36 if (ret) 62 if (ret)
37 return ret; 63 return ret;
38 ret = phy_write(phydev, 0x14, 0x0000); 64 ret = phy_write(phydev, TSTCNTL, 0);
39 if (ret) 65 if (ret)
40 return ret; 66 return ret;
41 ret = phy_write(phydev, 0x14, 0x0400); 67 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
42 if (ret) 68 if (ret)
43 return ret; 69 return ret;
44 70
45 /* Write Analog register 23 */ 71 /* Write CONFIG_A6*/
46 ret = phy_write(phydev, 0x17, 0x8E0D); 72 ret = phy_write(phydev, TSTWRITE, 0x8e0d);
47 if (ret) 73 if (ret)
48 return ret; 74 return ret;
49 ret = phy_write(phydev, 0x14, 0x4417); 75 ret = phy_write(phydev, TSTCNTL,
76 TSTCNTL_WRITE
77 | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_ANALOG_DSP)
78 | TSTCNTL_TEST_MODE
79 | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, A6_CONFIG_REG));
50 if (ret) 80 if (ret)
51 return ret; 81 return ret;
52 82
53 /* Enable fractional PLL */ 83 /* Enable fractional PLL */
54 ret = phy_write(phydev, 0x17, 0x0005); 84 ret = phy_write(phydev, TSTWRITE, 0x0005);
55 if (ret) 85 if (ret)
56 return ret; 86 return ret;
57 ret = phy_write(phydev, 0x14, 0x5C1B); 87 ret = phy_write(phydev, TSTCNTL,
88 TSTCNTL_WRITE
89 | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST)
90 | TSTCNTL_TEST_MODE
91 | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_CONTROL));
58 if (ret) 92 if (ret)
59 return ret; 93 return ret;
60 94
61 /* Program fraction FR_PLL_DIV1 */ 95 /* Program fraction FR_PLL_DIV1 */
62 ret = phy_write(phydev, 0x17, 0x029A); 96 ret = phy_write(phydev, TSTWRITE, 0x029a);
63 if (ret) 97 if (ret)
64 return ret; 98 return ret;
65 ret = phy_write(phydev, 0x14, 0x5C1D); 99 ret = phy_write(phydev, TSTCNTL,
100 TSTCNTL_WRITE
101 | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST)
102 | TSTCNTL_TEST_MODE
103 | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_DIV1));
66 if (ret) 104 if (ret)
67 return ret; 105 return ret;
68 106
69 /* Program fraction FR_PLL_DIV1 */ 107 /* Program fraction FR_PLL_DIV1 */
70 ret = phy_write(phydev, 0x17, 0xAAAA); 108 ret = phy_write(phydev, TSTWRITE, 0xaaaa);
71 if (ret) 109 if (ret)
72 return ret; 110 return ret;
73 ret = phy_write(phydev, 0x14, 0x5C1C); 111 ret = phy_write(phydev, TSTCNTL,
112 TSTCNTL_WRITE
113 | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST)
114 | TSTCNTL_TEST_MODE
115 | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_DIV0));
74 if (ret) 116 if (ret)
75 return ret; 117 return ret;
76 118
@@ -105,26 +147,30 @@ static int meson_gxl_read_status(struct phy_device *phydev)
105 goto read_status_continue; 147 goto read_status_continue;
106 148
107 /* Need to access WOL bank, make sure the access is open */ 149 /* Need to access WOL bank, make sure the access is open */
108 ret = phy_write(phydev, 0x14, 0x0000); 150 ret = phy_write(phydev, TSTCNTL, 0);
109 if (ret) 151 if (ret)
110 return ret; 152 return ret;
111 ret = phy_write(phydev, 0x14, 0x0400); 153 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
112 if (ret) 154 if (ret)
113 return ret; 155 return ret;
114 ret = phy_write(phydev, 0x14, 0x0000); 156 ret = phy_write(phydev, TSTCNTL, 0);
115 if (ret) 157 if (ret)
116 return ret; 158 return ret;
117 ret = phy_write(phydev, 0x14, 0x0400); 159 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
118 if (ret) 160 if (ret)
119 return ret; 161 return ret;
120 162
121 /* Request LPI_STATUS WOL register */ 163 /* Request LPI_STATUS WOL register */
122 ret = phy_write(phydev, 0x14, 0x8D80); 164 ret = phy_write(phydev, TSTCNTL,
165 TSTCNTL_READ
166 | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_WOL)
167 | TSTCNTL_TEST_MODE
168 | FIELD_PREP(TSTCNTL_READ_ADDRESS, LPI_STATUS));
123 if (ret) 169 if (ret)
124 return ret; 170 return ret;
125 171
126 /* Read LPI_STATUS value */ 172 /* Read LPI_STATUS value */
127 wol = phy_read(phydev, 0x15); 173 wol = phy_read(phydev, TSTREAD1);
128 if (wol < 0) 174 if (wol < 0)
129 return wol; 175 return wol;
130 176
@@ -136,7 +182,7 @@ static int meson_gxl_read_status(struct phy_device *phydev)
136 if (exp < 0) 182 if (exp < 0)
137 return exp; 183 return exp;
138 184
139 if (!(wol & BIT(12)) || 185 if (!(wol & LPI_STATUS_RSV12) ||
140 ((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) { 186 ((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) {
141 /* Looks like aneg failed after all */ 187 /* Looks like aneg failed after all */
142 phydev_dbg(phydev, "LPA corruption - aneg restart\n"); 188 phydev_dbg(phydev, "LPA corruption - aneg restart\n");
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-17 14:24:50 -0400