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authorQiuxu Zhuo <qiuxu.zhuo@intel.com>2017-05-22 20:05:33 -0400
committerBorislav Petkov <bp@suse.de>2017-05-25 05:19:25 -0400
commit00cf50d90a99fac96644078f40c88a7ad43fb71c (patch)
tree12ac147ec00abfa45e8c8eab5a48cbfc330f29bd
parent18caec20bfa56911b5d23811ae344ae8dc163ba9 (diff)
EDAC, sb_edac: Classify PCI-IDs by topology
Each of the PCI device IDs belongs to a CPU socket, or to one of the integrated memory controllers. Provide an enum to specify the domain of each, and distinguish the resource number in each domain: the number of the PCI device IDs per integrated memory controller/socket, and the number of integrated memory controllers per socket. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/20170523000533.87704-1-qiuxu.zhuo@intel.com [ Realign pci_dev_descr_knl members. ] Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat
-rw-r--r--drivers/edac/sb_edac.c235
1 files changed, 121 insertions, 114 deletions
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index ea21cb651b3c..fe4ffeaa623b 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -294,6 +294,12 @@ enum type {
294 KNIGHTS_LANDING, 294 KNIGHTS_LANDING,
295}; 295};
296 296
297enum domain {
298 IMC0 = 0,
299 IMC1,
300 SOCK,
301};
302
297struct sbridge_pvt; 303struct sbridge_pvt;
298struct sbridge_info { 304struct sbridge_info {
299 enum type type; 305 enum type type;
@@ -324,11 +330,14 @@ struct sbridge_channel {
324struct pci_id_descr { 330struct pci_id_descr {
325 int dev_id; 331 int dev_id;
326 int optional; 332 int optional;
333 enum domain dom;
327}; 334};
328 335
329struct pci_id_table { 336struct pci_id_table {
330 const struct pci_id_descr *descr; 337 const struct pci_id_descr *descr;
331 int n_devs; 338 int n_devs_per_imc;
339 int n_devs_per_sock;
340 int n_imcs_per_sock;
332 enum type type; 341 enum type type;
333}; 342};
334 343
@@ -337,6 +346,7 @@ struct sbridge_dev {
337 u8 bus, mc; 346 u8 bus, mc;
338 u8 node_id, source_id; 347 u8 node_id, source_id;
339 struct pci_dev **pdev; 348 struct pci_dev **pdev;
349 enum domain dom;
340 int n_devs; 350 int n_devs;
341 struct mem_ctl_info *mci; 351 struct mem_ctl_info *mci;
342}; 352};
@@ -373,39 +383,42 @@ struct sbridge_pvt {
373 struct knl_pvt knl; 383 struct knl_pvt knl;
374}; 384};
375 385
376#define PCI_DESCR(device_id, opt) \ 386#define PCI_DESCR(device_id, opt, domain) \
377 .dev_id = (device_id), \ 387 .dev_id = (device_id), \
378 .optional = opt 388 .optional = opt, \
389 .dom = domain
379 390
380static const struct pci_id_descr pci_dev_descr_sbridge[] = { 391static const struct pci_id_descr pci_dev_descr_sbridge[] = {
381 /* Processor Home Agent */ 392 /* Processor Home Agent */
382 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) }, 393 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0, IMC0) },
383 394
384 /* Memory controller */ 395 /* Memory controller */
385 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) }, 396 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0, IMC0) },
386 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) }, 397 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0, IMC0) },
387 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) }, 398 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0, IMC0) },
388 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) }, 399 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0, IMC0) },
389 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) }, 400 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0, IMC0) },
390 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) }, 401 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0, IMC0) },
391 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) }, 402 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1, SOCK) },
392 403
393 /* System Address Decoder */ 404 /* System Address Decoder */
394 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) }, 405 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0, SOCK) },
395 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) }, 406 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0, SOCK) },
396 407
397 /* Broadcast Registers */ 408 /* Broadcast Registers */
398 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) }, 409 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0, SOCK) },
399}; 410};
400 411
401#define PCI_ID_TABLE_ENTRY(A, T) { \ 412#define PCI_ID_TABLE_ENTRY(A, N, M, T) { \
402 .descr = A, \ 413 .descr = A, \
403 .n_devs = ARRAY_SIZE(A), \ 414 .n_devs_per_imc = N, \
415 .n_devs_per_sock = ARRAY_SIZE(A), \
416 .n_imcs_per_sock = M, \
404 .type = T \ 417 .type = T \
405} 418}
406 419
407static const struct pci_id_table pci_dev_descr_sbridge_table[] = { 420static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
408 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge, SANDY_BRIDGE), 421 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge, ARRAY_SIZE(pci_dev_descr_sbridge), 1, SANDY_BRIDGE),
409 {0,} /* 0 terminated list. */ 422 {0,} /* 0 terminated list. */
410}; 423};
411 424
@@ -439,40 +452,39 @@ static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
439 452
440static const struct pci_id_descr pci_dev_descr_ibridge[] = { 453static const struct pci_id_descr pci_dev_descr_ibridge[] = {
441 /* Processor Home Agent */ 454 /* Processor Home Agent */
442 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) }, 455 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0, IMC0) },
443 456
444 /* Memory controller */ 457 /* Memory controller */
445 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) }, 458 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0, IMC0) },
446 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) }, 459 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0, IMC0) },
447 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) }, 460 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0, IMC0) },
448 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) }, 461 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0, IMC0) },
449 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) }, 462 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0, IMC0) },
450 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) }, 463 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0, IMC0) },
464
465 /* Optional, mode 2HA */
466 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1, IMC1) },
467 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1, IMC1) },
468 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1, IMC1) },
469 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1, IMC1) },
470 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1, IMC1) },
471 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1, IMC1) },
472 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1, IMC1) },
473
474 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1, SOCK) },
475 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1, SOCK) },
451 476
452 /* System Address Decoder */ 477 /* System Address Decoder */
453 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) }, 478 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0, SOCK) },
454 479
455 /* Broadcast Registers */ 480 /* Broadcast Registers */
456 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) }, 481 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1, SOCK) },
457 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) }, 482 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0, SOCK) },
458 483
459 /* Optional, mode 2HA */
460 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) },
461#if 0
462 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) },
463 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) },
464#endif
465 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) },
466 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) },
467 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1) },
468 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1) },
469
470 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) },
471 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) },
472}; 484};
473 485
474static const struct pci_id_table pci_dev_descr_ibridge_table[] = { 486static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
475 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge, IVY_BRIDGE), 487 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge, 12, 2, IVY_BRIDGE),
476 {0,} /* 0 terminated list. */ 488 {0,} /* 0 terminated list. */
477}; 489};
478 490
@@ -498,9 +510,9 @@ static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
498#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0 510#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0
499#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60 511#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60
500#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8 512#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8
501#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71 513#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM 0x2f71
502#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68 514#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68
503#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79 515#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM 0x2f79
504#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc 516#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
505#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd 517#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
506#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa 518#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
@@ -517,35 +529,33 @@ static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
517#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb 529#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
518static const struct pci_id_descr pci_dev_descr_haswell[] = { 530static const struct pci_id_descr pci_dev_descr_haswell[] = {
519 /* first item must be the HA */ 531 /* first item must be the HA */
520 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) }, 532 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0, IMC0) },
521 533 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1, IMC1) },
522 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0) }, 534
523 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0) }, 535 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0, IMC0) },
524 536 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM, 0, IMC0) },
525 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1) }, 537 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0, IMC0) },
526 538 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0, IMC0) },
527 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0) }, 539 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1, IMC0) },
528 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0) }, 540 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1, IMC0) },
529 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0) }, 541
530 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0) }, 542 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1, IMC1) },
531 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1) }, 543 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM, 1, IMC1) },
532 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) }, 544 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1, IMC1) },
533 545 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1, IMC1) },
534 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) }, 546 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1, IMC1) },
535 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1) }, 547 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1, IMC1) },
536 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1) }, 548
537 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1) }, 549 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0, SOCK) },
538 550 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0, SOCK) },
539 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) }, 551 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1, SOCK) },
540 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) }, 552 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1, SOCK) },
541 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1) }, 553 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1, SOCK) },
542 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1) }, 554 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1, SOCK) },
543 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1) },
544 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1) },
545}; 555};
546 556
547static const struct pci_id_table pci_dev_descr_haswell_table[] = { 557static const struct pci_id_table pci_dev_descr_haswell_table[] = {
548 PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell, HASWELL), 558 PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell, 13, 2, HASWELL),
549 {0,} /* 0 terminated list. */ 559 {0,} /* 0 terminated list. */
550}; 560};
551 561
@@ -559,7 +569,7 @@ static const struct pci_id_table pci_dev_descr_haswell_table[] = {
559/* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */ 569/* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */
560#define PCI_DEVICE_ID_INTEL_KNL_IMC_MC 0x7840 570#define PCI_DEVICE_ID_INTEL_KNL_IMC_MC 0x7840
561/* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */ 571/* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
562#define PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL 0x7843 572#define PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN 0x7843
563/* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */ 573/* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */
564#define PCI_DEVICE_ID_INTEL_KNL_IMC_TA 0x7844 574#define PCI_DEVICE_ID_INTEL_KNL_IMC_TA 0x7844
565/* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */ 575/* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */
@@ -579,17 +589,17 @@ static const struct pci_id_table pci_dev_descr_haswell_table[] = {
579 */ 589 */
580 590
581static const struct pci_id_descr pci_dev_descr_knl[] = { 591static const struct pci_id_descr pci_dev_descr_knl[] = {
582 [0] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0) }, 592 [0 ... 1] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0, IMC0)},
583 [1] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0) }, 593 [2 ... 7] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN, 0, IMC0) },
584 [2 ... 3] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0)}, 594 [8] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0, IMC0) },
585 [4 ... 41] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0) }, 595 [9] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0, IMC0) },
586 [42 ... 47] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL, 0) }, 596 [10] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0, SOCK) },
587 [48] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0) }, 597 [11] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0, SOCK) },
588 [49] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0) }, 598 [12 ... 49] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0, SOCK) },
589}; 599};
590 600
591static const struct pci_id_table pci_dev_descr_knl_table[] = { 601static const struct pci_id_table pci_dev_descr_knl_table[] = {
592 PCI_ID_TABLE_ENTRY(pci_dev_descr_knl, KNIGHTS_LANDING), 602 PCI_ID_TABLE_ENTRY(pci_dev_descr_knl, ARRAY_SIZE(pci_dev_descr_knl), 1, KNIGHTS_LANDING),
593 {0,} 603 {0,}
594}; 604};
595 605
@@ -615,9 +625,9 @@ static const struct pci_id_table pci_dev_descr_knl_table[] = {
615#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0 625#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0
616#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60 626#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60
617#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8 627#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8
618#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71 628#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM 0x6f71
619#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68 629#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68
620#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL 0x6f79 630#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM 0x6f79
621#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc 631#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
622#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd 632#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
623#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa 633#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
@@ -632,32 +642,30 @@ static const struct pci_id_table pci_dev_descr_knl_table[] = {
632 642
633static const struct pci_id_descr pci_dev_descr_broadwell[] = { 643static const struct pci_id_descr pci_dev_descr_broadwell[] = {
634 /* first item must be the HA */ 644 /* first item must be the HA */
635 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0) }, 645 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0, IMC0) },
636 646 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1, IMC1) },
637 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0) }, 647
638 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0) }, 648 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0, IMC0) },
639 649 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM, 0, IMC0) },
640 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1) }, 650 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0, IMC0) },
641 651 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0, IMC0) },
642 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0) }, 652 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1, IMC0) },
643 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0) }, 653 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1, IMC0) },
644 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0) }, 654
645 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0) }, 655 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1, IMC1) },
646 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1) }, 656 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM, 1, IMC1) },
647 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1) }, 657 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1, IMC1) },
648 658 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1, IMC1) },
649 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1) }, 659 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1, IMC1) },
650 660 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1, IMC1) },
651 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1) }, 661
652 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL, 1) }, 662 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0, SOCK) },
653 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1) }, 663 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0, SOCK) },
654 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1) }, 664 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1, SOCK) },
655 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1) },
656 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1) },
657}; 665};
658 666
659static const struct pci_id_table pci_dev_descr_broadwell_table[] = { 667static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
660 PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell, BROADWELL), 668 PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell, 10, 2, BROADWELL),
661 {0,} /* 0 terminated list. */ 669 {0,} /* 0 terminated list. */
662}; 670};
663 671
@@ -730,8 +738,7 @@ static struct sbridge_dev *get_sbridge_dev(u8 bus, int multi_bus)
730 return NULL; 738 return NULL;
731} 739}
732 740
733static struct sbridge_dev *alloc_sbridge_dev(u8 bus, 741static struct sbridge_dev *alloc_sbridge_dev(u8 bus, enum domain dom, const struct pci_id_table *table)
734 const struct pci_id_table *table)
735{ 742{
736 struct sbridge_dev *sbridge_dev; 743 struct sbridge_dev *sbridge_dev;
737 744
@@ -739,15 +746,15 @@ static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
739 if (!sbridge_dev) 746 if (!sbridge_dev)
740 return NULL; 747 return NULL;
741 748
742 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs, 749 sbridge_dev->pdev = kcalloc(table->n_devs_per_sock, sizeof(*sbridge_dev->pdev), GFP_KERNEL);
743 GFP_KERNEL);
744 if (!sbridge_dev->pdev) { 750 if (!sbridge_dev->pdev) {
745 kfree(sbridge_dev); 751 kfree(sbridge_dev);
746 return NULL; 752 return NULL;
747 } 753 }
748 754
749 sbridge_dev->bus = bus; 755 sbridge_dev->bus = bus;
750 sbridge_dev->n_devs = table->n_devs; 756 sbridge_dev->dom = dom;
757 sbridge_dev->n_devs = table->n_devs_per_sock;
751 list_add_tail(&sbridge_dev->list, &sbridge_edac_list); 758 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
752 759
753 return sbridge_dev; 760 return sbridge_dev;
@@ -2313,7 +2320,7 @@ static int sbridge_get_onedevice(struct pci_dev **prev,
2313 2320
2314 sbridge_dev = get_sbridge_dev(bus, multi_bus); 2321 sbridge_dev = get_sbridge_dev(bus, multi_bus);
2315 if (!sbridge_dev) { 2322 if (!sbridge_dev) {
2316 sbridge_dev = alloc_sbridge_dev(bus, table); 2323 sbridge_dev = alloc_sbridge_dev(bus, dev_descr->dom, table);
2317 if (!sbridge_dev) { 2324 if (!sbridge_dev) {
2318 pci_dev_put(pdev); 2325 pci_dev_put(pdev);
2319 return -ENOMEM; 2326 return -ENOMEM;
@@ -2374,7 +2381,7 @@ static int sbridge_get_all_devices(u8 *num_mc,
2374 if (table->type == KNIGHTS_LANDING) 2381 if (table->type == KNIGHTS_LANDING)
2375 allow_dups = multi_bus = 1; 2382 allow_dups = multi_bus = 1;
2376 while (table && table->descr) { 2383 while (table && table->descr) {
2377 for (i = 0; i < table->n_devs; i++) { 2384 for (i = 0; i < table->n_devs_per_sock; i++) {
2378 if (!allow_dups || i == 0 || 2385 if (!allow_dups || i == 0 ||
2379 table->descr[i].dev_id != 2386 table->descr[i].dev_id !=
2380 table->descr[i-1].dev_id) { 2387 table->descr[i-1].dev_id) {
@@ -2385,7 +2392,7 @@ static int sbridge_get_all_devices(u8 *num_mc,
2385 table, i, multi_bus); 2392 table, i, multi_bus);
2386 if (rc < 0) { 2393 if (rc < 0) {
2387 if (i == 0) { 2394 if (i == 0) {
2388 i = table->n_devs; 2395 i = table->n_devs_per_sock;
2389 break; 2396 break;
2390 } 2397 }
2391 sbridge_put_all_devices(); 2398 sbridge_put_all_devices();
@@ -2598,7 +2605,7 @@ static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
2598 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA: 2605 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
2599 pvt->pci_ta = pdev; 2606 pvt->pci_ta = pdev;
2600 break; 2607 break;
2601 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL: 2608 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM:
2602 pvt->pci_ras = pdev; 2609 pvt->pci_ras = pdev;
2603 break; 2610 break;
2604 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0: 2611 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
@@ -2695,7 +2702,7 @@ static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
2695 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA: 2702 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
2696 pvt->pci_ta = pdev; 2703 pvt->pci_ta = pdev;
2697 break; 2704 break;
2698 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL: 2705 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM:
2699 pvt->pci_ras = pdev; 2706 pvt->pci_ras = pdev;
2700 break; 2707 break;
2701 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0: 2708 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
@@ -2812,7 +2819,7 @@ static int knl_mci_bind_devs(struct mem_ctl_info *mci,
2812 pvt->knl.pci_cha[devidx] = pdev; 2819 pvt->knl.pci_cha[devidx] = pdev;
2813 break; 2820 break;
2814 2821
2815 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL: 2822 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN:
2816 devidx = -1; 2823 devidx = -1;
2817 2824
2818 /* 2825 /*
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-17 20:18:41 -0400