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authorHuang Rui <ray.huang@amd.com>2016-06-12 03:44:44 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-07-07 14:51:33 -0400
commit000cab9a61ea9e8dc42144e39a6eb8333a402b86 (patch)
tree562c610fd09ee824cf1f4fae3cee78f4312e88f6
parent8db6f83bef165bc47d1f1cd56afdec37b47917d1 (diff)
drm/amdgpu: factor out the AMDGPU_INFO_FW_VERSION case branch into amdgpu_firmware_info
The new amdgpu_firmware_info function will be used on amdgpu firmware version debugfs. Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c116
-rw-r--r--include/uapi/drm/amdgpu_drm.h32
2 files changed, 81 insertions, 67 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index d851ea15059f..56c857f6e7ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -142,6 +142,65 @@ out:
142 return r; 142 return r;
143} 143}
144 144
145static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
146 struct drm_amdgpu_query_fw *query_fw,
147 struct amdgpu_device *adev)
148{
149 switch (query_fw->fw_type) {
150 case AMDGPU_INFO_FW_VCE:
151 fw_info->ver = adev->vce.fw_version;
152 fw_info->feature = adev->vce.fb_version;
153 break;
154 case AMDGPU_INFO_FW_UVD:
155 fw_info->ver = adev->uvd.fw_version;
156 fw_info->feature = 0;
157 break;
158 case AMDGPU_INFO_FW_GMC:
159 fw_info->ver = adev->mc.fw_version;
160 fw_info->feature = 0;
161 break;
162 case AMDGPU_INFO_FW_GFX_ME:
163 fw_info->ver = adev->gfx.me_fw_version;
164 fw_info->feature = adev->gfx.me_feature_version;
165 break;
166 case AMDGPU_INFO_FW_GFX_PFP:
167 fw_info->ver = adev->gfx.pfp_fw_version;
168 fw_info->feature = adev->gfx.pfp_feature_version;
169 break;
170 case AMDGPU_INFO_FW_GFX_CE:
171 fw_info->ver = adev->gfx.ce_fw_version;
172 fw_info->feature = adev->gfx.ce_feature_version;
173 break;
174 case AMDGPU_INFO_FW_GFX_RLC:
175 fw_info->ver = adev->gfx.rlc_fw_version;
176 fw_info->feature = adev->gfx.rlc_feature_version;
177 break;
178 case AMDGPU_INFO_FW_GFX_MEC:
179 if (query_fw->index == 0) {
180 fw_info->ver = adev->gfx.mec_fw_version;
181 fw_info->feature = adev->gfx.mec_feature_version;
182 } else if (query_fw->index == 1) {
183 fw_info->ver = adev->gfx.mec2_fw_version;
184 fw_info->feature = adev->gfx.mec2_feature_version;
185 } else
186 return -EINVAL;
187 break;
188 case AMDGPU_INFO_FW_SMC:
189 fw_info->ver = adev->pm.fw_version;
190 fw_info->feature = 0;
191 break;
192 case AMDGPU_INFO_FW_SDMA:
193 if (query_fw->index >= adev->sdma.num_instances)
194 return -EINVAL;
195 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
196 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
197 break;
198 default:
199 return -EINVAL;
200 }
201 return 0;
202}
203
145/* 204/*
146 * Userspace get information ioctl 205 * Userspace get information ioctl
147 */ 206 */
@@ -292,63 +351,16 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
292 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 351 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
293 case AMDGPU_INFO_FW_VERSION: { 352 case AMDGPU_INFO_FW_VERSION: {
294 struct drm_amdgpu_info_firmware fw_info; 353 struct drm_amdgpu_info_firmware fw_info;
354 int ret;
295 355
296 /* We only support one instance of each IP block right now. */ 356 /* We only support one instance of each IP block right now. */
297 if (info->query_fw.ip_instance != 0) 357 if (info->query_fw.ip_instance != 0)
298 return -EINVAL; 358 return -EINVAL;
299 359
300 switch (info->query_fw.fw_type) { 360 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
301 case AMDGPU_INFO_FW_VCE: 361 if (ret)
302 fw_info.ver = adev->vce.fw_version; 362 return ret;
303 fw_info.feature = adev->vce.fb_version; 363
304 break;
305 case AMDGPU_INFO_FW_UVD:
306 fw_info.ver = adev->uvd.fw_version;
307 fw_info.feature = 0;
308 break;
309 case AMDGPU_INFO_FW_GMC:
310 fw_info.ver = adev->mc.fw_version;
311 fw_info.feature = 0;
312 break;
313 case AMDGPU_INFO_FW_GFX_ME:
314 fw_info.ver = adev->gfx.me_fw_version;
315 fw_info.feature = adev->gfx.me_feature_version;
316 break;
317 case AMDGPU_INFO_FW_GFX_PFP:
318 fw_info.ver = adev->gfx.pfp_fw_version;
319 fw_info.feature = adev->gfx.pfp_feature_version;
320 break;
321 case AMDGPU_INFO_FW_GFX_CE:
322 fw_info.ver = adev->gfx.ce_fw_version;
323 fw_info.feature = adev->gfx.ce_feature_version;
324 break;
325 case AMDGPU_INFO_FW_GFX_RLC:
326 fw_info.ver = adev->gfx.rlc_fw_version;
327 fw_info.feature = adev->gfx.rlc_feature_version;
328 break;
329 case AMDGPU_INFO_FW_GFX_MEC:
330 if (info->query_fw.index == 0) {
331 fw_info.ver = adev->gfx.mec_fw_version;
332 fw_info.feature = adev->gfx.mec_feature_version;
333 } else if (info->query_fw.index == 1) {
334 fw_info.ver = adev->gfx.mec2_fw_version;
335 fw_info.feature = adev->gfx.mec2_feature_version;
336 } else
337 return -EINVAL;
338 break;
339 case AMDGPU_INFO_FW_SMC:
340 fw_info.ver = adev->pm.fw_version;
341 fw_info.feature = 0;
342 break;
343 case AMDGPU_INFO_FW_SDMA:
344 if (info->query_fw.index >= adev->sdma.num_instances)
345 return -EINVAL;
346 fw_info.ver = adev->sdma.instance[info->query_fw.index].fw_version;
347 fw_info.feature = adev->sdma.instance[info->query_fw.index].feature_version;
348 break;
349 default:
350 return -EINVAL;
351 }
352 return copy_to_user(out, &fw_info, 364 return copy_to_user(out, &fw_info,
353 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 365 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
354 } 366 }
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index cdecf87576e8..462246aa200e 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -487,6 +487,22 @@ struct drm_amdgpu_cs_chunk_data {
487#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 487#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
488#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 488#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
489 489
490struct drm_amdgpu_query_fw {
491 /** AMDGPU_INFO_FW_* */
492 __u32 fw_type;
493 /**
494 * Index of the IP if there are more IPs of
495 * the same type.
496 */
497 __u32 ip_instance;
498 /**
499 * Index of the engine. Whether this is used depends
500 * on the firmware type. (e.g. MEC, SDMA)
501 */
502 __u32 index;
503 __u32 _pad;
504};
505
490/* Input structure for the INFO ioctl */ 506/* Input structure for the INFO ioctl */
491struct drm_amdgpu_info { 507struct drm_amdgpu_info {
492 /* Where the return value will be stored */ 508 /* Where the return value will be stored */
@@ -522,21 +538,7 @@ struct drm_amdgpu_info {
522 __u32 flags; 538 __u32 flags;
523 } read_mmr_reg; 539 } read_mmr_reg;
524 540
525 struct { 541 struct drm_amdgpu_query_fw query_fw;
526 /** AMDGPU_INFO_FW_* */
527 __u32 fw_type;
528 /**
529 * Index of the IP if there are more IPs of
530 * the same type.
531 */
532 __u32 ip_instance;
533 /**
534 * Index of the engine. Whether this is used depends
535 * on the firmware type. (e.g. MEC, SDMA)
536 */
537 __u32 index;
538 __u32 _pad;
539 } query_fw;
540 }; 542 };
541}; 543};
542 544
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 19:45:45 -0400