diff options
author | Dave Airlie <airlied@redhat.com> | 2018-01-04 18:24:26 -0500 |
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committer | Dave Airlie <airlied@redhat.com> | 2018-01-04 18:24:26 -0500 |
commit | 0007b9cad799a7280d60b1a8a4b9462e613c6b5a (patch) | |
tree | 1c1642154a34a4edc52c2c97d1362f9dddecdfce | |
parent | dc042da05f6d5f5ba234412e2019483e64535738 (diff) | |
parent | 19d859a7205bc59ffc38303eb25ae394f61d21dc (diff) |
Merge branch 'drm-fixes-4.15' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
- backport of a DC change which fixes a greenish tint on some RV hw
- properly handle kzalloc fail in ttm
* 'drm-fixes-4.15' of git://people.freedesktop.org/~agd5f/linux:
drm/ttm: check the return value of kzalloc
drm/amd/display: call set csc_default if enable adjustment is false
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/ttm/ttm_page_alloc.c | 2 |
5 files changed, 8 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index a9782b1aba47..34daf895f848 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | |||
@@ -1360,7 +1360,7 @@ void dpp1_cm_set_output_csc_adjustment( | |||
1360 | 1360 | ||
1361 | void dpp1_cm_set_output_csc_default( | 1361 | void dpp1_cm_set_output_csc_default( |
1362 | struct dpp *dpp_base, | 1362 | struct dpp *dpp_base, |
1363 | const struct default_adjustment *default_adjust); | 1363 | enum dc_color_space colorspace); |
1364 | 1364 | ||
1365 | void dpp1_cm_set_gamut_remap( | 1365 | void dpp1_cm_set_gamut_remap( |
1366 | struct dpp *dpp, | 1366 | struct dpp *dpp, |
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index 40627c244bf5..ed1216b53465 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | |||
@@ -225,14 +225,13 @@ void dpp1_cm_set_gamut_remap( | |||
225 | 225 | ||
226 | void dpp1_cm_set_output_csc_default( | 226 | void dpp1_cm_set_output_csc_default( |
227 | struct dpp *dpp_base, | 227 | struct dpp *dpp_base, |
228 | const struct default_adjustment *default_adjust) | 228 | enum dc_color_space colorspace) |
229 | { | 229 | { |
230 | 230 | ||
231 | struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); | 231 | struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); |
232 | uint32_t ocsc_mode = 0; | 232 | uint32_t ocsc_mode = 0; |
233 | 233 | ||
234 | if (default_adjust != NULL) { | 234 | switch (colorspace) { |
235 | switch (default_adjust->out_color_space) { | ||
236 | case COLOR_SPACE_SRGB: | 235 | case COLOR_SPACE_SRGB: |
237 | case COLOR_SPACE_2020_RGB_FULLRANGE: | 236 | case COLOR_SPACE_2020_RGB_FULLRANGE: |
238 | ocsc_mode = 0; | 237 | ocsc_mode = 0; |
@@ -253,7 +252,6 @@ void dpp1_cm_set_output_csc_default( | |||
253 | case COLOR_SPACE_UNKNOWN: | 252 | case COLOR_SPACE_UNKNOWN: |
254 | default: | 253 | default: |
255 | break; | 254 | break; |
256 | } | ||
257 | } | 255 | } |
258 | 256 | ||
259 | REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); | 257 | REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); |
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 961ad5c3b454..05dc01e54531 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | |||
@@ -2097,6 +2097,8 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, | |||
2097 | tbl_entry.color_space = color_space; | 2097 | tbl_entry.color_space = color_space; |
2098 | //tbl_entry.regval = matrix; | 2098 | //tbl_entry.regval = matrix; |
2099 | pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry); | 2099 | pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry); |
2100 | } else { | ||
2101 | pipe_ctx->plane_res.dpp->funcs->opp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace); | ||
2100 | } | 2102 | } |
2101 | } | 2103 | } |
2102 | static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) | 2104 | static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) |
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index 83a68460edcd..9420dfb94d39 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | |||
@@ -64,7 +64,7 @@ struct dpp_funcs { | |||
64 | 64 | ||
65 | void (*opp_set_csc_default)( | 65 | void (*opp_set_csc_default)( |
66 | struct dpp *dpp, | 66 | struct dpp *dpp, |
67 | const struct default_adjustment *default_adjust); | 67 | enum dc_color_space colorspace); |
68 | 68 | ||
69 | void (*opp_set_csc_adjustment)( | 69 | void (*opp_set_csc_adjustment)( |
70 | struct dpp *dpp, | 70 | struct dpp *dpp, |
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index b5ba6441489f..5d252fb27a82 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c | |||
@@ -1007,6 +1007,8 @@ int ttm_page_alloc_init(struct ttm_mem_global *glob, unsigned max_pages) | |||
1007 | pr_info("Initializing pool allocator\n"); | 1007 | pr_info("Initializing pool allocator\n"); |
1008 | 1008 | ||
1009 | _manager = kzalloc(sizeof(*_manager), GFP_KERNEL); | 1009 | _manager = kzalloc(sizeof(*_manager), GFP_KERNEL); |
1010 | if (!_manager) | ||
1011 | return -ENOMEM; | ||
1010 | 1012 | ||
1011 | ttm_page_pool_init_locked(&_manager->wc_pool, GFP_HIGHUSER, "wc", 0); | 1013 | ttm_page_pool_init_locked(&_manager->wc_pool, GFP_HIGHUSER, "wc", 0); |
1012 | 1014 | ||